Commit | Line | Data |
---|---|---|
64fbf444 PB |
1 | /* |
2 | * | |
3 | * Support for a cx23417 mpeg encoder via cx231xx host port. | |
4 | * | |
5 | * (c) 2004 Jelle Foks <jelle@foks.us> | |
6 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> | |
7 | * (c) 2008 Steven Toth <stoth@linuxtv.org> | |
8 | * - CX23885/7/8 support | |
9 | * | |
10 | * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/), | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
26 | ||
589dadf2 MCC |
27 | #include "cx231xx.h" |
28 | ||
64fbf444 PB |
29 | #include <linux/module.h> |
30 | #include <linux/moduleparam.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/fs.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/device.h> | |
35 | #include <linux/firmware.h> | |
94399431 | 36 | #include <linux/vmalloc.h> |
64fbf444 PB |
37 | #include <media/v4l2-common.h> |
38 | #include <media/v4l2-ioctl.h> | |
88b6ffed | 39 | #include <media/v4l2-event.h> |
d647f0b7 | 40 | #include <media/drv-intf/cx2341x.h> |
b86d1544 | 41 | #include <media/tuner.h> |
64fbf444 | 42 | |
64fbf444 PB |
43 | #define CX231xx_FIRM_IMAGE_SIZE 376836 |
44 | #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" | |
45 | ||
955e6ed8 | 46 | /* for polaris ITVC */ |
64fbf444 PB |
47 | #define ITVC_WRITE_DIR 0x03FDFC00 |
48 | #define ITVC_READ_DIR 0x0001FC00 | |
49 | ||
50 | #define MCI_MEMORY_DATA_BYTE0 0x00 | |
51 | #define MCI_MEMORY_DATA_BYTE1 0x08 | |
52 | #define MCI_MEMORY_DATA_BYTE2 0x10 | |
53 | #define MCI_MEMORY_DATA_BYTE3 0x18 | |
54 | ||
55 | #define MCI_MEMORY_ADDRESS_BYTE2 0x20 | |
56 | #define MCI_MEMORY_ADDRESS_BYTE1 0x28 | |
57 | #define MCI_MEMORY_ADDRESS_BYTE0 0x30 | |
58 | ||
59 | #define MCI_REGISTER_DATA_BYTE0 0x40 | |
60 | #define MCI_REGISTER_DATA_BYTE1 0x48 | |
61 | #define MCI_REGISTER_DATA_BYTE2 0x50 | |
62 | #define MCI_REGISTER_DATA_BYTE3 0x58 | |
63 | ||
64 | #define MCI_REGISTER_ADDRESS_BYTE0 0x60 | |
65 | #define MCI_REGISTER_ADDRESS_BYTE1 0x68 | |
66 | ||
67 | #define MCI_REGISTER_MODE 0x70 | |
68 | ||
955e6ed8 | 69 | /* Read and write modes for polaris ITVC */ |
64fbf444 PB |
70 | #define MCI_MODE_REGISTER_READ 0x000 |
71 | #define MCI_MODE_REGISTER_WRITE 0x100 | |
72 | #define MCI_MODE_MEMORY_READ 0x000 | |
73 | #define MCI_MODE_MEMORY_WRITE 0x4000 | |
74 | ||
75 | static unsigned int mpegbufs = 8; | |
76 | module_param(mpegbufs, int, 0644); | |
77 | MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); | |
5b8acdc5 | 78 | |
64fbf444 PB |
79 | static unsigned int mpeglines = 128; |
80 | module_param(mpeglines, int, 0644); | |
81 | MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); | |
5b8acdc5 | 82 | |
64fbf444 PB |
83 | static unsigned int mpeglinesize = 512; |
84 | module_param(mpeglinesize, int, 0644); | |
85 | MODULE_PARM_DESC(mpeglinesize, | |
86 | "number of bytes in each line of an MPEG buffer, range 512-1024"); | |
87 | ||
88 | static unsigned int v4l_debug = 1; | |
89 | module_param(v4l_debug, int, 0644); | |
90 | MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); | |
5b8acdc5 | 91 | |
ed0e3729 MCC |
92 | #define dprintk(level, fmt, arg...) \ |
93 | do { \ | |
94 | if (v4l_debug >= level) \ | |
95 | printk(KERN_DEBUG pr_fmt(fmt), ## arg); \ | |
64fbf444 PB |
96 | } while (0) |
97 | ||
98 | static struct cx231xx_tvnorm cx231xx_tvnorms[] = { | |
99 | { | |
100 | .name = "NTSC-M", | |
101 | .id = V4L2_STD_NTSC_M, | |
102 | }, { | |
103 | .name = "NTSC-JP", | |
104 | .id = V4L2_STD_NTSC_M_JP, | |
105 | }, { | |
106 | .name = "PAL-BG", | |
107 | .id = V4L2_STD_PAL_BG, | |
108 | }, { | |
109 | .name = "PAL-DK", | |
110 | .id = V4L2_STD_PAL_DK, | |
111 | }, { | |
112 | .name = "PAL-I", | |
113 | .id = V4L2_STD_PAL_I, | |
114 | }, { | |
115 | .name = "PAL-M", | |
116 | .id = V4L2_STD_PAL_M, | |
117 | }, { | |
118 | .name = "PAL-N", | |
119 | .id = V4L2_STD_PAL_N, | |
120 | }, { | |
121 | .name = "PAL-Nc", | |
122 | .id = V4L2_STD_PAL_Nc, | |
123 | }, { | |
124 | .name = "PAL-60", | |
125 | .id = V4L2_STD_PAL_60, | |
126 | }, { | |
127 | .name = "SECAM-L", | |
128 | .id = V4L2_STD_SECAM_L, | |
129 | }, { | |
130 | .name = "SECAM-DK", | |
131 | .id = V4L2_STD_SECAM_DK, | |
132 | } | |
133 | }; | |
134 | ||
135 | /* ------------------------------------------------------------------ */ | |
5b8acdc5 | 136 | |
64fbf444 PB |
137 | enum cx231xx_capture_type { |
138 | CX231xx_MPEG_CAPTURE, | |
139 | CX231xx_RAW_CAPTURE, | |
140 | CX231xx_RAW_PASSTHRU_CAPTURE | |
141 | }; | |
5b8acdc5 | 142 | |
64fbf444 PB |
143 | enum cx231xx_capture_bits { |
144 | CX231xx_RAW_BITS_NONE = 0x00, | |
145 | CX231xx_RAW_BITS_YUV_CAPTURE = 0x01, | |
146 | CX231xx_RAW_BITS_PCM_CAPTURE = 0x02, | |
147 | CX231xx_RAW_BITS_VBI_CAPTURE = 0x04, | |
148 | CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08, | |
149 | CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10 | |
150 | }; | |
5b8acdc5 | 151 | |
64fbf444 PB |
152 | enum cx231xx_capture_end { |
153 | CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */ | |
154 | CX231xx_END_NOW, /* stop immediately, no irq */ | |
155 | }; | |
5b8acdc5 | 156 | |
64fbf444 PB |
157 | enum cx231xx_framerate { |
158 | CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */ | |
159 | CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */ | |
160 | }; | |
5b8acdc5 | 161 | |
64fbf444 PB |
162 | enum cx231xx_stream_port { |
163 | CX231xx_OUTPUT_PORT_MEMORY, | |
164 | CX231xx_OUTPUT_PORT_STREAMING, | |
165 | CX231xx_OUTPUT_PORT_SERIAL | |
166 | }; | |
5b8acdc5 | 167 | |
64fbf444 PB |
168 | enum cx231xx_data_xfer_status { |
169 | CX231xx_MORE_BUFFERS_FOLLOW, | |
170 | CX231xx_LAST_BUFFER, | |
171 | }; | |
5b8acdc5 | 172 | |
64fbf444 PB |
173 | enum cx231xx_picture_mask { |
174 | CX231xx_PICTURE_MASK_NONE, | |
175 | CX231xx_PICTURE_MASK_I_FRAMES, | |
176 | CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3, | |
177 | CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7, | |
178 | }; | |
5b8acdc5 | 179 | |
64fbf444 PB |
180 | enum cx231xx_vbi_mode_bits { |
181 | CX231xx_VBI_BITS_SLICED, | |
182 | CX231xx_VBI_BITS_RAW, | |
183 | }; | |
5b8acdc5 | 184 | |
64fbf444 PB |
185 | enum cx231xx_vbi_insertion_bits { |
186 | CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, | |
187 | CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, | |
188 | CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1, | |
189 | CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, | |
190 | CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, | |
191 | }; | |
5b8acdc5 | 192 | |
64fbf444 PB |
193 | enum cx231xx_dma_unit { |
194 | CX231xx_DMA_BYTES, | |
195 | CX231xx_DMA_FRAMES, | |
196 | }; | |
5b8acdc5 | 197 | |
64fbf444 PB |
198 | enum cx231xx_dma_transfer_status_bits { |
199 | CX231xx_DMA_TRANSFER_BITS_DONE = 0x01, | |
200 | CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04, | |
201 | CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10, | |
202 | }; | |
5b8acdc5 | 203 | |
64fbf444 PB |
204 | enum cx231xx_pause { |
205 | CX231xx_PAUSE_ENCODING, | |
206 | CX231xx_RESUME_ENCODING, | |
207 | }; | |
5b8acdc5 | 208 | |
64fbf444 PB |
209 | enum cx231xx_copyright { |
210 | CX231xx_COPYRIGHT_OFF, | |
211 | CX231xx_COPYRIGHT_ON, | |
212 | }; | |
5b8acdc5 | 213 | |
64fbf444 PB |
214 | enum cx231xx_notification_type { |
215 | CX231xx_NOTIFICATION_REFRESH, | |
216 | }; | |
5b8acdc5 | 217 | |
64fbf444 PB |
218 | enum cx231xx_notification_status { |
219 | CX231xx_NOTIFICATION_OFF, | |
220 | CX231xx_NOTIFICATION_ON, | |
221 | }; | |
5b8acdc5 | 222 | |
64fbf444 PB |
223 | enum cx231xx_notification_mailbox { |
224 | CX231xx_NOTIFICATION_NO_MAILBOX = -1, | |
225 | }; | |
5b8acdc5 | 226 | |
64fbf444 PB |
227 | enum cx231xx_field1_lines { |
228 | CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */ | |
229 | CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */ | |
230 | CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */ | |
231 | }; | |
5b8acdc5 | 232 | |
64fbf444 PB |
233 | enum cx231xx_field2_lines { |
234 | CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */ | |
235 | CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */ | |
236 | CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */ | |
237 | }; | |
5b8acdc5 | 238 | |
64fbf444 PB |
239 | enum cx231xx_custom_data_type { |
240 | CX231xx_CUSTOM_EXTENSION_USR_DATA, | |
241 | CX231xx_CUSTOM_PRIVATE_PACKET, | |
242 | }; | |
5b8acdc5 | 243 | |
64fbf444 PB |
244 | enum cx231xx_mute { |
245 | CX231xx_UNMUTE, | |
246 | CX231xx_MUTE, | |
247 | }; | |
5b8acdc5 | 248 | |
64fbf444 PB |
249 | enum cx231xx_mute_video_mask { |
250 | CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00, | |
251 | CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000, | |
252 | CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000, | |
253 | }; | |
5b8acdc5 | 254 | |
64fbf444 PB |
255 | enum cx231xx_mute_video_shift { |
256 | CX231xx_MUTE_VIDEO_V_SHIFT = 8, | |
257 | CX231xx_MUTE_VIDEO_U_SHIFT = 16, | |
258 | CX231xx_MUTE_VIDEO_Y_SHIFT = 24, | |
259 | }; | |
260 | ||
261 | /* defines below are from ivtv-driver.h */ | |
262 | #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF | |
263 | ||
264 | /* Firmware API commands */ | |
265 | #define IVTV_API_STD_TIMEOUT 500 | |
266 | ||
267 | /* Registers */ | |
268 | /* IVTV_REG_OFFSET */ | |
269 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) | |
270 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) | |
271 | #define IVTV_REG_SPU (0x9050) | |
272 | #define IVTV_REG_HW_BLOCKS (0x9054) | |
273 | #define IVTV_REG_VPU (0x9058) | |
274 | #define IVTV_REG_APU (0xA064) | |
275 | ||
955e6ed8 MCC |
276 | /* |
277 | * Bit definitions for MC417_RWD and MC417_OEN registers | |
278 | * | |
279 | * bits 31-16 | |
280 | *+-----------+ | |
281 | *| Reserved | | |
282 | *|+-----------+ | |
283 | *| bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 | |
284 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
285 | *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| | |
286 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
287 | *| bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 | |
288 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
289 | *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| | |
290 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
291 | */ | |
64fbf444 PB |
292 | #define MC417_MIWR 0x8000 |
293 | #define MC417_MIRD 0x4000 | |
294 | #define MC417_MICS 0x2000 | |
295 | #define MC417_MIRDY 0x1000 | |
296 | #define MC417_MIADDR 0x0F00 | |
297 | #define MC417_MIDATA 0x00FF | |
298 | ||
299 | ||
955e6ed8 MCC |
300 | /* Bit definitions for MC417_CTL register **** |
301 | *bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 | |
302 | *+--------+-------------+--------+--------------+------------+ | |
303 | *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| | |
304 | *+--------+-------------+--------+--------------+------------+ | |
305 | */ | |
64fbf444 PB |
306 | #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) |
307 | #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) | |
308 | #define MC417_UART_GPIO_EN 0x00000001 | |
309 | ||
310 | /* Values for speed control */ | |
311 | #define MC417_SPD_CTL_SLOW 0x1 | |
312 | #define MC417_SPD_CTL_MEDIUM 0x0 | |
313 | #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */ | |
314 | ||
315 | /* Values for GPIO select */ | |
316 | #define MC417_GPIO_SEL_GPIO3 0x3 | |
317 | #define MC417_GPIO_SEL_GPIO2 0x2 | |
318 | #define MC417_GPIO_SEL_GPIO1 0x1 | |
319 | #define MC417_GPIO_SEL_GPIO0 0x0 | |
320 | ||
321 | ||
322 | #define CX23417_GPIO_MASK 0xFC0003FF | |
5b8acdc5 HV |
323 | |
324 | static int set_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 value) | |
64fbf444 PB |
325 | { |
326 | int status = 0; | |
327 | u32 _gpio_direction = 0; | |
328 | ||
329 | _gpio_direction = _gpio_direction & CX23417_GPIO_MASK; | |
5b8acdc5 | 330 | _gpio_direction = _gpio_direction | gpio_direction; |
64fbf444 PB |
331 | status = cx231xx_send_gpio_cmd(dev, _gpio_direction, |
332 | (u8 *)&value, 4, 0, 0); | |
333 | return status; | |
334 | } | |
5b8acdc5 HV |
335 | |
336 | static int get_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 *val_ptr) | |
64fbf444 PB |
337 | { |
338 | int status = 0; | |
339 | u32 _gpio_direction = 0; | |
340 | ||
341 | _gpio_direction = _gpio_direction & CX23417_GPIO_MASK; | |
5b8acdc5 | 342 | _gpio_direction = _gpio_direction | gpio_direction; |
64fbf444 PB |
343 | |
344 | status = cx231xx_send_gpio_cmd(dev, _gpio_direction, | |
5b8acdc5 | 345 | (u8 *)val_ptr, 4, 0, 1); |
64fbf444 PB |
346 | return status; |
347 | } | |
82c3ccaa | 348 | |
5b8acdc5 | 349 | static int wait_for_mci_complete(struct cx231xx *dev) |
64fbf444 | 350 | { |
955e6ed8 | 351 | u32 gpio; |
5b8acdc5 | 352 | u32 gpio_direction = 0; |
955e6ed8 | 353 | u8 count = 0; |
5b8acdc5 | 354 | get_itvc_reg(dev, gpio_direction, &gpio); |
64fbf444 | 355 | |
955e6ed8 MCC |
356 | while (!(gpio&0x020000)) { |
357 | msleep(10); | |
64fbf444 | 358 | |
5b8acdc5 | 359 | get_itvc_reg(dev, gpio_direction, &gpio); |
64fbf444 | 360 | |
955e6ed8 MCC |
361 | if (count++ > 100) { |
362 | dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio); | |
363 | return -1; | |
364 | } | |
64fbf444 | 365 | } |
64fbf444 PB |
366 | return 0; |
367 | } | |
955e6ed8 | 368 | |
82c3ccaa | 369 | static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value) |
64fbf444 | 370 | { |
955e6ed8 | 371 | u32 temp; |
64fbf444 PB |
372 | int status = 0; |
373 | ||
5b8acdc5 HV |
374 | temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8); |
375 | temp = temp << 10; | |
376 | status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
64fbf444 PB |
377 | if (status < 0) |
378 | return status; | |
5b8acdc5 HV |
379 | temp = temp | (0x05 << 10); |
380 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
381 | |
382 | /*write data byte 1;*/ | |
5b8acdc5 HV |
383 | temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00); |
384 | temp = temp << 10; | |
385 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
386 | temp = temp | (0x05 << 10); | |
387 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
388 | |
389 | /*write data byte 2;*/ | |
5b8acdc5 HV |
390 | temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8); |
391 | temp = temp << 10; | |
392 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
393 | temp = temp | (0x05 << 10); | |
394 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
395 | |
396 | /*write data byte 3;*/ | |
5b8acdc5 HV |
397 | temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16); |
398 | temp = temp << 10; | |
399 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
400 | temp = temp | (0x05 << 10); | |
401 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
402 | |
403 | /*write address byte 0;*/ | |
5b8acdc5 HV |
404 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8); |
405 | temp = temp << 10; | |
406 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
407 | temp = temp | (0x05 << 10); | |
408 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
409 | |
410 | /*write address byte 1;*/ | |
5b8acdc5 HV |
411 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00); |
412 | temp = temp << 10; | |
413 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
414 | temp = temp | (0x05 << 10); | |
415 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
416 | |
417 | /*Write that the mode is write.*/ | |
418 | temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE; | |
5b8acdc5 HV |
419 | temp = temp << 10; |
420 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
421 | temp = temp | (0x05 << 10); | |
422 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 | 423 | |
5b8acdc5 | 424 | return wait_for_mci_complete(dev); |
64fbf444 PB |
425 | } |
426 | ||
82c3ccaa | 427 | static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value) |
64fbf444 | 428 | { |
955e6ed8 MCC |
429 | /*write address byte 0;*/ |
430 | u32 temp; | |
431 | u32 return_value = 0; | |
64fbf444 PB |
432 | int ret = 0; |
433 | ||
955e6ed8 MCC |
434 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
435 | temp = temp << 10; | |
5b8acdc5 | 436 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 | 437 | temp = temp | ((0x05) << 10); |
5b8acdc5 | 438 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 MCC |
439 | |
440 | /*write address byte 1;*/ | |
441 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00); | |
442 | temp = temp << 10; | |
5b8acdc5 | 443 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 | 444 | temp = temp | ((0x05) << 10); |
5b8acdc5 | 445 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 MCC |
446 | |
447 | /*write that the mode is read;*/ | |
448 | temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ; | |
449 | temp = temp << 10; | |
5b8acdc5 | 450 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 | 451 | temp = temp | ((0x05) << 10); |
5b8acdc5 | 452 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 MCC |
453 | |
454 | /*wait for the MIRDY line to be asserted , | |
455 | signalling that the read is done;*/ | |
5b8acdc5 | 456 | ret = wait_for_mci_complete(dev); |
955e6ed8 MCC |
457 | |
458 | /*switch the DATA- GPIO to input mode;*/ | |
459 | ||
460 | /*Read data byte 0;*/ | |
461 | temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10; | |
5b8acdc5 | 462 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 463 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10); |
5b8acdc5 HV |
464 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
465 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 | 466 | return_value |= ((temp & 0x03FC0000) >> 18); |
5b8acdc5 | 467 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
955e6ed8 MCC |
468 | |
469 | /* Read data byte 1;*/ | |
470 | temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10; | |
5b8acdc5 | 471 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 472 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10); |
5b8acdc5 HV |
473 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
474 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 MCC |
475 | |
476 | return_value |= ((temp & 0x03FC0000) >> 10); | |
5b8acdc5 | 477 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
955e6ed8 MCC |
478 | |
479 | /*Read data byte 2;*/ | |
480 | temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10; | |
5b8acdc5 | 481 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 482 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10); |
5b8acdc5 HV |
483 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
484 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 | 485 | return_value |= ((temp & 0x03FC0000) >> 2); |
5b8acdc5 | 486 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
955e6ed8 MCC |
487 | |
488 | /*Read data byte 3;*/ | |
489 | temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10; | |
5b8acdc5 | 490 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 491 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10); |
5b8acdc5 HV |
492 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
493 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 | 494 | return_value |= ((temp & 0x03FC0000) << 6); |
5b8acdc5 | 495 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
64fbf444 PB |
496 | |
497 | *value = return_value; | |
955e6ed8 | 498 | return ret; |
64fbf444 PB |
499 | } |
500 | ||
82c3ccaa | 501 | static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value) |
64fbf444 | 502 | { |
955e6ed8 | 503 | /*write data byte 0;*/ |
64fbf444 | 504 | |
955e6ed8 | 505 | u32 temp; |
64fbf444 PB |
506 | int ret = 0; |
507 | ||
5b8acdc5 | 508 | temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8); |
955e6ed8 | 509 | temp = temp << 10; |
5b8acdc5 | 510 | ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
64fbf444 PB |
511 | if (ret < 0) |
512 | return ret; | |
5b8acdc5 HV |
513 | temp = temp | (0x05 << 10); |
514 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
515 | |
516 | /*write data byte 1;*/ | |
517 | temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00); | |
518 | temp = temp << 10; | |
5b8acdc5 HV |
519 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
520 | temp = temp | (0x05 << 10); | |
521 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
522 | |
523 | /*write data byte 2;*/ | |
5b8acdc5 HV |
524 | temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8); |
525 | temp = temp << 10; | |
526 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
527 | temp = temp | (0x05 << 10); | |
528 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
529 | |
530 | /*write data byte 3;*/ | |
5b8acdc5 HV |
531 | temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16); |
532 | temp = temp << 10; | |
533 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
534 | temp = temp | (0x05 << 10); | |
535 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
536 | |
537 | /* write address byte 2;*/ | |
5b8acdc5 HV |
538 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | |
539 | ((address & 0x003F0000) >> 8); | |
540 | temp = temp << 10; | |
541 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
542 | temp = temp | (0x05 << 10); | |
543 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
544 | |
545 | /* write address byte 1;*/ | |
5b8acdc5 HV |
546 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
547 | temp = temp << 10; | |
548 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
549 | temp = temp | (0x05 << 10); | |
550 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
551 | |
552 | /* write address byte 0;*/ | |
5b8acdc5 HV |
553 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
554 | temp = temp << 10; | |
555 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
556 | temp = temp | (0x05 << 10); | |
557 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
558 | |
559 | /*wait for MIRDY line;*/ | |
5b8acdc5 | 560 | wait_for_mci_complete(dev); |
64fbf444 | 561 | |
955e6ed8 | 562 | return 0; |
64fbf444 PB |
563 | } |
564 | ||
82c3ccaa | 565 | static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value) |
64fbf444 | 566 | { |
955e6ed8 MCC |
567 | u32 temp = 0; |
568 | u32 return_value = 0; | |
64fbf444 PB |
569 | int ret = 0; |
570 | ||
955e6ed8 | 571 | /*write address byte 2;*/ |
5b8acdc5 HV |
572 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ | |
573 | ((address & 0x003F0000) >> 8); | |
574 | temp = temp << 10; | |
575 | ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
64fbf444 PB |
576 | if (ret < 0) |
577 | return ret; | |
5b8acdc5 HV |
578 | temp = temp | (0x05 << 10); |
579 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
580 | |
581 | /*write address byte 1*/ | |
5b8acdc5 HV |
582 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
583 | temp = temp << 10; | |
584 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
585 | temp = temp | (0x05 << 10); | |
586 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
587 | |
588 | /*write address byte 0*/ | |
5b8acdc5 HV |
589 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
590 | temp = temp << 10; | |
591 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
592 | temp = temp | (0x05 << 10); | |
593 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
594 | |
595 | /*Wait for MIRDY line*/ | |
5b8acdc5 | 596 | ret = wait_for_mci_complete(dev); |
955e6ed8 MCC |
597 | |
598 | ||
599 | /*Read data byte 3;*/ | |
5b8acdc5 HV |
600 | temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10; |
601 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
602 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10); | |
603 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
604 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
605 | return_value |= ((temp & 0x03FC0000) << 6); | |
606 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
955e6ed8 MCC |
607 | |
608 | /*Read data byte 2;*/ | |
5b8acdc5 HV |
609 | temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10; |
610 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
611 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10); | |
612 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
613 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
614 | return_value |= ((temp & 0x03FC0000) >> 2); | |
615 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
955e6ed8 MCC |
616 | |
617 | /* Read data byte 1;*/ | |
5b8acdc5 HV |
618 | temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10; |
619 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
620 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10); | |
621 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
622 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
623 | return_value |= ((temp & 0x03FC0000) >> 10); | |
624 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
955e6ed8 MCC |
625 | |
626 | /*Read data byte 0;*/ | |
5b8acdc5 HV |
627 | temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10; |
628 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
629 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10); | |
630 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
631 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
632 | return_value |= ((temp & 0x03FC0000) >> 18); | |
633 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
64fbf444 PB |
634 | |
635 | *value = return_value; | |
955e6ed8 | 636 | return ret; |
64fbf444 PB |
637 | } |
638 | ||
64fbf444 PB |
639 | /* ------------------------------------------------------------------ */ |
640 | ||
641 | /* MPEG encoder API */ | |
642 | static char *cmd_to_str(int cmd) | |
643 | { | |
644 | switch (cmd) { | |
645 | case CX2341X_ENC_PING_FW: | |
5b8acdc5 | 646 | return "PING_FW"; |
64fbf444 | 647 | case CX2341X_ENC_START_CAPTURE: |
5b8acdc5 | 648 | return "START_CAPTURE"; |
64fbf444 | 649 | case CX2341X_ENC_STOP_CAPTURE: |
5b8acdc5 | 650 | return "STOP_CAPTURE"; |
64fbf444 | 651 | case CX2341X_ENC_SET_AUDIO_ID: |
5b8acdc5 | 652 | return "SET_AUDIO_ID"; |
64fbf444 | 653 | case CX2341X_ENC_SET_VIDEO_ID: |
5b8acdc5 | 654 | return "SET_VIDEO_ID"; |
64fbf444 | 655 | case CX2341X_ENC_SET_PCR_ID: |
5b8acdc5 | 656 | return "SET_PCR_PID"; |
64fbf444 | 657 | case CX2341X_ENC_SET_FRAME_RATE: |
5b8acdc5 | 658 | return "SET_FRAME_RATE"; |
64fbf444 | 659 | case CX2341X_ENC_SET_FRAME_SIZE: |
5b8acdc5 | 660 | return "SET_FRAME_SIZE"; |
64fbf444 | 661 | case CX2341X_ENC_SET_BIT_RATE: |
5b8acdc5 | 662 | return "SET_BIT_RATE"; |
64fbf444 | 663 | case CX2341X_ENC_SET_GOP_PROPERTIES: |
5b8acdc5 | 664 | return "SET_GOP_PROPERTIES"; |
64fbf444 | 665 | case CX2341X_ENC_SET_ASPECT_RATIO: |
5b8acdc5 | 666 | return "SET_ASPECT_RATIO"; |
64fbf444 | 667 | case CX2341X_ENC_SET_DNR_FILTER_MODE: |
5b8acdc5 | 668 | return "SET_DNR_FILTER_PROPS"; |
64fbf444 | 669 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: |
5b8acdc5 | 670 | return "SET_DNR_FILTER_PROPS"; |
64fbf444 | 671 | case CX2341X_ENC_SET_CORING_LEVELS: |
5b8acdc5 | 672 | return "SET_CORING_LEVELS"; |
64fbf444 | 673 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: |
5b8acdc5 | 674 | return "SET_SPATIAL_FILTER_TYPE"; |
64fbf444 | 675 | case CX2341X_ENC_SET_VBI_LINE: |
5b8acdc5 | 676 | return "SET_VBI_LINE"; |
64fbf444 | 677 | case CX2341X_ENC_SET_STREAM_TYPE: |
5b8acdc5 | 678 | return "SET_STREAM_TYPE"; |
64fbf444 | 679 | case CX2341X_ENC_SET_OUTPUT_PORT: |
5b8acdc5 | 680 | return "SET_OUTPUT_PORT"; |
64fbf444 | 681 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: |
5b8acdc5 | 682 | return "SET_AUDIO_PROPERTIES"; |
64fbf444 | 683 | case CX2341X_ENC_HALT_FW: |
5b8acdc5 | 684 | return "HALT_FW"; |
64fbf444 | 685 | case CX2341X_ENC_GET_VERSION: |
5b8acdc5 | 686 | return "GET_VERSION"; |
64fbf444 | 687 | case CX2341X_ENC_SET_GOP_CLOSURE: |
5b8acdc5 | 688 | return "SET_GOP_CLOSURE"; |
64fbf444 | 689 | case CX2341X_ENC_GET_SEQ_END: |
5b8acdc5 | 690 | return "GET_SEQ_END"; |
64fbf444 | 691 | case CX2341X_ENC_SET_PGM_INDEX_INFO: |
5b8acdc5 | 692 | return "SET_PGM_INDEX_INFO"; |
64fbf444 | 693 | case CX2341X_ENC_SET_VBI_CONFIG: |
5b8acdc5 | 694 | return "SET_VBI_CONFIG"; |
64fbf444 | 695 | case CX2341X_ENC_SET_DMA_BLOCK_SIZE: |
5b8acdc5 | 696 | return "SET_DMA_BLOCK_SIZE"; |
64fbf444 | 697 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10: |
5b8acdc5 | 698 | return "GET_PREV_DMA_INFO_MB_10"; |
64fbf444 | 699 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9: |
5b8acdc5 | 700 | return "GET_PREV_DMA_INFO_MB_9"; |
64fbf444 | 701 | case CX2341X_ENC_SCHED_DMA_TO_HOST: |
5b8acdc5 | 702 | return "SCHED_DMA_TO_HOST"; |
64fbf444 | 703 | case CX2341X_ENC_INITIALIZE_INPUT: |
5b8acdc5 | 704 | return "INITIALIZE_INPUT"; |
64fbf444 | 705 | case CX2341X_ENC_SET_FRAME_DROP_RATE: |
5b8acdc5 | 706 | return "SET_FRAME_DROP_RATE"; |
64fbf444 | 707 | case CX2341X_ENC_PAUSE_ENCODER: |
5b8acdc5 | 708 | return "PAUSE_ENCODER"; |
64fbf444 | 709 | case CX2341X_ENC_REFRESH_INPUT: |
5b8acdc5 | 710 | return "REFRESH_INPUT"; |
64fbf444 | 711 | case CX2341X_ENC_SET_COPYRIGHT: |
5b8acdc5 | 712 | return "SET_COPYRIGHT"; |
64fbf444 | 713 | case CX2341X_ENC_SET_EVENT_NOTIFICATION: |
5b8acdc5 | 714 | return "SET_EVENT_NOTIFICATION"; |
64fbf444 | 715 | case CX2341X_ENC_SET_NUM_VSYNC_LINES: |
5b8acdc5 | 716 | return "SET_NUM_VSYNC_LINES"; |
64fbf444 | 717 | case CX2341X_ENC_SET_PLACEHOLDER: |
5b8acdc5 | 718 | return "SET_PLACEHOLDER"; |
64fbf444 | 719 | case CX2341X_ENC_MUTE_VIDEO: |
5b8acdc5 | 720 | return "MUTE_VIDEO"; |
64fbf444 | 721 | case CX2341X_ENC_MUTE_AUDIO: |
5b8acdc5 | 722 | return "MUTE_AUDIO"; |
64fbf444 | 723 | case CX2341X_ENC_MISC: |
5b8acdc5 | 724 | return "MISC"; |
64fbf444 PB |
725 | default: |
726 | return "UNKNOWN"; | |
727 | } | |
728 | } | |
729 | ||
5b8acdc5 | 730 | static int cx231xx_mbox_func(void *priv, u32 command, int in, int out, |
64fbf444 PB |
731 | u32 data[CX2341X_MBOX_MAX_DATA]) |
732 | { | |
733 | struct cx231xx *dev = priv; | |
734 | unsigned long timeout; | |
735 | u32 value, flag, retval = 0; | |
736 | int i; | |
737 | ||
738 | dprintk(3, "%s: command(0x%X) = %s\n", __func__, command, | |
739 | cmd_to_str(command)); | |
740 | ||
741 | /* this may not be 100% safe if we can't read any memory location | |
742 | without side effects */ | |
743 | mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); | |
744 | if (value != 0x12345678) { | |
5b8acdc5 HV |
745 | dprintk(3, "Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n", |
746 | value, cmd_to_str(command)); | |
88b6ffed | 747 | return -EIO; |
64fbf444 PB |
748 | } |
749 | ||
750 | /* This read looks at 32 bits, but flag is only 8 bits. | |
751 | * Seems we also bail if CMD or TIMEOUT bytes are set??? | |
752 | */ | |
753 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
754 | if (flag) { | |
5b8acdc5 HV |
755 | dprintk(3, "ERROR: Mailbox appears to be in use (%x), cmd = %s\n", |
756 | flag, cmd_to_str(command)); | |
88b6ffed | 757 | return -EBUSY; |
64fbf444 PB |
758 | } |
759 | ||
760 | flag |= 1; /* tell 'em we're working on it */ | |
761 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
762 | ||
763 | /* write command + args + fill remaining with zeros */ | |
764 | /* command code */ | |
765 | mc417_memory_write(dev, dev->cx23417_mailbox + 1, command); | |
766 | mc417_memory_write(dev, dev->cx23417_mailbox + 3, | |
767 | IVTV_API_STD_TIMEOUT); /* timeout */ | |
768 | for (i = 0; i < in; i++) { | |
769 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]); | |
770 | dprintk(3, "API Input %d = %d\n", i, data[i]); | |
771 | } | |
772 | for (; i < CX2341X_MBOX_MAX_DATA; i++) | |
773 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0); | |
774 | ||
775 | flag |= 3; /* tell 'em we're done writing */ | |
776 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
777 | ||
778 | /* wait for firmware to handle the API command */ | |
779 | timeout = jiffies + msecs_to_jiffies(10); | |
780 | for (;;) { | |
781 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
782 | if (0 != (flag & 4)) | |
783 | break; | |
784 | if (time_after(jiffies, timeout)) { | |
785 | dprintk(3, "ERROR: API Mailbox timeout\n"); | |
88b6ffed | 786 | return -EIO; |
64fbf444 PB |
787 | } |
788 | udelay(10); | |
789 | } | |
790 | ||
791 | /* read output values */ | |
792 | for (i = 0; i < out; i++) { | |
793 | mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i); | |
794 | dprintk(3, "API Output %d = %d\n", i, data[i]); | |
795 | } | |
796 | ||
797 | mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval); | |
798 | dprintk(3, "API result = %d\n", retval); | |
799 | ||
800 | flag = 0; | |
801 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
802 | ||
88b6ffed | 803 | return 0; |
64fbf444 PB |
804 | } |
805 | ||
806 | /* We don't need to call the API often, so using just one | |
807 | * mailbox will probably suffice | |
808 | */ | |
5b8acdc5 HV |
809 | static int cx231xx_api_cmd(struct cx231xx *dev, u32 command, |
810 | u32 inputcnt, u32 outputcnt, ...) | |
64fbf444 PB |
811 | { |
812 | u32 data[CX2341X_MBOX_MAX_DATA]; | |
813 | va_list vargs; | |
814 | int i, err; | |
815 | ||
816 | dprintk(3, "%s() cmds = 0x%08x\n", __func__, command); | |
817 | ||
818 | va_start(vargs, outputcnt); | |
819 | for (i = 0; i < inputcnt; i++) | |
820 | data[i] = va_arg(vargs, int); | |
821 | ||
822 | err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data); | |
823 | for (i = 0; i < outputcnt; i++) { | |
824 | int *vptr = va_arg(vargs, int *); | |
825 | *vptr = data[i]; | |
826 | } | |
827 | va_end(vargs); | |
828 | ||
829 | return err; | |
830 | } | |
831 | ||
88b6ffed | 832 | |
64fbf444 PB |
833 | static int cx231xx_find_mailbox(struct cx231xx *dev) |
834 | { | |
835 | u32 signature[4] = { | |
836 | 0x12345678, 0x34567812, 0x56781234, 0x78123456 | |
837 | }; | |
838 | int signaturecnt = 0; | |
839 | u32 value; | |
840 | int i; | |
841 | int ret = 0; | |
842 | ||
843 | dprintk(2, "%s()\n", __func__); | |
844 | ||
845 | for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/ | |
846 | ret = mc417_memory_read(dev, i, &value); | |
847 | if (ret < 0) | |
848 | return ret; | |
849 | if (value == signature[signaturecnt]) | |
850 | signaturecnt++; | |
851 | else | |
852 | signaturecnt = 0; | |
853 | if (4 == signaturecnt) { | |
5b8acdc5 HV |
854 | dprintk(1, "Mailbox signature found at 0x%x\n", i + 1); |
855 | return i + 1; | |
64fbf444 PB |
856 | } |
857 | } | |
858 | dprintk(3, "Mailbox signature values not found!\n"); | |
859 | return -1; | |
860 | } | |
82c3ccaa | 861 | |
5b8acdc5 | 862 | static void mci_write_memory_to_gpio(struct cx231xx *dev, u32 address, u32 value, |
64fbf444 PB |
863 | u32 *p_fw_image) |
864 | { | |
64fbf444 PB |
865 | u32 temp = 0; |
866 | int i = 0; | |
867 | ||
5b8acdc5 HV |
868 | temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8); |
869 | temp = temp << 10; | |
955e6ed8 MCC |
870 | *p_fw_image = temp; |
871 | p_fw_image++; | |
5b8acdc5 | 872 | temp = temp | (0x05 << 10); |
955e6ed8 | 873 | *p_fw_image = temp; |
64fbf444 | 874 | p_fw_image++; |
64fbf444 | 875 | |
955e6ed8 | 876 | /*write data byte 1;*/ |
5b8acdc5 HV |
877 | temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00); |
878 | temp = temp << 10; | |
955e6ed8 MCC |
879 | *p_fw_image = temp; |
880 | p_fw_image++; | |
5b8acdc5 | 881 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
882 | *p_fw_image = temp; |
883 | p_fw_image++; | |
884 | ||
885 | /*write data byte 2;*/ | |
5b8acdc5 HV |
886 | temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8); |
887 | temp = temp << 10; | |
955e6ed8 MCC |
888 | *p_fw_image = temp; |
889 | p_fw_image++; | |
5b8acdc5 | 890 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
891 | *p_fw_image = temp; |
892 | p_fw_image++; | |
893 | ||
894 | /*write data byte 3;*/ | |
5b8acdc5 HV |
895 | temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16); |
896 | temp = temp << 10; | |
955e6ed8 MCC |
897 | *p_fw_image = temp; |
898 | p_fw_image++; | |
5b8acdc5 | 899 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
900 | *p_fw_image = temp; |
901 | p_fw_image++; | |
902 | ||
903 | /* write address byte 2;*/ | |
5b8acdc5 HV |
904 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | |
905 | ((address & 0x003F0000) >> 8); | |
906 | temp = temp << 10; | |
955e6ed8 MCC |
907 | *p_fw_image = temp; |
908 | p_fw_image++; | |
5b8acdc5 | 909 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
910 | *p_fw_image = temp; |
911 | p_fw_image++; | |
912 | ||
913 | /* write address byte 1;*/ | |
5b8acdc5 HV |
914 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
915 | temp = temp << 10; | |
955e6ed8 MCC |
916 | *p_fw_image = temp; |
917 | p_fw_image++; | |
5b8acdc5 | 918 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
919 | *p_fw_image = temp; |
920 | p_fw_image++; | |
921 | ||
922 | /* write address byte 0;*/ | |
5b8acdc5 HV |
923 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
924 | temp = temp << 10; | |
955e6ed8 MCC |
925 | *p_fw_image = temp; |
926 | p_fw_image++; | |
5b8acdc5 | 927 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
928 | *p_fw_image = temp; |
929 | p_fw_image++; | |
930 | ||
931 | for (i = 0; i < 6; i++) { | |
932 | *p_fw_image = 0xFFFFFFFF; | |
933 | p_fw_image++; | |
934 | } | |
64fbf444 PB |
935 | } |
936 | ||
937 | ||
938 | static int cx231xx_load_firmware(struct cx231xx *dev) | |
939 | { | |
940 | static const unsigned char magic[8] = { | |
941 | 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa | |
942 | }; | |
943 | const struct firmware *firmware; | |
944 | int i, retval = 0; | |
945 | u32 value = 0; | |
946 | u32 gpio_output = 0; | |
947 | /*u32 checksum = 0;*/ | |
948 | /*u32 *dataptr;*/ | |
949 | u32 transfer_size = 0; | |
950 | u32 fw_data = 0; | |
951 | u32 address = 0; | |
952 | /*u32 current_fw[800];*/ | |
953 | u32 *p_current_fw, *p_fw; | |
954 | u32 *p_fw_data; | |
955 | int frame = 0; | |
956 | u16 _buffer_size = 4096; | |
957 | u8 *p_buffer; | |
958 | ||
9a9dcb4a | 959 | p_current_fw = vmalloc(1884180 * 4); |
64fbf444 | 960 | p_fw = p_current_fw; |
f72cfd85 | 961 | if (p_current_fw == NULL) { |
64fbf444 PB |
962 | dprintk(2, "FAIL!!!\n"); |
963 | return -1; | |
964 | } | |
965 | ||
9a9dcb4a | 966 | p_buffer = vmalloc(4096); |
f72cfd85 | 967 | if (p_buffer == NULL) { |
64fbf444 PB |
968 | dprintk(2, "FAIL!!!\n"); |
969 | return -1; | |
970 | } | |
971 | ||
972 | dprintk(2, "%s()\n", __func__); | |
973 | ||
974 | /* Save GPIO settings before reset of APU */ | |
975 | retval |= mc417_memory_read(dev, 0x9020, &gpio_output); | |
976 | retval |= mc417_memory_read(dev, 0x900C, &value); | |
977 | ||
978 | retval = mc417_register_write(dev, | |
979 | IVTV_REG_VPU, 0xFFFFFFED); | |
980 | retval |= mc417_register_write(dev, | |
981 | IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST); | |
982 | retval |= mc417_register_write(dev, | |
983 | IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800); | |
984 | retval |= mc417_register_write(dev, | |
985 | IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A); | |
986 | retval |= mc417_register_write(dev, | |
987 | IVTV_REG_APU, 0); | |
988 | ||
989 | if (retval != 0) { | |
336fea92 | 990 | dev_err(dev->dev, |
b7085c08 | 991 | "%s: Error with mc417_register_write\n", __func__); |
64fbf444 PB |
992 | return -1; |
993 | } | |
994 | ||
995 | retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME, | |
336fea92 | 996 | dev->dev); |
64fbf444 PB |
997 | |
998 | if (retval != 0) { | |
336fea92 | 999 | dev_err(dev->dev, |
b7085c08 | 1000 | "ERROR: Hotplug firmware request failed (%s).\n", |
64fbf444 | 1001 | CX231xx_FIRM_IMAGE_NAME); |
336fea92 | 1002 | dev_err(dev->dev, |
b7085c08 | 1003 | "Please fix your hotplug setup, the board will not work without firmware loaded!\n"); |
64fbf444 PB |
1004 | return -1; |
1005 | } | |
1006 | ||
1007 | if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) { | |
336fea92 | 1008 | dev_err(dev->dev, |
b7085c08 | 1009 | "ERROR: Firmware size mismatch (have %zd, expected %d)\n", |
64fbf444 PB |
1010 | firmware->size, CX231xx_FIRM_IMAGE_SIZE); |
1011 | release_firmware(firmware); | |
1012 | return -1; | |
1013 | } | |
1014 | ||
1015 | if (0 != memcmp(firmware->data, magic, 8)) { | |
336fea92 | 1016 | dev_err(dev->dev, |
b7085c08 | 1017 | "ERROR: Firmware magic mismatch, wrong file?\n"); |
64fbf444 PB |
1018 | release_firmware(firmware); |
1019 | return -1; | |
1020 | } | |
1021 | ||
1022 | initGPIO(dev); | |
1023 | ||
1024 | /* transfer to the chip */ | |
1025 | dprintk(2, "Loading firmware to GPIO...\n"); | |
1026 | p_fw_data = (u32 *)firmware->data; | |
62c78c96 | 1027 | dprintk(2, "firmware->size=%zd\n", firmware->size); |
64fbf444 PB |
1028 | for (transfer_size = 0; transfer_size < firmware->size; |
1029 | transfer_size += 4) { | |
1030 | fw_data = *p_fw_data; | |
1031 | ||
5b8acdc5 | 1032 | mci_write_memory_to_gpio(dev, address, fw_data, p_current_fw); |
64fbf444 PB |
1033 | address = address + 1; |
1034 | p_current_fw += 20; | |
1035 | p_fw_data += 1; | |
1036 | } | |
1037 | ||
955e6ed8 | 1038 | /*download the firmware by ep5-out*/ |
64fbf444 PB |
1039 | |
1040 | for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size); | |
bae94dc3 | 1041 | frame++) { |
64fbf444 | 1042 | for (i = 0; i < _buffer_size; i++) { |
bae94dc3 MCC |
1043 | *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF); |
1044 | i++; | |
1045 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8); | |
1046 | i++; | |
1047 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16); | |
1048 | i++; | |
1049 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24); | |
64fbf444 PB |
1050 | } |
1051 | cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size); | |
1052 | } | |
1053 | ||
1054 | p_current_fw = p_fw; | |
1055 | vfree(p_current_fw); | |
1056 | p_current_fw = NULL; | |
1057 | uninitGPIO(dev); | |
1058 | release_firmware(firmware); | |
1059 | dprintk(1, "Firmware upload successful.\n"); | |
1060 | ||
1061 | retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, | |
1062 | IVTV_CMD_HW_BLOCKS_RST); | |
1063 | if (retval < 0) { | |
336fea92 | 1064 | dev_err(dev->dev, |
b7085c08 | 1065 | "%s: Error with mc417_register_write\n", |
64fbf444 PB |
1066 | __func__); |
1067 | return retval; | |
1068 | } | |
1069 | /* F/W power up disturbs the GPIOs, restore state */ | |
1070 | retval |= mc417_register_write(dev, 0x9020, gpio_output); | |
1071 | retval |= mc417_register_write(dev, 0x900C, value); | |
1072 | ||
1073 | retval |= mc417_register_read(dev, IVTV_REG_VPU, &value); | |
1074 | retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); | |
1075 | ||
1076 | if (retval < 0) { | |
336fea92 | 1077 | dev_err(dev->dev, |
b7085c08 | 1078 | "%s: Error with mc417_register_write\n", |
64fbf444 PB |
1079 | __func__); |
1080 | return retval; | |
1081 | } | |
1082 | return 0; | |
1083 | } | |
1084 | ||
82c3ccaa | 1085 | static void cx231xx_417_check_encoder(struct cx231xx *dev) |
64fbf444 PB |
1086 | { |
1087 | u32 status, seq; | |
1088 | ||
1089 | status = 0; | |
1090 | seq = 0; | |
1091 | cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq); | |
1092 | dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq); | |
1093 | } | |
1094 | ||
1095 | static void cx231xx_codec_settings(struct cx231xx *dev) | |
1096 | { | |
1097 | dprintk(1, "%s()\n", __func__); | |
1098 | ||
1099 | /* assign frame size */ | |
1100 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0, | |
1101 | dev->ts1.height, dev->ts1.width); | |
1102 | ||
88b6ffed HV |
1103 | dev->mpeg_ctrl_handler.width = dev->ts1.width; |
1104 | dev->mpeg_ctrl_handler.height = dev->ts1.height; | |
64fbf444 | 1105 | |
88b6ffed | 1106 | cx2341x_handler_setup(&dev->mpeg_ctrl_handler); |
64fbf444 PB |
1107 | |
1108 | cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1); | |
1109 | cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1); | |
1110 | } | |
1111 | ||
1112 | static int cx231xx_initialize_codec(struct cx231xx *dev) | |
1113 | { | |
1114 | int version; | |
1115 | int retval; | |
da983503 | 1116 | u32 i; |
64fbf444 PB |
1117 | u32 val = 0; |
1118 | ||
1119 | dprintk(1, "%s()\n", __func__); | |
1120 | cx231xx_disable656(dev); | |
1121 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */ | |
1122 | if (retval < 0) { | |
ed0e3729 | 1123 | dprintk(2, "%s: PING OK\n", __func__); |
64fbf444 PB |
1124 | retval = cx231xx_load_firmware(dev); |
1125 | if (retval < 0) { | |
336fea92 | 1126 | dev_err(dev->dev, |
b7085c08 | 1127 | "%s: f/w load failed\n", __func__); |
64fbf444 PB |
1128 | return retval; |
1129 | } | |
1130 | retval = cx231xx_find_mailbox(dev); | |
1131 | if (retval < 0) { | |
336fea92 | 1132 | dev_err(dev->dev, "%s: mailbox < 0, error\n", |
64fbf444 PB |
1133 | __func__); |
1134 | return -1; | |
1135 | } | |
1136 | dev->cx23417_mailbox = retval; | |
1137 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); | |
1138 | if (retval < 0) { | |
336fea92 | 1139 | dev_err(dev->dev, |
b7085c08 | 1140 | "ERROR: cx23417 firmware ping failed!\n"); |
64fbf444 PB |
1141 | return -1; |
1142 | } | |
1143 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, | |
1144 | &version); | |
1145 | if (retval < 0) { | |
336fea92 | 1146 | dev_err(dev->dev, |
b7085c08 | 1147 | "ERROR: cx23417 firmware get encoder: version failed!\n"); |
64fbf444 PB |
1148 | return -1; |
1149 | } | |
1150 | dprintk(1, "cx23417 firmware version is 0x%08x\n", version); | |
1151 | msleep(200); | |
1152 | } | |
1153 | ||
1154 | for (i = 0; i < 1; i++) { | |
1155 | retval = mc417_register_read(dev, 0x20f8, &val); | |
5b8acdc5 | 1156 | dprintk(3, "***before enable656() VIM Capture Lines = %d ***\n", |
64fbf444 PB |
1157 | val); |
1158 | if (retval < 0) | |
1159 | return retval; | |
1160 | } | |
1161 | ||
1162 | cx231xx_enable656(dev); | |
69626853 MCC |
1163 | |
1164 | /* stop mpeg capture */ | |
1165 | cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, 1, 3, 4); | |
64fbf444 PB |
1166 | |
1167 | cx231xx_codec_settings(dev); | |
1168 | msleep(60); | |
1169 | ||
1170 | /* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0, | |
1171 | CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115); | |
1172 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0, | |
1173 | CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1174 | 0, 0); | |
1175 | */ | |
da983503 HV |
1176 | |
1177 | #if 0 | |
1178 | /* TODO */ | |
1179 | u32 data[7]; | |
1180 | ||
64fbf444 PB |
1181 | /* Setup to capture VBI */ |
1182 | data[0] = 0x0001BD00; | |
1183 | data[1] = 1; /* frames per interrupt */ | |
1184 | data[2] = 4; /* total bufs */ | |
1185 | data[3] = 0x91559155; /* start codes */ | |
1186 | data[4] = 0x206080C0; /* stop codes */ | |
1187 | data[5] = 6; /* lines */ | |
1188 | data[6] = 64; /* BPL */ | |
da983503 | 1189 | |
64fbf444 PB |
1190 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1], |
1191 | data[2], data[3], data[4], data[5], data[6]); | |
1192 | ||
1193 | for (i = 2; i <= 24; i++) { | |
1194 | int valid; | |
1195 | ||
1196 | valid = ((i >= 19) && (i <= 21)); | |
1197 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i, | |
1198 | valid, 0 , 0, 0); | |
1199 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, | |
1200 | i | 0x80000000, valid, 0, 0, 0); | |
1201 | } | |
da983503 | 1202 | #endif |
64fbf444 PB |
1203 | /* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE); |
1204 | msleep(60); | |
1205 | */ | |
1206 | /* initialize the video input */ | |
1207 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0); | |
1208 | if (retval < 0) | |
1209 | return retval; | |
1210 | msleep(60); | |
1211 | ||
1212 | /* Enable VIP style pixel invalidation so we work with scaled mode */ | |
1213 | mc417_memory_write(dev, 2120, 0x00000080); | |
1214 | ||
1215 | /* start capturing to the host interface */ | |
1216 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0, | |
1217 | CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE); | |
1218 | if (retval < 0) | |
1219 | return retval; | |
1220 | msleep(10); | |
1221 | ||
1222 | for (i = 0; i < 1; i++) { | |
1223 | mc417_register_read(dev, 0x20f8, &val); | |
5b8acdc5 | 1224 | dprintk(3, "***VIM Capture Lines =%d ***\n", val); |
64fbf444 PB |
1225 | } |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 | ||
1230 | /* ------------------------------------------------------------------ */ | |
1231 | ||
1232 | static int bb_buf_setup(struct videobuf_queue *q, | |
1233 | unsigned int *count, unsigned int *size) | |
1234 | { | |
1235 | struct cx231xx_fh *fh = q->priv_data; | |
1236 | ||
1237 | fh->dev->ts1.ts_packet_size = mpeglinesize; | |
1238 | fh->dev->ts1.ts_packet_count = mpeglines; | |
1239 | ||
1240 | *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; | |
1241 | *count = mpegbufs; | |
1242 | ||
1243 | return 0; | |
1244 | } | |
5aa95991 | 1245 | |
64fbf444 PB |
1246 | static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf) |
1247 | { | |
1248 | struct cx231xx_fh *fh = vq->priv_data; | |
1249 | struct cx231xx *dev = fh->dev; | |
1250 | unsigned long flags = 0; | |
1251 | ||
09f2082e | 1252 | BUG_ON(in_interrupt()); |
64fbf444 PB |
1253 | |
1254 | spin_lock_irqsave(&dev->video_mode.slock, flags); | |
1255 | if (dev->USE_ISO) { | |
1256 | if (dev->video_mode.isoc_ctl.buf == buf) | |
1257 | dev->video_mode.isoc_ctl.buf = NULL; | |
1258 | } else { | |
1259 | if (dev->video_mode.bulk_ctl.buf == buf) | |
1260 | dev->video_mode.bulk_ctl.buf = NULL; | |
1261 | } | |
1262 | spin_unlock_irqrestore(&dev->video_mode.slock, flags); | |
1263 | videobuf_waiton(vq, &buf->vb, 0, 0); | |
1264 | videobuf_vmalloc_free(&buf->vb); | |
1265 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
1266 | } | |
1267 | ||
82c3ccaa | 1268 | static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb, |
64fbf444 PB |
1269 | struct cx231xx_dmaqueue *dma_q) |
1270 | { | |
5b8acdc5 HV |
1271 | void *vbuf; |
1272 | struct cx231xx_buffer *buf; | |
1273 | u32 tail_data = 0; | |
1274 | char *p_data; | |
64fbf444 | 1275 | |
5b8acdc5 | 1276 | if (dma_q->mpeg_buffer_done == 0) { |
64fbf444 PB |
1277 | if (list_empty(&dma_q->active)) |
1278 | return; | |
1279 | ||
64fbf444 | 1280 | buf = list_entry(dma_q->active.next, |
5b8acdc5 HV |
1281 | struct cx231xx_buffer, vb.queue); |
1282 | dev->video_mode.isoc_ctl.buf = buf; | |
1283 | dma_q->mpeg_buffer_done = 1; | |
1284 | } | |
1285 | /* Fill buffer */ | |
1286 | buf = dev->video_mode.isoc_ctl.buf; | |
1287 | vbuf = videobuf_to_vmalloc(&buf->vb); | |
1288 | ||
1289 | if ((dma_q->mpeg_buffer_completed+len) < | |
1290 | mpeglines*mpeglinesize) { | |
1291 | if (dma_q->add_ps_package_head == | |
1292 | CX231XX_NEED_ADD_PS_PACKAGE_HEAD) { | |
1293 | memcpy(vbuf+dma_q->mpeg_buffer_completed, | |
1294 | dma_q->ps_head, 3); | |
1295 | dma_q->mpeg_buffer_completed = | |
1296 | dma_q->mpeg_buffer_completed + 3; | |
1297 | dma_q->add_ps_package_head = | |
1298 | CX231XX_NONEED_PS_PACKAGE_HEAD; | |
1299 | } | |
1300 | memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len); | |
1301 | dma_q->mpeg_buffer_completed = | |
1302 | dma_q->mpeg_buffer_completed + len; | |
1303 | } else { | |
1304 | dma_q->mpeg_buffer_done = 0; | |
64fbf444 | 1305 | |
5b8acdc5 HV |
1306 | tail_data = |
1307 | mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed; | |
1308 | memcpy(vbuf+dma_q->mpeg_buffer_completed, | |
1309 | data, tail_data); | |
64fbf444 | 1310 | |
64fbf444 PB |
1311 | buf->vb.state = VIDEOBUF_DONE; |
1312 | buf->vb.field_count++; | |
8e6057b5 | 1313 | v4l2_get_timestamp(&buf->vb.ts); |
64fbf444 PB |
1314 | list_del(&buf->vb.queue); |
1315 | wake_up(&buf->vb.done); | |
5b8acdc5 HV |
1316 | dma_q->mpeg_buffer_completed = 0; |
1317 | ||
1318 | if (len - tail_data > 0) { | |
1319 | p_data = data + tail_data; | |
1320 | dma_q->left_data_count = len - tail_data; | |
1321 | memcpy(dma_q->p_left_data, | |
1322 | p_data, len - tail_data); | |
1323 | } | |
1324 | } | |
1325 | } | |
64fbf444 | 1326 | |
5b8acdc5 HV |
1327 | static void buffer_filled(char *data, int len, struct urb *urb, |
1328 | struct cx231xx_dmaqueue *dma_q) | |
1329 | { | |
1330 | void *vbuf; | |
1331 | struct cx231xx_buffer *buf; | |
1332 | ||
1333 | if (list_empty(&dma_q->active)) | |
1334 | return; | |
1335 | ||
1336 | buf = list_entry(dma_q->active.next, | |
1337 | struct cx231xx_buffer, vb.queue); | |
1338 | ||
1339 | /* Fill buffer */ | |
1340 | vbuf = videobuf_to_vmalloc(&buf->vb); | |
1341 | memcpy(vbuf, data, len); | |
1342 | buf->vb.state = VIDEOBUF_DONE; | |
1343 | buf->vb.field_count++; | |
1344 | v4l2_get_timestamp(&buf->vb.ts); | |
1345 | list_del(&buf->vb.queue); | |
1346 | wake_up(&buf->vb.done); | |
64fbf444 | 1347 | } |
5b8acdc5 HV |
1348 | |
1349 | static int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb) | |
64fbf444 PB |
1350 | { |
1351 | struct cx231xx_dmaqueue *dma_q = urb->context; | |
1352 | unsigned char *p_buffer; | |
1353 | u32 buffer_size = 0; | |
1354 | u32 i = 0; | |
1355 | ||
1356 | for (i = 0; i < urb->number_of_packets; i++) { | |
1357 | if (dma_q->left_data_count > 0) { | |
1358 | buffer_copy(dev, dma_q->p_left_data, | |
1359 | dma_q->left_data_count, urb, dma_q); | |
1360 | dma_q->mpeg_buffer_completed = dma_q->left_data_count; | |
1361 | dma_q->left_data_count = 0; | |
1362 | } | |
1363 | ||
1364 | p_buffer = urb->transfer_buffer + | |
1365 | urb->iso_frame_desc[i].offset; | |
1366 | buffer_size = urb->iso_frame_desc[i].actual_length; | |
1367 | ||
1368 | if (buffer_size > 0) | |
1369 | buffer_copy(dev, p_buffer, buffer_size, urb, dma_q); | |
1370 | } | |
1371 | ||
1372 | return 0; | |
1373 | } | |
64fbf444 | 1374 | |
5b8acdc5 HV |
1375 | static int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb) |
1376 | { | |
64fbf444 PB |
1377 | struct cx231xx_dmaqueue *dma_q = urb->context; |
1378 | unsigned char *p_buffer, *buffer; | |
1379 | u32 buffer_size = 0; | |
1380 | ||
1381 | p_buffer = urb->transfer_buffer; | |
1382 | buffer_size = urb->actual_length; | |
1383 | ||
1384 | buffer = kmalloc(buffer_size, GFP_ATOMIC); | |
f8433226 IY |
1385 | if (!buffer) |
1386 | return -ENOMEM; | |
64fbf444 PB |
1387 | |
1388 | memcpy(buffer, dma_q->ps_head, 3); | |
1389 | memcpy(buffer+3, p_buffer, buffer_size-3); | |
1390 | memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3); | |
1391 | ||
1392 | p_buffer = buffer; | |
1393 | buffer_filled(p_buffer, buffer_size, urb, dma_q); | |
1394 | ||
1395 | kfree(buffer); | |
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | static int bb_buf_prepare(struct videobuf_queue *q, | |
1400 | struct videobuf_buffer *vb, enum v4l2_field field) | |
1401 | { | |
1402 | struct cx231xx_fh *fh = q->priv_data; | |
1403 | struct cx231xx_buffer *buf = | |
1404 | container_of(vb, struct cx231xx_buffer, vb); | |
1405 | struct cx231xx *dev = fh->dev; | |
1406 | int rc = 0, urb_init = 0; | |
1407 | int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; | |
1408 | ||
64fbf444 PB |
1409 | if (0 != buf->vb.baddr && buf->vb.bsize < size) |
1410 | return -EINVAL; | |
1411 | buf->vb.width = fh->dev->ts1.ts_packet_size; | |
1412 | buf->vb.height = fh->dev->ts1.ts_packet_count; | |
1413 | buf->vb.size = size; | |
1414 | buf->vb.field = field; | |
1415 | ||
1416 | if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { | |
1417 | rc = videobuf_iolock(q, &buf->vb, NULL); | |
1418 | if (rc < 0) | |
1419 | goto fail; | |
1420 | } | |
1421 | ||
1422 | if (dev->USE_ISO) { | |
1423 | if (!dev->video_mode.isoc_ctl.num_bufs) | |
1424 | urb_init = 1; | |
1425 | } else { | |
1426 | if (!dev->video_mode.bulk_ctl.num_bufs) | |
1427 | urb_init = 1; | |
1428 | } | |
336fea92 | 1429 | dev_dbg(dev->dev, |
b7085c08 MCC |
1430 | "urb_init=%d dev->video_mode.max_pkt_size=%d\n", |
1431 | urb_init, dev->video_mode.max_pkt_size); | |
64fbf444 PB |
1432 | dev->mode_tv = 1; |
1433 | ||
1434 | if (urb_init) { | |
1435 | rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); | |
1436 | rc = cx231xx_unmute_audio(dev); | |
1437 | if (dev->USE_ISO) { | |
1438 | cx231xx_set_alt_setting(dev, INDEX_TS1, 4); | |
1439 | rc = cx231xx_init_isoc(dev, mpeglines, | |
1440 | mpegbufs, | |
1441 | dev->ts1_mode.max_pkt_size, | |
1442 | cx231xx_isoc_copy); | |
1443 | } else { | |
1444 | cx231xx_set_alt_setting(dev, INDEX_TS1, 0); | |
1445 | rc = cx231xx_init_bulk(dev, mpeglines, | |
1446 | mpegbufs, | |
1447 | dev->ts1_mode.max_pkt_size, | |
1448 | cx231xx_bulk_copy); | |
1449 | } | |
1450 | if (rc < 0) | |
1451 | goto fail; | |
1452 | } | |
1453 | ||
1454 | buf->vb.state = VIDEOBUF_PREPARED; | |
1455 | return 0; | |
1456 | ||
1457 | fail: | |
1458 | free_buffer(q, buf); | |
1459 | return rc; | |
1460 | } | |
1461 | ||
1462 | static void bb_buf_queue(struct videobuf_queue *q, | |
1463 | struct videobuf_buffer *vb) | |
1464 | { | |
1465 | struct cx231xx_fh *fh = q->priv_data; | |
1466 | ||
1467 | struct cx231xx_buffer *buf = | |
1468 | container_of(vb, struct cx231xx_buffer, vb); | |
1469 | struct cx231xx *dev = fh->dev; | |
1470 | struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq; | |
1471 | ||
1472 | buf->vb.state = VIDEOBUF_QUEUED; | |
1473 | list_add_tail(&buf->vb.queue, &vidq->active); | |
1474 | ||
1475 | } | |
1476 | ||
1477 | static void bb_buf_release(struct videobuf_queue *q, | |
1478 | struct videobuf_buffer *vb) | |
1479 | { | |
1480 | struct cx231xx_buffer *buf = | |
1481 | container_of(vb, struct cx231xx_buffer, vb); | |
1482 | /*struct cx231xx_fh *fh = q->priv_data;*/ | |
1483 | /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/ | |
1484 | ||
1485 | free_buffer(q, buf); | |
1486 | } | |
1487 | ||
1488 | static struct videobuf_queue_ops cx231xx_qops = { | |
1489 | .buf_setup = bb_buf_setup, | |
1490 | .buf_prepare = bb_buf_prepare, | |
1491 | .buf_queue = bb_buf_queue, | |
1492 | .buf_release = bb_buf_release, | |
1493 | }; | |
1494 | ||
1495 | /* ------------------------------------------------------------------ */ | |
1496 | ||
e25cb200 HV |
1497 | static int vidioc_cropcap(struct file *file, void *priv, |
1498 | struct v4l2_cropcap *cc) | |
1499 | { | |
1500 | struct cx231xx_fh *fh = priv; | |
1501 | struct cx231xx *dev = fh->dev; | |
1502 | bool is_50hz = dev->encodernorm.id & V4L2_STD_625_50; | |
1503 | ||
1504 | if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1505 | return -EINVAL; | |
1506 | ||
1507 | cc->bounds.left = 0; | |
1508 | cc->bounds.top = 0; | |
1509 | cc->bounds.width = dev->ts1.width; | |
1510 | cc->bounds.height = dev->ts1.height; | |
1511 | cc->defrect = cc->bounds; | |
1512 | cc->pixelaspect.numerator = is_50hz ? 54 : 11; | |
1513 | cc->pixelaspect.denominator = is_50hz ? 59 : 10; | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
64fbf444 PB |
1518 | static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm) |
1519 | { | |
1520 | struct cx231xx_fh *fh = file->private_data; | |
1521 | struct cx231xx *dev = fh->dev; | |
1522 | ||
1523 | *norm = dev->encodernorm.id; | |
1524 | return 0; | |
1525 | } | |
5b8acdc5 | 1526 | |
314527ac | 1527 | static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id) |
64fbf444 PB |
1528 | { |
1529 | struct cx231xx_fh *fh = file->private_data; | |
1530 | struct cx231xx *dev = fh->dev; | |
1531 | unsigned int i; | |
1532 | ||
1533 | for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++) | |
314527ac | 1534 | if (id & cx231xx_tvnorms[i].id) |
64fbf444 PB |
1535 | break; |
1536 | if (i == ARRAY_SIZE(cx231xx_tvnorms)) | |
1537 | return -EINVAL; | |
1538 | dev->encodernorm = cx231xx_tvnorms[i]; | |
1539 | ||
1540 | if (dev->encodernorm.id & 0xb000) { | |
1541 | dprintk(3, "encodernorm set to NTSC\n"); | |
1542 | dev->norm = V4L2_STD_NTSC; | |
1543 | dev->ts1.height = 480; | |
88b6ffed | 1544 | cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false); |
64fbf444 PB |
1545 | } else { |
1546 | dprintk(3, "encodernorm set to PAL\n"); | |
1547 | dev->norm = V4L2_STD_PAL_B; | |
1548 | dev->ts1.height = 576; | |
88b6ffed | 1549 | cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, true); |
64fbf444 | 1550 | } |
8774bed9 | 1551 | call_all(dev, video, s_std, dev->norm); |
64fbf444 PB |
1552 | /* do mode control overrides */ |
1553 | cx231xx_do_mode_ctrl_overrides(dev); | |
1554 | ||
1555 | dprintk(3, "exit vidioc_s_std() i=0x%x\n", i); | |
1556 | return 0; | |
1557 | } | |
5b8acdc5 | 1558 | |
64fbf444 PB |
1559 | static int vidioc_s_ctrl(struct file *file, void *priv, |
1560 | struct v4l2_control *ctl) | |
1561 | { | |
1562 | struct cx231xx_fh *fh = file->private_data; | |
1563 | struct cx231xx *dev = fh->dev; | |
5b8acdc5 | 1564 | |
64fbf444 PB |
1565 | dprintk(3, "enter vidioc_s_ctrl()\n"); |
1566 | /* Update the A/V core */ | |
1567 | call_all(dev, core, s_ctrl, ctl); | |
1568 | dprintk(3, "exit vidioc_s_ctrl()\n"); | |
1569 | return 0; | |
1570 | } | |
64fbf444 PB |
1571 | |
1572 | static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, | |
1573 | struct v4l2_fmtdesc *f) | |
1574 | { | |
64fbf444 PB |
1575 | if (f->index != 0) |
1576 | return -EINVAL; | |
1577 | ||
1578 | strlcpy(f->description, "MPEG", sizeof(f->description)); | |
1579 | f->pixelformat = V4L2_PIX_FMT_MPEG; | |
1580 | ||
1581 | return 0; | |
1582 | } | |
1583 | ||
1584 | static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, | |
1585 | struct v4l2_format *f) | |
1586 | { | |
1587 | struct cx231xx_fh *fh = file->private_data; | |
1588 | struct cx231xx *dev = fh->dev; | |
5aa95991 | 1589 | |
64fbf444 | 1590 | dprintk(3, "enter vidioc_g_fmt_vid_cap()\n"); |
5aa95991 | 1591 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
64fbf444 | 1592 | f->fmt.pix.bytesperline = 0; |
5aa95991 HV |
1593 | f->fmt.pix.sizeimage = mpeglines * mpeglinesize; |
1594 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
1595 | f->fmt.pix.width = dev->ts1.width; | |
1596 | f->fmt.pix.height = dev->ts1.height; | |
1597 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; | |
5aa95991 HV |
1598 | dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n", |
1599 | dev->ts1.width, dev->ts1.height); | |
64fbf444 PB |
1600 | dprintk(3, "exit vidioc_g_fmt_vid_cap()\n"); |
1601 | return 0; | |
1602 | } | |
1603 | ||
1604 | static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, | |
1605 | struct v4l2_format *f) | |
1606 | { | |
1607 | struct cx231xx_fh *fh = file->private_data; | |
1608 | struct cx231xx *dev = fh->dev; | |
5aa95991 | 1609 | |
64fbf444 | 1610 | dprintk(3, "enter vidioc_try_fmt_vid_cap()\n"); |
5aa95991 | 1611 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
64fbf444 | 1612 | f->fmt.pix.bytesperline = 0; |
5aa95991 HV |
1613 | f->fmt.pix.sizeimage = mpeglines * mpeglinesize; |
1614 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; | |
1615 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
5aa95991 HV |
1616 | dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n", |
1617 | dev->ts1.width, dev->ts1.height); | |
64fbf444 PB |
1618 | dprintk(3, "exit vidioc_try_fmt_vid_cap()\n"); |
1619 | return 0; | |
1620 | } | |
1621 | ||
64fbf444 PB |
1622 | static int vidioc_reqbufs(struct file *file, void *priv, |
1623 | struct v4l2_requestbuffers *p) | |
1624 | { | |
1625 | struct cx231xx_fh *fh = file->private_data; | |
1626 | ||
1627 | return videobuf_reqbufs(&fh->vidq, p); | |
1628 | } | |
1629 | ||
1630 | static int vidioc_querybuf(struct file *file, void *priv, | |
1631 | struct v4l2_buffer *p) | |
1632 | { | |
1633 | struct cx231xx_fh *fh = file->private_data; | |
1634 | ||
1635 | return videobuf_querybuf(&fh->vidq, p); | |
1636 | } | |
1637 | ||
1638 | static int vidioc_qbuf(struct file *file, void *priv, | |
1639 | struct v4l2_buffer *p) | |
1640 | { | |
1641 | struct cx231xx_fh *fh = file->private_data; | |
1642 | ||
1643 | return videobuf_qbuf(&fh->vidq, p); | |
1644 | } | |
1645 | ||
1646 | static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) | |
1647 | { | |
1648 | struct cx231xx_fh *fh = priv; | |
1649 | ||
1650 | return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK); | |
1651 | } | |
1652 | ||
1653 | ||
1654 | static int vidioc_streamon(struct file *file, void *priv, | |
1655 | enum v4l2_buf_type i) | |
1656 | { | |
1657 | struct cx231xx_fh *fh = file->private_data; | |
64fbf444 | 1658 | struct cx231xx *dev = fh->dev; |
5b8acdc5 | 1659 | |
64fbf444 | 1660 | dprintk(3, "enter vidioc_streamon()\n"); |
5b8acdc5 HV |
1661 | cx231xx_set_alt_setting(dev, INDEX_TS1, 0); |
1662 | cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); | |
1663 | if (dev->USE_ISO) | |
1664 | cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS, | |
1665 | CX231XX_NUM_BUFS, | |
1666 | dev->video_mode.max_pkt_size, | |
1667 | cx231xx_isoc_copy); | |
1668 | else { | |
1669 | cx231xx_init_bulk(dev, 320, | |
1670 | 5, | |
1671 | dev->ts1_mode.max_pkt_size, | |
1672 | cx231xx_bulk_copy); | |
1673 | } | |
64fbf444 PB |
1674 | dprintk(3, "exit vidioc_streamon()\n"); |
1675 | return videobuf_streamon(&fh->vidq); | |
1676 | } | |
1677 | ||
1678 | static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) | |
1679 | { | |
1680 | struct cx231xx_fh *fh = file->private_data; | |
1681 | ||
1682 | return videobuf_streamoff(&fh->vidq); | |
1683 | } | |
1684 | ||
64fbf444 PB |
1685 | static int vidioc_log_status(struct file *file, void *priv) |
1686 | { | |
1687 | struct cx231xx_fh *fh = priv; | |
1688 | struct cx231xx *dev = fh->dev; | |
64fbf444 | 1689 | |
64fbf444 | 1690 | call_all(dev, core, log_status); |
88b6ffed | 1691 | return v4l2_ctrl_log_status(file, priv); |
64fbf444 PB |
1692 | } |
1693 | ||
1694 | static int mpeg_open(struct file *file) | |
1695 | { | |
b86d1544 HV |
1696 | struct video_device *vdev = video_devdata(file); |
1697 | struct cx231xx *dev = video_drvdata(file); | |
64fbf444 | 1698 | struct cx231xx_fh *fh; |
64fbf444 PB |
1699 | |
1700 | dprintk(2, "%s()\n", __func__); | |
1701 | ||
1265f080 HV |
1702 | if (mutex_lock_interruptible(&dev->lock)) |
1703 | return -ERESTARTSYS; | |
64fbf444 PB |
1704 | |
1705 | /* allocate + initialize per filehandle data */ | |
1706 | fh = kzalloc(sizeof(*fh), GFP_KERNEL); | |
1707 | if (NULL == fh) { | |
1708 | mutex_unlock(&dev->lock); | |
1709 | return -ENOMEM; | |
1710 | } | |
1711 | ||
1712 | file->private_data = fh; | |
b86d1544 HV |
1713 | v4l2_fh_init(&fh->fh, vdev); |
1714 | fh->dev = dev; | |
64fbf444 PB |
1715 | |
1716 | ||
1717 | videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops, | |
1718 | NULL, &dev->video_mode.slock, | |
1719 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED, | |
1265f080 | 1720 | sizeof(struct cx231xx_buffer), fh, &dev->lock); |
64fbf444 PB |
1721 | /* |
1722 | videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops, | |
336fea92 | 1723 | dev->dev, &dev->ts1.slock, |
64fbf444 PB |
1724 | V4L2_BUF_TYPE_VIDEO_CAPTURE, |
1725 | V4L2_FIELD_INTERLACED, | |
1726 | sizeof(struct cx231xx_buffer), | |
1265f080 | 1727 | fh, &dev->lock); |
64fbf444 PB |
1728 | */ |
1729 | ||
64fbf444 PB |
1730 | cx231xx_set_alt_setting(dev, INDEX_VANC, 1); |
1731 | cx231xx_set_gpio_value(dev, 2, 0); | |
1732 | ||
1733 | cx231xx_initialize_codec(dev); | |
1734 | ||
1735 | mutex_unlock(&dev->lock); | |
b86d1544 | 1736 | v4l2_fh_add(&fh->fh); |
64fbf444 PB |
1737 | cx231xx_start_TS1(dev); |
1738 | ||
1739 | return 0; | |
1740 | } | |
1741 | ||
1742 | static int mpeg_release(struct file *file) | |
1743 | { | |
1744 | struct cx231xx_fh *fh = file->private_data; | |
1745 | struct cx231xx *dev = fh->dev; | |
1746 | ||
dd067a8d | 1747 | dprintk(3, "mpeg_release()! dev=0x%p\n", dev); |
64fbf444 | 1748 | |
64fbf444 PB |
1749 | mutex_lock(&dev->lock); |
1750 | ||
1751 | cx231xx_stop_TS1(dev); | |
1752 | ||
5b8acdc5 HV |
1753 | /* do this before setting alternate! */ |
1754 | if (dev->USE_ISO) | |
1755 | cx231xx_uninit_isoc(dev); | |
1756 | else | |
1757 | cx231xx_uninit_bulk(dev); | |
1758 | cx231xx_set_mode(dev, CX231XX_SUSPEND); | |
64fbf444 | 1759 | |
5b8acdc5 HV |
1760 | cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, |
1761 | CX231xx_END_NOW, CX231xx_MPEG_CAPTURE, | |
1762 | CX231xx_RAW_BITS_NONE); | |
64fbf444 PB |
1763 | |
1764 | /* FIXME: Review this crap */ | |
1765 | /* Shut device down on last close */ | |
1766 | if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) { | |
1767 | if (atomic_dec_return(&dev->v4l_reader_count) == 0) { | |
1768 | /* stop mpeg capture */ | |
1769 | ||
1770 | msleep(500); | |
1771 | cx231xx_417_check_encoder(dev); | |
1772 | ||
1773 | } | |
1774 | } | |
1775 | ||
1776 | if (fh->vidq.streaming) | |
1777 | videobuf_streamoff(&fh->vidq); | |
1778 | if (fh->vidq.reading) | |
1779 | videobuf_read_stop(&fh->vidq); | |
1780 | ||
1781 | videobuf_mmap_free(&fh->vidq); | |
b86d1544 HV |
1782 | v4l2_fh_del(&fh->fh); |
1783 | v4l2_fh_exit(&fh->fh); | |
64fbf444 PB |
1784 | kfree(fh); |
1785 | mutex_unlock(&dev->lock); | |
1786 | return 0; | |
1787 | } | |
1788 | ||
1789 | static ssize_t mpeg_read(struct file *file, char __user *data, | |
1790 | size_t count, loff_t *ppos) | |
1791 | { | |
1792 | struct cx231xx_fh *fh = file->private_data; | |
1793 | struct cx231xx *dev = fh->dev; | |
1794 | ||
64fbf444 PB |
1795 | /* Deal w/ A/V decoder * and mpeg encoder sync issues. */ |
1796 | /* Start mpeg encoder on first read. */ | |
1797 | if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) { | |
1798 | if (atomic_inc_return(&dev->v4l_reader_count) == 1) { | |
1799 | if (cx231xx_initialize_codec(dev) < 0) | |
1800 | return -EINVAL; | |
1801 | } | |
1802 | } | |
1803 | ||
1804 | return videobuf_read_stream(&fh->vidq, data, count, ppos, 0, | |
1805 | file->f_flags & O_NONBLOCK); | |
1806 | } | |
1807 | ||
1808 | static unsigned int mpeg_poll(struct file *file, | |
1809 | struct poll_table_struct *wait) | |
1810 | { | |
88b6ffed | 1811 | unsigned long req_events = poll_requested_events(wait); |
64fbf444 | 1812 | struct cx231xx_fh *fh = file->private_data; |
88b6ffed HV |
1813 | struct cx231xx *dev = fh->dev; |
1814 | unsigned int res = 0; | |
64fbf444 | 1815 | |
88b6ffed HV |
1816 | if (v4l2_event_pending(&fh->fh)) |
1817 | res |= POLLPRI; | |
1818 | else | |
1819 | poll_wait(file, &fh->fh.wait, wait); | |
1820 | ||
1821 | if (!(req_events & (POLLIN | POLLRDNORM))) | |
1822 | return res; | |
1823 | ||
1824 | mutex_lock(&dev->lock); | |
1825 | res |= videobuf_poll_stream(file, &fh->vidq, wait); | |
1826 | mutex_unlock(&dev->lock); | |
1827 | return res; | |
64fbf444 PB |
1828 | } |
1829 | ||
1830 | static int mpeg_mmap(struct file *file, struct vm_area_struct *vma) | |
1831 | { | |
1832 | struct cx231xx_fh *fh = file->private_data; | |
64fbf444 PB |
1833 | |
1834 | dprintk(2, "%s()\n", __func__); | |
1835 | ||
1836 | return videobuf_mmap_mapper(&fh->vidq, vma); | |
1837 | } | |
1838 | ||
1839 | static struct v4l2_file_operations mpeg_fops = { | |
1840 | .owner = THIS_MODULE, | |
1841 | .open = mpeg_open, | |
1842 | .release = mpeg_release, | |
1843 | .read = mpeg_read, | |
1844 | .poll = mpeg_poll, | |
1845 | .mmap = mpeg_mmap, | |
1265f080 | 1846 | .unlocked_ioctl = video_ioctl2, |
64fbf444 PB |
1847 | }; |
1848 | ||
1849 | static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { | |
1850 | .vidioc_s_std = vidioc_s_std, | |
1851 | .vidioc_g_std = vidioc_g_std, | |
b86d1544 HV |
1852 | .vidioc_g_tuner = cx231xx_g_tuner, |
1853 | .vidioc_s_tuner = cx231xx_s_tuner, | |
1854 | .vidioc_g_frequency = cx231xx_g_frequency, | |
1855 | .vidioc_s_frequency = cx231xx_s_frequency, | |
1856 | .vidioc_enum_input = cx231xx_enum_input, | |
1857 | .vidioc_g_input = cx231xx_g_input, | |
1858 | .vidioc_s_input = cx231xx_s_input, | |
64fbf444 | 1859 | .vidioc_s_ctrl = vidioc_s_ctrl, |
e25cb200 | 1860 | .vidioc_cropcap = vidioc_cropcap, |
bc08734c | 1861 | .vidioc_querycap = cx231xx_querycap, |
64fbf444 PB |
1862 | .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, |
1863 | .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, | |
1864 | .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, | |
3f926e32 | 1865 | .vidioc_s_fmt_vid_cap = vidioc_try_fmt_vid_cap, |
64fbf444 PB |
1866 | .vidioc_reqbufs = vidioc_reqbufs, |
1867 | .vidioc_querybuf = vidioc_querybuf, | |
1868 | .vidioc_qbuf = vidioc_qbuf, | |
1869 | .vidioc_dqbuf = vidioc_dqbuf, | |
1870 | .vidioc_streamon = vidioc_streamon, | |
1871 | .vidioc_streamoff = vidioc_streamoff, | |
64fbf444 | 1872 | .vidioc_log_status = vidioc_log_status, |
64fbf444 | 1873 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
b86d1544 HV |
1874 | .vidioc_g_register = cx231xx_g_register, |
1875 | .vidioc_s_register = cx231xx_s_register, | |
64fbf444 | 1876 | #endif |
88b6ffed HV |
1877 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
1878 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
64fbf444 PB |
1879 | }; |
1880 | ||
1881 | static struct video_device cx231xx_mpeg_template = { | |
1882 | .name = "cx231xx", | |
1883 | .fops = &mpeg_fops, | |
1884 | .ioctl_ops = &mpeg_ioctl_ops, | |
1885 | .minor = -1, | |
88b6ffed | 1886 | .tvnorms = V4L2_STD_ALL, |
64fbf444 PB |
1887 | }; |
1888 | ||
1889 | void cx231xx_417_unregister(struct cx231xx *dev) | |
1890 | { | |
1891 | dprintk(1, "%s()\n", __func__); | |
1892 | dprintk(3, "%s()\n", __func__); | |
1893 | ||
60acf187 HV |
1894 | if (video_is_registered(&dev->v4l_device)) { |
1895 | video_unregister_device(&dev->v4l_device); | |
88b6ffed | 1896 | v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl); |
64fbf444 PB |
1897 | } |
1898 | } | |
1899 | ||
88b6ffed HV |
1900 | static int cx231xx_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val) |
1901 | { | |
1902 | struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler); | |
1903 | int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1; | |
ebf984bb HV |
1904 | struct v4l2_subdev_format format = { |
1905 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1906 | }; | |
88b6ffed HV |
1907 | |
1908 | /* fix videodecoder resolution */ | |
ebf984bb HV |
1909 | format.format.width = cxhdl->width / (is_mpeg1 ? 2 : 1); |
1910 | format.format.height = cxhdl->height; | |
1911 | format.format.code = MEDIA_BUS_FMT_FIXED; | |
1912 | v4l2_subdev_call(dev->sd_cx25840, pad, set_fmt, NULL, &format); | |
88b6ffed HV |
1913 | return 0; |
1914 | } | |
1915 | ||
1916 | static int cx231xx_s_audio_sampling_freq(struct cx2341x_handler *cxhdl, u32 idx) | |
1917 | { | |
1918 | static const u32 freqs[3] = { 44100, 48000, 32000 }; | |
1919 | struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler); | |
1920 | ||
1921 | /* The audio clock of the digitizer must match the codec sample | |
1922 | rate otherwise you get some very strange effects. */ | |
1923 | if (idx < ARRAY_SIZE(freqs)) | |
1924 | call_all(dev, audio, s_clock_freq, freqs[idx]); | |
1925 | return 0; | |
1926 | } | |
1927 | ||
083206fc | 1928 | static const struct cx2341x_handler_ops cx231xx_ops = { |
88b6ffed HV |
1929 | /* needed for the video clock freq */ |
1930 | .s_audio_sampling_freq = cx231xx_s_audio_sampling_freq, | |
1931 | /* needed for setting up the video resolution */ | |
1932 | .s_video_encoding = cx231xx_s_video_encoding, | |
1933 | }; | |
1934 | ||
60acf187 | 1935 | static void cx231xx_video_dev_init( |
64fbf444 PB |
1936 | struct cx231xx *dev, |
1937 | struct usb_device *usbdev, | |
60acf187 HV |
1938 | struct video_device *vfd, |
1939 | const struct video_device *template, | |
1940 | const char *type) | |
64fbf444 | 1941 | { |
64fbf444 | 1942 | dprintk(1, "%s()\n", __func__); |
64fbf444 | 1943 | *vfd = *template; |
64fbf444 PB |
1944 | snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, |
1945 | type, cx231xx_boards[dev->model].name); | |
1946 | ||
1947 | vfd->v4l2_dev = &dev->v4l2_dev; | |
1265f080 | 1948 | vfd->lock = &dev->lock; |
60acf187 | 1949 | vfd->release = video_device_release_empty; |
88b6ffed | 1950 | vfd->ctrl_handler = &dev->mpeg_ctrl_handler.hdl; |
b86d1544 HV |
1951 | video_set_drvdata(vfd, dev); |
1952 | if (dev->tuner_type == TUNER_ABSENT) { | |
1953 | v4l2_disable_ioctl(vfd, VIDIOC_G_FREQUENCY); | |
1954 | v4l2_disable_ioctl(vfd, VIDIOC_S_FREQUENCY); | |
1955 | v4l2_disable_ioctl(vfd, VIDIOC_G_TUNER); | |
1956 | v4l2_disable_ioctl(vfd, VIDIOC_S_TUNER); | |
1957 | } | |
64fbf444 PB |
1958 | } |
1959 | ||
1960 | int cx231xx_417_register(struct cx231xx *dev) | |
1961 | { | |
1962 | /* FIXME: Port1 hardcoded here */ | |
1963 | int err = -ENODEV; | |
1964 | struct cx231xx_tsport *tsport = &dev->ts1; | |
1965 | ||
1966 | dprintk(1, "%s()\n", __func__); | |
1967 | ||
1968 | /* Set default TV standard */ | |
1969 | dev->encodernorm = cx231xx_tvnorms[0]; | |
1970 | ||
1971 | if (dev->encodernorm.id & V4L2_STD_525_60) | |
1972 | tsport->height = 480; | |
1973 | else | |
1974 | tsport->height = 576; | |
1975 | ||
1976 | tsport->width = 720; | |
88b6ffed HV |
1977 | err = cx2341x_handler_init(&dev->mpeg_ctrl_handler, 50); |
1978 | if (err) { | |
1979 | dprintk(3, "%s: can't init cx2341x controls\n", dev->name); | |
1980 | return err; | |
1981 | } | |
1982 | dev->mpeg_ctrl_handler.func = cx231xx_mbox_func; | |
1983 | dev->mpeg_ctrl_handler.priv = dev; | |
1984 | dev->mpeg_ctrl_handler.ops = &cx231xx_ops; | |
1985 | if (dev->sd_cx25840) | |
1986 | v4l2_ctrl_add_handler(&dev->mpeg_ctrl_handler.hdl, | |
1987 | dev->sd_cx25840->ctrl_handler, NULL); | |
1988 | if (dev->mpeg_ctrl_handler.hdl.error) { | |
1989 | err = dev->mpeg_ctrl_handler.hdl.error; | |
1990 | dprintk(3, "%s: can't add cx25840 controls\n", dev->name); | |
1991 | v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl); | |
1992 | return err; | |
1993 | } | |
64fbf444 PB |
1994 | dev->norm = V4L2_STD_NTSC; |
1995 | ||
88b6ffed HV |
1996 | dev->mpeg_ctrl_handler.port = CX2341X_PORT_SERIAL; |
1997 | cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false); | |
64fbf444 PB |
1998 | |
1999 | /* Allocate and initialize V4L video device */ | |
60acf187 HV |
2000 | cx231xx_video_dev_init(dev, dev->udev, |
2001 | &dev->v4l_device, &cx231xx_mpeg_template, "mpeg"); | |
2002 | err = video_register_device(&dev->v4l_device, | |
64fbf444 PB |
2003 | VFL_TYPE_GRABBER, -1); |
2004 | if (err < 0) { | |
2005 | dprintk(3, "%s: can't register mpeg device\n", dev->name); | |
88b6ffed | 2006 | v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl); |
64fbf444 PB |
2007 | return err; |
2008 | } | |
2009 | ||
2010 | dprintk(3, "%s: registered device video%d [mpeg]\n", | |
60acf187 | 2011 | dev->name, dev->v4l_device.num); |
64fbf444 PB |
2012 | |
2013 | return 0; | |
2014 | } | |
b8320e95 TG |
2015 | |
2016 | MODULE_FIRMWARE(CX231xx_FIRM_IMAGE_NAME); |