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1da177e4 LT |
1 | /* |
2 | * Colour AR M64278(VGA) driver for Video4Linux | |
3 | * | |
4 | * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Some code is taken from AR driver sample program for M3T-M32700UT. | |
12 | * | |
13 | * AR driver sample (M32R SDK): | |
14 | * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION | |
15 | * AND RENESAS SOLUTIONS CORPORATION | |
16 | * All Rights Reserved. | |
17 | * | |
18 | * 2003-09-01: Support w3cam by Takeo Takahashi | |
19 | */ | |
20 | ||
21 | #include <linux/config.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/devfs_fs_kernel.h> | |
24 | #include <linux/module.h> | |
1da177e4 LT |
25 | #include <linux/delay.h> |
26 | #include <linux/errno.h> | |
27 | #include <linux/fs.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/sched.h> | |
33 | #include <linux/videodev.h> | |
34 | ||
35 | #include <asm/semaphore.h> | |
36 | #include <asm/uaccess.h> | |
37 | #include <asm/m32r.h> | |
38 | #include <asm/io.h> | |
39 | #include <asm/dma.h> | |
40 | #include <asm/byteorder.h> | |
41 | ||
42 | #if 0 | |
43 | #define DEBUG(n, args...) printk(args) | |
44 | #define CHECK_LOST 1 | |
45 | #else | |
46 | #define DEBUG(n, args...) | |
47 | #define CHECK_LOST 0 | |
48 | #endif | |
49 | ||
50 | /* | |
51 | * USE_INT is always 0, interrupt mode is not available | |
52 | * on linux due to lack of speed | |
53 | */ | |
54 | #define USE_INT 0 /* Don't modify */ | |
55 | ||
56 | #define VERSION "0.03" | |
57 | ||
58 | #define ar_inl(addr) inl((unsigned long)(addr)) | |
59 | #define ar_outl(val, addr) outl((unsigned long)(val),(unsigned long)(addr)) | |
60 | ||
61 | extern struct cpuinfo_m32r boot_cpu_data; | |
62 | ||
63 | /* | |
64 | * CCD pixel size | |
65 | * Note that M32700UT does not support CIF mode, but QVGA is | |
66 | * supported by M32700UT hardware using VGA mode of AR LSI. | |
67 | * | |
68 | * Supported: VGA (Normal mode, Interlace mode) | |
69 | * QVGA (Always Interlace mode of VGA) | |
70 | * | |
71 | */ | |
72 | #define AR_WIDTH_VGA 640 | |
73 | #define AR_HEIGHT_VGA 480 | |
74 | #define AR_WIDTH_QVGA 320 | |
75 | #define AR_HEIGHT_QVGA 240 | |
76 | #define MIN_AR_WIDTH AR_WIDTH_QVGA | |
77 | #define MIN_AR_HEIGHT AR_HEIGHT_QVGA | |
78 | #define MAX_AR_WIDTH AR_WIDTH_VGA | |
79 | #define MAX_AR_HEIGHT AR_HEIGHT_VGA | |
80 | ||
81 | /* bits & bytes per pixel */ | |
82 | #define AR_BITS_PER_PIXEL 16 | |
83 | #define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8) | |
84 | ||
85 | /* line buffer size */ | |
86 | #define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL) | |
87 | #define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL) | |
88 | #define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA | |
89 | ||
90 | /* frame size & type */ | |
91 | #define AR_FRAME_BYTES_VGA \ | |
92 | (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL) | |
93 | #define AR_FRAME_BYTES_QVGA \ | |
94 | (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL) | |
95 | #define MAX_AR_FRAME_BYTES \ | |
96 | (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL) | |
97 | ||
98 | #define AR_MAX_FRAME 15 | |
99 | ||
100 | /* capture size */ | |
101 | #define AR_SIZE_VGA 0 | |
102 | #define AR_SIZE_QVGA 1 | |
103 | ||
104 | /* capture mode */ | |
105 | #define AR_MODE_INTERLACE 0 | |
106 | #define AR_MODE_NORMAL 1 | |
107 | ||
108 | struct ar_device { | |
109 | struct video_device *vdev; | |
110 | unsigned int start_capture; /* duaring capture in INT. mode. */ | |
111 | #if USE_INT | |
112 | unsigned char *line_buff; /* DMA line buffer */ | |
113 | #endif | |
114 | unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */ | |
115 | short size; /* capture size */ | |
116 | short mode; /* capture mode */ | |
117 | int width, height; | |
118 | int frame_bytes, line_bytes; | |
119 | wait_queue_head_t wait; | |
120 | struct semaphore lock; | |
121 | }; | |
122 | ||
123 | static int video_nr = -1; /* video device number (first free) */ | |
124 | static unsigned char yuv[MAX_AR_FRAME_BYTES]; | |
125 | ||
126 | /* module parameters */ | |
127 | /* default frequency */ | |
128 | #define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */ | |
129 | static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */ | |
130 | static int vga = 0; /* default mode(0:QVGA mode, other:VGA mode) */ | |
131 | static int vga_interlace = 0; /* 0 is normal mode for, else interlace mode */ | |
132 | MODULE_PARM(freq, "i"); | |
133 | MODULE_PARM(vga, "i"); | |
134 | MODULE_PARM(vga_interlace, "i"); | |
135 | ||
136 | static int ar_initialize(struct video_device *dev); | |
137 | ||
138 | static inline void wait_for_vsync(void) | |
139 | { | |
140 | while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */ | |
141 | cpu_relax(); | |
142 | while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */ | |
143 | cpu_relax(); | |
144 | } | |
145 | ||
146 | static inline void wait_acknowledge(void) | |
147 | { | |
148 | int i; | |
149 | ||
150 | for (i = 0; i < 1000; i++) | |
151 | cpu_relax(); | |
152 | while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK) | |
153 | cpu_relax(); | |
154 | } | |
155 | ||
156 | /******************************************************************* | |
157 | * I2C functions | |
158 | *******************************************************************/ | |
159 | void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2, | |
160 | unsigned long data3) | |
161 | { | |
162 | int i; | |
163 | ||
164 | /* Slave Address */ | |
165 | ar_outl(addr, PLDI2CDATA); | |
166 | wait_for_vsync(); | |
167 | ||
168 | /* Start */ | |
169 | ar_outl(1, PLDI2CCND); | |
170 | wait_acknowledge(); | |
171 | ||
172 | /* Transfer data 1 */ | |
173 | ar_outl(data1, PLDI2CDATA); | |
174 | wait_for_vsync(); | |
175 | ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); | |
176 | wait_acknowledge(); | |
177 | ||
178 | /* Transfer data 2 */ | |
179 | ar_outl(data2, PLDI2CDATA); | |
180 | wait_for_vsync(); | |
181 | ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); | |
182 | wait_acknowledge(); | |
183 | ||
184 | if (n == 3) { | |
185 | /* Transfer data 3 */ | |
186 | ar_outl(data3, PLDI2CDATA); | |
187 | wait_for_vsync(); | |
188 | ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); | |
189 | wait_acknowledge(); | |
190 | } | |
191 | ||
192 | /* Stop */ | |
193 | for (i = 0; i < 100; i++) | |
194 | cpu_relax(); | |
195 | ar_outl(2, PLDI2CCND); | |
196 | ar_outl(2, PLDI2CCND); | |
197 | ||
198 | while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB) | |
199 | cpu_relax(); | |
200 | } | |
201 | ||
202 | ||
203 | void init_iic(void) | |
204 | { | |
205 | DEBUG(1, "init_iic:\n"); | |
206 | ||
207 | /* | |
208 | * ICU Setting (iic) | |
209 | */ | |
210 | /* I2C Setting */ | |
211 | ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */ | |
212 | ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */ | |
213 | ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */ | |
214 | ||
215 | /* I2C CLK */ | |
216 | /* 50MH-100k */ | |
217 | if (freq == 75) { | |
218 | ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */ | |
219 | } else if (freq == 50) { | |
220 | ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */ | |
221 | } else { | |
222 | ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */ | |
223 | } | |
224 | ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */ | |
225 | } | |
226 | ||
227 | /************************************************************************** | |
228 | * | |
229 | * Video4Linux Interface functions | |
230 | * | |
231 | **************************************************************************/ | |
232 | ||
233 | static inline void disable_dma(void) | |
234 | { | |
235 | ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */ | |
236 | } | |
237 | ||
238 | static inline void enable_dma(void) | |
239 | { | |
240 | ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */ | |
241 | } | |
242 | ||
243 | static inline void clear_dma_status(void) | |
244 | { | |
245 | ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */ | |
246 | } | |
247 | ||
248 | static inline void wait_for_vertical_sync(int exp_line) | |
249 | { | |
250 | #if CHECK_LOST | |
251 | int tmout = 10000; /* FIXME */ | |
252 | int l; | |
253 | ||
254 | /* | |
255 | * check HCOUNT because we cannot check vertical sync. | |
256 | */ | |
257 | for (; tmout >= 0; tmout--) { | |
258 | l = ar_inl(ARVHCOUNT); | |
259 | if (l == exp_line) | |
260 | break; | |
261 | } | |
262 | if (tmout < 0) | |
263 | printk("arv: lost %d -> %d\n", exp_line, l); | |
264 | #else | |
265 | while (ar_inl(ARVHCOUNT) != exp_line) | |
266 | cpu_relax(); | |
267 | #endif | |
268 | } | |
269 | ||
270 | static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
271 | { | |
272 | struct video_device *v = video_devdata(file); | |
273 | struct ar_device *ar = v->priv; | |
274 | long ret = ar->frame_bytes; /* return read bytes */ | |
275 | unsigned long arvcr1 = 0; | |
276 | unsigned long flags; | |
277 | unsigned char *p; | |
278 | int h, w; | |
279 | unsigned char *py, *pu, *pv; | |
280 | #if ! USE_INT | |
281 | int l; | |
282 | #endif | |
283 | ||
284 | DEBUG(1, "ar_read()\n"); | |
285 | ||
286 | if (ar->size == AR_SIZE_QVGA) | |
287 | arvcr1 |= ARVCR1_QVGA; | |
288 | if (ar->mode == AR_MODE_NORMAL) | |
289 | arvcr1 |= ARVCR1_NORMAL; | |
290 | ||
291 | down(&ar->lock); | |
292 | ||
293 | #if USE_INT | |
294 | local_irq_save(flags); | |
295 | disable_dma(); | |
296 | ar_outl(0xa1871300, M32R_DMA0CR0_PORTL); | |
297 | ar_outl(0x01000000, M32R_DMA0CR1_PORTL); | |
298 | ||
299 | /* set AR FIFO address as source(BSEL5) */ | |
300 | ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); | |
301 | ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); | |
302 | ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */ | |
303 | ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */ | |
304 | ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */ | |
305 | ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */ | |
306 | ||
307 | /* | |
308 | * Okey , kicks AR LSI to invoke an interrupt | |
309 | */ | |
310 | ar->start_capture = 0; | |
311 | ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); | |
312 | local_irq_restore(flags); | |
313 | /* .... AR interrupts .... */ | |
314 | interruptible_sleep_on(&ar->wait); | |
315 | if (signal_pending(current)) { | |
316 | printk("arv: interrupted while get frame data.\n"); | |
317 | ret = -EINTR; | |
318 | goto out_up; | |
319 | } | |
320 | #else /* ! USE_INT */ | |
321 | /* polling */ | |
322 | ar_outl(arvcr1, ARVCR1); | |
323 | disable_dma(); | |
324 | ar_outl(0x8000, M32R_DMAEDET_PORTL); | |
325 | ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); | |
326 | ar_outl(0x01000000, M32R_DMA0CR1_PORTL); | |
327 | ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); | |
328 | ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); | |
329 | ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); | |
330 | ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); | |
331 | ||
332 | local_irq_save(flags); | |
333 | while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */ | |
334 | cpu_relax(); | |
335 | if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { | |
336 | for (h = 0; h < ar->height; h++) { | |
337 | wait_for_vertical_sync(h); | |
338 | if (h < (AR_HEIGHT_VGA/2)) | |
339 | l = h << 1; | |
340 | else | |
341 | l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1); | |
342 | ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL); | |
343 | enable_dma(); | |
344 | while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000)) | |
345 | cpu_relax(); | |
346 | disable_dma(); | |
347 | clear_dma_status(); | |
348 | ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); | |
349 | } | |
350 | } else { | |
351 | for (h = 0; h < ar->height; h++) { | |
352 | wait_for_vertical_sync(h); | |
353 | ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL); | |
354 | enable_dma(); | |
355 | while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000)) | |
356 | cpu_relax(); | |
357 | disable_dma(); | |
358 | clear_dma_status(); | |
359 | ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); | |
360 | } | |
361 | } | |
362 | local_irq_restore(flags); | |
363 | #endif /* ! USE_INT */ | |
364 | ||
365 | /* | |
366 | * convert YUV422 to YUV422P | |
367 | * +--------------------+ | |
368 | * | Y0,Y1,... | | |
369 | * | ..............Yn | | |
370 | * +--------------------+ | |
371 | * | U0,U1,........Un | | |
372 | * +--------------------+ | |
373 | * | V0,V1,........Vn | | |
374 | * +--------------------+ | |
375 | */ | |
376 | py = yuv; | |
377 | pu = py + (ar->frame_bytes / 2); | |
378 | pv = pu + (ar->frame_bytes / 4); | |
379 | for (h = 0; h < ar->height; h++) { | |
380 | p = ar->frame[h]; | |
381 | for (w = 0; w < ar->line_bytes; w += 4) { | |
382 | *py++ = *p++; | |
383 | *pu++ = *p++; | |
384 | *py++ = *p++; | |
385 | *pv++ = *p++; | |
386 | } | |
387 | } | |
388 | if (copy_to_user(buf, yuv, ar->frame_bytes)) { | |
389 | printk("arv: failed while copy_to_user yuv.\n"); | |
390 | ret = -EFAULT; | |
391 | goto out_up; | |
392 | } | |
393 | DEBUG(1, "ret = %d\n", ret); | |
394 | out_up: | |
395 | up(&ar->lock); | |
396 | return ret; | |
397 | } | |
398 | ||
399 | static int ar_do_ioctl(struct inode *inode, struct file *file, | |
400 | unsigned int cmd, void *arg) | |
401 | { | |
402 | struct video_device *dev = video_devdata(file); | |
403 | struct ar_device *ar = dev->priv; | |
404 | ||
405 | DEBUG(1, "ar_ioctl()\n"); | |
406 | switch(cmd) { | |
407 | case VIDIOCGCAP: | |
408 | { | |
409 | struct video_capability *b = arg; | |
410 | DEBUG(1, "VIDIOCGCAP:\n"); | |
411 | strcpy(b->name, ar->vdev->name); | |
412 | b->type = VID_TYPE_CAPTURE; | |
413 | b->channels = 0; | |
414 | b->audios = 0; | |
415 | b->maxwidth = MAX_AR_WIDTH; | |
416 | b->maxheight = MAX_AR_HEIGHT; | |
417 | b->minwidth = MIN_AR_WIDTH; | |
418 | b->minheight = MIN_AR_HEIGHT; | |
419 | return 0; | |
420 | } | |
421 | case VIDIOCGCHAN: | |
422 | DEBUG(1, "VIDIOCGCHAN:\n"); | |
423 | return 0; | |
424 | case VIDIOCSCHAN: | |
425 | DEBUG(1, "VIDIOCSCHAN:\n"); | |
426 | return 0; | |
427 | case VIDIOCGTUNER: | |
428 | DEBUG(1, "VIDIOCGTUNER:\n"); | |
429 | return 0; | |
430 | case VIDIOCSTUNER: | |
431 | DEBUG(1, "VIDIOCSTUNER:\n"); | |
432 | return 0; | |
433 | case VIDIOCGPICT: | |
434 | DEBUG(1, "VIDIOCGPICT:\n"); | |
435 | return 0; | |
436 | case VIDIOCSPICT: | |
437 | DEBUG(1, "VIDIOCSPICT:\n"); | |
438 | return 0; | |
439 | case VIDIOCCAPTURE: | |
440 | DEBUG(1, "VIDIOCCAPTURE:\n"); | |
441 | return -EINVAL; | |
442 | case VIDIOCGWIN: | |
443 | { | |
444 | struct video_window *w = arg; | |
445 | DEBUG(1, "VIDIOCGWIN:\n"); | |
446 | memset(w, 0, sizeof(w)); | |
447 | w->width = ar->width; | |
448 | w->height = ar->height; | |
449 | return 0; | |
450 | } | |
451 | case VIDIOCSWIN: | |
452 | { | |
453 | struct video_window *w = arg; | |
454 | DEBUG(1, "VIDIOCSWIN:\n"); | |
455 | if ((w->width != AR_WIDTH_VGA || w->height != AR_HEIGHT_VGA) && | |
456 | (w->width != AR_WIDTH_QVGA || w->height != AR_HEIGHT_QVGA)) | |
457 | return -EINVAL; | |
458 | ||
459 | down(&ar->lock); | |
460 | ar->width = w->width; | |
461 | ar->height = w->height; | |
462 | if (ar->width == AR_WIDTH_VGA) { | |
463 | ar->size = AR_SIZE_VGA; | |
464 | ar->frame_bytes = AR_FRAME_BYTES_VGA; | |
465 | ar->line_bytes = AR_LINE_BYTES_VGA; | |
466 | if (vga_interlace) | |
467 | ar->mode = AR_MODE_INTERLACE; | |
468 | else | |
469 | ar->mode = AR_MODE_NORMAL; | |
470 | } else { | |
471 | ar->size = AR_SIZE_QVGA; | |
472 | ar->frame_bytes = AR_FRAME_BYTES_QVGA; | |
473 | ar->line_bytes = AR_LINE_BYTES_QVGA; | |
474 | ar->mode = AR_MODE_INTERLACE; | |
475 | } | |
476 | up(&ar->lock); | |
477 | return 0; | |
478 | } | |
479 | case VIDIOCGFBUF: | |
480 | DEBUG(1, "VIDIOCGFBUF:\n"); | |
481 | return -EINVAL; | |
482 | case VIDIOCSFBUF: | |
483 | DEBUG(1, "VIDIOCSFBUF:\n"); | |
484 | return -EINVAL; | |
485 | case VIDIOCKEY: | |
486 | DEBUG(1, "VIDIOCKEY:\n"); | |
487 | return 0; | |
488 | case VIDIOCGFREQ: | |
489 | DEBUG(1, "VIDIOCGFREQ:\n"); | |
490 | return -EINVAL; | |
491 | case VIDIOCSFREQ: | |
492 | DEBUG(1, "VIDIOCSFREQ:\n"); | |
493 | return -EINVAL; | |
494 | case VIDIOCGAUDIO: | |
495 | DEBUG(1, "VIDIOCGAUDIO:\n"); | |
496 | return -EINVAL; | |
497 | case VIDIOCSAUDIO: | |
498 | DEBUG(1, "VIDIOCSAUDIO:\n"); | |
499 | return -EINVAL; | |
500 | case VIDIOCSYNC: | |
501 | DEBUG(1, "VIDIOCSYNC:\n"); | |
502 | return -EINVAL; | |
503 | case VIDIOCMCAPTURE: | |
504 | DEBUG(1, "VIDIOCMCAPTURE:\n"); | |
505 | return -EINVAL; | |
506 | case VIDIOCGMBUF: | |
507 | DEBUG(1, "VIDIOCGMBUF:\n"); | |
508 | return -EINVAL; | |
509 | case VIDIOCGUNIT: | |
510 | DEBUG(1, "VIDIOCGUNIT:\n"); | |
511 | return -EINVAL; | |
512 | case VIDIOCGCAPTURE: | |
513 | DEBUG(1, "VIDIOCGCAPTURE:\n"); | |
514 | return -EINVAL; | |
515 | case VIDIOCSCAPTURE: | |
516 | DEBUG(1, "VIDIOCSCAPTURE:\n"); | |
517 | return -EINVAL; | |
518 | case VIDIOCSPLAYMODE: | |
519 | DEBUG(1, "VIDIOCSPLAYMODE:\n"); | |
520 | return -EINVAL; | |
521 | case VIDIOCSWRITEMODE: | |
522 | DEBUG(1, "VIDIOCSWRITEMODE:\n"); | |
523 | return -EINVAL; | |
524 | case VIDIOCGPLAYINFO: | |
525 | DEBUG(1, "VIDIOCGPLAYINFO:\n"); | |
526 | return -EINVAL; | |
527 | case VIDIOCSMICROCODE: | |
528 | DEBUG(1, "VIDIOCSMICROCODE:\n"); | |
529 | return -EINVAL; | |
530 | case VIDIOCGVBIFMT: | |
531 | DEBUG(1, "VIDIOCGVBIFMT:\n"); | |
532 | return -EINVAL; | |
533 | case VIDIOCSVBIFMT: | |
534 | DEBUG(1, "VIDIOCSVBIFMT:\n"); | |
535 | return -EINVAL; | |
536 | default: | |
537 | DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd); | |
538 | return -ENOIOCTLCMD; | |
539 | } | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static int ar_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |
544 | unsigned long arg) | |
545 | { | |
546 | return video_usercopy(inode, file, cmd, arg, ar_do_ioctl); | |
547 | } | |
548 | ||
549 | #if USE_INT | |
550 | /* | |
551 | * Interrupt handler | |
552 | */ | |
553 | static void ar_interrupt(int irq, void *dev, struct pt_regs *regs) | |
554 | { | |
555 | struct ar_device *ar = dev; | |
556 | unsigned int line_count; | |
557 | unsigned int line_number; | |
558 | unsigned int arvcr1; | |
559 | ||
560 | line_count = ar_inl(ARVHCOUNT); /* line number */ | |
561 | if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { | |
562 | /* operations for interlace mode */ | |
563 | if ( line_count < (AR_HEIGHT_VGA/2) ) /* even line */ | |
564 | line_number = (line_count << 1); | |
565 | else /* odd line */ | |
566 | line_number = | |
567 | (((line_count - (AR_HEIGHT_VGA/2)) << 1) + 1); | |
568 | } else { | |
569 | line_number = line_count; | |
570 | } | |
571 | ||
572 | if (line_number == 0) { | |
573 | /* | |
574 | * It is an interrupt for line 0. | |
575 | * we have to start capture. | |
576 | */ | |
577 | disable_dma(); | |
578 | #if 0 | |
579 | ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */ | |
580 | #endif | |
581 | memcpy(ar->frame[0], ar->line_buff, ar->line_bytes); | |
582 | #if 0 | |
583 | ar_outl(0xa1861300, M32R_DMA0CR0_PORTL); | |
584 | #endif | |
585 | enable_dma(); | |
586 | ar->start_capture = 1; /* during capture */ | |
587 | return; | |
588 | } | |
589 | ||
590 | if (ar->start_capture == 1 && line_number <= (ar->height - 1)) { | |
591 | disable_dma(); | |
592 | memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes); | |
593 | ||
594 | /* | |
595 | * if captured all line of a frame, disable AR interrupt | |
596 | * and wake a process up. | |
597 | */ | |
598 | if (line_number == (ar->height - 1)) { /* end of line */ | |
599 | ||
600 | ar->start_capture = 0; | |
601 | ||
602 | /* disable AR interrupt request */ | |
603 | arvcr1 = ar_inl(ARVCR1); | |
604 | arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */ | |
605 | ar_outl(arvcr1, ARVCR1); /* disable */ | |
606 | wake_up_interruptible(&ar->wait); | |
607 | } else { | |
608 | #if 0 | |
609 | ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); | |
610 | ar_outl(0xa1861300, M32R_DMA0CR0_PORTL); | |
611 | #endif | |
612 | enable_dma(); | |
613 | } | |
614 | } | |
615 | } | |
616 | #endif | |
617 | ||
618 | /* | |
619 | * ar_initialize() | |
620 | * ar_initialize() is called by video_register_device() and | |
621 | * initializes AR LSI and peripherals. | |
622 | * | |
623 | * -1 is returned in all failures. | |
624 | * 0 is returned in success. | |
625 | * | |
626 | */ | |
627 | static int ar_initialize(struct video_device *dev) | |
628 | { | |
629 | struct ar_device *ar = dev->priv; | |
630 | unsigned long cr = 0; | |
631 | int i,found=0; | |
632 | ||
633 | DEBUG(1, "ar_initialize:\n"); | |
634 | ||
635 | /* | |
636 | * initialize AR LSI | |
637 | */ | |
638 | ar_outl(0, ARVCR0); /* assert reset of AR LSI */ | |
639 | for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */ | |
640 | cpu_relax(); | |
641 | ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */ | |
642 | for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */ | |
643 | cpu_relax(); | |
644 | ||
645 | /* AR uses INT3 of CPU as interrupt pin. */ | |
646 | ar_outl(ARINTSEL_INT3, ARINTSEL); | |
647 | ||
648 | if (ar->size == AR_SIZE_QVGA) | |
649 | cr |= ARVCR1_QVGA; | |
650 | if (ar->mode == AR_MODE_NORMAL) | |
651 | cr |= ARVCR1_NORMAL; | |
652 | ar_outl(cr, ARVCR1); | |
653 | ||
654 | /* | |
655 | * Initialize IIC so that CPU can communicate with AR LSI, | |
656 | * and send boot commands to AR LSI. | |
657 | */ | |
658 | init_iic(); | |
659 | ||
660 | for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */ | |
661 | if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */ | |
662 | found = 1; | |
663 | break; | |
664 | } | |
665 | } | |
666 | ||
667 | if (found == 0) | |
668 | return -ENODEV; | |
669 | ||
670 | printk("arv: Initializing "); | |
671 | ||
672 | iic(2,0x78,0x11,0x01,0x00); /* start */ | |
673 | iic(3,0x78,0x12,0x00,0x06); | |
674 | iic(3,0x78,0x12,0x12,0x30); | |
675 | iic(3,0x78,0x12,0x15,0x58); | |
676 | iic(3,0x78,0x12,0x17,0x30); | |
677 | printk("."); | |
678 | iic(3,0x78,0x12,0x1a,0x97); | |
679 | iic(3,0x78,0x12,0x1b,0xff); | |
680 | iic(3,0x78,0x12,0x1c,0xff); | |
681 | iic(3,0x78,0x12,0x26,0x10); | |
682 | iic(3,0x78,0x12,0x27,0x00); | |
683 | printk("."); | |
684 | iic(2,0x78,0x34,0x02,0x00); | |
685 | iic(2,0x78,0x7a,0x10,0x00); | |
686 | iic(2,0x78,0x80,0x39,0x00); | |
687 | iic(2,0x78,0x81,0xe6,0x00); | |
688 | iic(2,0x78,0x8d,0x00,0x00); | |
689 | printk("."); | |
690 | iic(2,0x78,0x8e,0x0c,0x00); | |
691 | iic(2,0x78,0x8f,0x00,0x00); | |
692 | #if 0 | |
693 | iic(2,0x78,0x90,0x00,0x00); /* AWB on=1 off=0 */ | |
694 | #endif | |
695 | iic(2,0x78,0x93,0x01,0x00); | |
696 | iic(2,0x78,0x94,0xcd,0x00); | |
697 | iic(2,0x78,0x95,0x00,0x00); | |
698 | printk("."); | |
699 | iic(2,0x78,0x96,0xa0,0x00); | |
700 | iic(2,0x78,0x97,0x00,0x00); | |
701 | iic(2,0x78,0x98,0x60,0x00); | |
702 | iic(2,0x78,0x99,0x01,0x00); | |
703 | iic(2,0x78,0x9a,0x19,0x00); | |
704 | printk("."); | |
705 | iic(2,0x78,0x9b,0x02,0x00); | |
706 | iic(2,0x78,0x9c,0xe8,0x00); | |
707 | iic(2,0x78,0x9d,0x02,0x00); | |
708 | iic(2,0x78,0x9e,0x2e,0x00); | |
709 | iic(2,0x78,0xb8,0x78,0x00); | |
710 | iic(2,0x78,0xba,0x05,0x00); | |
711 | #if 0 | |
712 | iic(2,0x78,0x83,0x8c,0x00); /* brightness */ | |
713 | #endif | |
714 | printk("."); | |
715 | ||
716 | /* color correction */ | |
717 | iic(3,0x78,0x49,0x00,0x95); /* a */ | |
718 | iic(3,0x78,0x49,0x01,0x96); /* b */ | |
719 | iic(3,0x78,0x49,0x03,0x85); /* c */ | |
720 | iic(3,0x78,0x49,0x04,0x97); /* d */ | |
721 | iic(3,0x78,0x49,0x02,0x7e); /* e(Lo) */ | |
722 | iic(3,0x78,0x49,0x05,0xa4); /* f(Lo) */ | |
723 | iic(3,0x78,0x49,0x06,0x04); /* e(Hi) */ | |
724 | iic(3,0x78,0x49,0x07,0x04); /* e(Hi) */ | |
725 | iic(2,0x78,0x48,0x01,0x00); /* on=1 off=0 */ | |
726 | ||
727 | printk("."); | |
728 | iic(2,0x78,0x11,0x00,0x00); /* end */ | |
729 | printk(" done\n"); | |
730 | return 0; | |
731 | } | |
732 | ||
733 | ||
734 | void ar_release(struct video_device *vfd) | |
735 | { | |
736 | struct ar_device *ar = vfd->priv; | |
737 | down(&ar->lock); | |
738 | video_device_release(vfd); | |
739 | } | |
740 | ||
741 | /**************************************************************************** | |
742 | * | |
743 | * Video4Linux Module functions | |
744 | * | |
745 | ****************************************************************************/ | |
746 | static struct file_operations ar_fops = { | |
747 | .owner = THIS_MODULE, | |
748 | .open = video_exclusive_open, | |
749 | .release = video_exclusive_release, | |
750 | .read = ar_read, | |
751 | .ioctl = ar_ioctl, | |
0d0fbf81 | 752 | .compat_ioctl = v4l_compat_ioctl32, |
1da177e4 LT |
753 | .llseek = no_llseek, |
754 | }; | |
755 | ||
756 | static struct video_device ar_template = { | |
757 | .owner = THIS_MODULE, | |
758 | .name = "Colour AR VGA", | |
759 | .type = VID_TYPE_CAPTURE, | |
760 | .hardware = VID_HARDWARE_ARV, | |
761 | .fops = &ar_fops, | |
762 | .release = ar_release, | |
763 | .minor = -1, | |
764 | }; | |
765 | ||
766 | #define ALIGN4(x) ((((int)(x)) & 0x3) == 0) | |
767 | static struct ar_device ardev; | |
768 | ||
769 | static int __init ar_init(void) | |
770 | { | |
771 | struct ar_device *ar; | |
772 | int ret; | |
773 | int i; | |
774 | ||
775 | DEBUG(1, "ar_init:\n"); | |
776 | ret = -EIO; | |
777 | printk(KERN_INFO "arv: Colour AR VGA driver %s\n", VERSION); | |
778 | ||
779 | ar = &ardev; | |
780 | memset(ar, 0, sizeof(struct ar_device)); | |
781 | ||
782 | #if USE_INT | |
783 | /* allocate a DMA buffer for 1 line. */ | |
784 | ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA); | |
785 | if (ar->line_buff == NULL || ! ALIGN4(ar->line_buff)) { | |
786 | printk("arv: buffer allocation failed for DMA.\n"); | |
787 | ret = -ENOMEM; | |
788 | goto out_end; | |
789 | } | |
790 | #endif | |
791 | /* allocate buffers for a frame */ | |
792 | for (i = 0; i < MAX_AR_HEIGHT; i++) { | |
793 | ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL); | |
794 | if (ar->frame[i] == NULL || ! ALIGN4(ar->frame[i])) { | |
795 | printk("arv: buffer allocation failed for frame.\n"); | |
796 | ret = -ENOMEM; | |
797 | goto out_line_buff; | |
798 | } | |
799 | } | |
800 | ||
801 | ar->vdev = video_device_alloc(); | |
802 | if (!ar->vdev) { | |
803 | printk(KERN_ERR "arv: video_device_alloc() failed\n"); | |
804 | return -ENOMEM; | |
805 | } | |
806 | memcpy(ar->vdev, &ar_template, sizeof(ar_template)); | |
807 | ar->vdev->priv = ar; | |
808 | ||
809 | if (vga) { | |
810 | ar->width = AR_WIDTH_VGA; | |
811 | ar->height = AR_HEIGHT_VGA; | |
812 | ar->size = AR_SIZE_VGA; | |
813 | ar->frame_bytes = AR_FRAME_BYTES_VGA; | |
814 | ar->line_bytes = AR_LINE_BYTES_VGA; | |
815 | if (vga_interlace) | |
816 | ar->mode = AR_MODE_INTERLACE; | |
817 | else | |
818 | ar->mode = AR_MODE_NORMAL; | |
819 | } else { | |
820 | ar->width = AR_WIDTH_QVGA; | |
821 | ar->height = AR_HEIGHT_QVGA; | |
822 | ar->size = AR_SIZE_QVGA; | |
823 | ar->frame_bytes = AR_FRAME_BYTES_QVGA; | |
824 | ar->line_bytes = AR_LINE_BYTES_QVGA; | |
825 | ar->mode = AR_MODE_INTERLACE; | |
826 | } | |
827 | init_MUTEX(&ar->lock); | |
828 | init_waitqueue_head(&ar->wait); | |
829 | ||
830 | #if USE_INT | |
831 | if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) { | |
832 | printk("arv: request_irq(%d) failed.\n", M32R_IRQ_INT3); | |
833 | ret = -EIO; | |
834 | goto out_irq; | |
835 | } | |
836 | #endif | |
837 | ||
838 | if (ar_initialize(ar->vdev) != 0) { | |
839 | printk("arv: M64278 not found.\n"); | |
840 | ret = -ENODEV; | |
841 | goto out_dev; | |
842 | } | |
843 | ||
844 | /* | |
845 | * ok, we can initialize h/w according to parameters, | |
846 | * so register video device as a frame grabber type. | |
847 | * device is named "video[0-64]". | |
848 | * video_register_device() initializes h/w using ar_initialize(). | |
849 | */ | |
850 | if (video_register_device(ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) { | |
851 | /* return -1, -ENFILE(full) or others */ | |
852 | printk("arv: register video (Colour AR) failed.\n"); | |
853 | ret = -ENODEV; | |
854 | goto out_dev; | |
855 | } | |
856 | ||
857 | printk("video%d: Found M64278 VGA (IRQ %d, Freq %dMHz).\n", | |
858 | ar->vdev->minor, M32R_IRQ_INT3, freq); | |
859 | ||
860 | return 0; | |
861 | ||
862 | out_dev: | |
863 | #if USE_INT | |
864 | free_irq(M32R_IRQ_INT3, ar); | |
865 | ||
866 | out_irq: | |
867 | #endif | |
2ea75330 JJ |
868 | for (i = 0; i < MAX_AR_HEIGHT; i++) |
869 | kfree(ar->frame[i]); | |
1da177e4 LT |
870 | |
871 | out_line_buff: | |
872 | #if USE_INT | |
873 | kfree(ar->line_buff); | |
874 | ||
875 | out_end: | |
876 | #endif | |
877 | return ret; | |
878 | } | |
879 | ||
880 | ||
881 | static int __init ar_init_module(void) | |
882 | { | |
883 | freq = (boot_cpu_data.bus_clock / 1000000); | |
884 | printk("arv: Bus clock %d\n", freq); | |
885 | if (freq != 50 && freq != 75) | |
886 | freq = DEFAULT_FREQ; | |
887 | return ar_init(); | |
888 | } | |
889 | ||
890 | static void __exit ar_cleanup_module(void) | |
891 | { | |
892 | struct ar_device *ar; | |
893 | int i; | |
894 | ||
895 | ar = &ardev; | |
896 | video_unregister_device(ar->vdev); | |
897 | #if USE_INT | |
898 | free_irq(M32R_IRQ_INT3, ar); | |
899 | #endif | |
2ea75330 JJ |
900 | for (i = 0; i < MAX_AR_HEIGHT; i++) |
901 | kfree(ar->frame[i]); | |
1da177e4 LT |
902 | #if USE_INT |
903 | kfree(ar->line_buff); | |
904 | #endif | |
905 | } | |
906 | ||
907 | module_init(ar_init_module); | |
908 | module_exit(ar_cleanup_module); | |
909 | ||
910 | MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>"); | |
911 | MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux"); | |
912 | MODULE_LICENSE("GPL"); |