Commit | Line | Data |
---|---|---|
1c1e45d1 HV |
1 | /* |
2 | * cx18 I2C functions | |
3 | * | |
4 | * Derived from ivtv-i2c.c | |
5 | * | |
6 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6afdeaf8 | 7 | * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> |
1c1e45d1 HV |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA | |
22 | * 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include "cx18-driver.h" | |
b1526421 | 26 | #include "cx18-io.h" |
1c1e45d1 HV |
27 | #include "cx18-cards.h" |
28 | #include "cx18-gpio.h" | |
50510993 | 29 | #include "cx18-i2c.h" |
ced07371 | 30 | #include "cx18-irq.h" |
1c1e45d1 | 31 | |
1c1e45d1 HV |
32 | #define CX18_REG_I2C_1_WR 0xf15000 |
33 | #define CX18_REG_I2C_1_RD 0xf15008 | |
34 | #define CX18_REG_I2C_2_WR 0xf25100 | |
35 | #define CX18_REG_I2C_2_RD 0xf25108 | |
36 | ||
37 | #define SETSCL_BIT 0x0001 | |
38 | #define SETSDL_BIT 0x0002 | |
39 | #define GETSCL_BIT 0x0004 | |
40 | #define GETSDL_BIT 0x0008 | |
41 | ||
1c1e45d1 | 42 | #define CX18_CS5345_I2C_ADDR 0x4c |
8ca95568 AW |
43 | #define CX18_Z8F0811_IR_TX_I2C_ADDR 0x70 |
44 | #define CX18_Z8F0811_IR_RX_I2C_ADDR 0x71 | |
1c1e45d1 | 45 | |
1c1e45d1 HV |
46 | /* This array should match the CX18_HW_ defines */ |
47 | static const u8 hw_addrs[] = { | |
8ca95568 AW |
48 | 0, /* CX18_HW_TUNER */ |
49 | 0, /* CX18_HW_TVEEPROM */ | |
50 | CX18_CS5345_I2C_ADDR, /* CX18_HW_CS5345 */ | |
51 | 0, /* CX18_HW_DVB */ | |
52 | 0, /* CX18_HW_418_AV */ | |
53 | 0, /* CX18_HW_GPIO_MUX */ | |
54 | 0, /* CX18_HW_GPIO_RESET_CTRL */ | |
55 | CX18_Z8F0811_IR_TX_I2C_ADDR, /* CX18_HW_Z8F0811_IR_TX_HAUP */ | |
56 | CX18_Z8F0811_IR_RX_I2C_ADDR, /* CX18_HW_Z8F0811_IR_RX_HAUP */ | |
1c1e45d1 HV |
57 | }; |
58 | ||
59 | /* This array should match the CX18_HW_ defines */ | |
60 | /* This might well become a card-specific array */ | |
61 | static const u8 hw_bus[] = { | |
ff2a2001 AW |
62 | 1, /* CX18_HW_TUNER */ |
63 | 0, /* CX18_HW_TVEEPROM */ | |
64 | 0, /* CX18_HW_CS5345 */ | |
65 | 0, /* CX18_HW_DVB */ | |
66 | 0, /* CX18_HW_418_AV */ | |
eefe1010 AW |
67 | 0, /* CX18_HW_GPIO_MUX */ |
68 | 0, /* CX18_HW_GPIO_RESET_CTRL */ | |
8ca95568 AW |
69 | 0, /* CX18_HW_Z8F0811_IR_TX_HAUP */ |
70 | 0, /* CX18_HW_Z8F0811_IR_RX_HAUP */ | |
ff2a2001 AW |
71 | }; |
72 | ||
1c1e45d1 | 73 | /* This array should match the CX18_HW_ defines */ |
af294867 | 74 | static const char * const hw_devicenames[] = { |
1c1e45d1 HV |
75 | "tuner", |
76 | "tveeprom", | |
77 | "cs5345", | |
ff2a2001 AW |
78 | "cx23418_DTV", |
79 | "cx23418_AV", | |
eefe1010 AW |
80 | "gpio_mux", |
81 | "gpio_reset_ctrl", | |
8ca95568 AW |
82 | "ir_tx_z8f0811_haup", |
83 | "ir_rx_z8f0811_haup", | |
1c1e45d1 HV |
84 | }; |
85 | ||
83526190 AW |
86 | static int cx18_i2c_new_ir(struct cx18 *cx, struct i2c_adapter *adap, u32 hw, |
87 | const char *type, u8 addr) | |
8ca95568 AW |
88 | { |
89 | struct i2c_board_info info; | |
83526190 | 90 | struct IR_i2c_init_data *init_data = &cx->ir_i2c_init_data; |
8ca95568 AW |
91 | unsigned short addr_list[2] = { addr, I2C_CLIENT_END }; |
92 | ||
93 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
94 | strlcpy(info.type, type, I2C_NAME_SIZE); | |
95 | ||
96 | /* Our default information for ir-kbd-i2c.c to use */ | |
97 | switch (hw) { | |
98 | case CX18_HW_Z8F0811_IR_RX_HAUP: | |
02858eed | 99 | init_data->ir_codes = RC_MAP_HAUPPAUGE_NEW; |
83526190 AW |
100 | init_data->internal_get_key_func = IR_KBD_GET_KEY_HAUP_XVR; |
101 | init_data->type = IR_TYPE_RC5; | |
102 | init_data->name = cx->card_name; | |
103 | info.platform_data = init_data; | |
8ca95568 AW |
104 | break; |
105 | } | |
106 | ||
9a94241a JD |
107 | return i2c_new_probed_device(adap, &info, addr_list, NULL) == NULL ? |
108 | -1 : 0; | |
8ca95568 AW |
109 | } |
110 | ||
1c1e45d1 HV |
111 | int cx18_i2c_register(struct cx18 *cx, unsigned idx) |
112 | { | |
ff2a2001 AW |
113 | struct v4l2_subdev *sd; |
114 | int bus = hw_bus[idx]; | |
115 | struct i2c_adapter *adap = &cx->i2c_adap[bus]; | |
ff2a2001 AW |
116 | const char *type = hw_devicenames[idx]; |
117 | u32 hw = 1 << idx; | |
118 | ||
119 | if (idx >= ARRAY_SIZE(hw_addrs)) | |
1c1e45d1 | 120 | return -1; |
1c1e45d1 | 121 | |
ff2a2001 AW |
122 | if (hw == CX18_HW_TUNER) { |
123 | /* special tuner group handling */ | |
53dacb15 | 124 | sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, |
aa55f3a4 | 125 | adap, NULL, type, 0, cx->card_i2c->radio); |
ff2a2001 AW |
126 | if (sd != NULL) |
127 | sd->grp_id = hw; | |
53dacb15 | 128 | sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, |
aa55f3a4 | 129 | adap, NULL, type, 0, cx->card_i2c->demod); |
ff2a2001 AW |
130 | if (sd != NULL) |
131 | sd->grp_id = hw; | |
53dacb15 | 132 | sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, |
aa55f3a4 | 133 | adap, NULL, type, 0, cx->card_i2c->tv); |
ff2a2001 AW |
134 | if (sd != NULL) |
135 | sd->grp_id = hw; | |
136 | return sd != NULL ? 0 : -1; | |
1c1e45d1 HV |
137 | } |
138 | ||
83526190 AW |
139 | if (hw & CX18_HW_IR_ANY) |
140 | return cx18_i2c_new_ir(cx, adap, hw, type, hw_addrs[idx]); | |
8ca95568 | 141 | |
ff2a2001 AW |
142 | /* Is it not an I2C device or one we do not wish to register? */ |
143 | if (!hw_addrs[idx]) | |
144 | return -1; | |
1c1e45d1 | 145 | |
8ca95568 | 146 | /* It's an I2C device other than an analog tuner or IR chip */ |
aa55f3a4 LP |
147 | sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, adap, NULL, type, hw_addrs[idx], |
148 | NULL); | |
ff2a2001 AW |
149 | if (sd != NULL) |
150 | sd->grp_id = hw; | |
151 | return sd != NULL ? 0 : -1; | |
1c1e45d1 HV |
152 | } |
153 | ||
ff2a2001 AW |
154 | /* Find the first member of the subdev group id in hw */ |
155 | struct v4l2_subdev *cx18_find_hw(struct cx18 *cx, u32 hw) | |
1c1e45d1 | 156 | { |
ff2a2001 AW |
157 | struct v4l2_subdev *result = NULL; |
158 | struct v4l2_subdev *sd; | |
1c1e45d1 | 159 | |
ff2a2001 AW |
160 | spin_lock(&cx->v4l2_dev.lock); |
161 | v4l2_device_for_each_subdev(sd, &cx->v4l2_dev) { | |
162 | if (sd->grp_id == hw) { | |
163 | result = sd; | |
1c1e45d1 HV |
164 | break; |
165 | } | |
166 | } | |
ff2a2001 AW |
167 | spin_unlock(&cx->v4l2_dev.lock); |
168 | return result; | |
1c1e45d1 HV |
169 | } |
170 | ||
171 | static void cx18_setscl(void *data, int state) | |
172 | { | |
173 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; | |
174 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | |
175 | u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR; | |
b1526421 | 176 | u32 r = cx18_read_reg(cx, addr); |
1c1e45d1 HV |
177 | |
178 | if (state) | |
3f75c616 | 179 | cx18_write_reg(cx, r | SETSCL_BIT, addr); |
1c1e45d1 | 180 | else |
3f75c616 | 181 | cx18_write_reg(cx, r & ~SETSCL_BIT, addr); |
1c1e45d1 HV |
182 | } |
183 | ||
184 | static void cx18_setsda(void *data, int state) | |
185 | { | |
186 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; | |
187 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | |
188 | u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR; | |
b1526421 | 189 | u32 r = cx18_read_reg(cx, addr); |
1c1e45d1 HV |
190 | |
191 | if (state) | |
3f75c616 | 192 | cx18_write_reg(cx, r | SETSDL_BIT, addr); |
1c1e45d1 | 193 | else |
3f75c616 | 194 | cx18_write_reg(cx, r & ~SETSDL_BIT, addr); |
1c1e45d1 HV |
195 | } |
196 | ||
197 | static int cx18_getscl(void *data) | |
198 | { | |
199 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; | |
200 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | |
201 | u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD; | |
202 | ||
b1526421 | 203 | return cx18_read_reg(cx, addr) & GETSCL_BIT; |
1c1e45d1 HV |
204 | } |
205 | ||
206 | static int cx18_getsda(void *data) | |
207 | { | |
208 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; | |
209 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | |
210 | u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD; | |
211 | ||
b1526421 | 212 | return cx18_read_reg(cx, addr) & GETSDL_BIT; |
1c1e45d1 HV |
213 | } |
214 | ||
215 | /* template for i2c-bit-algo */ | |
216 | static struct i2c_adapter cx18_i2c_adap_template = { | |
217 | .name = "cx18 i2c driver", | |
1c1e45d1 HV |
218 | .algo = NULL, /* set by i2c-algo-bit */ |
219 | .algo_data = NULL, /* filled from template */ | |
1c1e45d1 HV |
220 | .owner = THIS_MODULE, |
221 | }; | |
222 | ||
223 | #define CX18_SCL_PERIOD (10) /* usecs. 10 usec is period for a 100 KHz clock */ | |
224 | #define CX18_ALGO_BIT_TIMEOUT (2) /* seconds */ | |
225 | ||
226 | static struct i2c_algo_bit_data cx18_i2c_algo_template = { | |
227 | .setsda = cx18_setsda, | |
228 | .setscl = cx18_setscl, | |
229 | .getsda = cx18_getsda, | |
230 | .getscl = cx18_getscl, | |
231 | .udelay = CX18_SCL_PERIOD/2, /* 1/2 clock period in usec*/ | |
232 | .timeout = CX18_ALGO_BIT_TIMEOUT*HZ /* jiffies */ | |
233 | }; | |
234 | ||
1c1e45d1 HV |
235 | /* init + register i2c algo-bit adapter */ |
236 | int init_cx18_i2c(struct cx18 *cx) | |
237 | { | |
272aa396 | 238 | int i, err; |
1c1e45d1 HV |
239 | CX18_DEBUG_I2C("i2c init\n"); |
240 | ||
241 | for (i = 0; i < 2; i++) { | |
ff2a2001 | 242 | /* Setup algorithm for adapter */ |
1c1e45d1 HV |
243 | memcpy(&cx->i2c_algo[i], &cx18_i2c_algo_template, |
244 | sizeof(struct i2c_algo_bit_data)); | |
245 | cx->i2c_algo_cb_data[i].cx = cx; | |
246 | cx->i2c_algo_cb_data[i].bus_index = i; | |
247 | cx->i2c_algo[i].data = &cx->i2c_algo_cb_data[i]; | |
1c1e45d1 | 248 | |
ff2a2001 AW |
249 | /* Setup adapter */ |
250 | memcpy(&cx->i2c_adap[i], &cx18_i2c_adap_template, | |
251 | sizeof(struct i2c_adapter)); | |
252 | cx->i2c_adap[i].algo_data = &cx->i2c_algo[i]; | |
1c1e45d1 | 253 | sprintf(cx->i2c_adap[i].name + strlen(cx->i2c_adap[i].name), |
5811cf99 | 254 | " #%d-%d", cx->instance, i); |
ff2a2001 | 255 | i2c_set_adapdata(&cx->i2c_adap[i], &cx->v4l2_dev); |
3d05913d | 256 | cx->i2c_adap[i].dev.parent = &cx->pci_dev->dev; |
1c1e45d1 HV |
257 | } |
258 | ||
b1526421 | 259 | if (cx18_read_reg(cx, CX18_REG_I2C_2_WR) != 0x0003c02f) { |
1c1e45d1 | 260 | /* Reset/Unreset I2C hardware block */ |
b1526421 | 261 | /* Clock select 220MHz */ |
ced07371 AW |
262 | cx18_write_reg_expect(cx, 0x10000000, 0xc71004, |
263 | 0x00000000, 0x10001000); | |
b1526421 | 264 | /* Clock Enable */ |
ced07371 AW |
265 | cx18_write_reg_expect(cx, 0x10001000, 0xc71024, |
266 | 0x00001000, 0x10001000); | |
1c1e45d1 HV |
267 | } |
268 | /* courtesy of Steven Toth <stoth@hauppauge.com> */ | |
ced07371 | 269 | cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0); |
1c1e45d1 | 270 | mdelay(10); |
ced07371 | 271 | cx18_write_reg_expect(cx, 0x00c000c0, 0xc7001c, 0x000000c0, 0x00c000c0); |
1c1e45d1 | 272 | mdelay(10); |
ced07371 | 273 | cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0); |
53ad02ef | 274 | mdelay(10); |
1c1e45d1 | 275 | |
b1526421 | 276 | /* Set to edge-triggered intrs. */ |
ced07371 | 277 | cx18_write_reg(cx, 0x00c00000, 0xc730c8); |
b1526421 | 278 | /* Clear any stale intrs */ |
ced07371 AW |
279 | cx18_write_reg_expect(cx, HW2_I2C1_INT|HW2_I2C2_INT, HW2_INT_CLR_STATUS, |
280 | ~(HW2_I2C1_INT|HW2_I2C2_INT), HW2_I2C1_INT|HW2_I2C2_INT); | |
1c1e45d1 HV |
281 | |
282 | /* Hw I2C1 Clock Freq ~100kHz */ | |
3f75c616 | 283 | cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_1_WR); |
1c1e45d1 HV |
284 | cx18_setscl(&cx->i2c_algo_cb_data[0], 1); |
285 | cx18_setsda(&cx->i2c_algo_cb_data[0], 1); | |
286 | ||
287 | /* Hw I2C2 Clock Freq ~100kHz */ | |
3f75c616 | 288 | cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_2_WR); |
1c1e45d1 HV |
289 | cx18_setscl(&cx->i2c_algo_cb_data[1], 1); |
290 | cx18_setsda(&cx->i2c_algo_cb_data[1], 1); | |
291 | ||
eefe1010 AW |
292 | cx18_call_hw(cx, CX18_HW_GPIO_RESET_CTRL, |
293 | core, reset, (u32) CX18_GPIO_RESET_I2C); | |
1f09e8a2 | 294 | |
272aa396 JD |
295 | err = i2c_bit_add_bus(&cx->i2c_adap[0]); |
296 | if (err) | |
297 | goto err; | |
298 | err = i2c_bit_add_bus(&cx->i2c_adap[1]); | |
299 | if (err) | |
300 | goto err_del_bus_0; | |
301 | return 0; | |
302 | ||
303 | err_del_bus_0: | |
304 | i2c_del_adapter(&cx->i2c_adap[0]); | |
305 | err: | |
306 | return err; | |
1c1e45d1 HV |
307 | } |
308 | ||
309 | void exit_cx18_i2c(struct cx18 *cx) | |
310 | { | |
311 | int i; | |
312 | CX18_DEBUG_I2C("i2c exit\n"); | |
b1526421 AW |
313 | cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_1_WR) | 4, |
314 | CX18_REG_I2C_1_WR); | |
315 | cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_2_WR) | 4, | |
316 | CX18_REG_I2C_2_WR); | |
1c1e45d1 HV |
317 | |
318 | for (i = 0; i < 2; i++) { | |
319 | i2c_del_adapter(&cx->i2c_adap[i]); | |
320 | } | |
321 | } | |
322 | ||
323 | /* | |
324 | Hauppauge HVR1600 should have: | |
325 | 32 cx24227 | |
326 | 98 unknown | |
327 | a0 eeprom | |
328 | c2 tuner | |
329 | e? zilog ir | |
330 | */ |