Commit | Line | Data |
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1c1e45d1 HV |
1 | /* |
2 | * cx18 interrupt handling | |
3 | * | |
4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA | |
19 | * 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include "cx18-driver.h" | |
b1526421 | 23 | #include "cx18-io.h" |
1c1e45d1 | 24 | #include "cx18-irq.h" |
1c1e45d1 | 25 | #include "cx18-mailbox.h" |
1c1e45d1 | 26 | #include "cx18-scb.h" |
465f8a80 AW |
27 | |
28 | static void xpu_ack(struct cx18 *cx, u32 sw2) | |
29 | { | |
30 | if (sw2 & IRQ_CPU_TO_EPU_ACK) | |
31 | wake_up(&cx->mb_cpu_waitq); | |
32 | if (sw2 & IRQ_APU_TO_EPU_ACK) | |
33 | wake_up(&cx->mb_apu_waitq); | |
1c1e45d1 HV |
34 | } |
35 | ||
ee2d64f5 AW |
36 | static void epu_cmd(struct cx18 *cx, u32 sw1) |
37 | { | |
38 | if (sw1 & IRQ_CPU_TO_EPU) | |
39 | cx18_api_epu_cmd_irq(cx, CPU); | |
40 | if (sw1 & IRQ_APU_TO_EPU) | |
41 | cx18_api_epu_cmd_irq(cx, APU); | |
42 | } | |
43 | ||
1c1e45d1 HV |
44 | irqreturn_t cx18_irq_handler(int irq, void *dev_id) |
45 | { | |
46 | struct cx18 *cx = (struct cx18 *)dev_id; | |
47 | u32 sw1, sw1_mask; | |
48 | u32 sw2, sw2_mask; | |
49 | u32 hw2, hw2_mask; | |
50 | ||
465f8a80 | 51 | sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); |
b1526421 | 52 | sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; |
465f8a80 | 53 | sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); |
f056d29e AW |
54 | sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask; |
55 | hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI); | |
56 | hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask; | |
1c1e45d1 | 57 | |
f056d29e AW |
58 | if (sw1) |
59 | cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1); | |
60 | if (sw2) | |
61 | cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2); | |
62 | if (hw2) | |
63 | cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2); | |
1c1e45d1 HV |
64 | |
65 | if (sw1 || sw2 || hw2) | |
ac504417 AW |
66 | CX18_DEBUG_HI_IRQ("received interrupts " |
67 | "SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); | |
1c1e45d1 | 68 | |
ee2d64f5 AW |
69 | /* |
70 | * SW1 responses have to happen first. The sending XPU times out the | |
71 | * incoming mailboxes on us rather rapidly. | |
72 | */ | |
73 | if (sw1) | |
74 | epu_cmd(cx, sw1); | |
75 | ||
1c1e45d1 | 76 | /* To do: interrupt-based I2C handling |
465f8a80 | 77 | if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) { |
1c1e45d1 HV |
78 | } |
79 | */ | |
80 | ||
465f8a80 AW |
81 | if (sw2) |
82 | xpu_ack(cx, sw2); | |
1c1e45d1 | 83 | |
f056d29e | 84 | return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE; |
1c1e45d1 | 85 | } |