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V4L/DVB (10277): cx18, cx2341x: Fix bugs in cx18 AC3 control and comply with V4L2...
[deliverable/linux.git] / drivers / media / video / cx18 / cx18-mailbox.c
CommitLineData
1c1e45d1
HV		 1/*
2 * cx18 mailbox functions
3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
1ed9dcc8 5 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
1c1e45d1
HV		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307 USA
21 */
22
23#include <stdarg.h>
24
25#include "cx18-driver.h"
b1526421 26#include "cx18-io.h"
1c1e45d1
HV		 27#include "cx18-scb.h"
28#include "cx18-irq.h"
29#include "cx18-mailbox.h"
ee2d64f5
AW		 30#include "cx18-queue.h"
31#include "cx18-streams.h"
32
33static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
1c1e45d1
HV		 34
35#define API_FAST (1 << 2) /* Short timeout */
36#define API_SLOW (1 << 3) /* Additional 300ms timeout */
37
1c1e45d1
HV		 38struct cx18_api_info {
39 u32 cmd;
40 u8 flags; /* Flags, see above */
41 u8 rpu; /* Processing unit */
42 const char *name; /* The name of the command */
43};
44
45#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
46
47static const struct cx18_api_info api_info[] = {
48 /* MPEG encoder API */
49 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
50 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
51 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
52 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
53 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
56 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
57 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
69 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
70 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
71 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
72 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
73 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
74 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
75 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
76 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
77 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
78 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
79 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
80 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
81 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
82 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
84 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
4e6b6104 85 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
fd6b9c97
AW		 86 API_ENTRY(APU, CX18_APU_RESETAI, 0),
87 API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32, 0),
1c1e45d1
HV		 88 API_ENTRY(0, 0, 0),
89};
90
91static const struct cx18_api_info *find_api_info(u32 cmd)
92{
93 int i;
94
95 for (i = 0; api_info[i].cmd; i++)
96 if (api_info[i].cmd == cmd)
97 return &api_info[i];
98 return NULL;
99}
100
50299994
AW		 101/* Call with buf of n*11+1 bytes */
102static char *u32arr2hex(u32 data[], int n, char *buf)
ee2d64f5 103{
ee2d64f5
AW		 104 char *p;
105 int i;
106
50299994
AW		 107 for (i = 0, p = buf; i < n; i++, p += 11) {
108 /* kernel snprintf() appends '\0' always */
109 snprintf(p, 12, " %#010x", data[i]);
110 }
111 *p = '\0';
112 return buf;
113}
114
115static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
116{
117 char argstr[MAX_MB_ARGUMENTS*11+1];
118
ee2d64f5
AW		 119 if (!(cx18_debug & CX18_DBGFLG_API))
120 return;
121
ee2d64f5 122 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
50299994
AW		 123 "\n", name, mb->request, mb->ack, mb->cmd, mb->error,
124 u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
ee2d64f5
AW		 125}
126
127
128/*
129 * Functions that run in a work_queue work handling context
130 */
131
132static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
133{
bca11a57 134 u32 handle, mdl_ack_count, id;
ee2d64f5
AW		 135 struct cx18_mailbox *mb;
136 struct cx18_mdl_ack *mdl_ack;
137 struct cx18_stream *s;
138 struct cx18_buffer *buf;
139 int i;
140
141 mb = &order->mb;
142 handle = mb->args[0];
143 s = cx18_handle_to_stream(cx, handle);
144
145 if (s == NULL) {
146 CX18_WARN("Got DMA done notification for unknown/inactive"
bca11a57
AW		 147 " handle %d, %s mailbox seq no %d\n", handle,
148 (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
149 "stale" : "good", mb->request);
ee2d64f5
AW		 150 return;
151 }
152
153 mdl_ack_count = mb->args[2];
154 mdl_ack = order->mdl_ack;
155 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
bca11a57
AW		 156 id = mdl_ack->id;
157 /*
158 * Simple integrity check for processing a stale (and possibly
159 * inconsistent mailbox): make sure the buffer id is in the
160 * valid range for the stream.
161 *
162 * We go through the trouble of dealing with stale mailboxes
163 * because most of the time, the mailbox data is still valid and
164 * unchanged (and in practice the firmware ping-pongs the
165 * two mdl_ack buffers so mdl_acks are not stale).
166 *
167 * There are occasions when we get a half changed mailbox,
168 * which this check catches for a handle & id mismatch. If the
169 * handle and id do correspond, the worst case is that we
170 * completely lost the old buffer, but pick up the new buffer
171 * early (but the new mdl_ack is guaranteed to be good in this
172 * case as the firmware wouldn't point us to a new mdl_ack until
173 * it's filled in).
174 *
175 * cx18_queue_get buf() will detect the lost buffers
abb096de 176 * and send them back to q_free for fw rotation eventually.
bca11a57
AW		 177 */
178 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
179 !(id >= s->mdl_offset &&
180 id < (s->mdl_offset + s->buffers))) {
181 CX18_WARN("Fell behind! Ignoring stale mailbox with "
182 " inconsistent data. Lost buffer for mailbox "
183 "seq no %d\n", mb->request);
184 break;
185 }
186 buf = cx18_queue_get_buf(s, id, mdl_ack->data_used);
abb096de 187
bca11a57 188 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
ee2d64f5
AW		 189 if (buf == NULL) {
190 CX18_WARN("Could not find buf %d for stream %s\n",
bca11a57 191 id, s->name);
abb096de
AW		 192 /* Put as many buffers as possible back into fw use */
193 cx18_stream_load_fw_queue(s);
ee2d64f5
AW		 194 continue;
195 }
196
ee2d64f5
AW		 197 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
198 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
199 buf->bytesused);
ee2d64f5
AW		 200 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
201 buf->bytesused);
abb096de
AW		 202 }
203 /* Put as many buffers as possible back into fw use */
204 cx18_stream_load_fw_queue(s);
205 /* Put back TS buffer, since it was removed from all queues */
206 if (s->type == CX18_ENC_STREAM_TYPE_TS)
66c2a6b0 207 cx18_stream_put_buf_fw(s, buf);
ee2d64f5
AW		 208 }
209 wake_up(&cx->dma_waitq);
210 if (s->id != -1)
211 wake_up(&s->waitq);
212}
213
214static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
215{
216 char *p;
217 char *str = order->str;
218
219 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
220 p = strchr(str, '.');
221 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
222 CX18_INFO("FW version: %s\n", p - 1);
223}
224
225static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
226{
227 switch (order->rpu) {
228 case CPU:
229 {
230 switch (order->mb.cmd) {
231 case CX18_EPU_DMA_DONE:
232 epu_dma_done(cx, order);
233 break;
234 case CX18_EPU_DEBUG:
235 epu_debug(cx, order);
236 break;
237 default:
238 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
239 order->mb.cmd);
240 break;
241 }
242 break;
243 }
244 case APU:
245 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
246 order->mb.cmd);
247 break;
248 default:
249 break;
250 }
251}
252
253static
254void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order)
255{
256 atomic_set(&order->pending, 0);
257}
258
259void cx18_epu_work_handler(struct work_struct *work)
260{
261 struct cx18_epu_work_order *order =
262 container_of(work, struct cx18_epu_work_order, work);
263 struct cx18 *cx = order->cx;
264 epu_cmd(cx, order);
265 free_epu_work_order(cx, order);
266}
267
268
269/*
270 * Functions that run in an interrupt handling context
271 */
272
72a4f808 273static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
1c1e45d1 274{
990c81c8 275 struct cx18_mailbox __iomem *ack_mb;
ee2d64f5 276 u32 ack_irq, req;
1c1e45d1 277
ee2d64f5 278 switch (order->rpu) {
1c1e45d1
HV		 279 case APU:
280 ack_irq = IRQ_EPU_TO_APU_ACK;
281 ack_mb = &cx->scb->apu2epu_mb;
282 break;
283 case CPU:
284 ack_irq = IRQ_EPU_TO_CPU_ACK;
285 ack_mb = &cx->scb->cpu2epu_mb;
286 break;
287 default:
72c2d6d3 288 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
ee2d64f5
AW		 289 order->rpu, order->mb.cmd);
290 return;
1c1e45d1
HV		 291 }
292
ee2d64f5
AW		 293 req = order->mb.request;
294 /* Don't ack if the RPU has gotten impatient and timed us out */
295 if (req != cx18_readl(cx, &ack_mb->request) ||
72a4f808 296 req == cx18_readl(cx, &ack_mb->ack)) {
bca11a57
AW		 297 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
298 "incoming %s to EPU mailbox (sequence no. %u) "
299 "while processing\n",
300 rpu_str[order->rpu], rpu_str[order->rpu], req);
72a4f808 301 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
ee2d64f5 302 return;
72a4f808 303 }
ee2d64f5 304 cx18_writel(cx, req, &ack_mb->ack);
f056d29e 305 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
ee2d64f5
AW		 306 return;
307}
308
72a4f808 309static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 310{
311 u32 handle, mdl_ack_offset, mdl_ack_count;
312 struct cx18_mailbox *mb;
313
314 mb = &order->mb;
315 handle = mb->args[0];
316 mdl_ack_offset = mb->args[1];
317 mdl_ack_count = mb->args[2];
318
319 if (handle == CX18_INVALID_TASK_HANDLE ||
320 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
72a4f808 321 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 322 mb_ack_irq(cx, order);
323 return -1;
324 }
325
326 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
327 sizeof(struct cx18_mdl_ack) * mdl_ack_count);
72a4f808
AW		 328
329 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 330 mb_ack_irq(cx, order);
331 return 1;
332}
333
334static
72a4f808 335int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 336{
337 u32 str_offset;
338 char *str = order->str;
339
340 str[0] = '\0';
341 str_offset = order->mb.args[1];
342 if (str_offset) {
343 cx18_setup_page(cx, str_offset);
344 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
345 str[252] = '\0';
346 cx18_setup_page(cx, SCB_OFFSET);
347 }
348
72a4f808 349 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 350 mb_ack_irq(cx, order);
351
352 return str_offset ? 1 : 0;
353}
354
355static inline
72a4f808 356int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 357{
358 int ret = -1;
359
360 switch (order->rpu) {
361 case CPU:
362 {
363 switch (order->mb.cmd) {
364 case CX18_EPU_DMA_DONE:
72a4f808 365 ret = epu_dma_done_irq(cx, order);
ee2d64f5
AW		 366 break;
367 case CX18_EPU_DEBUG:
72a4f808 368 ret = epu_debug_irq(cx, order);
ee2d64f5
AW		 369 break;
370 default:
371 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
372 order->mb.cmd);
373 break;
374 }
375 break;
376 }
377 case APU:
378 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
379 order->mb.cmd);
380 break;
381 default:
382 break;
383 }
384 return ret;
1c1e45d1
HV		 385}
386
ee2d64f5
AW		 387static inline
388struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
389{
390 int i;
391 struct cx18_epu_work_order *order = NULL;
392
393 for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
394 /*
395 * We only need "pending" atomic to inspect its contents,
396 * and need not do a check and set because:
397 * 1. Any work handler thread only clears "pending" and only
398 * on one, particular work order at a time, per handler thread.
399 * 2. "pending" is only set here, and we're serialized because
400 * we're called in an IRQ handler context.
401 */
402 if (atomic_read(&cx->epu_work_order[i].pending) == 0) {
403 order = &cx->epu_work_order[i];
404 atomic_set(&order->pending, 1);
405 break;
406 }
407 }
408 return order;
409}
410
411void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
412{
413 struct cx18_mailbox __iomem *mb;
414 struct cx18_mailbox *order_mb;
415 struct cx18_epu_work_order *order;
ee2d64f5
AW		 416 int submit;
417
418 switch (rpu) {
419 case CPU:
420 mb = &cx->scb->cpu2epu_mb;
421 break;
422 case APU:
423 mb = &cx->scb->apu2epu_mb;
424 break;
425 default:
426 return;
427 }
428
429 order = alloc_epu_work_order_irq(cx);
430 if (order == NULL) {
431 CX18_WARN("Unable to find blank work order form to schedule "
432 "incoming mailbox command processing\n");
433 return;
434 }
435
72a4f808 436 order->flags = 0;
ee2d64f5
AW		 437 order->rpu = rpu;
438 order_mb = &order->mb;
d6c7e5f8
AW		 439
440 /* mb->cmd and mb->args[0] through mb->args[2] */
441 cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
442 /* mb->request and mb->ack. N.B. we want to read mb->ack last */
443 cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
444 2 * sizeof(u32));
ee2d64f5
AW		 445
446 if (order_mb->request == order_mb->ack) {
bca11a57
AW		 447 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
448 "incoming %s to EPU mailbox (sequence no. %u)"
449 "\n",
450 rpu_str[rpu], rpu_str[rpu], order_mb->request);
50299994
AW		 451 if (cx18_debug & CX18_DBGFLG_WARN)
452 dump_mb(cx, order_mb, "incoming");
72a4f808 453 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
ee2d64f5
AW		 454 }
455
456 /*
457 * Individual EPU command processing is responsible for ack-ing
458 * a non-stale mailbox as soon as possible
459 */
72a4f808 460 submit = epu_cmd_irq(cx, order);
ee2d64f5 461 if (submit > 0) {
572bfea7 462 queue_work(cx->work_queue, &order->work);
ee2d64f5
AW		 463 }
464}
465
466
467/*
468 * Functions called from a non-interrupt, non work_queue context
469 */
470
1c1e45d1
HV		 471static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
472{
473 const struct cx18_api_info *info = find_api_info(cmd);
ac504417 474 u32 state, irq, req, ack, err;
990c81c8 475 struct cx18_mailbox __iomem *mb;
ac504417 476 u32 __iomem *xpu_state;
1c1e45d1 477 wait_queue_head_t *waitq;
72c2d6d3 478 struct mutex *mb_lock;
330c6ec8 479 long int timeout, ret;
1c1e45d1 480 int i;
50299994 481 char argstr[MAX_MB_ARGUMENTS*11+1];
1c1e45d1
HV		 482
483 if (info == NULL) {
484 CX18_WARN("unknown cmd %x\n", cmd);
485 return -EINVAL;
486 }
487
50299994
AW		 488 if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
489 if (cmd == CX18_CPU_DE_SET_MDL) {
490 if (cx18_debug & CX18_DBGFLG_HIGHVOL)
491 CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
492 info->name, cmd,
493 u32arr2hex(data, args, argstr));
494 } else
495 CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
496 info->name, cmd,
497 u32arr2hex(data, args, argstr));
498 }
72c2d6d3
AW		 499
500 switch (info->rpu) {
501 case APU:
502 waitq = &cx->mb_apu_waitq;
503 mb_lock = &cx->epu2apu_mb_lock;
ac504417
AW		 504 irq = IRQ_EPU_TO_APU;
505 mb = &cx->scb->epu2apu_mb;
506 xpu_state = &cx->scb->apu_state;
72c2d6d3
AW		 507 break;
508 case CPU:
509 waitq = &cx->mb_cpu_waitq;
510 mb_lock = &cx->epu2cpu_mb_lock;
ac504417
AW		 511 irq = IRQ_EPU_TO_CPU;
512 mb = &cx->scb->epu2cpu_mb;
513 xpu_state = &cx->scb->cpu_state;
72c2d6d3
AW		 514 break;
515 default:
516 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
517 return -EINVAL;
518 }
519
520 mutex_lock(mb_lock);
ac504417
AW		 521 /*
522 * Wait for an in-use mailbox to complete
523 *
524 * If the XPU is responding with Ack's, the mailbox shouldn't be in
525 * a busy state, since we serialize access to it on our end.
526 *
527 * If the wait for ack after sending a previous command was interrupted
528 * by a signal, we may get here and find a busy mailbox. After waiting,
529 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
530 */
531 state = cx18_readl(cx, xpu_state);
532 req = cx18_readl(cx, &mb->request);
2bb49f1b 533 timeout = msecs_to_jiffies(10);
ac504417
AW		 534 ret = wait_event_timeout(*waitq,
535 (ack = cx18_readl(cx, &mb->ack)) == req,
330c6ec8 536 timeout);
ac504417
AW		 537 if (req != ack) {
538 /* waited long enough, make the mbox "not busy" from our end */
539 cx18_writel(cx, req, &mb->ack);
540 CX18_ERR("mbox was found stuck busy when setting up for %s; "
541 "clearing busy and trying to proceed\n", info->name);
330c6ec8 542 } else if (ret != timeout)
2bb49f1b
AW		 543 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
544 jiffies_to_msecs(timeout-ret));
ac504417
AW		 545
546 /* Build the outgoing mailbox */
547 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
1c1e45d1 548
b1526421 549 cx18_writel(cx, cmd, &mb->cmd);
1c1e45d1 550 for (i = 0; i < args; i++)
b1526421
AW		 551 cx18_writel(cx, data[i], &mb->args[i]);
552 cx18_writel(cx, 0, &mb->error);
553 cx18_writel(cx, req, &mb->request);
ac504417 554 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
1c1e45d1 555
330c6ec8
AW		 556 /*
557 * Notify the XPU and wait for it to send an Ack back
330c6ec8 558 */
2bb49f1b 559 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
ac504417
AW		 560
561 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
562 irq, info->name);
f056d29e 563 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
1c1e45d1 564
330c6ec8 565 ret = wait_event_timeout(
72c2d6d3
AW		 566 *waitq,
567 cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
330c6ec8 568 timeout);
2bb49f1b 569
ac504417 570 if (ret == 0) {
72c2d6d3 571 /* Timed out */
72c2d6d3 572 mutex_unlock(mb_lock);
ec984f43
AW		 573 CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU "
574 "acknowledgement\n",
575 info->name, jiffies_to_msecs(timeout));
1c1e45d1 576 return -EINVAL;
330c6ec8
AW		 577 }
578
330c6ec8
AW		 579 if (ret != timeout)
580 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
2bb49f1b 581 jiffies_to_msecs(timeout-ret), info->name);
72c2d6d3 582
ac504417 583 /* Collect data returned by the XPU */
1c1e45d1 584 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
b1526421
AW		 585 data[i] = cx18_readl(cx, &mb->args[i]);
586 err = cx18_readl(cx, &mb->error);
72c2d6d3 587 mutex_unlock(mb_lock);
ac504417
AW		 588
589 /*
590 * Wait for XPU to perform extra actions for the caller in some cases.
591 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
592 * back in a burst shortly thereafter
593 */
72c2d6d3 594 if (info->flags & API_SLOW)
1c1e45d1 595 cx18_msleep_timeout(300, 0);
ac504417 596
1c1e45d1
HV		 597 if (err)
598 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
599 info->name);
600 return err ? -EIO : 0;
601}
602
603int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
604{
ac504417 605 return cx18_api_call(cx, cmd, args, data);
1c1e45d1
HV		 606}
607
608static int cx18_set_filter_param(struct cx18_stream *s)
609{
610 struct cx18 *cx = s->cx;
611 u32 mode;
612 int ret;
613
614 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
615 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
616 s->handle, 1, mode, cx->spatial_strength);
617 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
618 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
619 s->handle, 0, mode, cx->temporal_strength);
620 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
621 s->handle, 2, cx->filter_mode >> 2, 0);
622 return ret;
623}
624
625int cx18_api_func(void *priv, u32 cmd, int in, int out,
626 u32 data[CX2341X_MBOX_MAX_DATA])
627{
50b86bac
AW		 628 struct cx18_api_func_private *api_priv = priv;
629 struct cx18 *cx = api_priv->cx;
630 struct cx18_stream *s = api_priv->s;
1c1e45d1
HV		 631
632 switch (cmd) {
633 case CX2341X_ENC_SET_OUTPUT_PORT:
634 return 0;
635 case CX2341X_ENC_SET_FRAME_RATE:
636 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
637 s->handle, 0, 0, 0, 0, data[0]);
638 case CX2341X_ENC_SET_FRAME_SIZE:
639 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
640 s->handle, data[1], data[0]);
641 case CX2341X_ENC_SET_STREAM_TYPE:
642 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
643 s->handle, data[0]);
644 case CX2341X_ENC_SET_ASPECT_RATIO:
645 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
646 s->handle, data[0]);
647
648 case CX2341X_ENC_SET_GOP_PROPERTIES:
649 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
650 s->handle, data[0], data[1]);
651 case CX2341X_ENC_SET_GOP_CLOSURE:
652 return 0;
653 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
654 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
655 s->handle, data[0]);
656 case CX2341X_ENC_MUTE_AUDIO:
657 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
658 s->handle, data[0]);
659 case CX2341X_ENC_SET_BIT_RATE:
660 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
661 s->handle, data[0], data[1], data[2], data[3]);
662 case CX2341X_ENC_MUTE_VIDEO:
663 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
664 s->handle, data[0]);
665 case CX2341X_ENC_SET_FRAME_DROP_RATE:
666 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
667 s->handle, data[0]);
668 case CX2341X_ENC_MISC:
669 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
670 s->handle, data[0], data[1], data[2]);
671 case CX2341X_ENC_SET_DNR_FILTER_MODE:
672 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
673 return cx18_set_filter_param(s);
674 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
675 cx->spatial_strength = data[0];
676 cx->temporal_strength = data[1];
677 return cx18_set_filter_param(s);
678 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
679 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
680 s->handle, data[0], data[1]);
681 case CX2341X_ENC_SET_CORING_LEVELS:
682 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
683 s->handle, data[0], data[1], data[2], data[3]);
684 }
685 CX18_WARN("Unknown cmd %x\n", cmd);
686 return 0;
687}
688
689int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
690 u32 cmd, int args, ...)
691{
692 va_list ap;
693 int i;
694
695 va_start(ap, args);
696 for (i = 0; i < args; i++)
697 data[i] = va_arg(ap, u32);
698 va_end(ap);
699 return cx18_api(cx, cmd, args, data);
700}
701
702int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
703{
704 u32 data[MAX_MB_ARGUMENTS];
705 va_list ap;
706 int i;
707
708 if (cx == NULL) {
709 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
710 return 0;
711 }
712 if (args > MAX_MB_ARGUMENTS) {
713 CX18_ERR("args too big (cmd=%x)\n", cmd);
714 args = MAX_MB_ARGUMENTS;
715 }
716 va_start(ap, args);
717 for (i = 0; i < args; i++)
718 data[i] = va_arg(ap, u32);
719 va_end(ap);
720 return cx18_api(cx, cmd, args, data);
721}
Linux kernel - Deliverables
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