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V4L/DVB (9724): cx18: Streamline cx18-io[ch] wrappers and enforce MMIO retry strategy
[deliverable/linux.git] / drivers / media / video / cx18 / cx18-mailbox.c
CommitLineData
1c1e45d1
HV		 1/*
2 * cx18 mailbox functions
3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
19 * 02111-1307 USA
20 */
21
22#include <stdarg.h>
23
24#include "cx18-driver.h"
b1526421 25#include "cx18-io.h"
1c1e45d1
HV		 26#include "cx18-scb.h"
27#include "cx18-irq.h"
28#include "cx18-mailbox.h"
ee2d64f5
AW		 29#include "cx18-queue.h"
30#include "cx18-streams.h"
31
32static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
1c1e45d1
HV		 33
34#define API_FAST (1 << 2) /* Short timeout */
35#define API_SLOW (1 << 3) /* Additional 300ms timeout */
36
1c1e45d1
HV		 37struct cx18_api_info {
38 u32 cmd;
39 u8 flags; /* Flags, see above */
40 u8 rpu; /* Processing unit */
41 const char *name; /* The name of the command */
42};
43
44#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
45
46static const struct cx18_api_info api_info[] = {
47 /* MPEG encoder API */
48 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
49 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
50 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
51 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
52 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
53 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
56 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
57 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
69 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
70 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
71 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
72 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
73 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
74 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
75 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
76 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
77 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
78 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
79 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
80 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
81 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
82 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
81cb727d 84 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST),
4e6b6104 85 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
1c1e45d1
HV		 86 API_ENTRY(0, 0, 0),
87};
88
89static const struct cx18_api_info *find_api_info(u32 cmd)
90{
91 int i;
92
93 for (i = 0; api_info[i].cmd; i++)
94 if (api_info[i].cmd == cmd)
95 return &api_info[i];
96 return NULL;
97}
98
ee2d64f5
AW		 99static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
100{
101 char argstr[MAX_MB_ARGUMENTS*11+1];
102 char *p;
103 int i;
104
105 if (!(cx18_debug & CX18_DBGFLG_API))
106 return;
107
108 for (i = 0, p = argstr; i < MAX_MB_ARGUMENTS; i++, p += 11) {
109 /* kernel snprintf() appends '\0' always */
110 snprintf(p, 12, " %#010x", mb->args[i]);
111 }
112 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
113 "\n", name, mb->request, mb->ack, mb->cmd, mb->error, argstr);
114}
115
116
117/*
118 * Functions that run in a work_queue work handling context
119 */
120
121static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
122{
123 u32 handle, mdl_ack_count;
124 struct cx18_mailbox *mb;
125 struct cx18_mdl_ack *mdl_ack;
126 struct cx18_stream *s;
127 struct cx18_buffer *buf;
128 int i;
129
130 mb = &order->mb;
131 handle = mb->args[0];
132 s = cx18_handle_to_stream(cx, handle);
133
134 if (s == NULL) {
135 CX18_WARN("Got DMA done notification for unknown/inactive"
136 " handle %d\n", handle);
137 return;
138 }
139
140 mdl_ack_count = mb->args[2];
141 mdl_ack = order->mdl_ack;
142 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
143 buf = cx18_queue_get_buf(s, mdl_ack->id, mdl_ack->data_used);
144 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name,
145 mdl_ack->id);
146 if (buf == NULL) {
147 CX18_WARN("Could not find buf %d for stream %s\n",
148 mdl_ack->id, s->name);
149 continue;
150 }
151
152 cx18_buf_sync_for_cpu(s, buf);
153 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
154 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
155 buf->bytesused);
156
157 dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
158 buf->bytesused);
159
160 cx18_buf_sync_for_device(s, buf);
161
162 if (s->handle != CX18_INVALID_TASK_HANDLE &&
163 test_bit(CX18_F_S_STREAMING, &s->s_flags))
164 cx18_vapi(cx,
165 CX18_CPU_DE_SET_MDL, 5, s->handle,
166 (void __iomem *)
167 &cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
168 1, buf->id, s->buf_size);
169 } else
170 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
171 }
172 wake_up(&cx->dma_waitq);
173 if (s->id != -1)
174 wake_up(&s->waitq);
175}
176
177static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
178{
179 char *p;
180 char *str = order->str;
181
182 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
183 p = strchr(str, '.');
184 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
185 CX18_INFO("FW version: %s\n", p - 1);
186}
187
188static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
189{
190 switch (order->rpu) {
191 case CPU:
192 {
193 switch (order->mb.cmd) {
194 case CX18_EPU_DMA_DONE:
195 epu_dma_done(cx, order);
196 break;
197 case CX18_EPU_DEBUG:
198 epu_debug(cx, order);
199 break;
200 default:
201 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
202 order->mb.cmd);
203 break;
204 }
205 break;
206 }
207 case APU:
208 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
209 order->mb.cmd);
210 break;
211 default:
212 break;
213 }
214}
215
216static
217void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order)
218{
219 atomic_set(&order->pending, 0);
220}
221
222void cx18_epu_work_handler(struct work_struct *work)
223{
224 struct cx18_epu_work_order *order =
225 container_of(work, struct cx18_epu_work_order, work);
226 struct cx18 *cx = order->cx;
227 epu_cmd(cx, order);
228 free_epu_work_order(cx, order);
229}
230
231
232/*
233 * Functions that run in an interrupt handling context
234 */
235
72a4f808 236static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
1c1e45d1 237{
990c81c8 238 struct cx18_mailbox __iomem *ack_mb;
ee2d64f5 239 u32 ack_irq, req;
1c1e45d1 240
ee2d64f5 241 switch (order->rpu) {
1c1e45d1
HV		 242 case APU:
243 ack_irq = IRQ_EPU_TO_APU_ACK;
244 ack_mb = &cx->scb->apu2epu_mb;
245 break;
246 case CPU:
247 ack_irq = IRQ_EPU_TO_CPU_ACK;
248 ack_mb = &cx->scb->cpu2epu_mb;
249 break;
250 default:
72c2d6d3 251 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
ee2d64f5
AW		 252 order->rpu, order->mb.cmd);
253 return;
1c1e45d1
HV		 254 }
255
ee2d64f5
AW		 256 req = order->mb.request;
257 /* Don't ack if the RPU has gotten impatient and timed us out */
258 if (req != cx18_readl(cx, &ack_mb->request) ||
72a4f808
AW		 259 req == cx18_readl(cx, &ack_mb->ack)) {
260 CX18_WARN("Possibly falling behind: %s self-ack'ed our incoming"
261 " %s to EPU mailbox (sequence no. %u) while "
262 "processing\n",
263 rpu_str[order->rpu], rpu_str[order->rpu], req);
264 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
ee2d64f5 265 return;
72a4f808 266 }
ee2d64f5 267 cx18_writel(cx, req, &ack_mb->ack);
f056d29e 268 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
ee2d64f5
AW		 269 return;
270}
271
72a4f808 272static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 273{
274 u32 handle, mdl_ack_offset, mdl_ack_count;
275 struct cx18_mailbox *mb;
276
277 mb = &order->mb;
278 handle = mb->args[0];
279 mdl_ack_offset = mb->args[1];
280 mdl_ack_count = mb->args[2];
281
282 if (handle == CX18_INVALID_TASK_HANDLE ||
283 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
72a4f808 284 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 285 mb_ack_irq(cx, order);
286 return -1;
287 }
288
289 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
290 sizeof(struct cx18_mdl_ack) * mdl_ack_count);
72a4f808
AW		 291
292 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 293 mb_ack_irq(cx, order);
294 return 1;
295}
296
297static
72a4f808 298int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 299{
300 u32 str_offset;
301 char *str = order->str;
302
303 str[0] = '\0';
304 str_offset = order->mb.args[1];
305 if (str_offset) {
306 cx18_setup_page(cx, str_offset);
307 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
308 str[252] = '\0';
309 cx18_setup_page(cx, SCB_OFFSET);
310 }
311
72a4f808 312 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
ee2d64f5
AW		 313 mb_ack_irq(cx, order);
314
315 return str_offset ? 1 : 0;
316}
317
318static inline
72a4f808 319int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
ee2d64f5
AW		 320{
321 int ret = -1;
322
323 switch (order->rpu) {
324 case CPU:
325 {
326 switch (order->mb.cmd) {
327 case CX18_EPU_DMA_DONE:
72a4f808 328 ret = epu_dma_done_irq(cx, order);
ee2d64f5
AW		 329 break;
330 case CX18_EPU_DEBUG:
72a4f808 331 ret = epu_debug_irq(cx, order);
ee2d64f5
AW		 332 break;
333 default:
334 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
335 order->mb.cmd);
336 break;
337 }
338 break;
339 }
340 case APU:
341 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
342 order->mb.cmd);
343 break;
344 default:
345 break;
346 }
347 return ret;
1c1e45d1
HV		 348}
349
ee2d64f5
AW		 350static inline
351struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
352{
353 int i;
354 struct cx18_epu_work_order *order = NULL;
355
356 for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
357 /*
358 * We only need "pending" atomic to inspect its contents,
359 * and need not do a check and set because:
360 * 1. Any work handler thread only clears "pending" and only
361 * on one, particular work order at a time, per handler thread.
362 * 2. "pending" is only set here, and we're serialized because
363 * we're called in an IRQ handler context.
364 */
365 if (atomic_read(&cx->epu_work_order[i].pending) == 0) {
366 order = &cx->epu_work_order[i];
367 atomic_set(&order->pending, 1);
368 break;
369 }
370 }
371 return order;
372}
373
374void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
375{
376 struct cx18_mailbox __iomem *mb;
377 struct cx18_mailbox *order_mb;
378 struct cx18_epu_work_order *order;
ee2d64f5
AW		 379 int submit;
380
381 switch (rpu) {
382 case CPU:
383 mb = &cx->scb->cpu2epu_mb;
384 break;
385 case APU:
386 mb = &cx->scb->apu2epu_mb;
387 break;
388 default:
389 return;
390 }
391
392 order = alloc_epu_work_order_irq(cx);
393 if (order == NULL) {
394 CX18_WARN("Unable to find blank work order form to schedule "
395 "incoming mailbox command processing\n");
396 return;
397 }
398
72a4f808 399 order->flags = 0;
ee2d64f5
AW		 400 order->rpu = rpu;
401 order_mb = &order->mb;
402 cx18_memcpy_fromio(cx, order_mb, mb, sizeof(struct cx18_mailbox));
403
404 if (order_mb->request == order_mb->ack) {
405 CX18_WARN("Possibly falling behind: %s self-ack'ed our incoming"
406 " %s to EPU mailbox (sequence no. %u)\n",
407 rpu_str[rpu], rpu_str[rpu], order_mb->request);
408 dump_mb(cx, order_mb, "incoming");
72a4f808 409 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
ee2d64f5
AW		 410 }
411
412 /*
413 * Individual EPU command processing is responsible for ack-ing
414 * a non-stale mailbox as soon as possible
415 */
72a4f808 416 submit = epu_cmd_irq(cx, order);
ee2d64f5 417 if (submit > 0) {
18b5dc2e 418 queue_work(cx18_work_queue, &order->work);
ee2d64f5
AW		 419 }
420}
421
422
423/*
424 * Functions called from a non-interrupt, non work_queue context
425 */
426
330c6ec8
AW		 427static void cx18_api_log_ack_delay(struct cx18 *cx, int msecs)
428{
429 if (msecs > CX18_MAX_MB_ACK_DELAY)
430 msecs = CX18_MAX_MB_ACK_DELAY;
431 atomic_inc(&cx->mbox_stats.mb_ack_delay[msecs]);
432}
1c1e45d1
HV		 433
434static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
435{
436 const struct cx18_api_info *info = find_api_info(cmd);
ac504417 437 u32 state, irq, req, ack, err;
990c81c8 438 struct cx18_mailbox __iomem *mb;
ac504417 439 u32 __iomem *xpu_state;
1c1e45d1 440 wait_queue_head_t *waitq;
72c2d6d3 441 struct mutex *mb_lock;
330c6ec8 442 long int timeout, ret;
1c1e45d1
HV		 443 int i;
444
445 if (info == NULL) {
446 CX18_WARN("unknown cmd %x\n", cmd);
447 return -EINVAL;
448 }
449
450 if (cmd == CX18_CPU_DE_SET_MDL)
451 CX18_DEBUG_HI_API("%s\n", info->name);
452 else
453 CX18_DEBUG_API("%s\n", info->name);
72c2d6d3
AW		 454
455 switch (info->rpu) {
456 case APU:
457 waitq = &cx->mb_apu_waitq;
458 mb_lock = &cx->epu2apu_mb_lock;
ac504417
AW		 459 irq = IRQ_EPU_TO_APU;
460 mb = &cx->scb->epu2apu_mb;
461 xpu_state = &cx->scb->apu_state;
72c2d6d3
AW		 462 break;
463 case CPU:
464 waitq = &cx->mb_cpu_waitq;
465 mb_lock = &cx->epu2cpu_mb_lock;
ac504417
AW		 466 irq = IRQ_EPU_TO_CPU;
467 mb = &cx->scb->epu2cpu_mb;
468 xpu_state = &cx->scb->cpu_state;
72c2d6d3
AW		 469 break;
470 default:
471 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
472 return -EINVAL;
473 }
474
475 mutex_lock(mb_lock);
ac504417
AW		 476 /*
477 * Wait for an in-use mailbox to complete
478 *
479 * If the XPU is responding with Ack's, the mailbox shouldn't be in
480 * a busy state, since we serialize access to it on our end.
481 *
482 * If the wait for ack after sending a previous command was interrupted
483 * by a signal, we may get here and find a busy mailbox. After waiting,
484 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
485 */
486 state = cx18_readl(cx, xpu_state);
487 req = cx18_readl(cx, &mb->request);
330c6ec8 488 timeout = msecs_to_jiffies(20); /* 1 field at 50 Hz vertical refresh */
ac504417
AW		 489 ret = wait_event_timeout(*waitq,
490 (ack = cx18_readl(cx, &mb->ack)) == req,
330c6ec8 491 timeout);
ac504417
AW		 492 if (req != ack) {
493 /* waited long enough, make the mbox "not busy" from our end */
494 cx18_writel(cx, req, &mb->ack);
495 CX18_ERR("mbox was found stuck busy when setting up for %s; "
496 "clearing busy and trying to proceed\n", info->name);
330c6ec8 497 } else if (ret != timeout)
ac504417 498 CX18_DEBUG_API("waited %u usecs for busy mbox to be acked\n",
330c6ec8 499 jiffies_to_usecs(timeout-ret));
ac504417
AW		 500
501 /* Build the outgoing mailbox */
502 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
1c1e45d1 503
b1526421 504 cx18_writel(cx, cmd, &mb->cmd);
1c1e45d1 505 for (i = 0; i < args; i++)
b1526421
AW		 506 cx18_writel(cx, data[i], &mb->args[i]);
507 cx18_writel(cx, 0, &mb->error);
508 cx18_writel(cx, req, &mb->request);
ac504417 509 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
1c1e45d1 510
330c6ec8
AW		 511 /*
512 * Notify the XPU and wait for it to send an Ack back
513 * 21 ms = ~ 0.5 frames at a frame rate of 24 fps
514 * 42 ms = ~ 1 frame at a frame rate of 24 fps
515 */
516 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 21 : 42);
ac504417
AW		 517
518 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
519 irq, info->name);
f056d29e 520 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
1c1e45d1 521
330c6ec8 522 ret = wait_event_timeout(
72c2d6d3
AW		 523 *waitq,
524 cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
330c6ec8 525 timeout);
ac504417 526 if (ret == 0) {
72c2d6d3 527 /* Timed out */
72c2d6d3 528 mutex_unlock(mb_lock);
330c6ec8
AW		 529 i = jiffies_to_msecs(timeout);
530 cx18_api_log_ack_delay(cx, i);
531 CX18_WARN("sending %s timed out waiting %d msecs for RPU "
532 "acknowledgement\n", info->name, i);
1c1e45d1 533 return -EINVAL;
ac504417 534 } else if (ret < 0) {
72c2d6d3 535 /* Interrupted */
72c2d6d3 536 mutex_unlock(mb_lock);
ac504417
AW		 537 CX18_WARN("sending %s was interrupted waiting for RPU"
538 "acknowledgement\n", info->name);
72c2d6d3 539 return -EINTR;
330c6ec8
AW		 540 }
541
542 i = jiffies_to_msecs(timeout-ret);
543 cx18_api_log_ack_delay(cx, i);
544 if (ret != timeout)
545 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
546 i, info->name);
72c2d6d3 547
ac504417 548 /* Collect data returned by the XPU */
1c1e45d1 549 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
b1526421
AW		 550 data[i] = cx18_readl(cx, &mb->args[i]);
551 err = cx18_readl(cx, &mb->error);
72c2d6d3 552 mutex_unlock(mb_lock);
ac504417
AW		 553
554 /*
555 * Wait for XPU to perform extra actions for the caller in some cases.
556 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
557 * back in a burst shortly thereafter
558 */
72c2d6d3 559 if (info->flags & API_SLOW)
1c1e45d1 560 cx18_msleep_timeout(300, 0);
ac504417 561
1c1e45d1
HV		 562 if (err)
563 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
564 info->name);
565 return err ? -EIO : 0;
566}
567
568int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
569{
ac504417 570 return cx18_api_call(cx, cmd, args, data);
1c1e45d1
HV		 571}
572
573static int cx18_set_filter_param(struct cx18_stream *s)
574{
575 struct cx18 *cx = s->cx;
576 u32 mode;
577 int ret;
578
579 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
580 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
581 s->handle, 1, mode, cx->spatial_strength);
582 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
583 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
584 s->handle, 0, mode, cx->temporal_strength);
585 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
586 s->handle, 2, cx->filter_mode >> 2, 0);
587 return ret;
588}
589
590int cx18_api_func(void *priv, u32 cmd, int in, int out,
591 u32 data[CX2341X_MBOX_MAX_DATA])
592{
593 struct cx18 *cx = priv;
594 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
595
596 switch (cmd) {
597 case CX2341X_ENC_SET_OUTPUT_PORT:
598 return 0;
599 case CX2341X_ENC_SET_FRAME_RATE:
600 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
601 s->handle, 0, 0, 0, 0, data[0]);
602 case CX2341X_ENC_SET_FRAME_SIZE:
603 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
604 s->handle, data[1], data[0]);
605 case CX2341X_ENC_SET_STREAM_TYPE:
606 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
607 s->handle, data[0]);
608 case CX2341X_ENC_SET_ASPECT_RATIO:
609 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
610 s->handle, data[0]);
611
612 case CX2341X_ENC_SET_GOP_PROPERTIES:
613 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
614 s->handle, data[0], data[1]);
615 case CX2341X_ENC_SET_GOP_CLOSURE:
616 return 0;
617 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
618 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
619 s->handle, data[0]);
620 case CX2341X_ENC_MUTE_AUDIO:
621 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
622 s->handle, data[0]);
623 case CX2341X_ENC_SET_BIT_RATE:
624 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
625 s->handle, data[0], data[1], data[2], data[3]);
626 case CX2341X_ENC_MUTE_VIDEO:
627 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
628 s->handle, data[0]);
629 case CX2341X_ENC_SET_FRAME_DROP_RATE:
630 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
631 s->handle, data[0]);
632 case CX2341X_ENC_MISC:
633 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
634 s->handle, data[0], data[1], data[2]);
635 case CX2341X_ENC_SET_DNR_FILTER_MODE:
636 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
637 return cx18_set_filter_param(s);
638 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
639 cx->spatial_strength = data[0];
640 cx->temporal_strength = data[1];
641 return cx18_set_filter_param(s);
642 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
643 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
644 s->handle, data[0], data[1]);
645 case CX2341X_ENC_SET_CORING_LEVELS:
646 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
647 s->handle, data[0], data[1], data[2], data[3]);
648 }
649 CX18_WARN("Unknown cmd %x\n", cmd);
650 return 0;
651}
652
653int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
654 u32 cmd, int args, ...)
655{
656 va_list ap;
657 int i;
658
659 va_start(ap, args);
660 for (i = 0; i < args; i++)
661 data[i] = va_arg(ap, u32);
662 va_end(ap);
663 return cx18_api(cx, cmd, args, data);
664}
665
666int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
667{
668 u32 data[MAX_MB_ARGUMENTS];
669 va_list ap;
670 int i;
671
672 if (cx == NULL) {
673 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
674 return 0;
675 }
676 if (args > MAX_MB_ARGUMENTS) {
677 CX18_ERR("args too big (cmd=%x)\n", cmd);
678 args = MAX_MB_ARGUMENTS;
679 }
680 va_start(ap, args);
681 for (i = 0; i < args; i++)
682 data[i] = va_arg(ap, u32);
683 va_end(ap);
684 return cx18_api(cx, cmd, args, data);
685}
Linux kernel - Deliverables
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