[media] cx18: Use the control framework
[deliverable/linux.git] / drivers / media / video / cx18 / cx18-streams.c
CommitLineData
1c1e45d1
HV
1/*
2 * cx18 init/start/stop/exit stream functions
3 *
4 * Derived from ivtv-streams.c
5 *
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6afdeaf8 7 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
1c1e45d1
HV
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
22 * 02111-1307 USA
23 */
24
25#include "cx18-driver.h"
b1526421 26#include "cx18-io.h"
1c1e45d1
HV
27#include "cx18-fileops.h"
28#include "cx18-mailbox.h"
29#include "cx18-i2c.h"
30#include "cx18-queue.h"
31#include "cx18-ioctl.h"
32#include "cx18-streams.h"
33#include "cx18-cards.h"
34#include "cx18-scb.h"
1c1e45d1
HV
35#include "cx18-dvb.h"
36
37#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
38
bec43661 39static struct v4l2_file_operations cx18_v4l2_enc_fops = {
daf20d95
HV
40 .owner = THIS_MODULE,
41 .read = cx18_v4l2_read,
42 .open = cx18_v4l2_open,
3b6fe58f 43 /* FIXME change to video_ioctl2 if serialization lock can be removed */
78b055be 44 .unlocked_ioctl = cx18_v4l2_ioctl,
daf20d95
HV
45 .release = cx18_v4l2_close,
46 .poll = cx18_v4l2_enc_poll,
1c1e45d1
HV
47};
48
49/* offset from 0 to register ts v4l2 minors on */
50#define CX18_V4L2_ENC_TS_OFFSET 16
51/* offset from 0 to register pcm v4l2 minors on */
52#define CX18_V4L2_ENC_PCM_OFFSET 24
53/* offset from 0 to register yuv v4l2 minors on */
54#define CX18_V4L2_ENC_YUV_OFFSET 32
55
56static struct {
57 const char *name;
58 int vfl_type;
dd89601d 59 int num_offset;
1c1e45d1
HV
60 int dma;
61 enum v4l2_buf_type buf_type;
1c1e45d1
HV
62} cx18_stream_info[] = {
63 { /* CX18_ENC_STREAM_TYPE_MPG */
64 "encoder MPEG",
65 VFL_TYPE_GRABBER, 0,
66 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
67 },
68 { /* CX18_ENC_STREAM_TYPE_TS */
69 "TS",
70 VFL_TYPE_GRABBER, -1,
71 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
72 },
73 { /* CX18_ENC_STREAM_TYPE_YUV */
74 "encoder YUV",
75 VFL_TYPE_GRABBER, CX18_V4L2_ENC_YUV_OFFSET,
76 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
77 },
78 { /* CX18_ENC_STREAM_TYPE_VBI */
79 "encoder VBI",
80 VFL_TYPE_VBI, 0,
81 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VBI_CAPTURE,
1c1e45d1
HV
82 },
83 { /* CX18_ENC_STREAM_TYPE_PCM */
84 "encoder PCM audio",
85 VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET,
86 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_PRIVATE,
1c1e45d1
HV
87 },
88 { /* CX18_ENC_STREAM_TYPE_IDX */
89 "encoder IDX",
90 VFL_TYPE_GRABBER, -1,
91 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
92 },
93 { /* CX18_ENC_STREAM_TYPE_RAD */
94 "encoder radio",
95 VFL_TYPE_RADIO, 0,
96 PCI_DMA_NONE, V4L2_BUF_TYPE_PRIVATE,
1c1e45d1
HV
97 },
98};
99
100static void cx18_stream_init(struct cx18 *cx, int type)
101{
102 struct cx18_stream *s = &cx->streams[type];
3d05913d 103 struct video_device *video_dev = s->video_dev;
1c1e45d1 104
3d05913d 105 /* we need to keep video_dev, so restore it afterwards */
1c1e45d1 106 memset(s, 0, sizeof(*s));
3d05913d 107 s->video_dev = video_dev;
1c1e45d1
HV
108
109 /* initialize cx18_stream fields */
754f9969 110 s->dvb = NULL;
1c1e45d1
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111 s->cx = cx;
112 s->type = type;
113 s->name = cx18_stream_info[type].name;
d3c5e707 114 s->handle = CX18_INVALID_TASK_HANDLE;
1c1e45d1
HV
115
116 s->dma = cx18_stream_info[type].dma;
6ecd86dc 117 s->buffers = cx->stream_buffers[type];
1c1e45d1 118 s->buf_size = cx->stream_buf_size[type];
52fcb3ec
AW
119 INIT_LIST_HEAD(&s->buf_pool);
120 s->bufs_per_mdl = 1;
121 s->mdl_size = s->buf_size * s->bufs_per_mdl;
6ecd86dc 122
1c1e45d1
HV
123 init_waitqueue_head(&s->waitq);
124 s->id = -1;
40c5520f 125 spin_lock_init(&s->q_free.lock);
1c1e45d1 126 cx18_queue_init(&s->q_free);
40c5520f 127 spin_lock_init(&s->q_busy.lock);
66c2a6b0 128 cx18_queue_init(&s->q_busy);
40c5520f 129 spin_lock_init(&s->q_full.lock);
1c1e45d1 130 cx18_queue_init(&s->q_full);
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131 spin_lock_init(&s->q_idle.lock);
132 cx18_queue_init(&s->q_idle);
21a278b8
AW
133
134 INIT_WORK(&s->out_work_order, cx18_out_work_handler);
1c1e45d1
HV
135}
136
137static int cx18_prep_dev(struct cx18 *cx, int type)
138{
139 struct cx18_stream *s = &cx->streams[type];
140 u32 cap = cx->v4l2_cap;
dd89601d 141 int num_offset = cx18_stream_info[type].num_offset;
5811cf99 142 int num = cx->instance + cx18_first_minor + num_offset;
1c1e45d1 143
754f9969
AW
144 /*
145 * These five fields are always initialized.
146 * For analog capture related streams, if video_dev == NULL then the
147 * stream is not in use.
148 * For the TS stream, if dvb == NULL then the stream is not in use.
149 * In those cases no other fields but these four can be used.
150 */
3d05913d 151 s->video_dev = NULL;
754f9969 152 s->dvb = NULL;
1c1e45d1
HV
153 s->cx = cx;
154 s->type = type;
155 s->name = cx18_stream_info[type].name;
156
157 /* Check whether the radio is supported */
158 if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO))
159 return 0;
160
161 /* Check whether VBI is supported */
162 if (type == CX18_ENC_STREAM_TYPE_VBI &&
163 !(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE)))
164 return 0;
165
1c1e45d1
HV
166 /* User explicitly selected 0 buffers for these streams, so don't
167 create them. */
168 if (cx18_stream_info[type].dma != PCI_DMA_NONE &&
6ecd86dc 169 cx->stream_buffers[type] == 0) {
1c1e45d1
HV
170 CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name);
171 return 0;
172 }
173
174 cx18_stream_init(cx, type);
175
754f9969
AW
176 /* Allocate the cx18_dvb struct only for the TS on cards with DTV */
177 if (type == CX18_ENC_STREAM_TYPE_TS) {
178 if (cx->card->hw_all & CX18_HW_DVB) {
179 s->dvb = kzalloc(sizeof(struct cx18_dvb), GFP_KERNEL);
180 if (s->dvb == NULL) {
181 CX18_ERR("Couldn't allocate cx18_dvb structure"
182 " for %s\n", s->name);
183 return -ENOMEM;
184 }
185 } else {
186 /* Don't need buffers for the TS, if there is no DVB */
187 s->buffers = 0;
188 }
189 }
190
dd89601d 191 if (num_offset == -1)
1c1e45d1
HV
192 return 0;
193
194 /* allocate and initialize the v4l2 video device structure */
3d05913d
AW
195 s->video_dev = video_device_alloc();
196 if (s->video_dev == NULL) {
1c1e45d1
HV
197 CX18_ERR("Couldn't allocate v4l2 video_device for %s\n",
198 s->name);
199 return -ENOMEM;
200 }
201
5811cf99
AW
202 snprintf(s->video_dev->name, sizeof(s->video_dev->name), "%s %s",
203 cx->v4l2_dev.name, s->name);
1c1e45d1 204
3d05913d 205 s->video_dev->num = num;
5811cf99 206 s->video_dev->v4l2_dev = &cx->v4l2_dev;
3d05913d
AW
207 s->video_dev->fops = &cx18_v4l2_enc_fops;
208 s->video_dev->release = video_device_release;
209 s->video_dev->tvnorms = V4L2_STD_ALL;
210 cx18_set_funcs(s->video_dev);
1c1e45d1
HV
211 return 0;
212}
213
214/* Initialize v4l2 variables and register v4l2 devices */
215int cx18_streams_setup(struct cx18 *cx)
216{
9b4a7c8a 217 int type, ret;
1c1e45d1
HV
218
219 /* Setup V4L2 Devices */
220 for (type = 0; type < CX18_MAX_STREAMS; type++) {
221 /* Prepare device */
9b4a7c8a
AW
222 ret = cx18_prep_dev(cx, type);
223 if (ret < 0)
1c1e45d1
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224 break;
225
226 /* Allocate Stream */
9b4a7c8a
AW
227 ret = cx18_stream_alloc(&cx->streams[type]);
228 if (ret < 0)
1c1e45d1
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229 break;
230 }
231 if (type == CX18_MAX_STREAMS)
232 return 0;
233
234 /* One or more streams could not be initialized. Clean 'em all up. */
3f98387e 235 cx18_streams_cleanup(cx, 0);
9b4a7c8a 236 return ret;
1c1e45d1
HV
237}
238
239static int cx18_reg_dev(struct cx18 *cx, int type)
240{
241 struct cx18_stream *s = &cx->streams[type];
242 int vfl_type = cx18_stream_info[type].vfl_type;
38c7c036 243 const char *name;
9b4a7c8a 244 int num, ret;
1c1e45d1 245
754f9969 246 if (type == CX18_ENC_STREAM_TYPE_TS && s->dvb != NULL) {
9b4a7c8a
AW
247 ret = cx18_dvb_register(s);
248 if (ret < 0) {
1c1e45d1 249 CX18_ERR("DVB failed to register\n");
9b4a7c8a 250 return ret;
1c1e45d1
HV
251 }
252 }
253
3d05913d 254 if (s->video_dev == NULL)
1c1e45d1
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255 return 0;
256
3d05913d 257 num = s->video_dev->num;
dd89601d
HV
258 /* card number + user defined offset + device offset */
259 if (type != CX18_ENC_STREAM_TYPE_MPG) {
260 struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
261
3d05913d
AW
262 if (s_mpg->video_dev)
263 num = s_mpg->video_dev->num
264 + cx18_stream_info[type].num_offset;
dd89601d 265 }
5811cf99 266 video_set_drvdata(s->video_dev, s);
1c1e45d1
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267
268 /* Register device. First try the desired minor, then any free one. */
6b5270d2 269 ret = video_register_device_no_warn(s->video_dev, vfl_type, num);
9b4a7c8a 270 if (ret < 0) {
581644d9 271 CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n",
dd89601d 272 s->name, num);
3d05913d
AW
273 video_device_release(s->video_dev);
274 s->video_dev = NULL;
9b4a7c8a 275 return ret;
1c1e45d1 276 }
38c7c036
LP
277
278 name = video_device_node_name(s->video_dev);
1c1e45d1
HV
279
280 switch (vfl_type) {
281 case VFL_TYPE_GRABBER:
38c7c036
LP
282 CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n",
283 name, s->name, cx->stream_buffers[type],
22dce188
AW
284 cx->stream_buf_size[type] / 1024,
285 (cx->stream_buf_size[type] * 100 / 1024) % 100);
1c1e45d1
HV
286 break;
287
288 case VFL_TYPE_RADIO:
38c7c036 289 CX18_INFO("Registered device %s for %s\n", name, s->name);
1c1e45d1
HV
290 break;
291
292 case VFL_TYPE_VBI:
6ecd86dc 293 if (cx->stream_buffers[type])
38c7c036 294 CX18_INFO("Registered device %s for %s "
6ecd86dc 295 "(%d x %d bytes)\n",
38c7c036 296 name, s->name, cx->stream_buffers[type],
6ecd86dc 297 cx->stream_buf_size[type]);
1c1e45d1 298 else
38c7c036
LP
299 CX18_INFO("Registered device %s for %s\n",
300 name, s->name);
1c1e45d1
HV
301 break;
302 }
303
304 return 0;
305}
306
307/* Register v4l2 devices */
308int cx18_streams_register(struct cx18 *cx)
309{
310 int type;
9b4a7c8a
AW
311 int err;
312 int ret = 0;
1c1e45d1
HV
313
314 /* Register V4L2 devices */
9b4a7c8a
AW
315 for (type = 0; type < CX18_MAX_STREAMS; type++) {
316 err = cx18_reg_dev(cx, type);
317 if (err && ret == 0)
318 ret = err;
319 }
1c1e45d1 320
9b4a7c8a 321 if (ret == 0)
1c1e45d1
HV
322 return 0;
323
324 /* One or more streams could not be initialized. Clean 'em all up. */
3f98387e 325 cx18_streams_cleanup(cx, 1);
9b4a7c8a 326 return ret;
1c1e45d1
HV
327}
328
329/* Unregister v4l2 devices */
3f98387e 330void cx18_streams_cleanup(struct cx18 *cx, int unregister)
1c1e45d1
HV
331{
332 struct video_device *vdev;
333 int type;
334
335 /* Teardown all streams */
336 for (type = 0; type < CX18_MAX_STREAMS; type++) {
7b1dde03 337
754f9969 338 /* The TS has a cx18_dvb structure, not a video_device */
7b1dde03 339 if (type == CX18_ENC_STREAM_TYPE_TS) {
754f9969
AW
340 if (cx->streams[type].dvb != NULL) {
341 if (unregister)
342 cx18_dvb_unregister(&cx->streams[type]);
343 kfree(cx->streams[type].dvb);
344 cx->streams[type].dvb = NULL;
7b1dde03
AW
345 cx18_stream_free(&cx->streams[type]);
346 }
347 continue;
348 }
349
350 /* No struct video_device, but can have buffers allocated */
351 if (type == CX18_ENC_STREAM_TYPE_IDX) {
352 if (cx->stream_buffers[type] != 0) {
353 cx->stream_buffers[type] = 0;
354 cx18_stream_free(&cx->streams[type]);
355 }
356 continue;
fac3639d 357 }
1c1e45d1 358
7b1dde03 359 /* If struct video_device exists, can have buffers allocated */
3d05913d 360 vdev = cx->streams[type].video_dev;
1c1e45d1 361
3d05913d 362 cx->streams[type].video_dev = NULL;
1c1e45d1
HV
363 if (vdev == NULL)
364 continue;
365
366 cx18_stream_free(&cx->streams[type]);
367
3f98387e
HV
368 /* Unregister or release device */
369 if (unregister)
370 video_unregister_device(vdev);
371 else
372 video_device_release(vdev);
1c1e45d1
HV
373 }
374}
375
376static void cx18_vbi_setup(struct cx18_stream *s)
377{
378 struct cx18 *cx = s->cx;
dd073434 379 int raw = cx18_raw_vbi(cx);
1c1e45d1
HV
380 u32 data[CX2341X_MBOX_MAX_DATA];
381 int lines;
382
383 if (cx->is_60hz) {
384 cx->vbi.count = 12;
385 cx->vbi.start[0] = 10;
386 cx->vbi.start[1] = 273;
387 } else { /* PAL/SECAM */
388 cx->vbi.count = 18;
389 cx->vbi.start[0] = 6;
390 cx->vbi.start[1] = 318;
391 }
392
393 /* setup VBI registers */
add632cd
HV
394 if (raw)
395 v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &cx->vbi.in.fmt.vbi);
396 else
397 v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &cx->vbi.in.fmt.sliced);
1c1e45d1 398
dcc0ef88
AW
399 /*
400 * Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw
401 * VBI when the first analog capture channel starts, as once it starts
402 * (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup
403 * (i.e. for the VBI capture channels). We also send it for each
404 * analog capture channel anyway just to make sure we get the proper
405 * behavior
406 */
1c1e45d1
HV
407 if (raw) {
408 lines = cx->vbi.count * 2;
409 } else {
812b1f9d
AW
410 /*
411 * For 525/60 systems, according to the VIP 2 & BT.656 std:
412 * The EAV RP code's Field bit toggles on line 4, a few lines
413 * after the Vertcal Blank bit has already toggled.
414 * Tell the encoder to capture 21-4+1=18 lines per field,
415 * since we want lines 10 through 21.
416 *
5ab74052
AW
417 * For 625/50 systems, according to the VIP 2 & BT.656 std:
418 * The EAV RP code's Field bit toggles on line 1, a few lines
419 * after the Vertcal Blank bit has already toggled.
929a3ad1
AW
420 * (We've actually set the digitizer so that the Field bit
421 * toggles on line 2.) Tell the encoder to capture 23-2+1=22
422 * lines per field, since we want lines 6 through 23.
812b1f9d 423 */
929a3ad1 424 lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2;
1c1e45d1
HV
425 }
426
1c1e45d1
HV
427 data[0] = s->handle;
428 /* Lines per field */
429 data[1] = (lines / 2) | ((lines / 2) << 16);
430 /* bytes per line */
302df970
AW
431 data[2] = (raw ? vbi_active_samples
432 : (cx->is_60hz ? vbi_hblank_samples_60Hz
433 : vbi_hblank_samples_50Hz));
1c1e45d1
HV
434 /* Every X number of frames a VBI interrupt arrives
435 (frames as in 25 or 30 fps) */
436 data[3] = 1;
302df970
AW
437 /*
438 * Set the SAV/EAV RP codes to look for as start/stop points
439 * when in VIP-1.1 mode
440 */
1c1e45d1 441 if (raw) {
302df970
AW
442 /*
443 * Start codes for beginning of "active" line in vertical blank
444 * 0x20 ( VerticalBlank )
445 * 0x60 ( EvenField VerticalBlank )
446 */
1c1e45d1 447 data[4] = 0x20602060;
302df970
AW
448 /*
449 * End codes for end of "active" raw lines and regular lines
450 * 0x30 ( VerticalBlank HorizontalBlank)
451 * 0x70 ( EvenField VerticalBlank HorizontalBlank)
452 * 0x90 (Task HorizontalBlank)
453 * 0xd0 (Task EvenField HorizontalBlank)
454 */
af009cf6 455 data[5] = 0x307090d0;
1c1e45d1 456 } else {
302df970
AW
457 /*
458 * End codes for active video, we want data in the hblank region
459 * 0xb0 (Task 0 VerticalBlank HorizontalBlank)
460 * 0xf0 (Task EvenField VerticalBlank HorizontalBlank)
461 *
462 * Since the V bit is only allowed to toggle in the EAV RP code,
463 * just before the first active region line, these two
812b1f9d 464 * are problematic:
302df970
AW
465 * 0x90 (Task HorizontalBlank)
466 * 0xd0 (Task EvenField HorizontalBlank)
812b1f9d 467 *
af7c58b1
AW
468 * We have set the digitzer such that we don't have to worry
469 * about these problem codes.
302df970 470 */
1c1e45d1 471 data[4] = 0xB0F0B0F0;
302df970
AW
472 /*
473 * Start codes for beginning of active line in vertical blank
474 * 0xa0 (Task VerticalBlank )
475 * 0xe0 (Task EvenField VerticalBlank )
476 */
1c1e45d1
HV
477 data[5] = 0xA0E0A0E0;
478 }
479
480 CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n",
481 data[0], data[1], data[2], data[3], data[4], data[5]);
482
dcc0ef88 483 cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
1c1e45d1
HV
484}
485
ef991797
AW
486void cx18_stream_rotate_idx_mdls(struct cx18 *cx)
487{
488 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
489 struct cx18_mdl *mdl;
490
491 if (!cx18_stream_enabled(s))
492 return;
493
494 /* Return if the firmware is not running low on MDLs */
495 if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >=
496 CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN)
497 return;
498
499 /* Return if there are no MDLs to rotate back to the firmware */
500 if (atomic_read(&s->q_full.depth) < 2)
501 return;
502
503 /*
504 * Take the oldest IDX MDL still holding data, and discard its index
505 * entries by scheduling the MDL to go back to the firmware
506 */
507 mdl = cx18_dequeue(s, &s->q_full);
508 if (mdl != NULL)
509 cx18_enqueue(s, mdl, &s->q_free);
510}
511
87116159 512static
52fcb3ec
AW
513struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s,
514 struct cx18_mdl *mdl)
66c2a6b0
AW
515{
516 struct cx18 *cx = s->cx;
517 struct cx18_queue *q;
518
519 /* Don't give it to the firmware, if we're not running a capture */
520 if (s->handle == CX18_INVALID_TASK_HANDLE ||
87116159 521 test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
66c2a6b0 522 !test_bit(CX18_F_S_STREAMING, &s->s_flags))
52fcb3ec 523 return cx18_enqueue(s, mdl, &s->q_free);
66c2a6b0 524
52fcb3ec 525 q = cx18_enqueue(s, mdl, &s->q_busy);
66c2a6b0 526 if (q != &s->q_busy)
52fcb3ec 527 return q; /* The firmware has the max MDLs it can handle */
66c2a6b0 528
52fcb3ec 529 cx18_mdl_sync_for_device(s, mdl);
66c2a6b0 530 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
52fcb3ec
AW
531 (void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem,
532 s->bufs_per_mdl, mdl->id, s->mdl_size);
66c2a6b0
AW
533 return q;
534}
535
87116159
AW
536static
537void _cx18_stream_load_fw_queue(struct cx18_stream *s)
66c2a6b0 538{
abb096de 539 struct cx18_queue *q;
52fcb3ec 540 struct cx18_mdl *mdl;
66c2a6b0 541
c37b11bf
AW
542 if (atomic_read(&s->q_free.depth) == 0 ||
543 atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
abb096de
AW
544 return;
545
546 /* Move from q_free to q_busy notifying the firmware, until the limit */
547 do {
52fcb3ec
AW
548 mdl = cx18_dequeue(s, &s->q_free);
549 if (mdl == NULL)
abb096de 550 break;
52fcb3ec 551 q = _cx18_stream_put_mdl_fw(s, mdl);
c37b11bf 552 } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM
0ef02892 553 && q == &s->q_busy);
66c2a6b0
AW
554}
555
87116159
AW
556void cx18_out_work_handler(struct work_struct *work)
557{
21a278b8
AW
558 struct cx18_stream *s =
559 container_of(work, struct cx18_stream, out_work_order);
87116159 560
21a278b8 561 _cx18_stream_load_fw_queue(s);
87116159
AW
562}
563
52fcb3ec
AW
564static void cx18_stream_configure_mdls(struct cx18_stream *s)
565{
566 cx18_unload_queues(s);
567
22dce188
AW
568 switch (s->type) {
569 case CX18_ENC_STREAM_TYPE_YUV:
570 /*
571 * Height should be a multiple of 32 lines.
572 * Set the MDL size to the exact size needed for one frame.
573 * Use enough buffers per MDL to cover the MDL size
574 */
a75b9be1 575 s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2;
22dce188
AW
576 s->bufs_per_mdl = s->mdl_size / s->buf_size;
577 if (s->mdl_size % s->buf_size)
578 s->bufs_per_mdl++;
579 break;
127ce5f0
AW
580 case CX18_ENC_STREAM_TYPE_VBI:
581 s->bufs_per_mdl = 1;
582 if (cx18_raw_vbi(s->cx)) {
583 s->mdl_size = (s->cx->is_60hz ? 12 : 18)
584 * 2 * vbi_active_samples;
585 } else {
586 /*
587 * See comment in cx18_vbi_setup() below about the
588 * extra lines we capture in sliced VBI mode due to
589 * the lines on which EAV RP codes toggle.
590 */
591 s->mdl_size = s->cx->is_60hz
592 ? (21 - 4 + 1) * 2 * vbi_hblank_samples_60Hz
593 : (23 - 2 + 1) * 2 * vbi_hblank_samples_50Hz;
594 }
595 break;
22dce188
AW
596 default:
597 s->bufs_per_mdl = 1;
598 s->mdl_size = s->buf_size * s->bufs_per_mdl;
599 break;
600 }
52fcb3ec
AW
601
602 cx18_load_queues(s);
603}
604
1c1e45d1
HV
605int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
606{
607 u32 data[MAX_MB_ARGUMENTS];
608 struct cx18 *cx = s->cx;
1c1e45d1 609 int captype = 0;
e46c54a8 610 struct cx18_stream *s_idx;
1c1e45d1 611
540bab93 612 if (!cx18_stream_enabled(s))
1c1e45d1
HV
613 return -EINVAL;
614
615 CX18_DEBUG_INFO("Start encoder stream %s\n", s->name);
616
617 switch (s->type) {
618 case CX18_ENC_STREAM_TYPE_MPG:
619 captype = CAPTURE_CHANNEL_TYPE_MPEG;
620 cx->mpg_data_received = cx->vbi_data_inserted = 0;
621 cx->dualwatch_jiffies = jiffies;
a75b9be1 622 cx->dualwatch_stereo_mode = v4l2_ctrl_g_ctrl(cx->cxhdl.audio_mode);
1c1e45d1
HV
623 cx->search_pack_header = 0;
624 break;
625
e46c54a8
AW
626 case CX18_ENC_STREAM_TYPE_IDX:
627 captype = CAPTURE_CHANNEL_TYPE_INDEX;
628 break;
1c1e45d1
HV
629 case CX18_ENC_STREAM_TYPE_TS:
630 captype = CAPTURE_CHANNEL_TYPE_TS;
1c1e45d1
HV
631 break;
632 case CX18_ENC_STREAM_TYPE_YUV:
633 captype = CAPTURE_CHANNEL_TYPE_YUV;
634 break;
635 case CX18_ENC_STREAM_TYPE_PCM:
636 captype = CAPTURE_CHANNEL_TYPE_PCM;
637 break;
638 case CX18_ENC_STREAM_TYPE_VBI:
dcc0ef88 639#ifdef CX18_ENCODER_PARSES_SLICED
dd073434
AW
640 captype = cx18_raw_vbi(cx) ?
641 CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI;
dcc0ef88
AW
642#else
643 /*
644 * Currently we set things up so that Sliced VBI from the
645 * digitizer is handled as Raw VBI by the encoder
646 */
647 captype = CAPTURE_CHANNEL_TYPE_VBI;
648#endif
1c1e45d1
HV
649 cx->vbi.frame = 0;
650 cx->vbi.inserted_frame = 0;
651 memset(cx->vbi.sliced_mpeg_size,
652 0, sizeof(cx->vbi.sliced_mpeg_size));
653 break;
654 default:
655 return -EINVAL;
656 }
1c1e45d1 657
1c1e45d1
HV
658 /* Clear Streamoff flags in case left from last capture */
659 clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
660
661 cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE);
662 s->handle = data[0];
663 cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype);
664
dcc0ef88
AW
665 /*
666 * For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and
667 * set up all the parameters, as it is not obvious which parameters the
668 * firmware shares across capture channel types and which it does not.
669 *
670 * Some of the cx18_vapi() calls below apply to only certain capture
671 * channel types. We're hoping there's no harm in calling most of them
672 * anyway, as long as the values are all consistent. Setting some
673 * shared parameters will have no effect once an analog capture channel
674 * has started streaming.
675 */
676 if (captype != CAPTURE_CHANNEL_TYPE_TS) {
1c1e45d1
HV
677 cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0);
678 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1);
679 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0);
680 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1);
1c1e45d1 681
dcc0ef88
AW
682 /*
683 * Audio related reset according to
684 * Documentation/video4linux/cx2341x/fw-encoder-api.txt
685 */
686 if (atomic_read(&cx->ana_capturing) == 0)
687 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2,
688 s->handle, 12);
689
690 /*
691 * Number of lines for Field 1 & Field 2 according to
692 * Documentation/video4linux/cx2341x/fw-encoder-api.txt
f37aa511
AW
693 * Field 1 is 312 for 625 line systems in BT.656
694 * Field 2 is 313 for 625 line systems in BT.656
dcc0ef88 695 */
1c1e45d1 696 cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3,
f37aa511 697 s->handle, 312, 313);
1c1e45d1 698
1c1e45d1
HV
699 if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE)
700 cx18_vbi_setup(s);
701
dcc0ef88 702 /*
e46c54a8
AW
703 * Select to receive I, P, and B frame index entries, if the
704 * index stream is enabled. Otherwise disable index entry
705 * generation.
dcc0ef88 706 */
e46c54a8 707 s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
5ada5773
AW
708 cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2,
709 s->handle, cx18_stream_enabled(s_idx) ? 7 : 0);
1c1e45d1 710
dcc0ef88 711 /* Call out to the common CX2341x API setup for user controls */
a75b9be1
HV
712 cx->cxhdl.priv = s;
713 cx2341x_handler_setup(&cx->cxhdl);
dcc0ef88
AW
714
715 /*
716 * When starting a capture and we're set for radio,
717 * ensure the video is muted, despite the user control.
718 */
a75b9be1 719 if (!cx->cxhdl.video_mute &&
dcc0ef88
AW
720 test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
721 cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
a75b9be1 722 (v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8) | 1);
1c1e45d1
HV
723 }
724
31554ae5 725 if (atomic_read(&cx->tot_capturing) == 0) {
a75b9be1 726 cx2341x_handler_set_busy(&cx->cxhdl, 1);
1c1e45d1 727 clear_bit(CX18_F_I_EOS, &cx->i_flags);
b1526421 728 cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK);
1c1e45d1
HV
729 }
730
731 cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle,
990c81c8
AV
732 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem,
733 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem);
1c1e45d1 734
66c2a6b0 735 /* Init all the cpu_mdls for this stream */
52fcb3ec 736 cx18_stream_configure_mdls(s);
87116159 737 _cx18_stream_load_fw_queue(s);
66c2a6b0 738
1c1e45d1
HV
739 /* begin_capture */
740 if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
741 CX18_DEBUG_WARN("Error starting capture!\n");
3b5df8ea 742 /* Ensure we're really not capturing before releasing MDLs */
87116159 743 set_bit(CX18_F_S_STOPPING, &s->s_flags);
3b5df8ea
AW
744 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
745 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
746 else
747 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
66c2a6b0
AW
748 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
749 /* FIXME - CX18_F_S_STREAMOFF as well? */
3b5df8ea 750 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
1c1e45d1 751 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
66c2a6b0 752 s->handle = CX18_INVALID_TASK_HANDLE;
87116159 753 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
66c2a6b0
AW
754 if (atomic_read(&cx->tot_capturing) == 0) {
755 set_bit(CX18_F_I_EOS, &cx->i_flags);
756 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
757 }
1c1e45d1
HV
758 return -EINVAL;
759 }
760
761 /* you're live! sit back and await interrupts :) */
dcc0ef88 762 if (captype != CAPTURE_CHANNEL_TYPE_TS)
31554ae5
HV
763 atomic_inc(&cx->ana_capturing);
764 atomic_inc(&cx->tot_capturing);
1c1e45d1
HV
765 return 0;
766}
0f4cf676 767EXPORT_SYMBOL(cx18_start_v4l2_encode_stream);
1c1e45d1
HV
768
769void cx18_stop_all_captures(struct cx18 *cx)
770{
771 int i;
772
773 for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) {
774 struct cx18_stream *s = &cx->streams[i];
775
540bab93 776 if (!cx18_stream_enabled(s))
1c1e45d1
HV
777 continue;
778 if (test_bit(CX18_F_S_STREAMING, &s->s_flags))
779 cx18_stop_v4l2_encode_stream(s, 0);
780 }
781}
782
783int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
784{
785 struct cx18 *cx = s->cx;
786 unsigned long then;
787
540bab93 788 if (!cx18_stream_enabled(s))
1c1e45d1
HV
789 return -EINVAL;
790
791 /* This function assumes that you are allowed to stop the capture
792 and that we are actually capturing */
793
794 CX18_DEBUG_INFO("Stop Capture\n");
795
31554ae5 796 if (atomic_read(&cx->tot_capturing) == 0)
1c1e45d1
HV
797 return 0;
798
87116159 799 set_bit(CX18_F_S_STOPPING, &s->s_flags);
1c1e45d1
HV
800 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
801 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
802 else
803 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
804
805 then = jiffies;
806
807 if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) {
808 CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n");
809 }
810
31554ae5
HV
811 if (s->type != CX18_ENC_STREAM_TYPE_TS)
812 atomic_dec(&cx->ana_capturing);
813 atomic_dec(&cx->tot_capturing);
1c1e45d1
HV
814
815 /* Clear capture and no-read bits */
816 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
817
f68d0cf5
AW
818 /* Tell the CX23418 it can't use our buffers anymore */
819 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
820
1c1e45d1 821 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
d3c5e707 822 s->handle = CX18_INVALID_TASK_HANDLE;
87116159 823 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
1c1e45d1 824
31554ae5 825 if (atomic_read(&cx->tot_capturing) > 0)
1c1e45d1
HV
826 return 0;
827
a75b9be1 828 cx2341x_handler_set_busy(&cx->cxhdl, 0);
b1526421 829 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
1c1e45d1
HV
830 wake_up(&s->waitq);
831
832 return 0;
833}
0f4cf676 834EXPORT_SYMBOL(cx18_stop_v4l2_encode_stream);
1c1e45d1
HV
835
836u32 cx18_find_handle(struct cx18 *cx)
837{
838 int i;
839
840 /* find first available handle to be used for global settings */
841 for (i = 0; i < CX18_MAX_STREAMS; i++) {
842 struct cx18_stream *s = &cx->streams[i];
843
3d05913d 844 if (s->video_dev && (s->handle != CX18_INVALID_TASK_HANDLE))
1c1e45d1
HV
845 return s->handle;
846 }
d3c5e707 847 return CX18_INVALID_TASK_HANDLE;
1c1e45d1 848}
ee2d64f5
AW
849
850struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle)
851{
852 int i;
853 struct cx18_stream *s;
854
855 if (handle == CX18_INVALID_TASK_HANDLE)
856 return NULL;
857
858 for (i = 0; i < CX18_MAX_STREAMS; i++) {
859 s = &cx->streams[i];
860 if (s->handle != handle)
861 continue;
540bab93 862 if (cx18_stream_enabled(s))
ee2d64f5
AW
863 return s;
864 }
865 return NULL;
866}
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