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[media] cx231xx-417: Fix a gcc warning
[deliverable/linux.git] / drivers / media / video / cx231xx / cx231xx-417.c
CommitLineData
64fbf444
PB		 1/*
2 *
3 * Support for a cx23417 mpeg encoder via cx231xx host port.
4 *
5 * (c) 2004 Jelle Foks <jelle@foks.us>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
8 * - CX23885/7/8 support
9 *
10 * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/fs.h>
31#include <linux/delay.h>
32#include <linux/device.h>
33#include <linux/firmware.h>
34#include <linux/smp_lock.h>
35#include <media/v4l2-common.h>
36#include <media/v4l2-ioctl.h>
37#include <media/cx2341x.h>
38#include <linux/usb.h>
39
40#include "cx231xx.h"
41/*#include "cx23885-ioctl.h"*/
42
43#define CX231xx_FIRM_IMAGE_SIZE 376836
44#define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
45
955e6ed8 46/* for polaris ITVC */
64fbf444
PB		 47#define ITVC_WRITE_DIR 0x03FDFC00
48#define ITVC_READ_DIR 0x0001FC00
49
50#define MCI_MEMORY_DATA_BYTE0 0x00
51#define MCI_MEMORY_DATA_BYTE1 0x08
52#define MCI_MEMORY_DATA_BYTE2 0x10
53#define MCI_MEMORY_DATA_BYTE3 0x18
54
55#define MCI_MEMORY_ADDRESS_BYTE2 0x20
56#define MCI_MEMORY_ADDRESS_BYTE1 0x28
57#define MCI_MEMORY_ADDRESS_BYTE0 0x30
58
59#define MCI_REGISTER_DATA_BYTE0 0x40
60#define MCI_REGISTER_DATA_BYTE1 0x48
61#define MCI_REGISTER_DATA_BYTE2 0x50
62#define MCI_REGISTER_DATA_BYTE3 0x58
63
64#define MCI_REGISTER_ADDRESS_BYTE0 0x60
65#define MCI_REGISTER_ADDRESS_BYTE1 0x68
66
67#define MCI_REGISTER_MODE 0x70
68
955e6ed8 69/* Read and write modes for polaris ITVC */
64fbf444
PB		 70#define MCI_MODE_REGISTER_READ 0x000
71#define MCI_MODE_REGISTER_WRITE 0x100
72#define MCI_MODE_MEMORY_READ 0x000
73#define MCI_MODE_MEMORY_WRITE 0x4000
74
75static unsigned int mpegbufs = 8;
76module_param(mpegbufs, int, 0644);
77MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
78static unsigned int mpeglines = 128;
79module_param(mpeglines, int, 0644);
80MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
81static unsigned int mpeglinesize = 512;
82module_param(mpeglinesize, int, 0644);
83MODULE_PARM_DESC(mpeglinesize,
84 "number of bytes in each line of an MPEG buffer, range 512-1024");
85
86static unsigned int v4l_debug = 1;
87module_param(v4l_debug, int, 0644);
88MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
89struct cx231xx_dmaqueue *dma_qq;
90#define dprintk(level, fmt, arg...)\
91 do { if (v4l_debug >= level) \
92 printk(KERN_INFO "%s: " fmt, \
93 (dev) ? dev->name : "cx231xx[?]", ## arg); \
94 } while (0)
95
96static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
97 {
98 .name = "NTSC-M",
99 .id = V4L2_STD_NTSC_M,
100 }, {
101 .name = "NTSC-JP",
102 .id = V4L2_STD_NTSC_M_JP,
103 }, {
104 .name = "PAL-BG",
105 .id = V4L2_STD_PAL_BG,
106 }, {
107 .name = "PAL-DK",
108 .id = V4L2_STD_PAL_DK,
109 }, {
110 .name = "PAL-I",
111 .id = V4L2_STD_PAL_I,
112 }, {
113 .name = "PAL-M",
114 .id = V4L2_STD_PAL_M,
115 }, {
116 .name = "PAL-N",
117 .id = V4L2_STD_PAL_N,
118 }, {
119 .name = "PAL-Nc",
120 .id = V4L2_STD_PAL_Nc,
121 }, {
122 .name = "PAL-60",
123 .id = V4L2_STD_PAL_60,
124 }, {
125 .name = "SECAM-L",
126 .id = V4L2_STD_SECAM_L,
127 }, {
128 .name = "SECAM-DK",
129 .id = V4L2_STD_SECAM_DK,
130 }
131};
132
133/* ------------------------------------------------------------------ */
134enum cx231xx_capture_type {
135 CX231xx_MPEG_CAPTURE,
136 CX231xx_RAW_CAPTURE,
137 CX231xx_RAW_PASSTHRU_CAPTURE
138};
139enum cx231xx_capture_bits {
140 CX231xx_RAW_BITS_NONE = 0x00,
141 CX231xx_RAW_BITS_YUV_CAPTURE = 0x01,
142 CX231xx_RAW_BITS_PCM_CAPTURE = 0x02,
143 CX231xx_RAW_BITS_VBI_CAPTURE = 0x04,
144 CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
145 CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10
146};
147enum cx231xx_capture_end {
148 CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
149 CX231xx_END_NOW, /* stop immediately, no irq */
150};
151enum cx231xx_framerate {
152 CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
153 CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */
154};
155enum cx231xx_stream_port {
156 CX231xx_OUTPUT_PORT_MEMORY,
157 CX231xx_OUTPUT_PORT_STREAMING,
158 CX231xx_OUTPUT_PORT_SERIAL
159};
160enum cx231xx_data_xfer_status {
161 CX231xx_MORE_BUFFERS_FOLLOW,
162 CX231xx_LAST_BUFFER,
163};
164enum cx231xx_picture_mask {
165 CX231xx_PICTURE_MASK_NONE,
166 CX231xx_PICTURE_MASK_I_FRAMES,
167 CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
168 CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
169};
170enum cx231xx_vbi_mode_bits {
171 CX231xx_VBI_BITS_SLICED,
172 CX231xx_VBI_BITS_RAW,
173};
174enum cx231xx_vbi_insertion_bits {
175 CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
176 CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
177 CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
178 CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
179 CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
180};
181enum cx231xx_dma_unit {
182 CX231xx_DMA_BYTES,
183 CX231xx_DMA_FRAMES,
184};
185enum cx231xx_dma_transfer_status_bits {
186 CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
187 CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
188 CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
189};
190enum cx231xx_pause {
191 CX231xx_PAUSE_ENCODING,
192 CX231xx_RESUME_ENCODING,
193};
194enum cx231xx_copyright {
195 CX231xx_COPYRIGHT_OFF,
196 CX231xx_COPYRIGHT_ON,
197};
198enum cx231xx_notification_type {
199 CX231xx_NOTIFICATION_REFRESH,
200};
201enum cx231xx_notification_status {
202 CX231xx_NOTIFICATION_OFF,
203 CX231xx_NOTIFICATION_ON,
204};
205enum cx231xx_notification_mailbox {
206 CX231xx_NOTIFICATION_NO_MAILBOX = -1,
207};
208enum cx231xx_field1_lines {
209 CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
210 CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
211 CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
212};
213enum cx231xx_field2_lines {
214 CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
215 CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
216 CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
217};
218enum cx231xx_custom_data_type {
219 CX231xx_CUSTOM_EXTENSION_USR_DATA,
220 CX231xx_CUSTOM_PRIVATE_PACKET,
221};
222enum cx231xx_mute {
223 CX231xx_UNMUTE,
224 CX231xx_MUTE,
225};
226enum cx231xx_mute_video_mask {
227 CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
228 CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
229 CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
230};
231enum cx231xx_mute_video_shift {
232 CX231xx_MUTE_VIDEO_V_SHIFT = 8,
233 CX231xx_MUTE_VIDEO_U_SHIFT = 16,
234 CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
235};
236
237/* defines below are from ivtv-driver.h */
238#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
239
240/* Firmware API commands */
241#define IVTV_API_STD_TIMEOUT 500
242
243/* Registers */
244/* IVTV_REG_OFFSET */
245#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
246#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
247#define IVTV_REG_SPU (0x9050)
248#define IVTV_REG_HW_BLOCKS (0x9054)
249#define IVTV_REG_VPU (0x9058)
250#define IVTV_REG_APU (0xA064)
251
955e6ed8
MCC		 252/*
253 * Bit definitions for MC417_RWD and MC417_OEN registers
254 *
255 * bits 31-16
256 *+-----------+
257 *| Reserved |
258 *|+-----------+
259 *| bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
260 *|+-------+-------+-------+-------+-------+-------+-------+-------+
261 *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
262 *|+-------+-------+-------+-------+-------+-------+-------+-------+
263 *| bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
264 *|+-------+-------+-------+-------+-------+-------+-------+-------+
265 *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
266 *|+-------+-------+-------+-------+-------+-------+-------+-------+
267 */
64fbf444
PB		 268#define MC417_MIWR 0x8000
269#define MC417_MIRD 0x4000
270#define MC417_MICS 0x2000
271#define MC417_MIRDY 0x1000
272#define MC417_MIADDR 0x0F00
273#define MC417_MIDATA 0x00FF
274
275
955e6ed8
MCC		 276/* Bit definitions for MC417_CTL register ****
277 *bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
278 *+--------+-------------+--------+--------------+------------+
279 *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
280 *+--------+-------------+--------+--------------+------------+
281 */
64fbf444
PB		 282#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
283#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
284#define MC417_UART_GPIO_EN 0x00000001
285
286/* Values for speed control */
287#define MC417_SPD_CTL_SLOW 0x1
288#define MC417_SPD_CTL_MEDIUM 0x0
289#define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
290
291/* Values for GPIO select */
292#define MC417_GPIO_SEL_GPIO3 0x3
293#define MC417_GPIO_SEL_GPIO2 0x2
294#define MC417_GPIO_SEL_GPIO1 0x1
295#define MC417_GPIO_SEL_GPIO0 0x0
296
297
298#define CX23417_GPIO_MASK 0xFC0003FF
299int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value)
300{
301 int status = 0;
302 u32 _gpio_direction = 0;
303
304 _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
305 _gpio_direction = _gpio_direction|gpio_direction;
306 status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
307 (u8 *)&value, 4, 0, 0);
308 return status;
309}
310int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
311{
312 int status = 0;
313 u32 _gpio_direction = 0;
314
315 _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
316 _gpio_direction = _gpio_direction|gpio_direction;
317
318 status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
319 (u8 *)pValue, 4, 0, 1);
320 return status;
321}
322int waitForMciComplete(struct cx231xx *dev)
323{
955e6ed8
MCC		 324 u32 gpio;
325 u32 gpio_driection = 0;
326 u8 count = 0;
327 getITVCReg(dev, gpio_driection, &gpio);
64fbf444 328
955e6ed8
MCC		 329 while (!(gpio&0x020000)) {
330 msleep(10);
64fbf444 331
955e6ed8 332 getITVCReg(dev, gpio_driection, &gpio);
64fbf444 333
955e6ed8
MCC		 334 if (count++ > 100) {
335 dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
336 return -1;
337 }
64fbf444 338 }
64fbf444
PB		 339 return 0;
340}
955e6ed8 341
64fbf444
PB		 342int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
343{
955e6ed8 344 u32 temp;
64fbf444
PB		 345 int status = 0;
346
955e6ed8
MCC		 347 temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8);
348 temp = temp<<10;
349 status = setITVCReg(dev, ITVC_WRITE_DIR, temp);
64fbf444
PB		 350 if (status < 0)
351 return status;
955e6ed8
MCC		 352 temp = temp|((0x05)<<10);
353 setITVCReg(dev, ITVC_WRITE_DIR, temp);
354
355 /*write data byte 1;*/
356 temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00);
357 temp = temp<<10;
358 setITVCReg(dev, ITVC_WRITE_DIR, temp);
359 temp = temp|((0x05)<<10);
360 setITVCReg(dev, ITVC_WRITE_DIR, temp);
361
362 /*write data byte 2;*/
363 temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8);
364 temp = temp<<10;
365 setITVCReg(dev, ITVC_WRITE_DIR, temp);
366 temp = temp|((0x05)<<10);
367 setITVCReg(dev, ITVC_WRITE_DIR, temp);
368
369 /*write data byte 3;*/
370 temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16);
371 temp = temp<<10;
372 setITVCReg(dev, ITVC_WRITE_DIR, temp);
373 temp = temp|((0x05)<<10);
374 setITVCReg(dev, ITVC_WRITE_DIR, temp);
375
376 /*write address byte 0;*/
377 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8);
378 temp = temp<<10;
379 setITVCReg(dev, ITVC_WRITE_DIR, temp);
380 temp = temp|((0x05)<<10);
381 setITVCReg(dev, ITVC_WRITE_DIR, temp);
382
383 /*write address byte 1;*/
384 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00);
385 temp = temp<<10;
386 setITVCReg(dev, ITVC_WRITE_DIR, temp);
387 temp = temp|((0x05)<<10);
388 setITVCReg(dev, ITVC_WRITE_DIR, temp);
389
390 /*Write that the mode is write.*/
391 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
392 temp = temp<<10;
393 setITVCReg(dev, ITVC_WRITE_DIR, temp);
394 temp = temp|((0x05)<<10);
395 setITVCReg(dev, ITVC_WRITE_DIR, temp);
396
397 return waitForMciComplete(dev);
64fbf444
PB		 398}
399
64fbf444
PB		 400int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
401{
955e6ed8
MCC		 402 /*write address byte 0;*/
403 u32 temp;
404 u32 return_value = 0;
64fbf444
PB		 405 int ret = 0;
406
955e6ed8
MCC		 407 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
408 temp = temp << 10;
409 setITVCReg(dev, ITVC_WRITE_DIR, temp);
410 temp = temp | ((0x05) << 10);
411 setITVCReg(dev, ITVC_WRITE_DIR, temp);
412
413 /*write address byte 1;*/
414 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
415 temp = temp << 10;
416 setITVCReg(dev, ITVC_WRITE_DIR, temp);
417 temp = temp | ((0x05) << 10);
418 setITVCReg(dev, ITVC_WRITE_DIR, temp);
419
420 /*write that the mode is read;*/
421 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
422 temp = temp << 10;
423 setITVCReg(dev, ITVC_WRITE_DIR, temp);
424 temp = temp | ((0x05) << 10);
425 setITVCReg(dev, ITVC_WRITE_DIR, temp);
426
427 /*wait for the MIRDY line to be asserted ,
428 signalling that the read is done;*/
429 ret = waitForMciComplete(dev);
430
431 /*switch the DATA- GPIO to input mode;*/
432
433 /*Read data byte 0;*/
434 temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
435 setITVCReg(dev, ITVC_READ_DIR, temp);
436 temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
437 setITVCReg(dev, ITVC_READ_DIR, temp);
438 getITVCReg(dev, ITVC_READ_DIR, &temp);
439 return_value |= ((temp & 0x03FC0000) >> 18);
440 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
441
442 /* Read data byte 1;*/
443 temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
444 setITVCReg(dev, ITVC_READ_DIR, temp);
445 temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
446 setITVCReg(dev, ITVC_READ_DIR, temp);
447 getITVCReg(dev, ITVC_READ_DIR, &temp);
448
449 return_value |= ((temp & 0x03FC0000) >> 10);
450 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
451
452 /*Read data byte 2;*/
453 temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
454 setITVCReg(dev, ITVC_READ_DIR, temp);
455 temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
456 setITVCReg(dev, ITVC_READ_DIR, temp);
457 getITVCReg(dev, ITVC_READ_DIR, &temp);
458 return_value |= ((temp & 0x03FC0000) >> 2);
459 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
460
461 /*Read data byte 3;*/
462 temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
463 setITVCReg(dev, ITVC_READ_DIR, temp);
464 temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
465 setITVCReg(dev, ITVC_READ_DIR, temp);
466 getITVCReg(dev, ITVC_READ_DIR, &temp);
467 return_value |= ((temp & 0x03FC0000) << 6);
468 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
64fbf444
PB		 469
470 *value = return_value;
471
472
955e6ed8 473 return ret;
64fbf444
PB		 474}
475
476int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
477{
955e6ed8 478 /*write data byte 0;*/
64fbf444 479
955e6ed8 480 u32 temp;
64fbf444
PB		 481 int ret = 0;
482
955e6ed8
MCC		 483 temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8);
484 temp = temp << 10;
485 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
64fbf444
PB		 486 if (ret < 0)
487 return ret;
955e6ed8
MCC		 488 temp = temp | ((0x05) << 10);
489 setITVCReg(dev, ITVC_WRITE_DIR, temp);
490
491 /*write data byte 1;*/
492 temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
493 temp = temp << 10;
494 setITVCReg(dev, ITVC_WRITE_DIR, temp);
495 temp = temp | ((0x05) << 10);
496 setITVCReg(dev, ITVC_WRITE_DIR, temp);
497
498 /*write data byte 2;*/
499 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
500 temp = temp<<10;
501 setITVCReg(dev, ITVC_WRITE_DIR, temp);
502 temp = temp|((0x05)<<10);
503 setITVCReg(dev, ITVC_WRITE_DIR, temp);
504
505 /*write data byte 3;*/
506 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
507 temp = temp<<10;
508 setITVCReg(dev, ITVC_WRITE_DIR, temp);
509 temp = temp|((0x05)<<10);
510 setITVCReg(dev, ITVC_WRITE_DIR, temp);
511
512 /* write address byte 2;*/
513 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
64fbf444 514 ((address & 0x003F0000)>>8);
955e6ed8
MCC		 515 temp = temp<<10;
516 setITVCReg(dev, ITVC_WRITE_DIR, temp);
517 temp = temp|((0x05)<<10);
518 setITVCReg(dev, ITVC_WRITE_DIR, temp);
519
520 /* write address byte 1;*/
521 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
522 temp = temp<<10;
523 setITVCReg(dev, ITVC_WRITE_DIR, temp);
524 temp = temp|((0x05)<<10);
525 setITVCReg(dev, ITVC_WRITE_DIR, temp);
526
527 /* write address byte 0;*/
528 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
529 temp = temp<<10;
530 setITVCReg(dev, ITVC_WRITE_DIR, temp);
531 temp = temp|((0x05)<<10);
532 setITVCReg(dev, ITVC_WRITE_DIR, temp);
533
534 /*wait for MIRDY line;*/
535 waitForMciComplete(dev);
64fbf444 536
955e6ed8 537 return 0;
64fbf444
PB		 538}
539
540int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
541{
955e6ed8
MCC		 542 u32 temp = 0;
543 u32 return_value = 0;
64fbf444
PB		 544 int ret = 0;
545
955e6ed8
MCC		 546 /*write address byte 2;*/
547 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
64fbf444 548 ((address & 0x003F0000)>>8);
955e6ed8
MCC		 549 temp = temp<<10;
550 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
64fbf444
PB		 551 if (ret < 0)
552 return ret;
955e6ed8
MCC		 553 temp = temp|((0x05)<<10);
554 setITVCReg(dev, ITVC_WRITE_DIR, temp);
555
556 /*write address byte 1*/
557 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
558 temp = temp<<10;
559 setITVCReg(dev, ITVC_WRITE_DIR, temp);
560 temp = temp|((0x05)<<10);
561 setITVCReg(dev, ITVC_WRITE_DIR, temp);
562
563 /*write address byte 0*/
564 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8);
565 temp = temp<<10;
566 setITVCReg(dev, ITVC_WRITE_DIR, temp);
567 temp = temp|((0x05)<<10);
568 setITVCReg(dev, ITVC_WRITE_DIR, temp);
569
570 /*Wait for MIRDY line*/
571 ret = waitForMciComplete(dev);
572
573
574 /*Read data byte 3;*/
575 temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10;
576 setITVCReg(dev, ITVC_READ_DIR, temp);
577 temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10);
578 setITVCReg(dev, ITVC_READ_DIR, temp);
579 getITVCReg(dev, ITVC_READ_DIR, &temp);
580 return_value |= ((temp&0x03FC0000)<<6);
581 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
582
583 /*Read data byte 2;*/
584 temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10;
585 setITVCReg(dev, ITVC_READ_DIR, temp);
586 temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10);
587 setITVCReg(dev, ITVC_READ_DIR, temp);
588 getITVCReg(dev, ITVC_READ_DIR, &temp);
589 return_value |= ((temp&0x03FC0000)>>2);
590 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
591
592 /* Read data byte 1;*/
593 temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10;
594 setITVCReg(dev, ITVC_READ_DIR, temp);
595 temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10);
596 setITVCReg(dev, ITVC_READ_DIR, temp);
597 getITVCReg(dev, ITVC_READ_DIR, &temp);
598 return_value |= ((temp&0x03FC0000)>>10);
599 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
600
601 /*Read data byte 0;*/
602 temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10;
603 setITVCReg(dev, ITVC_READ_DIR, temp);
604 temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10);
605 setITVCReg(dev, ITVC_READ_DIR, temp);
606 getITVCReg(dev, ITVC_READ_DIR, &temp);
607 return_value |= ((temp&0x03FC0000)>>18);
608 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
64fbf444
PB		 609
610 *value = return_value;
955e6ed8 611 return ret;
64fbf444
PB		 612}
613
614void mc417_gpio_set(struct cx231xx *dev, u32 mask)
615{
616 u32 val;
617
618 /* Set the gpio value */
619 mc417_register_read(dev, 0x900C, &val);
620 val |= (mask & 0x000ffff);
621 mc417_register_write(dev, 0x900C, val);
622}
623
624void mc417_gpio_clear(struct cx231xx *dev, u32 mask)
625{
626 u32 val;
627
628 /* Clear the gpio value */
629 mc417_register_read(dev, 0x900C, &val);
630 val &= ~(mask & 0x0000ffff);
631 mc417_register_write(dev, 0x900C, val);
632}
633
634void mc417_gpio_enable(struct cx231xx *dev, u32 mask, int asoutput)
635{
636 u32 val;
637
638 /* Enable GPIO direction bits */
639 mc417_register_read(dev, 0x9020, &val);
640 if (asoutput)
641 val |= (mask & 0x0000ffff);
642 else
643 val &= ~(mask & 0x0000ffff);
644
645 mc417_register_write(dev, 0x9020, val);
646}
647/* ------------------------------------------------------------------ */
648
649/* MPEG encoder API */
650static char *cmd_to_str(int cmd)
651{
652 switch (cmd) {
653 case CX2341X_ENC_PING_FW:
654 return "PING_FW";
655 case CX2341X_ENC_START_CAPTURE:
656 return "START_CAPTURE";
657 case CX2341X_ENC_STOP_CAPTURE:
658 return "STOP_CAPTURE";
659 case CX2341X_ENC_SET_AUDIO_ID:
660 return "SET_AUDIO_ID";
661 case CX2341X_ENC_SET_VIDEO_ID:
662 return "SET_VIDEO_ID";
663 case CX2341X_ENC_SET_PCR_ID:
664 return "SET_PCR_PID";
665 case CX2341X_ENC_SET_FRAME_RATE:
666 return "SET_FRAME_RATE";
667 case CX2341X_ENC_SET_FRAME_SIZE:
668 return "SET_FRAME_SIZE";
669 case CX2341X_ENC_SET_BIT_RATE:
670 return "SET_BIT_RATE";
671 case CX2341X_ENC_SET_GOP_PROPERTIES:
672 return "SET_GOP_PROPERTIES";
673 case CX2341X_ENC_SET_ASPECT_RATIO:
674 return "SET_ASPECT_RATIO";
675 case CX2341X_ENC_SET_DNR_FILTER_MODE:
676 return "SET_DNR_FILTER_PROPS";
677 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
678 return "SET_DNR_FILTER_PROPS";
679 case CX2341X_ENC_SET_CORING_LEVELS:
680 return "SET_CORING_LEVELS";
681 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
682 return "SET_SPATIAL_FILTER_TYPE";
683 case CX2341X_ENC_SET_VBI_LINE:
684 return "SET_VBI_LINE";
685 case CX2341X_ENC_SET_STREAM_TYPE:
686 return "SET_STREAM_TYPE";
687 case CX2341X_ENC_SET_OUTPUT_PORT:
688 return "SET_OUTPUT_PORT";
689 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
690 return "SET_AUDIO_PROPERTIES";
691 case CX2341X_ENC_HALT_FW:
692 return "HALT_FW";
693 case CX2341X_ENC_GET_VERSION:
694 return "GET_VERSION";
695 case CX2341X_ENC_SET_GOP_CLOSURE:
696 return "SET_GOP_CLOSURE";
697 case CX2341X_ENC_GET_SEQ_END:
698 return "GET_SEQ_END";
699 case CX2341X_ENC_SET_PGM_INDEX_INFO:
700 return "SET_PGM_INDEX_INFO";
701 case CX2341X_ENC_SET_VBI_CONFIG:
702 return "SET_VBI_CONFIG";
703 case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
704 return "SET_DMA_BLOCK_SIZE";
705 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
706 return "GET_PREV_DMA_INFO_MB_10";
707 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
708 return "GET_PREV_DMA_INFO_MB_9";
709 case CX2341X_ENC_SCHED_DMA_TO_HOST:
710 return "SCHED_DMA_TO_HOST";
711 case CX2341X_ENC_INITIALIZE_INPUT:
712 return "INITIALIZE_INPUT";
713 case CX2341X_ENC_SET_FRAME_DROP_RATE:
714 return "SET_FRAME_DROP_RATE";
715 case CX2341X_ENC_PAUSE_ENCODER:
716 return "PAUSE_ENCODER";
717 case CX2341X_ENC_REFRESH_INPUT:
718 return "REFRESH_INPUT";
719 case CX2341X_ENC_SET_COPYRIGHT:
720 return "SET_COPYRIGHT";
721 case CX2341X_ENC_SET_EVENT_NOTIFICATION:
722 return "SET_EVENT_NOTIFICATION";
723 case CX2341X_ENC_SET_NUM_VSYNC_LINES:
724 return "SET_NUM_VSYNC_LINES";
725 case CX2341X_ENC_SET_PLACEHOLDER:
726 return "SET_PLACEHOLDER";
727 case CX2341X_ENC_MUTE_VIDEO:
728 return "MUTE_VIDEO";
729 case CX2341X_ENC_MUTE_AUDIO:
730 return "MUTE_AUDIO";
731 case CX2341X_ENC_MISC:
732 return "MISC";
733 default:
734 return "UNKNOWN";
735 }
736}
737
738static int cx231xx_mbox_func(void *priv,
739 u32 command,
740 int in,
741 int out,
742 u32 data[CX2341X_MBOX_MAX_DATA])
743{
744 struct cx231xx *dev = priv;
745 unsigned long timeout;
746 u32 value, flag, retval = 0;
747 int i;
748
749 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
750 cmd_to_str(command));
751
752 /* this may not be 100% safe if we can't read any memory location
753 without side effects */
754 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
755 if (value != 0x12345678) {
756 dprintk(3,
757 "Firmware and/or mailbox pointer not initialized "
758 "or corrupted, signature = 0x%x, cmd = %s\n", value,
759 cmd_to_str(command));
760 return -1;
761 }
762
763 /* This read looks at 32 bits, but flag is only 8 bits.
764 * Seems we also bail if CMD or TIMEOUT bytes are set???
765 */
766 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
767 if (flag) {
768 dprintk(3, "ERROR: Mailbox appears to be in use "
769 "(%x), cmd = %s\n", flag, cmd_to_str(command));
770 return -1;
771 }
772
773 flag |= 1; /* tell 'em we're working on it */
774 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
775
776 /* write command + args + fill remaining with zeros */
777 /* command code */
778 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
779 mc417_memory_write(dev, dev->cx23417_mailbox + 3,
780 IVTV_API_STD_TIMEOUT); /* timeout */
781 for (i = 0; i < in; i++) {
782 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
783 dprintk(3, "API Input %d = %d\n", i, data[i]);
784 }
785 for (; i < CX2341X_MBOX_MAX_DATA; i++)
786 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
787
788 flag |= 3; /* tell 'em we're done writing */
789 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
790
791 /* wait for firmware to handle the API command */
792 timeout = jiffies + msecs_to_jiffies(10);
793 for (;;) {
794 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
795 if (0 != (flag & 4))
796 break;
797 if (time_after(jiffies, timeout)) {
798 dprintk(3, "ERROR: API Mailbox timeout\n");
799 return -1;
800 }
801 udelay(10);
802 }
803
804 /* read output values */
805 for (i = 0; i < out; i++) {
806 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
807 dprintk(3, "API Output %d = %d\n", i, data[i]);
808 }
809
810 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
811 dprintk(3, "API result = %d\n", retval);
812
813 flag = 0;
814 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
815
816 return retval;
817}
818
819/* We don't need to call the API often, so using just one
820 * mailbox will probably suffice
821 */
822static int cx231xx_api_cmd(struct cx231xx *dev,
823 u32 command,
824 u32 inputcnt,
825 u32 outputcnt,
826 ...)
827{
828 u32 data[CX2341X_MBOX_MAX_DATA];
829 va_list vargs;
830 int i, err;
831
832 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
833
834 va_start(vargs, outputcnt);
835 for (i = 0; i < inputcnt; i++)
836 data[i] = va_arg(vargs, int);
837
838 err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
839 for (i = 0; i < outputcnt; i++) {
840 int *vptr = va_arg(vargs, int *);
841 *vptr = data[i];
842 }
843 va_end(vargs);
844
845 return err;
846}
847
848static int cx231xx_find_mailbox(struct cx231xx *dev)
849{
850 u32 signature[4] = {
851 0x12345678, 0x34567812, 0x56781234, 0x78123456
852 };
853 int signaturecnt = 0;
854 u32 value;
855 int i;
856 int ret = 0;
857
858 dprintk(2, "%s()\n", __func__);
859
860 for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
861 ret = mc417_memory_read(dev, i, &value);
862 if (ret < 0)
863 return ret;
864 if (value == signature[signaturecnt])
865 signaturecnt++;
866 else
867 signaturecnt = 0;
868 if (4 == signaturecnt) {
869 dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
870 return i+1;
871 }
872 }
873 dprintk(3, "Mailbox signature values not found!\n");
874 return -1;
875}
876void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value,
877 u32 *p_fw_image)
878{
879
880 u32 temp = 0;
881 int i = 0;
882
955e6ed8
MCC		 883 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
884 temp = temp<<10;
885 *p_fw_image = temp;
886 p_fw_image++;
887 temp = temp|((0x05)<<10);
888 *p_fw_image = temp;
64fbf444 889 p_fw_image++;
64fbf444 890
955e6ed8
MCC		 891 /*write data byte 1;*/
892 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
893 temp = temp<<10;
894 *p_fw_image = temp;
895 p_fw_image++;
896 temp = temp|((0x05)<<10);
897 *p_fw_image = temp;
898 p_fw_image++;
899
900 /*write data byte 2;*/
901 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
902 temp = temp<<10;
903 *p_fw_image = temp;
904 p_fw_image++;
905 temp = temp|((0x05)<<10);
906 *p_fw_image = temp;
907 p_fw_image++;
908
909 /*write data byte 3;*/
910 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
911 temp = temp<<10;
912 *p_fw_image = temp;
913 p_fw_image++;
914 temp = temp|((0x05)<<10);
915 *p_fw_image = temp;
916 p_fw_image++;
917
918 /* write address byte 2;*/
919 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
920 ((address & 0x003F0000)>>8);
921 temp = temp<<10;
922 *p_fw_image = temp;
923 p_fw_image++;
924 temp = temp|((0x05)<<10);
925 *p_fw_image = temp;
926 p_fw_image++;
927
928 /* write address byte 1;*/
929 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
930 temp = temp<<10;
931 *p_fw_image = temp;
932 p_fw_image++;
933 temp = temp|((0x05)<<10);
934 *p_fw_image = temp;
935 p_fw_image++;
936
937 /* write address byte 0;*/
938 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
939 temp = temp<<10;
940 *p_fw_image = temp;
941 p_fw_image++;
942 temp = temp|((0x05)<<10);
943 *p_fw_image = temp;
944 p_fw_image++;
945
946 for (i = 0; i < 6; i++) {
947 *p_fw_image = 0xFFFFFFFF;
948 p_fw_image++;
949 }
64fbf444
PB		 950}
951
952
953static int cx231xx_load_firmware(struct cx231xx *dev)
954{
955 static const unsigned char magic[8] = {
956 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
957 };
958 const struct firmware *firmware;
959 int i, retval = 0;
960 u32 value = 0;
961 u32 gpio_output = 0;
962 /*u32 checksum = 0;*/
963 /*u32 *dataptr;*/
964 u32 transfer_size = 0;
965 u32 fw_data = 0;
966 u32 address = 0;
967 /*u32 current_fw[800];*/
968 u32 *p_current_fw, *p_fw;
969 u32 *p_fw_data;
970 int frame = 0;
971 u16 _buffer_size = 4096;
972 u8 *p_buffer;
973
974 p_current_fw = (u32 *)vmalloc(1884180*4);
975 p_fw = p_current_fw;
976 if (p_current_fw == 0) {
977 dprintk(2, "FAIL!!!\n");
978 return -1;
979 }
980
981 p_buffer = (u8 *)vmalloc(4096);
982 if (p_buffer == 0) {
983 dprintk(2, "FAIL!!!\n");
984 return -1;
985 }
986
987 dprintk(2, "%s()\n", __func__);
988
989 /* Save GPIO settings before reset of APU */
990 retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
991 retval |= mc417_memory_read(dev, 0x900C, &value);
992
993 retval = mc417_register_write(dev,
994 IVTV_REG_VPU, 0xFFFFFFED);
995 retval |= mc417_register_write(dev,
996 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
997 retval |= mc417_register_write(dev,
998 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
999 retval |= mc417_register_write(dev,
1000 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
1001 retval |= mc417_register_write(dev,
1002 IVTV_REG_APU, 0);
1003
1004 if (retval != 0) {
1005 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1006 __func__);
1007 return -1;
1008 }
1009
1010 retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
1011 &dev->udev->dev);
1012
1013 if (retval != 0) {
1014 printk(KERN_ERR
1015 "ERROR: Hotplug firmware request failed (%s).\n",
1016 CX231xx_FIRM_IMAGE_NAME);
1017 printk(KERN_ERR "Please fix your hotplug setup, the board will "
1018 "not work without firmware loaded!\n");
1019 return -1;
1020 }
1021
1022 if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
1023 printk(KERN_ERR "ERROR: Firmware size mismatch "
1024 "(have %zd, expected %d)\n",
1025 firmware->size, CX231xx_FIRM_IMAGE_SIZE);
1026 release_firmware(firmware);
1027 return -1;
1028 }
1029
1030 if (0 != memcmp(firmware->data, magic, 8)) {
1031 printk(KERN_ERR
1032 "ERROR: Firmware magic mismatch, wrong file?\n");
1033 release_firmware(firmware);
1034 return -1;
1035 }
1036
1037 initGPIO(dev);
1038
1039 /* transfer to the chip */
1040 dprintk(2, "Loading firmware to GPIO...\n");
1041 p_fw_data = (u32 *)firmware->data;
62c78c96 1042 dprintk(2, "firmware->size=%zd\n", firmware->size);
64fbf444
PB		 1043 for (transfer_size = 0; transfer_size < firmware->size;
1044 transfer_size += 4) {
1045 fw_data = *p_fw_data;
1046
1047 mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw);
1048 address = address + 1;
1049 p_current_fw += 20;
1050 p_fw_data += 1;
1051 }
1052
955e6ed8 1053 /*download the firmware by ep5-out*/
64fbf444
PB		 1054
1055 for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
bae94dc3 1056 frame++) {
64fbf444 1057 for (i = 0; i < _buffer_size; i++) {
bae94dc3
MCC		 1058 *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
1059 i++;
1060 *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
1061 i++;
1062 *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
1063 i++;
1064 *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
64fbf444
PB		 1065 }
1066 cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1067 }
1068
1069 p_current_fw = p_fw;
1070 vfree(p_current_fw);
1071 p_current_fw = NULL;
1072 uninitGPIO(dev);
1073 release_firmware(firmware);
1074 dprintk(1, "Firmware upload successful.\n");
1075
1076 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1077 IVTV_CMD_HW_BLOCKS_RST);
1078 if (retval < 0) {
1079 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1080 __func__);
1081 return retval;
1082 }
1083 /* F/W power up disturbs the GPIOs, restore state */
1084 retval |= mc417_register_write(dev, 0x9020, gpio_output);
1085 retval |= mc417_register_write(dev, 0x900C, value);
1086
1087 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1088 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1089
1090 if (retval < 0) {
1091 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1092 __func__);
1093 return retval;
1094 }
1095 return 0;
1096}
1097
1098void cx231xx_417_check_encoder(struct cx231xx *dev)
1099{
1100 u32 status, seq;
1101
1102 status = 0;
1103 seq = 0;
1104 cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1105 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1106}
1107
1108static void cx231xx_codec_settings(struct cx231xx *dev)
1109{
1110 dprintk(1, "%s()\n", __func__);
1111
1112 /* assign frame size */
1113 cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1114 dev->ts1.height, dev->ts1.width);
1115
1116 dev->mpeg_params.width = dev->ts1.width;
1117 dev->mpeg_params.height = dev->ts1.height;
1118
1119 cx2341x_update(dev, cx231xx_mbox_func, NULL, &dev->mpeg_params);
1120
1121 cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1122 cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1123}
1124
1125static int cx231xx_initialize_codec(struct cx231xx *dev)
1126{
1127 int version;
1128 int retval;
1129 u32 i, data[7];
1130 u32 val = 0;
1131
1132 dprintk(1, "%s()\n", __func__);
1133 cx231xx_disable656(dev);
1134 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1135 if (retval < 0) {
1136 dprintk(2, "%s() PING OK\n", __func__);
1137 retval = cx231xx_load_firmware(dev);
1138 if (retval < 0) {
1139 printk(KERN_ERR "%s() f/w load failed\n", __func__);
1140 return retval;
1141 }
1142 retval = cx231xx_find_mailbox(dev);
1143 if (retval < 0) {
1144 printk(KERN_ERR "%s() mailbox < 0, error\n",
1145 __func__);
1146 return -1;
1147 }
1148 dev->cx23417_mailbox = retval;
1149 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1150 if (retval < 0) {
1151 printk(KERN_ERR
1152 "ERROR: cx23417 firmware ping failed!\n");
1153 return -1;
1154 }
1155 retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1156 &version);
1157 if (retval < 0) {
1158 printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1159 "version failed!\n");
1160 return -1;
1161 }
1162 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1163 msleep(200);
1164 }
1165
1166 for (i = 0; i < 1; i++) {
1167 retval = mc417_register_read(dev, 0x20f8, &val);
1168 dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n",
1169 val);
1170 if (retval < 0)
1171 return retval;
1172 }
1173
1174 cx231xx_enable656(dev);
1175 /* stop mpeg capture */
1176 cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
1177 3, 0, 1, 3, 4);
1178
1179 cx231xx_codec_settings(dev);
1180 msleep(60);
1181
1182/* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1183 CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1184 cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1185 CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1186 0, 0);
1187*/
1188 /* Setup to capture VBI */
1189 data[0] = 0x0001BD00;
1190 data[1] = 1; /* frames per interrupt */
1191 data[2] = 4; /* total bufs */
1192 data[3] = 0x91559155; /* start codes */
1193 data[4] = 0x206080C0; /* stop codes */
1194 data[5] = 6; /* lines */
1195 data[6] = 64; /* BPL */
1196/*
1197 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1198 data[2], data[3], data[4], data[5], data[6]);
1199
1200 for (i = 2; i <= 24; i++) {
1201 int valid;
1202
1203 valid = ((i >= 19) && (i <= 21));
1204 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1205 valid, 0 , 0, 0);
1206 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1207 i | 0x80000000, valid, 0, 0, 0);
1208 }
1209*/
1210/* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1211 msleep(60);
1212*/
1213 /* initialize the video input */
1214 retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1215 if (retval < 0)
1216 return retval;
1217 msleep(60);
1218
1219 /* Enable VIP style pixel invalidation so we work with scaled mode */
1220 mc417_memory_write(dev, 2120, 0x00000080);
1221
1222 /* start capturing to the host interface */
1223 retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1224 CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1225 if (retval < 0)
1226 return retval;
1227 msleep(10);
1228
1229 for (i = 0; i < 1; i++) {
1230 mc417_register_read(dev, 0x20f8, &val);
1231 dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1232 }
1233
1234 return 0;
1235}
1236
1237/* ------------------------------------------------------------------ */
1238
1239static int bb_buf_setup(struct videobuf_queue *q,
1240 unsigned int *count, unsigned int *size)
1241{
1242 struct cx231xx_fh *fh = q->priv_data;
1243
1244 fh->dev->ts1.ts_packet_size = mpeglinesize;
1245 fh->dev->ts1.ts_packet_count = mpeglines;
1246
1247 *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1248 *count = mpegbufs;
1249
1250 return 0;
1251}
1252static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1253{
1254 struct cx231xx_fh *fh = vq->priv_data;
1255 struct cx231xx *dev = fh->dev;
1256 unsigned long flags = 0;
1257
1258 if (in_interrupt())
1259 BUG();
1260
1261 spin_lock_irqsave(&dev->video_mode.slock, flags);
1262 if (dev->USE_ISO) {
1263 if (dev->video_mode.isoc_ctl.buf == buf)
1264 dev->video_mode.isoc_ctl.buf = NULL;
1265 } else {
1266 if (dev->video_mode.bulk_ctl.buf == buf)
1267 dev->video_mode.bulk_ctl.buf = NULL;
1268 }
1269 spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1270 videobuf_waiton(vq, &buf->vb, 0, 0);
1271 videobuf_vmalloc_free(&buf->vb);
1272 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1273}
1274
1275void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1276 struct cx231xx_dmaqueue *dma_q)
1277{
1278 void *vbuf;
1279 struct cx231xx_buffer *buf;
1280 u32 tail_data = 0;
1281 char *p_data;
1282
1283 if (dma_q->mpeg_buffer_done == 0) {
1284 if (list_empty(&dma_q->active))
1285 return;
1286
1287 buf = list_entry(dma_q->active.next,
1288 struct cx231xx_buffer, vb.queue);
1289 dev->video_mode.isoc_ctl.buf = buf;
1290 dma_q->mpeg_buffer_done = 1;
1291 }
1292 /* Fill buffer */
1293 buf = dev->video_mode.isoc_ctl.buf;
1294 vbuf = videobuf_to_vmalloc(&buf->vb);
1295
1296 if ((dma_q->mpeg_buffer_completed+len) <
1297 mpeglines*mpeglinesize) {
1298 if (dma_q->add_ps_package_head ==
1299 CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1300 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1301 dma_q->ps_head, 3);
1302 dma_q->mpeg_buffer_completed =
1303 dma_q->mpeg_buffer_completed + 3;
1304 dma_q->add_ps_package_head =
1305 CX231XX_NONEED_PS_PACKAGE_HEAD;
1306 }
1307 memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1308 dma_q->mpeg_buffer_completed =
1309 dma_q->mpeg_buffer_completed + len;
1310 } else {
1311 dma_q->mpeg_buffer_done = 0;
1312
1313 tail_data =
1314 mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1315 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1316 data, tail_data);
1317
1318 buf->vb.state = VIDEOBUF_DONE;
1319 buf->vb.field_count++;
1320 do_gettimeofday(&buf->vb.ts);
1321 list_del(&buf->vb.queue);
1322 wake_up(&buf->vb.done);
1323 dma_q->mpeg_buffer_completed = 0;
1324
1325 if (len - tail_data > 0) {
1326 p_data = data + tail_data;
1327 dma_q->left_data_count = len - tail_data;
1328 memcpy(dma_q->p_left_data,
1329 p_data, len - tail_data);
1330 }
1331
1332 }
1333
1334 return;
1335}
1336
1337void buffer_filled(char *data, int len, struct urb *urb,
1338 struct cx231xx_dmaqueue *dma_q)
1339{
1340 void *vbuf;
1341 struct cx231xx_buffer *buf;
1342
1343 if (list_empty(&dma_q->active))
1344 return;
1345
1346
1347 buf = list_entry(dma_q->active.next,
1348 struct cx231xx_buffer, vb.queue);
1349
1350
1351 /* Fill buffer */
1352 vbuf = videobuf_to_vmalloc(&buf->vb);
1353 memcpy(vbuf, data, len);
1354 buf->vb.state = VIDEOBUF_DONE;
1355 buf->vb.field_count++;
1356 do_gettimeofday(&buf->vb.ts);
1357 list_del(&buf->vb.queue);
1358 wake_up(&buf->vb.done);
1359
1360 return;
1361}
1362static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1363{
1364 struct cx231xx_dmaqueue *dma_q = urb->context;
1365 unsigned char *p_buffer;
1366 u32 buffer_size = 0;
1367 u32 i = 0;
1368
1369 for (i = 0; i < urb->number_of_packets; i++) {
1370 if (dma_q->left_data_count > 0) {
1371 buffer_copy(dev, dma_q->p_left_data,
1372 dma_q->left_data_count, urb, dma_q);
1373 dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1374 dma_q->left_data_count = 0;
1375 }
1376
1377 p_buffer = urb->transfer_buffer +
1378 urb->iso_frame_desc[i].offset;
1379 buffer_size = urb->iso_frame_desc[i].actual_length;
1380
1381 if (buffer_size > 0)
1382 buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1383 }
1384
1385 return 0;
1386}
1387static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1388{
1389
1390 /*char *outp;*/
1391 /*struct cx231xx_buffer *buf;*/
1392 struct cx231xx_dmaqueue *dma_q = urb->context;
1393 unsigned char *p_buffer, *buffer;
1394 u32 buffer_size = 0;
1395
1396 p_buffer = urb->transfer_buffer;
1397 buffer_size = urb->actual_length;
1398
1399 buffer = kmalloc(buffer_size, GFP_ATOMIC);
1400
1401 memcpy(buffer, dma_q->ps_head, 3);
1402 memcpy(buffer+3, p_buffer, buffer_size-3);
1403 memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1404
1405 p_buffer = buffer;
1406 buffer_filled(p_buffer, buffer_size, urb, dma_q);
1407
1408 kfree(buffer);
1409 return 0;
1410}
1411
1412static int bb_buf_prepare(struct videobuf_queue *q,
1413 struct videobuf_buffer *vb, enum v4l2_field field)
1414{
1415 struct cx231xx_fh *fh = q->priv_data;
1416 struct cx231xx_buffer *buf =
1417 container_of(vb, struct cx231xx_buffer, vb);
1418 struct cx231xx *dev = fh->dev;
1419 int rc = 0, urb_init = 0;
1420 int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1421
1422 dma_qq = &dev->video_mode.vidq;
1423
1424 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1425 return -EINVAL;
1426 buf->vb.width = fh->dev->ts1.ts_packet_size;
1427 buf->vb.height = fh->dev->ts1.ts_packet_count;
1428 buf->vb.size = size;
1429 buf->vb.field = field;
1430
1431 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1432 rc = videobuf_iolock(q, &buf->vb, NULL);
1433 if (rc < 0)
1434 goto fail;
1435 }
1436
1437 if (dev->USE_ISO) {
1438 if (!dev->video_mode.isoc_ctl.num_bufs)
1439 urb_init = 1;
1440 } else {
1441 if (!dev->video_mode.bulk_ctl.num_bufs)
1442 urb_init = 1;
1443 }
1444 /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1445 urb_init, dev->video_mode.max_pkt_size);*/
1446 dev->mode_tv = 1;
1447
1448 if (urb_init) {
1449 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1450 rc = cx231xx_unmute_audio(dev);
1451 if (dev->USE_ISO) {
1452 cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1453 rc = cx231xx_init_isoc(dev, mpeglines,
1454 mpegbufs,
1455 dev->ts1_mode.max_pkt_size,
1456 cx231xx_isoc_copy);
1457 } else {
1458 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1459 rc = cx231xx_init_bulk(dev, mpeglines,
1460 mpegbufs,
1461 dev->ts1_mode.max_pkt_size,
1462 cx231xx_bulk_copy);
1463 }
1464 if (rc < 0)
1465 goto fail;
1466 }
1467
1468 buf->vb.state = VIDEOBUF_PREPARED;
1469 return 0;
1470
1471fail:
1472 free_buffer(q, buf);
1473 return rc;
1474}
1475
1476static void bb_buf_queue(struct videobuf_queue *q,
1477 struct videobuf_buffer *vb)
1478{
1479 struct cx231xx_fh *fh = q->priv_data;
1480
1481 struct cx231xx_buffer *buf =
1482 container_of(vb, struct cx231xx_buffer, vb);
1483 struct cx231xx *dev = fh->dev;
1484 struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1485
1486 buf->vb.state = VIDEOBUF_QUEUED;
1487 list_add_tail(&buf->vb.queue, &vidq->active);
1488
1489}
1490
1491static void bb_buf_release(struct videobuf_queue *q,
1492 struct videobuf_buffer *vb)
1493{
1494 struct cx231xx_buffer *buf =
1495 container_of(vb, struct cx231xx_buffer, vb);
1496 /*struct cx231xx_fh *fh = q->priv_data;*/
1497 /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1498
1499 free_buffer(q, buf);
1500}
1501
1502static struct videobuf_queue_ops cx231xx_qops = {
1503 .buf_setup = bb_buf_setup,
1504 .buf_prepare = bb_buf_prepare,
1505 .buf_queue = bb_buf_queue,
1506 .buf_release = bb_buf_release,
1507};
1508
1509/* ------------------------------------------------------------------ */
1510
1511static const u32 *ctrl_classes[] = {
1512 cx2341x_mpeg_ctrls,
1513 NULL
1514};
1515
1516static int cx231xx_queryctrl(struct cx231xx *dev,
1517 struct v4l2_queryctrl *qctrl)
1518{
1519 qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1520 if (qctrl->id == 0)
1521 return -EINVAL;
1522
1523 /* MPEG V4L2 controls */
1524 if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1525 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1526
1527 return 0;
1528}
1529
1530static int cx231xx_querymenu(struct cx231xx *dev,
1531 struct v4l2_querymenu *qmenu)
1532{
1533 struct v4l2_queryctrl qctrl;
1534
1535 qctrl.id = qmenu->id;
1536 cx231xx_queryctrl(dev, &qctrl);
1537 return v4l2_ctrl_query_menu(qmenu, &qctrl,
1538 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1539}
1540
1541static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1542{
1543 struct cx231xx_fh *fh = file->private_data;
1544 struct cx231xx *dev = fh->dev;
1545
1546 *norm = dev->encodernorm.id;
1547 return 0;
1548}
1549static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1550{
1551 struct cx231xx_fh *fh = file->private_data;
1552 struct cx231xx *dev = fh->dev;
1553 unsigned int i;
1554
1555 for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1556 if (*id & cx231xx_tvnorms[i].id)
1557 break;
1558 if (i == ARRAY_SIZE(cx231xx_tvnorms))
1559 return -EINVAL;
1560 dev->encodernorm = cx231xx_tvnorms[i];
1561
1562 if (dev->encodernorm.id & 0xb000) {
1563 dprintk(3, "encodernorm set to NTSC\n");
1564 dev->norm = V4L2_STD_NTSC;
1565 dev->ts1.height = 480;
1566 dev->mpeg_params.is_50hz = 0;
1567 } else {
1568 dprintk(3, "encodernorm set to PAL\n");
1569 dev->norm = V4L2_STD_PAL_B;
1570 dev->ts1.height = 576;
1571 dev->mpeg_params.is_50hz = 1;
1572 }
1573 call_all(dev, core, s_std, dev->norm);
1574 /* do mode control overrides */
1575 cx231xx_do_mode_ctrl_overrides(dev);
1576
1577 dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1578 return 0;
1579}
1580static int vidioc_g_audio(struct file *file, void *fh,
1581 struct v4l2_audio *a)
1582{
1583 struct v4l2_audio *vin = a;
1584
1585 int ret = -EINVAL;
1586 if (vin->index > 0)
1587 return ret;
1588 strncpy(vin->name, "VideoGrabber Audio", 14);
1589 vin->capability = V4L2_AUDCAP_STEREO;
1590return 0;
1591}
1592static int vidioc_enumaudio(struct file *file, void *fh,
1593 struct v4l2_audio *a)
1594{
1595 struct v4l2_audio *vin = a;
1596
1597 int ret = -EINVAL;
1598
1599 if (vin->index > 0)
1600 return ret;
1601 strncpy(vin->name, "VideoGrabber Audio", 14);
1602 vin->capability = V4L2_AUDCAP_STEREO;
1603
1604
1605return 0;
1606}
1607static const char *iname[] = {
1608 [CX231XX_VMUX_COMPOSITE1] = "Composite1",
1609 [CX231XX_VMUX_SVIDEO] = "S-Video",
1610 [CX231XX_VMUX_TELEVISION] = "Television",
1611 [CX231XX_VMUX_CABLE] = "Cable TV",
1612 [CX231XX_VMUX_DVB] = "DVB",
1613 [CX231XX_VMUX_DEBUG] = "for debug only",
1614};
1615static int vidioc_enum_input(struct file *file, void *priv,
1616 struct v4l2_input *i)
1617{
1618 struct cx231xx_fh *fh = file->private_data;
1619 struct cx231xx *dev = fh->dev;
1620 struct cx231xx_input *input;
1621 int n;
1622 dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i->index);
1623
1624 if (i->index >= 4)
1625 return -EINVAL;
1626
1627
1628 input = &cx231xx_boards[dev->model].input[i->index];
1629
1630 if (input->type == 0)
1631 return -EINVAL;
1632
1633 /* FIXME
1634 * strcpy(i->name, input->name); */
1635
1636 n = i->index;
1637 strcpy(i->name, iname[INPUT(n)->type]);
1638
1639 if (input->type == CX231XX_VMUX_TELEVISION ||
1640 input->type == CX231XX_VMUX_CABLE)
1641 i->type = V4L2_INPUT_TYPE_TUNER;
1642 else
1643 i->type = V4L2_INPUT_TYPE_CAMERA;
1644
1645
1646 return 0;
1647}
1648
1649static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1650{
1651 *i = 0;
1652 return 0;
1653}
1654
1655static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1656{
1657 struct cx231xx_fh *fh = file->private_data;
1658 struct cx231xx *dev = fh->dev;
1659
1660 dprintk(3, "enter vidioc_s_input() i=%d\n", i);
1661
1662 mutex_lock(&dev->lock);
1663
1664 video_mux(dev, i);
1665
1666 mutex_unlock(&dev->lock);
1667
1668 if (i >= 4)
1669 return -EINVAL;
1670 dev->input = i;
1671 dprintk(3, "exit vidioc_s_input()\n");
1672 return 0;
1673}
1674
1675static int vidioc_g_tuner(struct file *file, void *priv,
1676 struct v4l2_tuner *t)
1677{
1678 return 0;
1679}
1680
1681static int vidioc_s_tuner(struct file *file, void *priv,
1682 struct v4l2_tuner *t)
1683{
1684 return 0;
1685}
1686
1687static int vidioc_g_frequency(struct file *file, void *priv,
1688 struct v4l2_frequency *f)
1689{
1690 return 0;
1691}
1692
1693static int vidioc_s_frequency(struct file *file, void *priv,
1694 struct v4l2_frequency *f)
1695{
1696
1697
1698 return 0;
1699}
1700
1701static int vidioc_s_ctrl(struct file *file, void *priv,
1702 struct v4l2_control *ctl)
1703{
1704 struct cx231xx_fh *fh = file->private_data;
1705 struct cx231xx *dev = fh->dev;
1706 dprintk(3, "enter vidioc_s_ctrl()\n");
1707 /* Update the A/V core */
1708 call_all(dev, core, s_ctrl, ctl);
1709 dprintk(3, "exit vidioc_s_ctrl()\n");
1710 return 0;
1711}
1712static struct v4l2_capability pvr_capability = {
1713 .driver = "cx231xx",
1714 .card = "VideoGrabber",
1715 .bus_info = "usb",
1716 .version = 1,
1717 .capabilities = (V4L2_CAP_VIDEO_CAPTURE |
1718 V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_RADIO |
1719 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE),
1720 .reserved = {0, 0, 0, 0}
1721};
1722static int vidioc_querycap(struct file *file, void *priv,
1723 struct v4l2_capability *cap)
1724{
1725
1726
1727
1728 memcpy(cap, &pvr_capability, sizeof(struct v4l2_capability));
1729 return 0;
1730}
1731
1732static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1733 struct v4l2_fmtdesc *f)
1734{
1735
1736 if (f->index != 0)
1737 return -EINVAL;
1738
1739 strlcpy(f->description, "MPEG", sizeof(f->description));
1740 f->pixelformat = V4L2_PIX_FMT_MPEG;
1741
1742 return 0;
1743}
1744
1745static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1746 struct v4l2_format *f)
1747{
1748 struct cx231xx_fh *fh = file->private_data;
1749 struct cx231xx *dev = fh->dev;
1750 dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1751 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1752 f->fmt.pix.bytesperline = 0;
1753 f->fmt.pix.sizeimage =
1754 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1755 f->fmt.pix.colorspace = 0;
1756 f->fmt.pix.width = dev->ts1.width;
1757 f->fmt.pix.height = dev->ts1.height;
1758 f->fmt.pix.field = fh->vidq.field;
1759 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1760 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1761 dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1762 return 0;
1763}
1764
1765static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1766 struct v4l2_format *f)
1767{
1768 struct cx231xx_fh *fh = file->private_data;
1769 struct cx231xx *dev = fh->dev;
1770 dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1771 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1772 f->fmt.pix.bytesperline = 0;
1773 f->fmt.pix.sizeimage =
1774 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1775 f->fmt.pix.colorspace = 0;
1776 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1777 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1778 dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1779 return 0;
1780}
1781
1782static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1783 struct v4l2_format *f)
1784{
1785
1786 return 0;
1787}
1788
1789static int vidioc_reqbufs(struct file *file, void *priv,
1790 struct v4l2_requestbuffers *p)
1791{
1792 struct cx231xx_fh *fh = file->private_data;
1793
1794 return videobuf_reqbufs(&fh->vidq, p);
1795}
1796
1797static int vidioc_querybuf(struct file *file, void *priv,
1798 struct v4l2_buffer *p)
1799{
1800 struct cx231xx_fh *fh = file->private_data;
1801
1802 return videobuf_querybuf(&fh->vidq, p);
1803}
1804
1805static int vidioc_qbuf(struct file *file, void *priv,
1806 struct v4l2_buffer *p)
1807{
1808 struct cx231xx_fh *fh = file->private_data;
1809
1810 return videobuf_qbuf(&fh->vidq, p);
1811}
1812
1813static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1814{
1815 struct cx231xx_fh *fh = priv;
1816
1817 return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1818}
1819
1820
1821static int vidioc_streamon(struct file *file, void *priv,
1822 enum v4l2_buf_type i)
1823{
1824 struct cx231xx_fh *fh = file->private_data;
1825
1826 struct cx231xx *dev = fh->dev;
1827 int rc = 0;
1828 dprintk(3, "enter vidioc_streamon()\n");
1829 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1830 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1831 if (dev->USE_ISO)
1832 rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1833 CX231XX_NUM_BUFS,
1834 dev->video_mode.max_pkt_size,
1835 cx231xx_isoc_copy);
1836 else {
1837 rc = cx231xx_init_bulk(dev, 320,
1838 5,
1839 dev->ts1_mode.max_pkt_size,
1840 cx231xx_bulk_copy);
1841 }
1842 dprintk(3, "exit vidioc_streamon()\n");
1843 return videobuf_streamon(&fh->vidq);
1844}
1845
1846static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1847{
1848 struct cx231xx_fh *fh = file->private_data;
1849
1850 return videobuf_streamoff(&fh->vidq);
1851}
1852
1853static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1854 struct v4l2_ext_controls *f)
1855{
1856 struct cx231xx_fh *fh = priv;
1857 struct cx231xx *dev = fh->dev;
1858 dprintk(3, "enter vidioc_g_ext_ctrls()\n");
1859 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1860 return -EINVAL;
1861 dprintk(3, "exit vidioc_g_ext_ctrls()\n");
1862 return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1863}
1864
1865static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1866 struct v4l2_ext_controls *f)
1867{
1868 struct cx231xx_fh *fh = priv;
1869 struct cx231xx *dev = fh->dev;
1870 struct cx2341x_mpeg_params p;
1871 int err;
1872 dprintk(3, "enter vidioc_s_ext_ctrls()\n");
1873 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1874 return -EINVAL;
1875
1876 p = dev->mpeg_params;
1877 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1878 if (err == 0) {
1879 err = cx2341x_update(dev, cx231xx_mbox_func,
1880 &dev->mpeg_params, &p);
1881 dev->mpeg_params = p;
1882 }
1883
1884 return err;
1885
1886
1887return 0;
1888}
1889
1890static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1891 struct v4l2_ext_controls *f)
1892{
1893 struct cx231xx_fh *fh = priv;
1894 struct cx231xx *dev = fh->dev;
1895 struct cx2341x_mpeg_params p;
1896 int err;
1897 dprintk(3, "enter vidioc_try_ext_ctrls()\n");
1898 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1899 return -EINVAL;
1900
1901 p = dev->mpeg_params;
1902 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1903 dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err);
1904 return err;
1905}
1906
1907static int vidioc_log_status(struct file *file, void *priv)
1908{
1909 struct cx231xx_fh *fh = priv;
1910 struct cx231xx *dev = fh->dev;
1911 char name[32 + 2];
1912
1913 snprintf(name, sizeof(name), "%s/2", dev->name);
1914 dprintk(3,
1915 "%s/2: ============ START LOG STATUS ============\n",
1916 dev->name);
1917 call_all(dev, core, log_status);
1918 cx2341x_log_status(&dev->mpeg_params, name);
1919 dprintk(3,
1920 "%s/2: ============= END LOG STATUS =============\n",
1921 dev->name);
1922 return 0;
1923}
1924
1925static int vidioc_querymenu(struct file *file, void *priv,
1926 struct v4l2_querymenu *a)
1927{
1928 struct cx231xx_fh *fh = priv;
1929 struct cx231xx *dev = fh->dev;
1930 dprintk(3, "enter vidioc_querymenu()\n");
1931 dprintk(3, "exit vidioc_querymenu()\n");
1932 return cx231xx_querymenu(dev, a);
1933}
1934
1935static int vidioc_queryctrl(struct file *file, void *priv,
1936 struct v4l2_queryctrl *c)
1937{
1938 struct cx231xx_fh *fh = priv;
1939 struct cx231xx *dev = fh->dev;
1940 dprintk(3, "enter vidioc_queryctrl()\n");
1941 dprintk(3, "exit vidioc_queryctrl()\n");
1942 return cx231xx_queryctrl(dev, c);
1943}
1944
1945static int mpeg_open(struct file *file)
1946{
1947 int minor = video_devdata(file)->minor;
1948 struct cx231xx *h, *dev = NULL;
1949 /*struct list_head *list;*/
1950 struct cx231xx_fh *fh;
1951 /*u32 value = 0;*/
1952
1953 dprintk(2, "%s()\n", __func__);
1954
1955 list_for_each_entry(h, &cx231xx_devlist, devlist) {
1956 if (h->v4l_device->minor == minor)
1957 dev = h;
1958 }
1959
1960 if (dev == NULL) {
1961 unlock_kernel();
1962 return -ENODEV;
1963 }
1964 mutex_lock(&dev->lock);
1965
1966 /* allocate + initialize per filehandle data */
1967 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1968 if (NULL == fh) {
1969 mutex_unlock(&dev->lock);
1970 return -ENOMEM;
1971 }
1972
1973 file->private_data = fh;
1974 fh->dev = dev;
1975
1976
1977 videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1978 NULL, &dev->video_mode.slock,
1979 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1980 sizeof(struct cx231xx_buffer), fh, NULL);
1981/*
1982 videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1983 &dev->udev->dev, &dev->ts1.slock,
1984 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1985 V4L2_FIELD_INTERLACED,
1986 sizeof(struct cx231xx_buffer),
1987 fh, NULL);
1988*/
1989
1990
1991 cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1992 cx231xx_set_gpio_value(dev, 2, 0);
1993
1994 cx231xx_initialize_codec(dev);
1995
1996 mutex_unlock(&dev->lock);
1997 cx231xx_start_TS1(dev);
1998
1999 return 0;
2000}
2001
2002static int mpeg_release(struct file *file)
2003{
2004 struct cx231xx_fh *fh = file->private_data;
2005 struct cx231xx *dev = fh->dev;
2006
dd067a8d 2007 dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
64fbf444
PB		 2008
2009 if (!dev) {
2010 dprintk(3, "abort!!!\n");
2011 return 0;
2012 }
2013
2014 mutex_lock(&dev->lock);
2015
2016 cx231xx_stop_TS1(dev);
2017
2018 /* do this before setting alternate! */
2019 if (dev->USE_ISO)
2020 cx231xx_uninit_isoc(dev);
2021 else
2022 cx231xx_uninit_bulk(dev);
2023 cx231xx_set_mode(dev, CX231XX_SUSPEND);
2024
2025 cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
2026 CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
2027 CX231xx_RAW_BITS_NONE);
2028
2029 /* FIXME: Review this crap */
2030 /* Shut device down on last close */
2031 if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
2032 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
2033 /* stop mpeg capture */
2034
2035 msleep(500);
2036 cx231xx_417_check_encoder(dev);
2037
2038 }
2039 }
2040
2041 if (fh->vidq.streaming)
2042 videobuf_streamoff(&fh->vidq);
2043 if (fh->vidq.reading)
2044 videobuf_read_stop(&fh->vidq);
2045
2046 videobuf_mmap_free(&fh->vidq);
2047 file->private_data = NULL;
2048 kfree(fh);
2049 mutex_unlock(&dev->lock);
2050 return 0;
2051}
2052
2053static ssize_t mpeg_read(struct file *file, char __user *data,
2054 size_t count, loff_t *ppos)
2055{
2056 struct cx231xx_fh *fh = file->private_data;
2057 struct cx231xx *dev = fh->dev;
2058
2059
2060 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
2061 /* Start mpeg encoder on first read. */
2062 if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
2063 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
2064 if (cx231xx_initialize_codec(dev) < 0)
2065 return -EINVAL;
2066 }
2067 }
2068
2069 return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
2070 file->f_flags & O_NONBLOCK);
2071}
2072
2073static unsigned int mpeg_poll(struct file *file,
2074 struct poll_table_struct *wait)
2075{
2076 struct cx231xx_fh *fh = file->private_data;
2077 /*struct cx231xx *dev = fh->dev;*/
2078
2079 /*dprintk(2, "%s\n", __func__);*/
2080
2081 return videobuf_poll_stream(file, &fh->vidq, wait);
2082}
2083
2084static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
2085{
2086 struct cx231xx_fh *fh = file->private_data;
2087 struct cx231xx *dev = fh->dev;
2088
2089 dprintk(2, "%s()\n", __func__);
2090
2091 return videobuf_mmap_mapper(&fh->vidq, vma);
2092}
2093
2094static struct v4l2_file_operations mpeg_fops = {
2095 .owner = THIS_MODULE,
2096 .open = mpeg_open,
2097 .release = mpeg_release,
2098 .read = mpeg_read,
2099 .poll = mpeg_poll,
2100 .mmap = mpeg_mmap,
2101 .ioctl = video_ioctl2,
2102};
2103
2104static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
2105 .vidioc_s_std = vidioc_s_std,
2106 .vidioc_g_std = vidioc_g_std,
2107 .vidioc_enum_input = vidioc_enum_input,
2108 .vidioc_enumaudio = vidioc_enumaudio,
955e6ed8 2109 .vidioc_g_audio = vidioc_g_audio,
64fbf444
PB		 2110 .vidioc_g_input = vidioc_g_input,
2111 .vidioc_s_input = vidioc_s_input,
2112 .vidioc_g_tuner = vidioc_g_tuner,
2113 .vidioc_s_tuner = vidioc_s_tuner,
2114 .vidioc_g_frequency = vidioc_g_frequency,
2115 .vidioc_s_frequency = vidioc_s_frequency,
2116 .vidioc_s_ctrl = vidioc_s_ctrl,
2117 .vidioc_querycap = vidioc_querycap,
2118 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
2119 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
2120 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
2121 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
2122 .vidioc_reqbufs = vidioc_reqbufs,
2123 .vidioc_querybuf = vidioc_querybuf,
2124 .vidioc_qbuf = vidioc_qbuf,
2125 .vidioc_dqbuf = vidioc_dqbuf,
2126 .vidioc_streamon = vidioc_streamon,
2127 .vidioc_streamoff = vidioc_streamoff,
2128 .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
2129 .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
2130 .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
2131 .vidioc_log_status = vidioc_log_status,
2132 .vidioc_querymenu = vidioc_querymenu,
2133 .vidioc_queryctrl = vidioc_queryctrl,
2134/* .vidioc_g_chip_ident = cx231xx_g_chip_ident,*/
2135#ifdef CONFIG_VIDEO_ADV_DEBUG
2136/* .vidioc_g_register = cx231xx_g_register,*/
2137/* .vidioc_s_register = cx231xx_s_register,*/
2138#endif
2139};
2140
2141static struct video_device cx231xx_mpeg_template = {
2142 .name = "cx231xx",
2143 .fops = &mpeg_fops,
2144 .ioctl_ops = &mpeg_ioctl_ops,
2145 .minor = -1,
2146 .tvnorms = CX231xx_NORMS,
2147 .current_norm = V4L2_STD_NTSC_M,
2148};
2149
2150void cx231xx_417_unregister(struct cx231xx *dev)
2151{
2152 dprintk(1, "%s()\n", __func__);
2153 dprintk(3, "%s()\n", __func__);
2154
2155 if (dev->v4l_device) {
2156 if (-1 != dev->v4l_device->minor)
2157 video_unregister_device(dev->v4l_device);
2158 else
2159 video_device_release(dev->v4l_device);
2160 dev->v4l_device = NULL;
2161 }
2162}
2163
2164static struct video_device *cx231xx_video_dev_alloc(
2165 struct cx231xx *dev,
2166 struct usb_device *usbdev,
2167 struct video_device *template,
2168 char *type)
2169{
2170 struct video_device *vfd;
2171
2172 dprintk(1, "%s()\n", __func__);
2173 vfd = video_device_alloc();
2174 if (NULL == vfd)
2175 return NULL;
2176 *vfd = *template;
2177 vfd->minor = -1;
2178 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
2179 type, cx231xx_boards[dev->model].name);
2180
2181 vfd->v4l2_dev = &dev->v4l2_dev;
2182 vfd->release = video_device_release;
2183
2184 return vfd;
2185
2186}
2187
2188int cx231xx_417_register(struct cx231xx *dev)
2189{
2190 /* FIXME: Port1 hardcoded here */
2191 int err = -ENODEV;
2192 struct cx231xx_tsport *tsport = &dev->ts1;
2193
2194 dprintk(1, "%s()\n", __func__);
2195
2196 /* Set default TV standard */
2197 dev->encodernorm = cx231xx_tvnorms[0];
2198
2199 if (dev->encodernorm.id & V4L2_STD_525_60)
2200 tsport->height = 480;
2201 else
2202 tsport->height = 576;
2203
2204 tsport->width = 720;
2205 cx2341x_fill_defaults(&dev->mpeg_params);
2206 dev->norm = V4L2_STD_NTSC;
2207
2208 dev->mpeg_params.port = CX2341X_PORT_SERIAL;
2209
2210 /* Allocate and initialize V4L video device */
2211 dev->v4l_device = cx231xx_video_dev_alloc(dev,
2212 dev->udev, &cx231xx_mpeg_template, "mpeg");
2213 err = video_register_device(dev->v4l_device,
2214 VFL_TYPE_GRABBER, -1);
2215 if (err < 0) {
2216 dprintk(3, "%s: can't register mpeg device\n", dev->name);
2217 return err;
2218 }
2219
2220 dprintk(3, "%s: registered device video%d [mpeg]\n",
2221 dev->name, dev->v4l_device->num);
2222
2223 return 0;
2224}
Linux kernel - Deliverables
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