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[media] cx23885: Cleanup MPEG encoder GPIO handling
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-417.c
CommitLineData
b1b81f1d
ST		 1/*
2 *
3 * Support for a cx23417 mpeg encoder via cx23885 host port.
4 *
f8de18d4 5 * (c) 2004 Jelle Foks <jelle@foks.us>
b1b81f1d 6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
6d897616 7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
b1b81f1d
ST		 8 * - CX23885/7/8 support
9 *
631dd1a8 10 * Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/>
b1b81f1d
ST		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/fs.h>
31#include <linux/delay.h>
32#include <linux/device.h>
33#include <linux/firmware.h>
5a0e3ad6 34#include <linux/slab.h>
b1b81f1d 35#include <media/v4l2-common.h>
35ea11ff 36#include <media/v4l2-ioctl.h>
b1b81f1d
ST		 37#include <media/cx2341x.h>
38
39#include "cx23885.h"
74618244 40#include "cx23885-ioctl.h"
b1b81f1d
ST		 41
42#define CX23885_FIRM_IMAGE_SIZE 376836
43#define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
44
45static unsigned int mpegbufs = 32;
46module_param(mpegbufs, int, 0644);
47MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
48static unsigned int mpeglines = 32;
49module_param(mpeglines, int, 0644);
50MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
51static unsigned int mpeglinesize = 512;
52module_param(mpeglinesize, int, 0644);
53MODULE_PARM_DESC(mpeglinesize,
54 "number of bytes in each line of an MPEG buffer, range 512-1024");
55
56static unsigned int v4l_debug;
57module_param(v4l_debug, int, 0644);
58MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
59
60#define dprintk(level, fmt, arg...)\
61 do { if (v4l_debug >= level) \
ca4e771f
MK		 62 printk(KERN_DEBUG "%s: " fmt, \
63 (dev) ? dev->name : "cx23885[?]", ## arg); \
b1b81f1d
ST		 64 } while (0)
65
66static struct cx23885_tvnorm cx23885_tvnorms[] = {
67 {
68 .name = "NTSC-M",
69 .id = V4L2_STD_NTSC_M,
70 }, {
71 .name = "NTSC-JP",
72 .id = V4L2_STD_NTSC_M_JP,
73 }, {
74 .name = "PAL-BG",
75 .id = V4L2_STD_PAL_BG,
76 }, {
77 .name = "PAL-DK",
78 .id = V4L2_STD_PAL_DK,
79 }, {
80 .name = "PAL-I",
81 .id = V4L2_STD_PAL_I,
82 }, {
83 .name = "PAL-M",
84 .id = V4L2_STD_PAL_M,
85 }, {
86 .name = "PAL-N",
87 .id = V4L2_STD_PAL_N,
88 }, {
89 .name = "PAL-Nc",
90 .id = V4L2_STD_PAL_Nc,
91 }, {
92 .name = "PAL-60",
93 .id = V4L2_STD_PAL_60,
94 }, {
95 .name = "SECAM-L",
96 .id = V4L2_STD_SECAM_L,
97 }, {
98 .name = "SECAM-DK",
99 .id = V4L2_STD_SECAM_DK,
100 }
101};
102
103/* ------------------------------------------------------------------ */
104enum cx23885_capture_type {
105 CX23885_MPEG_CAPTURE,
106 CX23885_RAW_CAPTURE,
107 CX23885_RAW_PASSTHRU_CAPTURE
108};
109enum cx23885_capture_bits {
110 CX23885_RAW_BITS_NONE = 0x00,
111 CX23885_RAW_BITS_YUV_CAPTURE = 0x01,
112 CX23885_RAW_BITS_PCM_CAPTURE = 0x02,
113 CX23885_RAW_BITS_VBI_CAPTURE = 0x04,
114 CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
115 CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10
116};
117enum cx23885_capture_end {
118 CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
119 CX23885_END_NOW, /* stop immediately, no irq */
120};
121enum cx23885_framerate {
122 CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
123 CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */
124};
125enum cx23885_stream_port {
126 CX23885_OUTPUT_PORT_MEMORY,
127 CX23885_OUTPUT_PORT_STREAMING,
128 CX23885_OUTPUT_PORT_SERIAL
129};
130enum cx23885_data_xfer_status {
131 CX23885_MORE_BUFFERS_FOLLOW,
132 CX23885_LAST_BUFFER,
133};
134enum cx23885_picture_mask {
135 CX23885_PICTURE_MASK_NONE,
136 CX23885_PICTURE_MASK_I_FRAMES,
137 CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
138 CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
139};
140enum cx23885_vbi_mode_bits {
141 CX23885_VBI_BITS_SLICED,
142 CX23885_VBI_BITS_RAW,
143};
144enum cx23885_vbi_insertion_bits {
145 CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
146 CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
147 CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
148 CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
149 CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
150};
151enum cx23885_dma_unit {
152 CX23885_DMA_BYTES,
153 CX23885_DMA_FRAMES,
154};
155enum cx23885_dma_transfer_status_bits {
156 CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
157 CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
158 CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
159};
160enum cx23885_pause {
161 CX23885_PAUSE_ENCODING,
162 CX23885_RESUME_ENCODING,
163};
164enum cx23885_copyright {
165 CX23885_COPYRIGHT_OFF,
166 CX23885_COPYRIGHT_ON,
167};
168enum cx23885_notification_type {
169 CX23885_NOTIFICATION_REFRESH,
170};
171enum cx23885_notification_status {
172 CX23885_NOTIFICATION_OFF,
173 CX23885_NOTIFICATION_ON,
174};
175enum cx23885_notification_mailbox {
176 CX23885_NOTIFICATION_NO_MAILBOX = -1,
177};
178enum cx23885_field1_lines {
179 CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
180 CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
181 CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
182};
183enum cx23885_field2_lines {
184 CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
185 CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
186 CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
187};
188enum cx23885_custom_data_type {
189 CX23885_CUSTOM_EXTENSION_USR_DATA,
190 CX23885_CUSTOM_PRIVATE_PACKET,
191};
192enum cx23885_mute {
193 CX23885_UNMUTE,
194 CX23885_MUTE,
195};
196enum cx23885_mute_video_mask {
197 CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
198 CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
199 CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
200};
201enum cx23885_mute_video_shift {
202 CX23885_MUTE_VIDEO_V_SHIFT = 8,
203 CX23885_MUTE_VIDEO_U_SHIFT = 16,
204 CX23885_MUTE_VIDEO_Y_SHIFT = 24,
205};
206
207/* defines below are from ivtv-driver.h */
208#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
209
210/* Firmware API commands */
211#define IVTV_API_STD_TIMEOUT 500
212
213/* Registers */
214/* IVTV_REG_OFFSET */
215#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
216#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
217#define IVTV_REG_SPU (0x9050)
218#define IVTV_REG_HW_BLOCKS (0x9054)
219#define IVTV_REG_VPU (0x9058)
220#define IVTV_REG_APU (0xA064)
221
222/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
223 bits 31-16
224+-----------+
225| Reserved |
226+-----------+
227 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
228+-------+-------+-------+-------+-------+-------+-------+-------+
229| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
230+-------+-------+-------+-------+-------+-------+-------+-------+
231 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
232+-------+-------+-------+-------+-------+-------+-------+-------+
233|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
234+-------+-------+-------+-------+-------+-------+-------+-------+
235***/
236#define MC417_MIWR 0x8000
237#define MC417_MIRD 0x4000
238#define MC417_MICS 0x2000
239#define MC417_MIRDY 0x1000
240#define MC417_MIADDR 0x0F00
241#define MC417_MIDATA 0x00FF
242
243/* MIADDR* nibble definitions */
244#define MCI_MEMORY_DATA_BYTE0 0x000
245#define MCI_MEMORY_DATA_BYTE1 0x100
246#define MCI_MEMORY_DATA_BYTE2 0x200
247#define MCI_MEMORY_DATA_BYTE3 0x300
248#define MCI_MEMORY_ADDRESS_BYTE2 0x400
249#define MCI_MEMORY_ADDRESS_BYTE1 0x500
250#define MCI_MEMORY_ADDRESS_BYTE0 0x600
251#define MCI_REGISTER_DATA_BYTE0 0x800
252#define MCI_REGISTER_DATA_BYTE1 0x900
253#define MCI_REGISTER_DATA_BYTE2 0xA00
254#define MCI_REGISTER_DATA_BYTE3 0xB00
255#define MCI_REGISTER_ADDRESS_BYTE0 0xC00
256#define MCI_REGISTER_ADDRESS_BYTE1 0xD00
257#define MCI_REGISTER_MODE 0xE00
258
259/* Read and write modes */
260#define MCI_MODE_REGISTER_READ 0
261#define MCI_MODE_REGISTER_WRITE 1
262#define MCI_MODE_MEMORY_READ 0
263#define MCI_MODE_MEMORY_WRITE 0x40
264
265/*** Bit definitions for MC417_CTL register ****
266 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
267+--------+-------------+--------+--------------+------------+
268|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
269+--------+-------------+--------+--------------+------------+
270***/
271#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
272#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
273#define MC417_UART_GPIO_EN 0x00000001
274
275/* Values for speed control */
276#define MC417_SPD_CTL_SLOW 0x1
277#define MC417_SPD_CTL_MEDIUM 0x0
278#define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
279
280/* Values for GPIO select */
281#define MC417_GPIO_SEL_GPIO3 0x3
282#define MC417_GPIO_SEL_GPIO2 0x2
283#define MC417_GPIO_SEL_GPIO1 0x1
284#define MC417_GPIO_SEL_GPIO0 0x0
285
286void cx23885_mc417_init(struct cx23885_dev *dev)
287{
288 u32 regval;
289
290 dprintk(2, "%s()\n", __func__);
291
292 /* Configure MC417_CTL register to defaults. */
293 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |
294 MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) |
295 MC417_UART_GPIO_EN;
296 cx_write(MC417_CTL, regval);
297
298 /* Configure MC417_OEN to defaults. */
299 regval = MC417_MIRDY;
300 cx_write(MC417_OEN, regval);
301
302 /* Configure MC417_RWD to defaults. */
303 regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
304 cx_write(MC417_RWD, regval);
305}
306
307static int mc417_wait_ready(struct cx23885_dev *dev)
308{
309 u32 mi_ready;
310 unsigned long timeout = jiffies + msecs_to_jiffies(1);
311
312 for (;;) {
313 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
314 if (mi_ready != 0)
315 return 0;
316 if (time_after(jiffies, timeout))
317 return -1;
318 udelay(1);
319 }
320}
321
74618244 322int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
b1b81f1d
ST		 323{
324 u32 regval;
325
326 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
327 * which is an input.
328 */
329 cx_write(MC417_OEN, MC417_MIRDY);
330
331 /* Write data byte 0 */
332 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
333 (value & 0x000000FF);
334 cx_write(MC417_RWD, regval);
335
336 /* Transition CS/WR to effect write transaction across bus. */
337 regval |= MC417_MICS | MC417_MIWR;
338 cx_write(MC417_RWD, regval);
339
340 /* Write data byte 1 */
341 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
342 ((value >> 8) & 0x000000FF);
343 cx_write(MC417_RWD, regval);
344 regval |= MC417_MICS | MC417_MIWR;
345 cx_write(MC417_RWD, regval);
346
347 /* Write data byte 2 */
348 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
349 ((value >> 16) & 0x000000FF);
350 cx_write(MC417_RWD, regval);
351 regval |= MC417_MICS | MC417_MIWR;
352 cx_write(MC417_RWD, regval);
353
354 /* Write data byte 3 */
355 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
356 ((value >> 24) & 0x000000FF);
357 cx_write(MC417_RWD, regval);
358 regval |= MC417_MICS | MC417_MIWR;
359 cx_write(MC417_RWD, regval);
360
361 /* Write address byte 0 */
362 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
363 (address & 0xFF);
364 cx_write(MC417_RWD, regval);
365 regval |= MC417_MICS | MC417_MIWR;
366 cx_write(MC417_RWD, regval);
367
368 /* Write address byte 1 */
369 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
370 ((address >> 8) & 0xFF);
371 cx_write(MC417_RWD, regval);
372 regval |= MC417_MICS | MC417_MIWR;
373 cx_write(MC417_RWD, regval);
374
375 /* Indicate that this is a write. */
376 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
377 MCI_MODE_REGISTER_WRITE;
378 cx_write(MC417_RWD, regval);
379 regval |= MC417_MICS | MC417_MIWR;
380 cx_write(MC417_RWD, regval);
381
382 /* Wait for the trans to complete (MC417_MIRDY asserted). */
383 return mc417_wait_ready(dev);
384}
385
74618244 386int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
b1b81f1d
ST		 387{
388 int retval;
389 u32 regval;
390 u32 tempval;
391 u32 dataval;
392
393 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
394 * which is an input.
395 */
396 cx_write(MC417_OEN, MC417_MIRDY);
397
398 /* Write address byte 0 */
399 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
400 ((address & 0x00FF));
401 cx_write(MC417_RWD, regval);
402 regval |= MC417_MICS | MC417_MIWR;
403 cx_write(MC417_RWD, regval);
404
405 /* Write address byte 1 */
406 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
407 ((address >> 8) & 0xFF);
408 cx_write(MC417_RWD, regval);
409 regval |= MC417_MICS | MC417_MIWR;
410 cx_write(MC417_RWD, regval);
411
412 /* Indicate that this is a register read. */
413 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
414 MCI_MODE_REGISTER_READ;
415 cx_write(MC417_RWD, regval);
416 regval |= MC417_MICS | MC417_MIWR;
417 cx_write(MC417_RWD, regval);
418
419 /* Wait for the trans to complete (MC417_MIRDY asserted). */
420 retval = mc417_wait_ready(dev);
421
422 /* switch the DAT0-7 GPIO[10:3] to input mode */
423 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
424
425 /* Read data byte 0 */
426 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
427 cx_write(MC417_RWD, regval);
428
429 /* Transition RD to effect read transaction across bus.
430 * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
431 * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
432 * input only...)
433 */
434 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
435 cx_write(MC417_RWD, regval);
436
437 /* Collect byte */
438 tempval = cx_read(MC417_RWD);
439 dataval = tempval & 0x000000FF;
440
441 /* Bring CS and RD high. */
442 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
443 cx_write(MC417_RWD, regval);
444
445 /* Read data byte 1 */
446 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
447 cx_write(MC417_RWD, regval);
448 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
449 cx_write(MC417_RWD, regval);
450 tempval = cx_read(MC417_RWD);
451 dataval |= ((tempval & 0x000000FF) << 8);
452 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
453 cx_write(MC417_RWD, regval);
454
455 /* Read data byte 2 */
456 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
457 cx_write(MC417_RWD, regval);
458 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
459 cx_write(MC417_RWD, regval);
460 tempval = cx_read(MC417_RWD);
461 dataval |= ((tempval & 0x000000FF) << 16);
462 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
463 cx_write(MC417_RWD, regval);
464
465 /* Read data byte 3 */
466 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
467 cx_write(MC417_RWD, regval);
468 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
469 cx_write(MC417_RWD, regval);
470 tempval = cx_read(MC417_RWD);
471 dataval |= ((tempval & 0x000000FF) << 24);
472 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
473 cx_write(MC417_RWD, regval);
474
475 *value = dataval;
476
477 return retval;
478}
479
480int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
481{
482 u32 regval;
483
484 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
485 * which is an input.
486 */
487 cx_write(MC417_OEN, MC417_MIRDY);
488
489 /* Write data byte 0 */
490 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
491 (value & 0x000000FF);
492 cx_write(MC417_RWD, regval);
493
494 /* Transition CS/WR to effect write transaction across bus. */
495 regval |= MC417_MICS | MC417_MIWR;
496 cx_write(MC417_RWD, regval);
497
498 /* Write data byte 1 */
499 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
500 ((value >> 8) & 0x000000FF);
501 cx_write(MC417_RWD, regval);
502 regval |= MC417_MICS | MC417_MIWR;
503 cx_write(MC417_RWD, regval);
504
505 /* Write data byte 2 */
506 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
507 ((value >> 16) & 0x000000FF);
508 cx_write(MC417_RWD, regval);
509 regval |= MC417_MICS | MC417_MIWR;
510 cx_write(MC417_RWD, regval);
511
512 /* Write data byte 3 */
513 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
514 ((value >> 24) & 0x000000FF);
515 cx_write(MC417_RWD, regval);
516 regval |= MC417_MICS | MC417_MIWR;
517 cx_write(MC417_RWD, regval);
518
519 /* Write address byte 2 */
520 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
521 MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
522 cx_write(MC417_RWD, regval);
523 regval |= MC417_MICS | MC417_MIWR;
524 cx_write(MC417_RWD, regval);
525
526 /* Write address byte 1 */
527 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
528 ((address >> 8) & 0xFF);
529 cx_write(MC417_RWD, regval);
530 regval |= MC417_MICS | MC417_MIWR;
531 cx_write(MC417_RWD, regval);
532
533 /* Write address byte 0 */
534 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
535 (address & 0xFF);
536 cx_write(MC417_RWD, regval);
537 regval |= MC417_MICS | MC417_MIWR;
538 cx_write(MC417_RWD, regval);
539
540 /* Wait for the trans to complete (MC417_MIRDY asserted). */
541 return mc417_wait_ready(dev);
542}
543
544int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
545{
546 int retval;
547 u32 regval;
548 u32 tempval;
549 u32 dataval;
550
551 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
552 * which is an input.
553 */
554 cx_write(MC417_OEN, MC417_MIRDY);
555
556 /* Write address byte 2 */
557 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
558 MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
559 cx_write(MC417_RWD, regval);
560 regval |= MC417_MICS | MC417_MIWR;
561 cx_write(MC417_RWD, regval);
562
563 /* Write address byte 1 */
564 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
565 ((address >> 8) & 0xFF);
566 cx_write(MC417_RWD, regval);
567 regval |= MC417_MICS | MC417_MIWR;
568 cx_write(MC417_RWD, regval);
569
570 /* Write address byte 0 */
571 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
572 (address & 0xFF);
573 cx_write(MC417_RWD, regval);
574 regval |= MC417_MICS | MC417_MIWR;
575 cx_write(MC417_RWD, regval);
576
577 /* Wait for the trans to complete (MC417_MIRDY asserted). */
578 retval = mc417_wait_ready(dev);
579
580 /* switch the DAT0-7 GPIO[10:3] to input mode */
581 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
582
583 /* Read data byte 3 */
584 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
585 cx_write(MC417_RWD, regval);
586
587 /* Transition RD to effect read transaction across bus. */
588 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
589 cx_write(MC417_RWD, regval);
590
591 /* Collect byte */
592 tempval = cx_read(MC417_RWD);
593 dataval = ((tempval & 0x000000FF) << 24);
594
595 /* Bring CS and RD high. */
596 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
597 cx_write(MC417_RWD, regval);
598
599 /* Read data byte 2 */
600 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
601 cx_write(MC417_RWD, regval);
602 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
603 cx_write(MC417_RWD, regval);
604 tempval = cx_read(MC417_RWD);
605 dataval |= ((tempval & 0x000000FF) << 16);
606 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
607 cx_write(MC417_RWD, regval);
608
609 /* Read data byte 1 */
610 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
611 cx_write(MC417_RWD, regval);
612 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
613 cx_write(MC417_RWD, regval);
614 tempval = cx_read(MC417_RWD);
615 dataval |= ((tempval & 0x000000FF) << 8);
616 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
617 cx_write(MC417_RWD, regval);
618
619 /* Read data byte 0 */
620 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
621 cx_write(MC417_RWD, regval);
622 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
623 cx_write(MC417_RWD, regval);
624 tempval = cx_read(MC417_RWD);
625 dataval |= (tempval & 0x000000FF);
626 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
627 cx_write(MC417_RWD, regval);
628
629 *value = dataval;
630
631 return retval;
632}
633
f659c513
ST		 634void mc417_gpio_set(struct cx23885_dev *dev, u32 mask)
635{
636 u32 val;
637
638 /* Set the gpio value */
639 mc417_register_read(dev, 0x900C, &val);
640 val |= (mask & 0x000ffff);
641 mc417_register_write(dev, 0x900C, val);
642}
643
644void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask)
645{
646 u32 val;
647
648 /* Clear the gpio value */
649 mc417_register_read(dev, 0x900C, &val);
650 val &= ~(mask & 0x0000ffff);
651 mc417_register_write(dev, 0x900C, val);
652}
653
654void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
655{
656 u32 val;
657
658 /* Enable GPIO direction bits */
659 mc417_register_read(dev, 0x9020, &val);
660 if (asoutput)
661 val |= (mask & 0x0000ffff);
662 else
663 val &= ~(mask & 0x0000ffff);
664
665 mc417_register_write(dev, 0x9020, val);
666}
b1b81f1d
ST		 667/* ------------------------------------------------------------------ */
668
669/* MPEG encoder API */
d45b9b8a 670static char *cmd_to_str(int cmd)
b1b81f1d
ST		 671{
672 switch (cmd) {
673 case CX2341X_ENC_PING_FW:
674 return "PING_FW";
675 case CX2341X_ENC_START_CAPTURE:
676 return "START_CAPTURE";
677 case CX2341X_ENC_STOP_CAPTURE:
678 return "STOP_CAPTURE";
679 case CX2341X_ENC_SET_AUDIO_ID:
680 return "SET_AUDIO_ID";
681 case CX2341X_ENC_SET_VIDEO_ID:
682 return "SET_VIDEO_ID";
683 case CX2341X_ENC_SET_PCR_ID:
26ee91ef 684 return "SET_PCR_ID";
b1b81f1d
ST		 685 case CX2341X_ENC_SET_FRAME_RATE:
686 return "SET_FRAME_RATE";
687 case CX2341X_ENC_SET_FRAME_SIZE:
688 return "SET_FRAME_SIZE";
689 case CX2341X_ENC_SET_BIT_RATE:
690 return "SET_BIT_RATE";
691 case CX2341X_ENC_SET_GOP_PROPERTIES:
692 return "SET_GOP_PROPERTIES";
693 case CX2341X_ENC_SET_ASPECT_RATIO:
694 return "SET_ASPECT_RATIO";
695 case CX2341X_ENC_SET_DNR_FILTER_MODE:
26ee91ef 696 return "SET_DNR_FILTER_MODE";
b1b81f1d
ST		 697 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
698 return "SET_DNR_FILTER_PROPS";
699 case CX2341X_ENC_SET_CORING_LEVELS:
700 return "SET_CORING_LEVELS";
701 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
702 return "SET_SPATIAL_FILTER_TYPE";
703 case CX2341X_ENC_SET_VBI_LINE:
704 return "SET_VBI_LINE";
705 case CX2341X_ENC_SET_STREAM_TYPE:
706 return "SET_STREAM_TYPE";
707 case CX2341X_ENC_SET_OUTPUT_PORT:
708 return "SET_OUTPUT_PORT";
709 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
710 return "SET_AUDIO_PROPERTIES";
711 case CX2341X_ENC_HALT_FW:
712 return "HALT_FW";
713 case CX2341X_ENC_GET_VERSION:
714 return "GET_VERSION";
715 case CX2341X_ENC_SET_GOP_CLOSURE:
716 return "SET_GOP_CLOSURE";
717 case CX2341X_ENC_GET_SEQ_END:
718 return "GET_SEQ_END";
719 case CX2341X_ENC_SET_PGM_INDEX_INFO:
720 return "SET_PGM_INDEX_INFO";
721 case CX2341X_ENC_SET_VBI_CONFIG:
722 return "SET_VBI_CONFIG";
723 case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
724 return "SET_DMA_BLOCK_SIZE";
725 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
726 return "GET_PREV_DMA_INFO_MB_10";
727 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
728 return "GET_PREV_DMA_INFO_MB_9";
729 case CX2341X_ENC_SCHED_DMA_TO_HOST:
730 return "SCHED_DMA_TO_HOST";
731 case CX2341X_ENC_INITIALIZE_INPUT:
732 return "INITIALIZE_INPUT";
733 case CX2341X_ENC_SET_FRAME_DROP_RATE:
734 return "SET_FRAME_DROP_RATE";
735 case CX2341X_ENC_PAUSE_ENCODER:
736 return "PAUSE_ENCODER";
737 case CX2341X_ENC_REFRESH_INPUT:
738 return "REFRESH_INPUT";
739 case CX2341X_ENC_SET_COPYRIGHT:
740 return "SET_COPYRIGHT";
741 case CX2341X_ENC_SET_EVENT_NOTIFICATION:
742 return "SET_EVENT_NOTIFICATION";
743 case CX2341X_ENC_SET_NUM_VSYNC_LINES:
744 return "SET_NUM_VSYNC_LINES";
745 case CX2341X_ENC_SET_PLACEHOLDER:
746 return "SET_PLACEHOLDER";
747 case CX2341X_ENC_MUTE_VIDEO:
748 return "MUTE_VIDEO";
749 case CX2341X_ENC_MUTE_AUDIO:
750 return "MUTE_AUDIO";
751 case CX2341X_ENC_MISC:
752 return "MISC";
753 default:
754 return "UNKNOWN";
755 }
756}
757
758static int cx23885_mbox_func(void *priv,
759 u32 command,
760 int in,
761 int out,
762 u32 data[CX2341X_MBOX_MAX_DATA])
763{
764 struct cx23885_dev *dev = priv;
765 unsigned long timeout;
766 u32 value, flag, retval = 0;
767 int i;
768
769 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
770 cmd_to_str(command));
771
772 /* this may not be 100% safe if we can't read any memory location
773 without side effects */
774 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
775 if (value != 0x12345678) {
776 printk(KERN_ERR
777 "Firmware and/or mailbox pointer not initialized "
778 "or corrupted, signature = 0x%x, cmd = %s\n", value,
779 cmd_to_str(command));
780 return -1;
781 }
782
783 /* This read looks at 32 bits, but flag is only 8 bits.
784 * Seems we also bail if CMD or TIMEOUT bytes are set???
785 */
786 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
787 if (flag) {
788 printk(KERN_ERR "ERROR: Mailbox appears to be in use "
789 "(%x), cmd = %s\n", flag, cmd_to_str(command));
790 return -1;
791 }
792
793 flag |= 1; /* tell 'em we're working on it */
794 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
795
796 /* write command + args + fill remaining with zeros */
797 /* command code */
798 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
799 mc417_memory_write(dev, dev->cx23417_mailbox + 3,
800 IVTV_API_STD_TIMEOUT); /* timeout */
801 for (i = 0; i < in; i++) {
802 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
803 dprintk(3, "API Input %d = %d\n", i, data[i]);
804 }
805 for (; i < CX2341X_MBOX_MAX_DATA; i++)
806 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
807
808 flag |= 3; /* tell 'em we're done writing */
809 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
810
811 /* wait for firmware to handle the API command */
812 timeout = jiffies + msecs_to_jiffies(10);
813 for (;;) {
814 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
815 if (0 != (flag & 4))
816 break;
817 if (time_after(jiffies, timeout)) {
818 printk(KERN_ERR "ERROR: API Mailbox timeout\n");
819 return -1;
820 }
821 udelay(10);
822 }
823
824 /* read output values */
825 for (i = 0; i < out; i++) {
826 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
827 dprintk(3, "API Output %d = %d\n", i, data[i]);
828 }
829
830 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
831 dprintk(3, "API result = %d\n", retval);
832
833 flag = 0;
834 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
835
836 return retval;
837}
838
839/* We don't need to call the API often, so using just one
840 * mailbox will probably suffice
841 */
842static int cx23885_api_cmd(struct cx23885_dev *dev,
843 u32 command,
844 u32 inputcnt,
845 u32 outputcnt,
846 ...)
847{
848 u32 data[CX2341X_MBOX_MAX_DATA];
849 va_list vargs;
850 int i, err;
851
852 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
853
854 va_start(vargs, outputcnt);
855 for (i = 0; i < inputcnt; i++)
856 data[i] = va_arg(vargs, int);
857
858 err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
859 for (i = 0; i < outputcnt; i++) {
860 int *vptr = va_arg(vargs, int *);
861 *vptr = data[i];
862 }
863 va_end(vargs);
864
865 return err;
866}
867
868static int cx23885_find_mailbox(struct cx23885_dev *dev)
869{
870 u32 signature[4] = {
871 0x12345678, 0x34567812, 0x56781234, 0x78123456
872 };
873 int signaturecnt = 0;
874 u32 value;
875 int i;
876
877 dprintk(2, "%s()\n", __func__);
878
879 for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
880 mc417_memory_read(dev, i, &value);
881 if (value == signature[signaturecnt])
882 signaturecnt++;
883 else
884 signaturecnt = 0;
885 if (4 == signaturecnt) {
886 dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
887 return i+1;
888 }
889 }
890 printk(KERN_ERR "Mailbox signature values not found!\n");
891 return -1;
892}
893
894static int cx23885_load_firmware(struct cx23885_dev *dev)
895{
896 static const unsigned char magic[8] = {
897 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
898 };
899 const struct firmware *firmware;
900 int i, retval = 0;
901 u32 value = 0;
902 u32 gpio_output = 0;
182d29f3 903 u32 gpio_value;
b1b81f1d
ST		 904 u32 checksum = 0;
905 u32 *dataptr;
906
907 dprintk(2, "%s()\n", __func__);
908
909 /* Save GPIO settings before reset of APU */
910 retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
182d29f3 911 retval |= mc417_memory_read(dev, 0x900C, &gpio_value);
b1b81f1d
ST		 912
913 retval = mc417_register_write(dev,
914 IVTV_REG_VPU, 0xFFFFFFED);
915 retval |= mc417_register_write(dev,
916 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
917 retval |= mc417_register_write(dev,
918 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
919 retval |= mc417_register_write(dev,
920 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
921 retval |= mc417_register_write(dev,
922 IVTV_REG_APU, 0);
923
924 if (retval != 0) {
925 printk(KERN_ERR "%s: Error with mc417_register_write\n",
926 __func__);
927 return -1;
928 }
929
930 retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
931 &dev->pci->dev);
932
933 if (retval != 0) {
934 printk(KERN_ERR
935 "ERROR: Hotplug firmware request failed (%s).\n",
d35ed627 936 CX23885_FIRM_IMAGE_NAME);
b1b81f1d
ST		 937 printk(KERN_ERR "Please fix your hotplug setup, the board will "
938 "not work without firmware loaded!\n");
939 return -1;
940 }
941
942 if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
943 printk(KERN_ERR "ERROR: Firmware size mismatch "
944 "(have %zd, expected %d)\n",
945 firmware->size, CX23885_FIRM_IMAGE_SIZE);
946 release_firmware(firmware);
947 return -1;
948 }
949
950 if (0 != memcmp(firmware->data, magic, 8)) {
951 printk(KERN_ERR
952 "ERROR: Firmware magic mismatch, wrong file?\n");
953 release_firmware(firmware);
954 return -1;
955 }
956
957 /* transfer to the chip */
958 dprintk(2, "Loading firmware ...\n");
959 dataptr = (u32 *)firmware->data;
960 for (i = 0; i < (firmware->size >> 2); i++) {
961 value = *dataptr;
962 checksum += ~value;
963 if (mc417_memory_write(dev, i, value) != 0) {
964 printk(KERN_ERR "ERROR: Loading firmware failed!\n");
965 release_firmware(firmware);
966 return -1;
967 }
968 dataptr++;
969 }
970
971 /* read back to verify with the checksum */
972 dprintk(1, "Verifying firmware ...\n");
973 for (i--; i >= 0; i--) {
974 if (mc417_memory_read(dev, i, &value) != 0) {
975 printk(KERN_ERR "ERROR: Reading firmware failed!\n");
976 release_firmware(firmware);
977 return -1;
978 }
979 checksum -= ~value;
980 }
981 if (checksum) {
982 printk(KERN_ERR
983 "ERROR: Firmware load failed (checksum mismatch).\n");
984 release_firmware(firmware);
985 return -1;
986 }
987 release_firmware(firmware);
988 dprintk(1, "Firmware upload successful.\n");
989
990 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
991 IVTV_CMD_HW_BLOCKS_RST);
992
f659c513
ST		 993 /* F/W power up disturbs the GPIOs, restore state */
994 retval |= mc417_register_write(dev, 0x9020, gpio_output);
182d29f3 995 retval |= mc417_register_write(dev, 0x900C, gpio_value);
b1b81f1d
ST		 996
997 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
998 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
999
182d29f3
ST		 1000 /* Hardcoded GPIO's here */
1001 retval |= mc417_register_write(dev, 0x9020, 0x4000);
1002 retval |= mc417_register_write(dev, 0x900C, 0x4000);
1003
1004 mc417_register_read(dev, 0x9020, &gpio_output);
1005 mc417_register_read(dev, 0x900C, &gpio_value);
1006
b1b81f1d
ST		 1007 if (retval < 0)
1008 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1009 __func__);
1010 return 0;
1011}
1012
1013void cx23885_417_check_encoder(struct cx23885_dev *dev)
1014{
1015 u32 status, seq;
1016
1017 status = seq = 0;
1018 cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1019 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1020}
1021
1022static void cx23885_codec_settings(struct cx23885_dev *dev)
1023{
1024 dprintk(1, "%s()\n", __func__);
1025
1026 /* assign frame size */
1027 cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1028 dev->ts1.height, dev->ts1.width);
1029
1030 dev->mpeg_params.width = dev->ts1.width;
1031 dev->mpeg_params.height = dev->ts1.height;
1032 dev->mpeg_params.is_50hz =
1033 (dev->encodernorm.id & V4L2_STD_625_50) != 0;
1034
1035 cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params);
1036
1037 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1038 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1039}
1040
1041static int cx23885_initialize_codec(struct cx23885_dev *dev)
1042{
1043 int version;
1044 int retval;
1045 u32 i, data[7];
1046
1047 dprintk(1, "%s()\n", __func__);
1048
1049 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1050 if (retval < 0) {
1051 dprintk(2, "%s() PING OK\n", __func__);
1052 retval = cx23885_load_firmware(dev);
1053 if (retval < 0) {
1054 printk(KERN_ERR "%s() f/w load failed\n", __func__);
1055 return retval;
1056 }
f347535a 1057 retval = cx23885_find_mailbox(dev);
1058 if (retval < 0) {
b1b81f1d
ST		 1059 printk(KERN_ERR "%s() mailbox < 0, error\n",
1060 __func__);
1061 return -1;
1062 }
f347535a 1063 dev->cx23417_mailbox = retval;
b1b81f1d
ST		 1064 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1065 if (retval < 0) {
1066 printk(KERN_ERR
1067 "ERROR: cx23417 firmware ping failed!\n");
1068 return -1;
1069 }
1070 retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1071 &version);
1072 if (retval < 0) {
1073 printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1074 "version failed!\n");
1075 return -1;
1076 }
1077 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1078 msleep(200);
1079 }
1080
1081 cx23885_codec_settings(dev);
1082 msleep(60);
1083
1084 cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1085 CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
1086 cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1087 CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1088 0, 0);
1089
1090 /* Setup to capture VBI */
1091 data[0] = 0x0001BD00;
1092 data[1] = 1; /* frames per interrupt */
1093 data[2] = 4; /* total bufs */
1094 data[3] = 0x91559155; /* start codes */
1095 data[4] = 0x206080C0; /* stop codes */
1096 data[5] = 6; /* lines */
1097 data[6] = 64; /* BPL */
1098
1099 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1100 data[2], data[3], data[4], data[5], data[6]);
1101
1102 for (i = 2; i <= 24; i++) {
1103 int valid;
1104
1105 valid = ((i >= 19) && (i <= 21));
1106 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1107 valid, 0 , 0, 0);
1108 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1109 i | 0x80000000, valid, 0, 0, 0);
1110 }
1111
1112 cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
1113 msleep(60);
1114
1115 /* initialize the video input */
1116 cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1117 msleep(60);
1118
1119 /* Enable VIP style pixel invalidation so we work with scaled mode */
1120 mc417_memory_write(dev, 2120, 0x00000080);
1121
1122 /* start capturing to the host interface */
1123 cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1124 CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
1125 msleep(10);
1126
1127 return 0;
1128}
1129
1130/* ------------------------------------------------------------------ */
1131
1132static int bb_buf_setup(struct videobuf_queue *q,
1133 unsigned int *count, unsigned int *size)
1134{
1135 struct cx23885_fh *fh = q->priv_data;
1136
1137 fh->dev->ts1.ts_packet_size = mpeglinesize;
1138 fh->dev->ts1.ts_packet_count = mpeglines;
1139
1140 *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1141 *count = mpegbufs;
1142
1143 return 0;
1144}
1145
1146static int bb_buf_prepare(struct videobuf_queue *q,
1147 struct videobuf_buffer *vb, enum v4l2_field field)
1148{
1149 struct cx23885_fh *fh = q->priv_data;
1150 return cx23885_buf_prepare(q, &fh->dev->ts1,
1151 (struct cx23885_buffer *)vb,
1152 field);
1153}
1154
1155static void bb_buf_queue(struct videobuf_queue *q,
1156 struct videobuf_buffer *vb)
1157{
1158 struct cx23885_fh *fh = q->priv_data;
1159 cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb);
1160}
1161
1162static void bb_buf_release(struct videobuf_queue *q,
1163 struct videobuf_buffer *vb)
1164{
1165 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
1166}
1167
1168static struct videobuf_queue_ops cx23885_qops = {
1169 .buf_setup = bb_buf_setup,
1170 .buf_prepare = bb_buf_prepare,
1171 .buf_queue = bb_buf_queue,
1172 .buf_release = bb_buf_release,
1173};
1174
1175/* ------------------------------------------------------------------ */
1176
1177static const u32 *ctrl_classes[] = {
1178 cx2341x_mpeg_ctrls,
1179 NULL
1180};
1181
1182static int cx23885_queryctrl(struct cx23885_dev *dev,
1183 struct v4l2_queryctrl *qctrl)
1184{
1185 qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1186 if (qctrl->id == 0)
1187 return -EINVAL;
1188
1189 /* MPEG V4L2 controls */
1190 if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1191 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1192
1193 return 0;
1194}
1195
1196static int cx23885_querymenu(struct cx23885_dev *dev,
1197 struct v4l2_querymenu *qmenu)
1198{
1199 struct v4l2_queryctrl qctrl;
1200
1201 qctrl.id = qmenu->id;
1202 cx23885_queryctrl(dev, &qctrl);
1203 return v4l2_ctrl_query_menu(qmenu, &qctrl,
e0e31cdb 1204 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
b1b81f1d
ST		 1205}
1206
305519c9 1207static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
b1b81f1d 1208{
305519c9
DSL		 1209 struct cx23885_fh *fh = file->private_data;
1210 struct cx23885_dev *dev = fh->dev;
1211 unsigned int i;
b1b81f1d 1212
305519c9
DSL		 1213 for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
1214 if (*id & cx23885_tvnorms[i].id)
1215 break;
1216 if (i == ARRAY_SIZE(cx23885_tvnorms))
1217 return -EINVAL;
1218 dev->encodernorm = cx23885_tvnorms[i];
1219 return 0;
1220}
b1b81f1d 1221
305519c9
DSL		 1222static int vidioc_enum_input(struct file *file, void *priv,
1223 struct v4l2_input *i)
1224{
1225 struct cx23885_fh *fh = file->private_data;
1226 struct cx23885_dev *dev = fh->dev;
1227 struct cx23885_input *input;
f29816bc 1228 int n;
b1b81f1d 1229
f29816bc 1230 if (i->index >= 4)
305519c9 1231 return -EINVAL;
b1b81f1d 1232
f29816bc 1233 input = &cx23885_boards[dev->board].input[i->index];
b1b81f1d 1234
305519c9
DSL		 1235 if (input->type == 0)
1236 return -EINVAL;
b1b81f1d 1237
305519c9
DSL		 1238 /* FIXME
1239 * strcpy(i->name, input->name); */
1240 strcpy(i->name, "unset");
b1b81f1d 1241
305519c9
DSL		 1242 if (input->type == CX23885_VMUX_TELEVISION ||
1243 input->type == CX23885_VMUX_CABLE)
1244 i->type = V4L2_INPUT_TYPE_TUNER;
1245 else
1246 i->type = V4L2_INPUT_TYPE_CAMERA;
b1b81f1d 1247
305519c9
DSL		 1248 for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++)
1249 i->std |= cx23885_tvnorms[n].id;
1250 return 0;
1251}
b1b81f1d 1252
305519c9
DSL		 1253static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1254{
1255 struct cx23885_fh *fh = file->private_data;
1256 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1257
305519c9
DSL		 1258 *i = dev->input;
1259 return 0;
1260}
b1b81f1d 1261
305519c9
DSL		 1262static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1263{
1264 if (i >= 4)
1265 return -EINVAL;
b1b81f1d 1266
305519c9
DSL		 1267 return 0;
1268}
b1b81f1d 1269
305519c9
DSL		 1270static int vidioc_g_tuner(struct file *file, void *priv,
1271 struct v4l2_tuner *t)
1272{
1273 struct cx23885_fh *fh = file->private_data;
1274 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1275
305519c9
DSL		 1276 if (UNSET == dev->tuner_type)
1277 return -EINVAL;
1278 if (0 != t->index)
1279 return -EINVAL;
305519c9 1280 strcpy(t->name, "Television");
0d5a19f1 1281 call_all(dev, tuner, g_tuner, t);
b1b81f1d 1282
305519c9 1283 dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
b1b81f1d 1284
305519c9
DSL		 1285 return 0;
1286}
b1b81f1d 1287
305519c9
DSL		 1288static int vidioc_s_tuner(struct file *file, void *priv,
1289 struct v4l2_tuner *t)
1290{
1291 struct cx23885_fh *fh = file->private_data;
1292 struct cx23885_dev *dev = fh->dev;
1293
1294 if (UNSET == dev->tuner_type)
1295 return -EINVAL;
1296
1297 /* Update the A/V core */
0d5a19f1 1298 call_all(dev, tuner, s_tuner, t);
305519c9
DSL		 1299
1300 return 0;
1301}
1302
1303static int vidioc_g_frequency(struct file *file, void *priv,
1304 struct v4l2_frequency *f)
1305{
1306 struct cx23885_fh *fh = file->private_data;
1307 struct cx23885_dev *dev = fh->dev;
1308
305519c9
DSL		 1309 if (UNSET == dev->tuner_type)
1310 return -EINVAL;
1311 f->type = V4L2_TUNER_ANALOG_TV;
1312 f->frequency = dev->freq;
1313
0d5a19f1 1314 call_all(dev, tuner, g_frequency, f);
305519c9
DSL		 1315
1316 return 0;
1317}
1318
1319static int vidioc_s_frequency(struct file *file, void *priv,
1320 struct v4l2_frequency *f)
1321{
1322 struct cx23885_fh *fh = file->private_data;
1323 struct cx23885_dev *dev = fh->dev;
1324
1325 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1326 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1327 CX23885_RAW_BITS_NONE);
1328
1329 dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
1330 dev->tuner_type);
1331 dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
1332 f->tuner, f->type);
1333 if (UNSET == dev->tuner_type)
1334 return -EINVAL;
1335 if (f->tuner != 0)
1336 return -EINVAL;
1337 if (f->type != V4L2_TUNER_ANALOG_TV)
1338 return -EINVAL;
1339 dev->freq = f->frequency;
1340
0d5a19f1 1341 call_all(dev, tuner, s_frequency, f);
305519c9
DSL		 1342
1343 cx23885_initialize_codec(dev);
b1b81f1d
ST		 1344
1345 return 0;
1346}
1347
305519c9
DSL		 1348static int vidioc_s_ctrl(struct file *file, void *priv,
1349 struct v4l2_control *ctl)
1350{
1351 struct cx23885_fh *fh = file->private_data;
1352 struct cx23885_dev *dev = fh->dev;
1353
1354 /* Update the A/V core */
0d5a19f1 1355 call_all(dev, core, s_ctrl, ctl);
305519c9
DSL		 1356 return 0;
1357}
1358
1359static int vidioc_querycap(struct file *file, void *priv,
1360 struct v4l2_capability *cap)
b1b81f1d
ST		 1361{
1362 struct cx23885_fh *fh = file->private_data;
1363 struct cx23885_dev *dev = fh->dev;
1364 struct cx23885_tsport *tsport = &dev->ts1;
1365
b084307c 1366 strlcpy(cap->driver, dev->name, sizeof(cap->driver));
305519c9
DSL		 1367 strlcpy(cap->card, cx23885_boards[tsport->dev->board].name,
1368 sizeof(cap->card));
1369 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
305519c9
DSL		 1370 cap->capabilities =
1371 V4L2_CAP_VIDEO_CAPTURE |
1372 V4L2_CAP_READWRITE |
1373 V4L2_CAP_STREAMING |
1374 0;
1375 if (UNSET != dev->tuner_type)
1376 cap->capabilities |= V4L2_CAP_TUNER;
b1b81f1d 1377
305519c9
DSL		 1378 return 0;
1379}
b1b81f1d 1380
305519c9
DSL		 1381static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1382 struct v4l2_fmtdesc *f)
1383{
f29816bc 1384 if (f->index != 0)
305519c9 1385 return -EINVAL;
b1b81f1d 1386
305519c9 1387 strlcpy(f->description, "MPEG", sizeof(f->description));
305519c9 1388 f->pixelformat = V4L2_PIX_FMT_MPEG;
b1b81f1d 1389
305519c9
DSL		 1390 return 0;
1391}
b1b81f1d 1392
305519c9
DSL		 1393static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1394 struct v4l2_format *f)
1395{
1396 struct cx23885_fh *fh = file->private_data;
1397 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1398
305519c9
DSL		 1399 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1400 f->fmt.pix.bytesperline = 0;
1401 f->fmt.pix.sizeimage =
1402 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1403 f->fmt.pix.colorspace = 0;
1404 f->fmt.pix.width = dev->ts1.width;
1405 f->fmt.pix.height = dev->ts1.height;
1406 f->fmt.pix.field = fh->mpegq.field;
1407 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1408 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1409 return 0;
1410}
b1b81f1d 1411
305519c9
DSL		 1412static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1413 struct v4l2_format *f)
1414{
1415 struct cx23885_fh *fh = file->private_data;
1416 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1417
305519c9
DSL		 1418 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1419 f->fmt.pix.bytesperline = 0;
1420 f->fmt.pix.sizeimage =
1421 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
305519c9
DSL		 1422 f->fmt.pix.colorspace = 0;
1423 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1424 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1425 return 0;
1426}
b1b81f1d 1427
305519c9
DSL		 1428static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1429 struct v4l2_format *f)
1430{
1431 struct cx23885_fh *fh = file->private_data;
1432 struct cx23885_dev *dev = fh->dev;
b1b81f1d 1433
305519c9
DSL		 1434 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1435 f->fmt.pix.bytesperline = 0;
1436 f->fmt.pix.sizeimage =
1437 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1438 f->fmt.pix.colorspace = 0;
1439 dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
1440 f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
1441 return 0;
1442}
b1b81f1d 1443
305519c9
DSL		 1444static int vidioc_reqbufs(struct file *file, void *priv,
1445 struct v4l2_requestbuffers *p)
1446{
1447 struct cx23885_fh *fh = file->private_data;
b1b81f1d 1448
305519c9
DSL		 1449 return videobuf_reqbufs(&fh->mpegq, p);
1450}
1451
1452static int vidioc_querybuf(struct file *file, void *priv,
1453 struct v4l2_buffer *p)
1454{
1455 struct cx23885_fh *fh = file->private_data;
1456
1457 return videobuf_querybuf(&fh->mpegq, p);
1458}
1459
1460static int vidioc_qbuf(struct file *file, void *priv,
1461 struct v4l2_buffer *p)
1462{
1463 struct cx23885_fh *fh = file->private_data;
1464
1465 return videobuf_qbuf(&fh->mpegq, p);
1466}
1467
1468static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1469{
1470 struct cx23885_fh *fh = priv;
1471
1472 return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK);
1473}
1474
1475
1476static int vidioc_streamon(struct file *file, void *priv,
1477 enum v4l2_buf_type i)
1478{
1479 struct cx23885_fh *fh = file->private_data;
1480
1481 return videobuf_streamon(&fh->mpegq);
1482}
1483
1484static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1485{
1486 struct cx23885_fh *fh = file->private_data;
1487
1488 return videobuf_streamoff(&fh->mpegq);
1489}
1490
1491static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1492 struct v4l2_ext_controls *f)
1493{
1494 struct cx23885_fh *fh = priv;
1495 struct cx23885_dev *dev = fh->dev;
1496
1497 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1498 return -EINVAL;
1499 return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1500}
1501
1502static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1503 struct v4l2_ext_controls *f)
1504{
1505 struct cx23885_fh *fh = priv;
1506 struct cx23885_dev *dev = fh->dev;
1507 struct cx2341x_mpeg_params p;
1508 int err;
1509
1510 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1511 return -EINVAL;
1512
1513 p = dev->mpeg_params;
1514 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS);
1515
1516 if (err == 0) {
1517 err = cx2341x_update(dev, cx23885_mbox_func,
1518 &dev->mpeg_params, &p);
1519 dev->mpeg_params = p;
b1b81f1d 1520 }
305519c9
DSL		 1521 return err;
1522}
1523
1524static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1525 struct v4l2_ext_controls *f)
1526{
1527 struct cx23885_fh *fh = priv;
1528 struct cx23885_dev *dev = fh->dev;
1529 struct cx2341x_mpeg_params p;
1530 int err;
1531
1532 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1533 return -EINVAL;
1534
1535 p = dev->mpeg_params;
1536 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1537 return err;
1538}
1539
1540static int vidioc_log_status(struct file *file, void *priv)
1541{
1542 struct cx23885_fh *fh = priv;
1543 struct cx23885_dev *dev = fh->dev;
1544 char name[32 + 2];
1545
1546 snprintf(name, sizeof(name), "%s/2", dev->name);
1547 printk(KERN_INFO
1548 "%s/2: ============ START LOG STATUS ============\n",
1549 dev->name);
0d5a19f1 1550 call_all(dev, core, log_status);
305519c9
DSL		 1551 cx2341x_log_status(&dev->mpeg_params, name);
1552 printk(KERN_INFO
1553 "%s/2: ============= END LOG STATUS =============\n",
1554 dev->name);
b1b81f1d
ST		 1555 return 0;
1556}
1557
305519c9
DSL		 1558static int vidioc_querymenu(struct file *file, void *priv,
1559 struct v4l2_querymenu *a)
1560{
1561 struct cx23885_fh *fh = priv;
1562 struct cx23885_dev *dev = fh->dev;
1563
1564 return cx23885_querymenu(dev, a);
1565}
1566
1567static int vidioc_queryctrl(struct file *file, void *priv,
1568 struct v4l2_queryctrl *c)
b1b81f1d 1569{
305519c9
DSL		 1570 struct cx23885_fh *fh = priv;
1571 struct cx23885_dev *dev = fh->dev;
1572
1573 return cx23885_queryctrl(dev, c);
b1b81f1d
ST		 1574}
1575
bec43661 1576static int mpeg_open(struct file *file)
b1b81f1d 1577{
63b0d5ad 1578 struct cx23885_dev *dev = video_drvdata(file);
b1b81f1d
ST		 1579 struct cx23885_fh *fh;
1580
1581 dprintk(2, "%s()\n", __func__);
1582
b1b81f1d
ST		 1583 /* allocate + initialize per filehandle data */
1584 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
0edf2e5e 1585 if (!fh)
b1b81f1d 1586 return -ENOMEM;
63b0d5ad 1587
b1b81f1d
ST		 1588 file->private_data = fh;
1589 fh->dev = dev;
1590
1591 videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops,
1592 &dev->pci->dev, &dev->ts1.slock,
1593 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1594 V4L2_FIELD_INTERLACED,
1595 sizeof(struct cx23885_buffer),
08bff03e 1596 fh, NULL);
b1b81f1d
ST		 1597 return 0;
1598}
1599
bec43661 1600static int mpeg_release(struct file *file)
b1b81f1d
ST		 1601{
1602 struct cx23885_fh *fh = file->private_data;
1603 struct cx23885_dev *dev = fh->dev;
1604
1605 dprintk(2, "%s()\n", __func__);
1606
1607 /* FIXME: Review this crap */
1608 /* Shut device down on last close */
1609 if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1610 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1611 /* stop mpeg capture */
1612 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1613 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1614 CX23885_RAW_BITS_NONE);
1615
1616 msleep(500);
1617 cx23885_417_check_encoder(dev);
1618
1619 cx23885_cancel_buffers(&fh->dev->ts1);
1620 }
1621 }
1622
1623 if (fh->mpegq.streaming)
1624 videobuf_streamoff(&fh->mpegq);
1625 if (fh->mpegq.reading)
1626 videobuf_read_stop(&fh->mpegq);
1627
1628 videobuf_mmap_free(&fh->mpegq);
1629 file->private_data = NULL;
1630 kfree(fh);
1631
1632 return 0;
1633}
1634
1635static ssize_t mpeg_read(struct file *file, char __user *data,
1636 size_t count, loff_t *ppos)
1637{
1638 struct cx23885_fh *fh = file->private_data;
1639 struct cx23885_dev *dev = fh->dev;
1640
1641 dprintk(2, "%s()\n", __func__);
1642
1643 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1644 /* Start mpeg encoder on first read. */
1645 if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1646 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1647 if (cx23885_initialize_codec(dev) < 0)
1648 return -EINVAL;
1649 }
1650 }
1651
1652 return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0,
1653 file->f_flags & O_NONBLOCK);
1654}
1655
1656static unsigned int mpeg_poll(struct file *file,
1657 struct poll_table_struct *wait)
1658{
1659 struct cx23885_fh *fh = file->private_data;
1660 struct cx23885_dev *dev = fh->dev;
1661
1662 dprintk(2, "%s\n", __func__);
1663
1664 return videobuf_poll_stream(file, &fh->mpegq, wait);
1665}
1666
1667static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1668{
1669 struct cx23885_fh *fh = file->private_data;
1670 struct cx23885_dev *dev = fh->dev;
1671
1672 dprintk(2, "%s()\n", __func__);
1673
1674 return videobuf_mmap_mapper(&fh->mpegq, vma);
1675}
1676
bec43661 1677static struct v4l2_file_operations mpeg_fops = {
b1b81f1d
ST		 1678 .owner = THIS_MODULE,
1679 .open = mpeg_open,
1680 .release = mpeg_release,
1681 .read = mpeg_read,
1682 .poll = mpeg_poll,
1683 .mmap = mpeg_mmap,
12a34cc8 1684 .ioctl = video_ioctl2,
b1b81f1d
ST		 1685};
1686
a399810c 1687static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
305519c9
DSL		 1688 .vidioc_s_std = vidioc_s_std,
1689 .vidioc_enum_input = vidioc_enum_input,
1690 .vidioc_g_input = vidioc_g_input,
1691 .vidioc_s_input = vidioc_s_input,
1692 .vidioc_g_tuner = vidioc_g_tuner,
1693 .vidioc_s_tuner = vidioc_s_tuner,
1694 .vidioc_g_frequency = vidioc_g_frequency,
1695 .vidioc_s_frequency = vidioc_s_frequency,
1696 .vidioc_s_ctrl = vidioc_s_ctrl,
1697 .vidioc_querycap = vidioc_querycap,
1698 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1699 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
1700 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
1701 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
1702 .vidioc_reqbufs = vidioc_reqbufs,
1703 .vidioc_querybuf = vidioc_querybuf,
1704 .vidioc_qbuf = vidioc_qbuf,
1705 .vidioc_dqbuf = vidioc_dqbuf,
1706 .vidioc_streamon = vidioc_streamon,
1707 .vidioc_streamoff = vidioc_streamoff,
1708 .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
1709 .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
1710 .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
1711 .vidioc_log_status = vidioc_log_status,
1712 .vidioc_querymenu = vidioc_querymenu,
1713 .vidioc_queryctrl = vidioc_queryctrl,
74618244
AW		 1714 .vidioc_g_chip_ident = cx23885_g_chip_ident,
1715#ifdef CONFIG_VIDEO_ADV_DEBUG
1716 .vidioc_g_register = cx23885_g_register,
1717 .vidioc_s_register = cx23885_s_register,
1718#endif
b1b81f1d
ST		 1719};
1720
a399810c
HV		 1721static struct video_device cx23885_mpeg_template = {
1722 .name = "cx23885",
a399810c
HV		 1723 .fops = &mpeg_fops,
1724 .ioctl_ops = &mpeg_ioctl_ops,
6655be0f
MK		 1725 .tvnorms = CX23885_NORMS,
1726 .current_norm = V4L2_STD_NTSC_M,
a399810c
HV		 1727};
1728
b1b81f1d
ST		 1729void cx23885_417_unregister(struct cx23885_dev *dev)
1730{
1731 dprintk(1, "%s()\n", __func__);
1732
1733 if (dev->v4l_device) {
f0813b4c 1734 if (video_is_registered(dev->v4l_device))
b1b81f1d
ST		 1735 video_unregister_device(dev->v4l_device);
1736 else
1737 video_device_release(dev->v4l_device);
1738 dev->v4l_device = NULL;
1739 }
1740}
1741
1742static struct video_device *cx23885_video_dev_alloc(
1743 struct cx23885_tsport *tsport,
1744 struct pci_dev *pci,
1745 struct video_device *template,
1746 char *type)
1747{
1748 struct video_device *vfd;
1749 struct cx23885_dev *dev = tsport->dev;
1750
1751 dprintk(1, "%s()\n", __func__);
1752
1753 vfd = video_device_alloc();
1754 if (NULL == vfd)
1755 return NULL;
1756 *vfd = *template;
b1b81f1d
ST		 1757 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1758 type, cx23885_boards[tsport->dev->board].name);
5e85e732 1759 vfd->parent = &pci->dev;
b1b81f1d
ST		 1760 vfd->release = video_device_release;
1761 return vfd;
1762}
1763
1764int cx23885_417_register(struct cx23885_dev *dev)
1765{
1766 /* FIXME: Port1 hardcoded here */
1767 int err = -ENODEV;
1768 struct cx23885_tsport *tsport = &dev->ts1;
1769
1770 dprintk(1, "%s()\n", __func__);
1771
1772 if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
1773 return err;
1774
1775 /* Set default TV standard */
1776 dev->encodernorm = cx23885_tvnorms[0];
1777
1778 if (dev->encodernorm.id & V4L2_STD_525_60)
1779 tsport->height = 480;
1780 else
1781 tsport->height = 576;
1782
1783 tsport->width = 720;
1784 cx2341x_fill_defaults(&dev->mpeg_params);
1785
1786 dev->mpeg_params.port = CX2341X_PORT_SERIAL;
1787
1788 /* Allocate and initialize V4L video device */
1789 dev->v4l_device = cx23885_video_dev_alloc(tsport,
1790 dev->pci, &cx23885_mpeg_template, "mpeg");
63b0d5ad 1791 video_set_drvdata(dev->v4l_device, dev);
b1b81f1d
ST		 1792 err = video_register_device(dev->v4l_device,
1793 VFL_TYPE_GRABBER, -1);
1794 if (err < 0) {
1795 printk(KERN_INFO "%s: can't register mpeg device\n", dev->name);
1796 return err;
1797 }
1798
38c7c036
LP		 1799 printk(KERN_INFO "%s: registered device %s [mpeg]\n",
1800 dev->name, video_device_node_name(dev->v4l_device));
b1b81f1d
ST		 1801
1802 return 0;
1803}
Linux kernel - Deliverables
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