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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-cards.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
7b888014 26#include <media/cx25840.h>
78db8547 27#include <linux/firmware.h>
cff4fa84 28#include <misc/altera.h>
d19770e5
ST		 29
30#include "cx23885.h"
90a71b1c 31#include "tuner-xc2028.h"
b8f0d306 32#include "netup-eeprom.h"
5a23b076 33#include "netup-init.h"
78db8547 34#include "altera-ci.h"
0cf8af57 35#include "xc4000.h"
78db8547 36#include "xc5000.h"
29f8a0a5 37#include "cx23888-ir.h"
d19770e5 38
2d12421d
AO		 39static unsigned int netup_card_rev = 1;
40module_param(netup_card_rev, int, 0644);
41MODULE_PARM_DESC(netup_card_rev,
42 "NetUP Dual DVB-T/C CI card revision");
fa647f24
AW		 43static unsigned int enable_885_ir;
44module_param(enable_885_ir, int, 0644);
45MODULE_PARM_DESC(enable_885_ir,
46 "Enable integrated IR controller for supported\n"
47 "\t\t CX2388[57] boards that are wired for it:\n"
48 "\t\t\tHVR-1250 (reported safe)\n"
49 "\t\t\tTeVii S470 (reported unsafe)\n"
50 "\t\t This can cause an interrupt storm with some cards.\n"
51 "\t\t Default: 0 [Disabled]");
52
d19770e5
ST		 53/* ------------------------------------------------------------------ */
54/* board config info */
55
56struct cx23885_board cx23885_boards[] = {
57 [CX23885_BOARD_UNKNOWN] = {
58 .name = "UNKNOWN/GENERIC",
c7712613
ST		 59 /* Ensure safe default for unknown boards */
60 .clk_freq = 0,
d19770e5
ST		 61 .input = {{
62 .type = CX23885_VMUX_COMPOSITE1,
63 .vmux = 0,
9c8ced51 64 }, {
d19770e5
ST		 65 .type = CX23885_VMUX_COMPOSITE2,
66 .vmux = 1,
9c8ced51 67 }, {
d19770e5
ST		 68 .type = CX23885_VMUX_COMPOSITE3,
69 .vmux = 2,
9c8ced51 70 }, {
d19770e5
ST		 71 .type = CX23885_VMUX_COMPOSITE4,
72 .vmux = 3,
9c8ced51 73 } },
d19770e5
ST		 74 },
75 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
76 .name = "Hauppauge WinTV-HVR1800lp",
d19770e5
ST		 77 .portc = CX23885_MPEG_DVB,
78 .input = {{
79 .type = CX23885_VMUX_TELEVISION,
80 .vmux = 0,
81 .gpio0 = 0xff00,
9c8ced51 82 }, {
d19770e5
ST		 83 .type = CX23885_VMUX_DEBUG,
84 .vmux = 0,
85 .gpio0 = 0xff01,
9c8ced51 86 }, {
d19770e5
ST		 87 .type = CX23885_VMUX_COMPOSITE1,
88 .vmux = 1,
89 .gpio0 = 0xff02,
9c8ced51 90 }, {
d19770e5
ST		 91 .type = CX23885_VMUX_SVIDEO,
92 .vmux = 2,
93 .gpio0 = 0xff02,
9c8ced51 94 } },
d19770e5
ST		 95 },
96 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
97 .name = "Hauppauge WinTV-HVR1800",
7b888014 98 .porta = CX23885_ANALOG_VIDEO,
a589b665 99 .portb = CX23885_MPEG_ENCODER,
d19770e5 100 .portc = CX23885_MPEG_DVB,
7b888014
ST		 101 .tuner_type = TUNER_PHILIPS_TDA8290,
102 .tuner_addr = 0x42, /* 0x84 >> 1 */
557f48d5 103 .tuner_bus = 1,
d19770e5
ST		 104 .input = {{
105 .type = CX23885_VMUX_TELEVISION,
7b888014
ST		 106 .vmux = CX25840_VIN7_CH3 |
107 CX25840_VIN5_CH2 |
108 CX25840_VIN2_CH1,
33cdeb35 109 .amux = CX25840_AUDIO8,
7b888014 110 .gpio0 = 0,
9c8ced51 111 }, {
d19770e5 112 .type = CX23885_VMUX_COMPOSITE1,
7b888014
ST		 113 .vmux = CX25840_VIN7_CH3 |
114 CX25840_VIN4_CH2 |
115 CX25840_VIN6_CH1,
33cdeb35 116 .amux = CX25840_AUDIO7,
7b888014 117 .gpio0 = 0,
9c8ced51 118 }, {
d19770e5 119 .type = CX23885_VMUX_SVIDEO,
7b888014
ST		 120 .vmux = CX25840_VIN7_CH3 |
121 CX25840_VIN4_CH2 |
122 CX25840_VIN8_CH1 |
123 CX25840_SVIDEO_ON,
33cdeb35 124 .amux = CX25840_AUDIO7,
7b888014 125 .gpio0 = 0,
9c8ced51 126 } },
d19770e5 127 },
a77743bc
ST		 128 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
129 .name = "Hauppauge WinTV-HVR1250",
d214ddc8 130 .porta = CX23885_ANALOG_VIDEO,
a77743bc 131 .portc = CX23885_MPEG_DVB,
d214ddc8
DH		 132#ifdef MT2131_NO_ANALOG_SUPPORT_YET
133 .tuner_type = TUNER_PHILIPS_TDA8290,
134 .tuner_addr = 0x42, /* 0x84 >> 1 */
135 .tuner_bus = 1,
136#endif
137 .force_bff = 1,
a77743bc 138 .input = {{
d214ddc8 139#ifdef MT2131_NO_ANALOG_SUPPORT_YET
a77743bc 140 .type = CX23885_VMUX_TELEVISION,
d214ddc8
DH		 141 .vmux = CX25840_VIN7_CH3 |
142 CX25840_VIN5_CH2 |
143 CX25840_VIN2_CH1,
144 .amux = CX25840_AUDIO8,
a77743bc 145 .gpio0 = 0xff00,
9c8ced51 146 }, {
d214ddc8 147#endif
a77743bc 148 .type = CX23885_VMUX_COMPOSITE1,
d214ddc8
DH		 149 .vmux = CX25840_VIN7_CH3 |
150 CX25840_VIN4_CH2 |
151 CX25840_VIN6_CH1,
152 .amux = CX25840_AUDIO7,
a77743bc 153 .gpio0 = 0xff02,
9c8ced51 154 }, {
a77743bc 155 .type = CX23885_VMUX_SVIDEO,
d214ddc8
DH		 156 .vmux = CX25840_VIN7_CH3 |
157 CX25840_VIN4_CH2 |
158 CX25840_VIN8_CH1 |
159 CX25840_SVIDEO_ON,
160 .amux = CX25840_AUDIO7,
a77743bc 161 .gpio0 = 0xff02,
9c8ced51 162 } },
a77743bc 163 },
9bc37caa
MK		 164 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
165 .name = "DViCO FusionHDTV5 Express",
a6a3f140 166 .portb = CX23885_MPEG_DVB,
9bc37caa 167 },
d1987d55
ST		 168 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
169 .name = "Hauppauge WinTV-HVR1500Q",
170 .portc = CX23885_MPEG_DVB,
171 },
07b4a835
MK		 172 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
173 .name = "Hauppauge WinTV-HVR1500",
18d64476 174 .porta = CX23885_ANALOG_VIDEO,
07b4a835 175 .portc = CX23885_MPEG_DVB,
18d64476
MM		 176 .tuner_type = TUNER_XC2028,
177 .tuner_addr = 0x61, /* 0xc2 >> 1 */
178 .input = {{
179 .type = CX23885_VMUX_TELEVISION,
180 .vmux = CX25840_VIN7_CH3 |
181 CX25840_VIN5_CH2 |
182 CX25840_VIN2_CH1,
183 .gpio0 = 0,
184 }, {
185 .type = CX23885_VMUX_COMPOSITE1,
186 .vmux = CX25840_VIN7_CH3 |
187 CX25840_VIN4_CH2 |
188 CX25840_VIN6_CH1,
189 .gpio0 = 0,
190 }, {
191 .type = CX23885_VMUX_SVIDEO,
192 .vmux = CX25840_VIN7_CH3 |
193 CX25840_VIN4_CH2 |
194 CX25840_VIN8_CH1 |
195 CX25840_SVIDEO_ON,
196 .gpio0 = 0,
197 } },
07b4a835 198 },
b3ea0166
ST		 199 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
200 .name = "Hauppauge WinTV-HVR1200",
201 .portc = CX23885_MPEG_DVB,
202 },
a780a31c
ST		 203 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
204 .name = "Hauppauge WinTV-HVR1700",
205 .portc = CX23885_MPEG_DVB,
206 },
66762373
ST		 207 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
208 .name = "Hauppauge WinTV-HVR1400",
209 .portc = CX23885_MPEG_DVB,
210 },
335377b7
MK		 211 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
212 .name = "DViCO FusionHDTV7 Dual Express",
aaadeac8 213 .portb = CX23885_MPEG_DVB,
335377b7
MK		 214 .portc = CX23885_MPEG_DVB,
215 },
aef2d186
ST		 216 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
217 .name = "DViCO FusionHDTV DVB-T Dual Express",
218 .portb = CX23885_MPEG_DVB,
219 .portc = CX23885_MPEG_DVB,
220 },
4c56b04a
ST		 221 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
222 .name = "Leadtek Winfast PxDVR3200 H",
223 .portc = CX23885_MPEG_DVB,
224 },
0cf8af57 225 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
226 .name = "Leadtek Winfast PxDVR3200 H XC4000",
227 .porta = CX23885_ANALOG_VIDEO,
228 .portc = CX23885_MPEG_DVB,
229 .tuner_type = TUNER_XC4000,
230 .tuner_addr = 0x61,
9ee8537f
MS		 231 .radio_type = UNSET,
232 .radio_addr = ADDR_UNSET,
0cf8af57 233 .input = {{
234 .type = CX23885_VMUX_TELEVISION,
235 .vmux = CX25840_VIN2_CH1 |
236 CX25840_VIN5_CH2 |
237 CX25840_NONE0_CH3,
238 }, {
239 .type = CX23885_VMUX_COMPOSITE1,
240 .vmux = CX25840_COMPOSITE1,
241 }, {
242 .type = CX23885_VMUX_SVIDEO,
243 .vmux = CX25840_SVIDEO_LUMA3 |
244 CX25840_SVIDEO_CHROMA4,
245 }, {
246 .type = CX23885_VMUX_COMPONENT,
247 .vmux = CX25840_VIN7_CH1 |
248 CX25840_VIN6_CH2 |
249 CX25840_VIN8_CH3 |
250 CX25840_COMPONENT_ON,
251 } },
252 },
9bb1b7e8
IL		 253 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
254 .name = "Compro VideoMate E650F",
255 .portc = CX23885_MPEG_DVB,
256 },
96318d0c
IL		 257 [CX23885_BOARD_TBS_6920] = {
258 .name = "TurboSight TBS 6920",
259 .portb = CX23885_MPEG_DVB,
260 },
579943f5
IL		 261 [CX23885_BOARD_TEVII_S470] = {
262 .name = "TeVii S470",
263 .portb = CX23885_MPEG_DVB,
264 },
c9b8b04b
IL		 265 [CX23885_BOARD_DVBWORLD_2005] = {
266 .name = "DVBWorld DVB-S2 2005",
267 .portb = CX23885_MPEG_DVB,
268 },
5a23b076 269 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
78db8547 270 .ci_type = 1,
5a23b076
IL		 271 .name = "NetUP Dual DVB-S2 CI",
272 .portb = CX23885_MPEG_DVB,
273 .portc = CX23885_MPEG_DVB,
274 },
2074dffa
ST		 275 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
276 .name = "Hauppauge WinTV-HVR1270",
a5dbf457 277 .portc = CX23885_MPEG_DVB,
2074dffa 278 },
d099becb
MK		 279 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
280 .name = "Hauppauge WinTV-HVR1275",
281 .portc = CX23885_MPEG_DVB,
282 },
19bc5796
MK		 283 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
284 .name = "Hauppauge WinTV-HVR1255",
0ac60acb 285 .porta = CX23885_ANALOG_VIDEO,
19bc5796 286 .portc = CX23885_MPEG_DVB,
0ac60acb
DH		 287 .tuner_type = TUNER_ABSENT,
288 .tuner_addr = 0x42, /* 0x84 >> 1 */
289 .force_bff = 1,
290 .input = {{
291 .type = CX23885_VMUX_TELEVISION,
292 .vmux = CX25840_VIN7_CH3 |
293 CX25840_VIN5_CH2 |
294 CX25840_VIN2_CH1 |
295 CX25840_DIF_ON,
296 .amux = CX25840_AUDIO8,
297 }, {
298 .type = CX23885_VMUX_COMPOSITE1,
299 .vmux = CX25840_VIN7_CH3 |
300 CX25840_VIN4_CH2 |
301 CX25840_VIN6_CH1,
302 .amux = CX25840_AUDIO7,
303 }, {
304 .type = CX23885_VMUX_SVIDEO,
305 .vmux = CX25840_VIN7_CH3 |
306 CX25840_VIN4_CH2 |
307 CX25840_VIN8_CH1 |
308 CX25840_SVIDEO_ON,
309 .amux = CX25840_AUDIO7,
310 } },
311 },
312 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
313 .name = "Hauppauge WinTV-HVR1255",
314 .porta = CX23885_ANALOG_VIDEO,
315 .portc = CX23885_MPEG_DVB,
316 .tuner_type = TUNER_ABSENT,
317 .tuner_addr = 0x42, /* 0x84 >> 1 */
318 .force_bff = 1,
319 .input = {{
320 .type = CX23885_VMUX_TELEVISION,
321 .vmux = CX25840_VIN7_CH3 |
322 CX25840_VIN5_CH2 |
323 CX25840_VIN2_CH1 |
324 CX25840_DIF_ON,
325 .amux = CX25840_AUDIO8,
326 }, {
327 .type = CX23885_VMUX_SVIDEO,
328 .vmux = CX25840_VIN7_CH3 |
329 CX25840_VIN4_CH2 |
330 CX25840_VIN8_CH1 |
331 CX25840_SVIDEO_ON,
332 .amux = CX25840_AUDIO7,
333 } },
19bc5796 334 },
6b926eca
MK		 335 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
336 .name = "Hauppauge WinTV-HVR1210",
337 .portc = CX23885_MPEG_DVB,
338 },
493b7127
DW		 339 [CX23885_BOARD_MYGICA_X8506] = {
340 .name = "Mygica X8506 DMB-TH",
6f0d8c02
DW		 341 .tuner_type = TUNER_XC5000,
342 .tuner_addr = 0x61,
557f48d5 343 .tuner_bus = 1,
bc1548ad 344 .porta = CX23885_ANALOG_VIDEO,
493b7127 345 .portb = CX23885_MPEG_DVB,
bc1548ad 346 .input = {
6f0d8c02
DW		 347 {
348 .type = CX23885_VMUX_TELEVISION,
349 .vmux = CX25840_COMPOSITE2,
350 },
bc1548ad
DW		 351 {
352 .type = CX23885_VMUX_COMPOSITE1,
353 .vmux = CX25840_COMPOSITE8,
354 },
355 {
356 .type = CX23885_VMUX_SVIDEO,
357 .vmux = CX25840_SVIDEO_LUMA3 |
358 CX25840_SVIDEO_CHROMA4,
359 },
360 {
361 .type = CX23885_VMUX_COMPONENT,
362 .vmux = CX25840_COMPONENT_ON |
363 CX25840_VIN1_CH1 |
364 CX25840_VIN6_CH2 |
365 CX25840_VIN7_CH3,
366 },
367 },
493b7127 368 },
2365b2d3
DW		 369 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
370 .name = "Magic-Pro ProHDTV Extreme 2",
6f0d8c02
DW		 371 .tuner_type = TUNER_XC5000,
372 .tuner_addr = 0x61,
557f48d5 373 .tuner_bus = 1,
bc1548ad 374 .porta = CX23885_ANALOG_VIDEO,
2365b2d3 375 .portb = CX23885_MPEG_DVB,
bc1548ad 376 .input = {
6f0d8c02
DW		 377 {
378 .type = CX23885_VMUX_TELEVISION,
379 .vmux = CX25840_COMPOSITE2,
380 },
bc1548ad
DW		 381 {
382 .type = CX23885_VMUX_COMPOSITE1,
383 .vmux = CX25840_COMPOSITE8,
384 },
385 {
386 .type = CX23885_VMUX_SVIDEO,
387 .vmux = CX25840_SVIDEO_LUMA3 |
388 CX25840_SVIDEO_CHROMA4,
389 },
390 {
391 .type = CX23885_VMUX_COMPONENT,
392 .vmux = CX25840_COMPONENT_ON |
393 CX25840_VIN1_CH1 |
394 CX25840_VIN6_CH2 |
395 CX25840_VIN7_CH3,
396 },
397 },
2365b2d3 398 },
13697380
ST		 399 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
400 .name = "Hauppauge WinTV-HVR1850",
35045137 401 .porta = CX23885_ANALOG_VIDEO,
13697380
ST		 402 .portb = CX23885_MPEG_ENCODER,
403 .portc = CX23885_MPEG_DVB,
35045137
ST		 404 .tuner_type = TUNER_ABSENT,
405 .tuner_addr = 0x42, /* 0x84 >> 1 */
406 .force_bff = 1,
407 .input = {{
408 .type = CX23885_VMUX_TELEVISION,
409 .vmux = CX25840_VIN7_CH3 |
410 CX25840_VIN5_CH2 |
411 CX25840_VIN2_CH1 |
412 CX25840_DIF_ON,
413 .amux = CX25840_AUDIO8,
414 }, {
415 .type = CX23885_VMUX_COMPOSITE1,
416 .vmux = CX25840_VIN7_CH3 |
417 CX25840_VIN4_CH2 |
418 CX25840_VIN6_CH1,
419 .amux = CX25840_AUDIO7,
420 }, {
421 .type = CX23885_VMUX_SVIDEO,
422 .vmux = CX25840_VIN7_CH3 |
423 CX25840_VIN4_CH2 |
424 CX25840_VIN8_CH1 |
425 CX25840_SVIDEO_ON,
426 .amux = CX25840_AUDIO7,
427 } },
13697380 428 },
34e383dd
VG		 429 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
430 .name = "Compro VideoMate E800",
431 .portc = CX23885_MPEG_DVB,
432 },
aee0b24c
MK		 433 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
434 .name = "Hauppauge WinTV-HVR1290",
435 .portc = CX23885_MPEG_DVB,
436 },
ea5697fe
DW		 437 [CX23885_BOARD_MYGICA_X8558PRO] = {
438 .name = "Mygica X8558 PRO DMB-TH",
439 .portb = CX23885_MPEG_DVB,
440 .portc = CX23885_MPEG_DVB,
441 },
0b32d65c
KK		 442 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
443 .name = "LEADTEK WinFast PxTV1200",
444 .porta = CX23885_ANALOG_VIDEO,
445 .tuner_type = TUNER_XC2028,
446 .tuner_addr = 0x61,
557f48d5 447 .tuner_bus = 1,
0b32d65c
KK		 448 .input = {{
449 .type = CX23885_VMUX_TELEVISION,
450 .vmux = CX25840_VIN2_CH1 |
451 CX25840_VIN5_CH2 |
452 CX25840_NONE0_CH3,
453 }, {
454 .type = CX23885_VMUX_COMPOSITE1,
455 .vmux = CX25840_COMPOSITE1,
456 }, {
457 .type = CX23885_VMUX_SVIDEO,
458 .vmux = CX25840_SVIDEO_LUMA3 |
459 CX25840_SVIDEO_CHROMA4,
460 }, {
461 .type = CX23885_VMUX_COMPONENT,
462 .vmux = CX25840_VIN7_CH1 |
463 CX25840_VIN6_CH2 |
464 CX25840_VIN8_CH3 |
465 CX25840_COMPONENT_ON,
466 } },
467 },
9028f58f
AC		 468 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
469 .name = "GoTView X5 3D Hybrid",
470 .tuner_type = TUNER_XC5000,
471 .tuner_addr = 0x64,
557f48d5 472 .tuner_bus = 1,
9028f58f
AC		 473 .porta = CX23885_ANALOG_VIDEO,
474 .portb = CX23885_MPEG_DVB,
475 .input = {{
476 .type = CX23885_VMUX_TELEVISION,
477 .vmux = CX25840_VIN2_CH1 |
478 CX25840_VIN5_CH2,
479 .gpio0 = 0x02,
480 }, {
481 .type = CX23885_VMUX_COMPOSITE1,
482 .vmux = CX23885_VMUX_COMPOSITE1,
483 }, {
484 .type = CX23885_VMUX_SVIDEO,
485 .vmux = CX25840_SVIDEO_LUMA3 |
486 CX25840_SVIDEO_CHROMA4,
487 } },
488 },
78db8547
IL		 489 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
490 .ci_type = 2,
491 .name = "NetUP Dual DVB-T/C-CI RF",
492 .porta = CX23885_ANALOG_VIDEO,
493 .portb = CX23885_MPEG_DVB,
494 .portc = CX23885_MPEG_DVB,
10d0dcd7
IL		 495 .num_fds_portb = 2,
496 .num_fds_portc = 2,
78db8547
IL		 497 .tuner_type = TUNER_XC5000,
498 .tuner_addr = 0x64,
499 .input = { {
500 .type = CX23885_VMUX_TELEVISION,
501 .vmux = CX25840_COMPOSITE1,
502 } },
503 },
2cb9ccd4
ST		 504 [CX23885_BOARD_MPX885] = {
505 .name = "MPX-885",
506 .porta = CX23885_ANALOG_VIDEO,
507 .input = {{
508 .type = CX23885_VMUX_COMPOSITE1,
509 .vmux = CX25840_COMPOSITE1,
510 .amux = CX25840_AUDIO6,
511 .gpio0 = 0,
512 }, {
513 .type = CX23885_VMUX_COMPOSITE2,
514 .vmux = CX25840_COMPOSITE2,
515 .amux = CX25840_AUDIO6,
516 .gpio0 = 0,
517 }, {
518 .type = CX23885_VMUX_COMPOSITE3,
519 .vmux = CX25840_COMPOSITE3,
520 .amux = CX25840_AUDIO7,
521 .gpio0 = 0,
522 }, {
523 .type = CX23885_VMUX_COMPOSITE4,
524 .vmux = CX25840_COMPOSITE4,
525 .amux = CX25840_AUDIO7,
526 .gpio0 = 0,
527 } },
528 },
87988753
AJD		 529 [CX23885_BOARD_MYGICA_X8507] = {
530 .name = "Mygica X8507",
531 .tuner_type = TUNER_XC5000,
532 .tuner_addr = 0x61,
533 .tuner_bus = 1,
534 .porta = CX23885_ANALOG_VIDEO,
535 .input = {
536 {
537 .type = CX23885_VMUX_TELEVISION,
538 .vmux = CX25840_COMPOSITE2,
539 .amux = CX25840_AUDIO8,
540 },
541 {
542 .type = CX23885_VMUX_COMPOSITE1,
543 .vmux = CX25840_COMPOSITE8,
544 },
545 {
546 .type = CX23885_VMUX_SVIDEO,
547 .vmux = CX25840_SVIDEO_LUMA3 |
548 CX25840_SVIDEO_CHROMA4,
549 },
550 {
551 .type = CX23885_VMUX_COMPONENT,
552 .vmux = CX25840_COMPONENT_ON |
553 CX25840_VIN1_CH1 |
554 CX25840_VIN6_CH2 |
555 CX25840_VIN7_CH3,
556 },
557 },
722c90eb
SR		 558 },
559 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
560 .name = "TerraTec Cinergy T PCIe Dual",
561 .portb = CX23885_MPEG_DVB,
562 .portc = CX23885_MPEG_DVB,
7b134e85
IL		 563 },
564 [CX23885_BOARD_TEVII_S471] = {
565 .name = "TeVii S471",
566 .portb = CX23885_MPEG_DVB,
87988753 567 }
d19770e5
ST		 568};
569const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
570
571/* ------------------------------------------------------------------ */
572/* PCI subsystem IDs */
573
574struct cx23885_subid cx23885_subids[] = {
575 {
576 .subvendor = 0x0070,
577 .subdevice = 0x3400,
578 .card = CX23885_BOARD_UNKNOWN,
9c8ced51 579 }, {
d19770e5
ST		 580 .subvendor = 0x0070,
581 .subdevice = 0x7600,
582 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
9c8ced51 583 }, {
d19770e5
ST		 584 .subvendor = 0x0070,
585 .subdevice = 0x7800,
586 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 587 }, {
d19770e5
ST		 588 .subvendor = 0x0070,
589 .subdevice = 0x7801,
590 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 591 }, {
6ccb8cfb
MK		 592 .subvendor = 0x0070,
593 .subdevice = 0x7809,
594 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 595 }, {
a77743bc
ST		 596 .subvendor = 0x0070,
597 .subdevice = 0x7911,
598 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
9c8ced51 599 }, {
9bc37caa
MK		 600 .subvendor = 0x18ac,
601 .subdevice = 0xd500,
602 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
9c8ced51 603 }, {
b00fff0b
MK		 604 .subvendor = 0x0070,
605 .subdevice = 0x7790,
606 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 607 }, {
d1987d55
ST		 608 .subvendor = 0x0070,
609 .subdevice = 0x7797,
610 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 611 }, {
b00fff0b
MK		 612 .subvendor = 0x0070,
613 .subdevice = 0x7710,
614 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
9c8ced51 615 }, {
07b4a835
MK		 616 .subvendor = 0x0070,
617 .subdevice = 0x7717,
618 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
b3ea0166
ST		 619 }, {
620 .subvendor = 0x0070,
621 .subdevice = 0x71d1,
622 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
3c3852cd
MK		 623 }, {
624 .subvendor = 0x0070,
625 .subdevice = 0x71d3,
626 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
a780a31c
ST		 627 }, {
628 .subvendor = 0x0070,
629 .subdevice = 0x8101,
630 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
66762373
ST		 631 }, {
632 .subvendor = 0x0070,
633 .subdevice = 0x8010,
634 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
9c8ced51 635 }, {
335377b7
MK		 636 .subvendor = 0x18ac,
637 .subdevice = 0xd618,
638 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
9c8ced51 639 }, {
aef2d186
ST		 640 .subvendor = 0x18ac,
641 .subdevice = 0xdb78,
642 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
4c56b04a
ST		 643 }, {
644 .subvendor = 0x107d,
645 .subdevice = 0x6681,
646 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
0cf8af57 647 }, {
648 .subvendor = 0x107d,
649 .subdevice = 0x6f39,
650 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
9bb1b7e8
IL		 651 }, {
652 .subvendor = 0x185b,
653 .subdevice = 0xe800,
654 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
96318d0c
IL		 655 }, {
656 .subvendor = 0x6920,
657 .subdevice = 0x8888,
658 .card = CX23885_BOARD_TBS_6920,
579943f5
IL		 659 }, {
660 .subvendor = 0xd470,
661 .subdevice = 0x9022,
662 .card = CX23885_BOARD_TEVII_S470,
c9b8b04b
IL		 663 }, {
664 .subvendor = 0x0001,
665 .subdevice = 0x2005,
666 .card = CX23885_BOARD_DVBWORLD_2005,
5a23b076
IL		 667 }, {
668 .subvendor = 0x1b55,
669 .subdevice = 0x2a2c,
670 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
2074dffa
ST		 671 }, {
672 .subvendor = 0x0070,
673 .subdevice = 0x2211,
674 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
d099becb
MK		 675 }, {
676 .subvendor = 0x0070,
677 .subdevice = 0x2215,
678 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
7d7b5284
MK		 679 }, {
680 .subvendor = 0x0070,
681 .subdevice = 0x221d,
682 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
19bc5796
MK		 683 }, {
684 .subvendor = 0x0070,
685 .subdevice = 0x2251,
686 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
7d7b5284
MK		 687 }, {
688 .subvendor = 0x0070,
689 .subdevice = 0x2259,
0ac60acb 690 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
6b926eca
MK		 691 }, {
692 .subvendor = 0x0070,
693 .subdevice = 0x2291,
694 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
695 }, {
696 .subvendor = 0x0070,
697 .subdevice = 0x2295,
698 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
7d7b5284
MK		 699 }, {
700 .subvendor = 0x0070,
701 .subdevice = 0x2299,
702 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
703 }, {
704 .subvendor = 0x0070,
705 .subdevice = 0x229d,
706 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
707 }, {
708 .subvendor = 0x0070,
709 .subdevice = 0x22f0,
710 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
711 }, {
712 .subvendor = 0x0070,
713 .subdevice = 0x22f1,
714 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
715 }, {
716 .subvendor = 0x0070,
717 .subdevice = 0x22f2,
718 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
719 }, {
720 .subvendor = 0x0070,
721 .subdevice = 0x22f3,
722 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
723 }, {
724 .subvendor = 0x0070,
725 .subdevice = 0x22f4,
726 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
727 }, {
728 .subvendor = 0x0070,
729 .subdevice = 0x22f5,
730 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
493b7127
DW		 731 }, {
732 .subvendor = 0x14f1,
733 .subdevice = 0x8651,
734 .card = CX23885_BOARD_MYGICA_X8506,
2365b2d3
DW		 735 }, {
736 .subvendor = 0x14f1,
737 .subdevice = 0x8657,
738 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
13697380
ST		 739 }, {
740 .subvendor = 0x0070,
741 .subdevice = 0x8541,
742 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
34e383dd
VG		 743 }, {
744 .subvendor = 0x1858,
745 .subdevice = 0xe800,
746 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
aee0b24c
MK		 747 }, {
748 .subvendor = 0x0070,
749 .subdevice = 0x8551,
750 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
ea5697fe
DW		 751 }, {
752 .subvendor = 0x14f1,
753 .subdevice = 0x8578,
754 .card = CX23885_BOARD_MYGICA_X8558PRO,
0b32d65c
KK		 755 }, {
756 .subvendor = 0x107d,
757 .subdevice = 0x6f22,
758 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
9028f58f
AC		 759 }, {
760 .subvendor = 0x5654,
761 .subdevice = 0x2390,
762 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
78db8547
IL		 763 }, {
764 .subvendor = 0x1b55,
765 .subdevice = 0xe2e4,
766 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
87988753
AJD		 767 }, {
768 .subvendor = 0x14f1,
769 .subdevice = 0x8502,
770 .card = CX23885_BOARD_MYGICA_X8507,
722c90eb
SR		 771 }, {
772 .subvendor = 0x153b,
773 .subdevice = 0x117e,
774 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
7b134e85
IL		 775 }, {
776 .subvendor = 0xd471,
777 .subdevice = 0x9022,
778 .card = CX23885_BOARD_TEVII_S471,
d19770e5
ST		 779 },
780};
781const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
782
783void cx23885_card_list(struct cx23885_dev *dev)
784{
785 int i;
786
787 if (0 == dev->pci->subsystem_vendor &&
788 0 == dev->pci->subsystem_device) {
9c8ced51
ST		 789 printk(KERN_INFO
790 "%s: Board has no valid PCIe Subsystem ID and can't\n"
791 "%s: be autodetected. Pass card=<n> insmod option\n"
792 "%s: to workaround that. Redirect complaints to the\n"
793 "%s: vendor of the TV card. Best regards,\n"
d19770e5
ST		 794 "%s: -- tux\n",
795 dev->name, dev->name, dev->name, dev->name, dev->name);
796 } else {
9c8ced51
ST		 797 printk(KERN_INFO
798 "%s: Your board isn't known (yet) to the driver.\n"
799 "%s: Try to pick one of the existing card configs via\n"
d19770e5
ST		 800 "%s: card=<n> insmod option. Updating to the latest\n"
801 "%s: version might help as well.\n",
802 dev->name, dev->name, dev->name, dev->name);
803 }
9c8ced51 804 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
d19770e5
ST		 805 dev->name);
806 for (i = 0; i < cx23885_bcount; i++)
9c8ced51 807 printk(KERN_INFO "%s: card=%d -> %s\n",
d19770e5
ST		 808 dev->name, i, cx23885_boards[i].name);
809}
810
811static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
812{
813 struct tveeprom tv;
814
9c8ced51
ST		 815 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
816 eeprom_data);
d19770e5 817
d19770e5 818 /* Make sure we support the board model */
9c8ced51 819 switch (tv.model) {
5308cf09
MK		 820 case 22001:
821 /* WinTV-HVR1270 (PCIe, Retail, half height)
822 * ATSC/QAM and basic analog, IR Blast */
823 case 22009:
824 /* WinTV-HVR1210 (PCIe, Retail, half height)
825 * DVB-T and basic analog, IR Blast */
826 case 22011:
827 /* WinTV-HVR1270 (PCIe, Retail, half height)
828 * ATSC/QAM and basic analog, IR Recv */
829 case 22019:
830 /* WinTV-HVR1210 (PCIe, Retail, half height)
831 * DVB-T and basic analog, IR Recv */
832 case 22021:
833 /* WinTV-HVR1275 (PCIe, Retail, half height)
834 * ATSC/QAM and basic analog, IR Recv */
835 case 22029:
836 /* WinTV-HVR1210 (PCIe, Retail, half height)
837 * DVB-T and basic analog, IR Recv */
838 case 22101:
839 /* WinTV-HVR1270 (PCIe, Retail, full height)
840 * ATSC/QAM and basic analog, IR Blast */
841 case 22109:
842 /* WinTV-HVR1210 (PCIe, Retail, full height)
843 * DVB-T and basic analog, IR Blast */
844 case 22111:
845 /* WinTV-HVR1270 (PCIe, Retail, full height)
846 * ATSC/QAM and basic analog, IR Recv */
847 case 22119:
848 /* WinTV-HVR1210 (PCIe, Retail, full height)
849 * DVB-T and basic analog, IR Recv */
850 case 22121:
851 /* WinTV-HVR1275 (PCIe, Retail, full height)
852 * ATSC/QAM and basic analog, IR Recv */
853 case 22129:
854 /* WinTV-HVR1210 (PCIe, Retail, full height)
855 * DVB-T and basic analog, IR Recv */
36396c89
MK		 856 case 71009:
857 /* WinTV-HVR1200 (PCIe, Retail, full height)
858 * DVB-T and basic analog */
859 case 71359:
860 /* WinTV-HVR1200 (PCIe, OEM, half height)
861 * DVB-T and basic analog */
862 case 71439:
863 /* WinTV-HVR1200 (PCIe, OEM, half height)
864 * DVB-T and basic analog */
865 case 71449:
866 /* WinTV-HVR1200 (PCIe, OEM, full height)
867 * DVB-T and basic analog */
868 case 71939:
869 /* WinTV-HVR1200 (PCIe, OEM, half height)
870 * DVB-T and basic analog */
871 case 71949:
872 /* WinTV-HVR1200 (PCIe, OEM, full height)
873 * DVB-T and basic analog */
874 case 71959:
875 /* WinTV-HVR1200 (PCIe, OEM, full height)
876 * DVB-T and basic analog */
877 case 71979:
878 /* WinTV-HVR1200 (PCIe, OEM, half height)
879 * DVB-T and basic analog */
880 case 71999:
881 /* WinTV-HVR1200 (PCIe, OEM, full height)
882 * DVB-T and basic analog */
9c8ced51
ST		 883 case 76601:
884 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
885 channel ATSC and MPEG2 HW Encoder */
886 case 77001:
887 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
888 and Basic analog */
889 case 77011:
890 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
891 and Basic analog */
892 case 77041:
893 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
894 and Basic analog */
895 case 77051:
896 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
897 and Basic analog */
898 case 78011:
899 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
900 Dual channel ATSC and MPEG2 HW Encoder */
901 case 78501:
902 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
903 Dual channel ATSC and MPEG2 HW Encoder */
904 case 78521:
905 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
906 Dual channel ATSC and MPEG2 HW Encoder */
907 case 78531:
908 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
909 Dual channel ATSC and MPEG2 HW Encoder */
910 case 78631:
911 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
912 Dual channel ATSC and MPEG2 HW Encoder */
913 case 79001:
914 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
915 ATSC and Basic analog */
916 case 79101:
917 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
918 ATSC and Basic analog */
ebbeb460
AW		 919 case 79501:
920 /* WinTV-HVR1250 (PCIe, No IR, half height,
921 ATSC [at least] and Basic analog) */
9c8ced51
ST		 922 case 79561:
923 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
924 ATSC and Basic analog */
925 case 79571:
926 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
927 ATSC and Basic analog */
928 case 79671:
929 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
930 ATSC and Basic analog */
66762373
ST		 931 case 80019:
932 /* WinTV-HVR1400 (Express Card, Retail, IR,
933 * DVB-T and Basic analog */
36396c89
MK		 934 case 81509:
935 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
936 * DVB-T and MPEG2 HW Encoder */
a780a31c 937 case 81519:
36396c89 938 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
a780a31c 939 * DVB-T and MPEG2 HW Encoder */
d19770e5 940 break;
13697380 941 case 85021:
73a5f419 942 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
13697380
ST		 943 Dual channel ATSC and MPEG2 HW Encoder */
944 break;
73a5f419
MK		 945 case 85721:
946 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
947 Dual channel ATSC and Basic analog */
948 break;
d19770e5 949 default:
13697380
ST		 950 printk(KERN_WARNING "%s: warning: "
951 "unknown hauppauge model #%d\n",
9c8ced51 952 dev->name, tv.model);
d19770e5
ST		 953 break;
954 }
955
956 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
957 dev->name, tv.model);
958}
959
d7cba043 960int cx23885_tuner_callback(void *priv, int component, int command, int arg)
8c70017f 961{
89ce2216
ST		 962 struct cx23885_tsport *port = priv;
963 struct cx23885_dev *dev = port->dev;
6df51690
ST		 964 u32 bitmask = 0;
965
c6cff169 966 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
89ce2216
ST		 967 return 0;
968
6df51690
ST		 969 if (command != 0) {
970 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
971 __func__, command);
972 return -EINVAL;
973 }
8c70017f 974
9c8ced51 975 switch (dev->board) {
90a71b1c
ST		 976 case CX23885_BOARD_HAUPPAUGE_HVR1400:
977 case CX23885_BOARD_HAUPPAUGE_HVR1500:
8c70017f 978 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
4c56b04a 979 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 980 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 981 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 982 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 983 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
90a71b1c 984 /* Tuner Reset Command */
4c56b04a 985 bitmask = 0x04;
6df51690
ST		 986 break;
987 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 988 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
4c56b04a
ST		 989 /* Two identical tuners on two different i2c buses,
990 * we need to reset the correct gpio. */
d4dc673d 991 if (port->nr == 1)
4c56b04a 992 bitmask = 0x01;
d4dc673d 993 else if (port->nr == 2)
4c56b04a 994 bitmask = 0x04;
8c70017f 995 break;
9028f58f
AC		 996 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
997 /* Tuner Reset Command */
998 bitmask = 0x02;
999 break;
78db8547
IL		 1000 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1001 altera_ci_tuner_reset(dev, port->nr);
1002 break;
8c70017f
ST		 1003 }
1004
6df51690
ST		 1005 if (bitmask) {
1006 /* Drive the tuner into reset and back out */
1007 cx_clear(GP0_IO, bitmask);
1008 mdelay(200);
1009 cx_set(GP0_IO, bitmask);
1010 }
1011
1012 return 0;
8c70017f 1013}
73c993a8 1014
a6a3f140
ST		 1015void cx23885_gpio_setup(struct cx23885_dev *dev)
1016{
9c8ced51 1017 switch (dev->board) {
a6a3f140
ST		 1018 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1019 /* GPIO-0 cx24227 demodulator reset */
1020 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1021 break;
07b4a835
MK		 1022 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1023 /* GPIO-0 cx24227 demodulator */
1024 /* GPIO-2 xc3028 tuner */
1025
1026 /* Put the parts into reset */
1027 cx_set(GP0_IO, 0x00050000);
1028 cx_clear(GP0_IO, 0x00000005);
1029 msleep(5);
1030
1031 /* Bring the parts out of reset */
1032 cx_set(GP0_IO, 0x00050005);
1033 break;
d1987d55
ST		 1034 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1035 /* GPIO-0 cx24227 demodulator reset */
1036 /* GPIO-2 xc5000 tuner reset */
1037 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1038 break;
a6a3f140
ST		 1039 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1040 /* GPIO-0 656_CLK */
1041 /* GPIO-1 656_D0 */
1042 /* GPIO-2 8295A Reset */
1043 /* GPIO-3-10 cx23417 data0-7 */
1044 /* GPIO-11-14 cx23417 addr0-3 */
1045 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1046 /* GPIO-19 IR_RX */
3ba71d21 1047
a589b665
ST		 1048 /* CX23417 GPIO's */
1049 /* EIO15 Zilog Reset */
1050 /* EIO14 S5H1409/CX24227 Reset */
f659c513
ST		 1051 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1052
1053 /* Put the demod into reset and protect the eeprom */
1054 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1055 mdelay(100);
1056
1057 /* Bring the demod and blaster out of reset */
1058 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1059 mdelay(100);
a589b665 1060
5206d6ec 1061 /* Force the TDA8295A into reset and back */
21ff3e4f
ST		 1062 cx23885_gpio_enable(dev, GPIO_2, 1);
1063 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 1064 mdelay(20);
21ff3e4f 1065 cx23885_gpio_clear(dev, GPIO_2);
5206d6ec 1066 mdelay(20);
21ff3e4f 1067 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 1068 mdelay(20);
a6a3f140 1069 break;
b3ea0166
ST		 1070 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1071 /* GPIO-0 tda10048 demodulator reset */
1072 /* GPIO-2 tda18271 tuner reset */
1073
a780a31c
ST		 1074 /* Put the parts into reset and back */
1075 cx_set(GP0_IO, 0x00050000);
1076 mdelay(20);
1077 cx_clear(GP0_IO, 0x00000005);
1078 mdelay(20);
1079 cx_set(GP0_IO, 0x00050005);
1080 break;
1081 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1082 /* GPIO-0 TDA10048 demodulator reset */
1083 /* GPIO-2 TDA8295A Reset */
1084 /* GPIO-3-10 cx23417 data0-7 */
1085 /* GPIO-11-14 cx23417 addr0-3 */
1086 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1087
1088 /* The following GPIO's are on the interna AVCore (cx25840) */
1089 /* GPIO-19 IR_RX */
1090 /* GPIO-20 IR_TX 416/DVBT Select */
1091 /* GPIO-21 IIS DAT */
1092 /* GPIO-22 IIS WCLK */
1093 /* GPIO-23 IIS BCLK */
1094
66762373
ST		 1095 /* Put the parts into reset and back */
1096 cx_set(GP0_IO, 0x00050000);
1097 mdelay(20);
1098 cx_clear(GP0_IO, 0x00000005);
1099 mdelay(20);
1100 cx_set(GP0_IO, 0x00050005);
1101 break;
1102 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1103 /* GPIO-0 Dibcom7000p demodulator reset */
1104 /* GPIO-2 xc3028L tuner reset */
1105 /* GPIO-13 LED */
1106
b3ea0166
ST		 1107 /* Put the parts into reset and back */
1108 cx_set(GP0_IO, 0x00050000);
1109 mdelay(20);
1110 cx_clear(GP0_IO, 0x00000005);
1111 mdelay(20);
1112 cx_set(GP0_IO, 0x00050005);
1113 break;
1ecc5aed
ST		 1114 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1115 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1116 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1117 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1118 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1119
aef2d186
ST		 1120 /* Put the parts into reset and back */
1121 cx_set(GP0_IO, 0x000f0000);
1122 mdelay(20);
1123 cx_clear(GP0_IO, 0x0000000f);
1124 mdelay(20);
1125 cx_set(GP0_IO, 0x000f000f);
1126 break;
1127 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1128 /* GPIO-0 portb xc3028 reset */
1129 /* GPIO-1 portb zl10353 reset */
1130 /* GPIO-2 portc xc3028 reset */
1131 /* GPIO-3 portc zl10353 reset */
1132
1ecc5aed
ST		 1133 /* Put the parts into reset and back */
1134 cx_set(GP0_IO, 0x000f0000);
1135 mdelay(20);
1136 cx_clear(GP0_IO, 0x0000000f);
1137 mdelay(20);
1138 cx_set(GP0_IO, 0x000f000f);
1139 break;
4c56b04a 1140 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1141 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1142 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 1143 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 1144 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
4c56b04a
ST		 1145 /* GPIO-2 xc3028 tuner reset */
1146
1147 /* The following GPIO's are on the internal AVCore (cx25840) */
1148 /* GPIO-? zl10353 demod reset */
1149
1150 /* Put the parts into reset and back */
1151 cx_set(GP0_IO, 0x00040000);
1152 mdelay(20);
1153 cx_clear(GP0_IO, 0x00000004);
1154 mdelay(20);
1155 cx_set(GP0_IO, 0x00040004);
1156 break;
96318d0c
IL		 1157 case CX23885_BOARD_TBS_6920:
1158 cx_write(MC417_CTL, 0x00000036);
1159 cx_write(MC417_OEN, 0x00001000);
09ea33e5
IL		 1160 cx_set(MC417_RWD, 0x00000002);
1161 mdelay(200);
1162 cx_clear(MC417_RWD, 0x00000800);
1163 mdelay(200);
1164 cx_set(MC417_RWD, 0x00000800);
1165 mdelay(200);
96318d0c 1166 break;
5a23b076
IL		 1167 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1168 /* GPIO-0 INTA from CiMax1
1169 GPIO-1 INTB from CiMax2
1170 GPIO-2 reset chips
1171 GPIO-3 to GPIO-10 data/addr for CA
1172 GPIO-11 ~CS0 to CiMax1
1173 GPIO-12 ~CS1 to CiMax2
1174 GPIO-13 ADL0 load LSB addr
1175 GPIO-14 ADL1 load MSB addr
1176 GPIO-15 ~RDY from CiMax
1177 GPIO-17 ~RD to CiMax
1178 GPIO-18 ~WR to CiMax
1179 */
1180 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1181 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1182 cx_clear(GP0_IO, 0x00030004);
1183 mdelay(100);/* reset delay */
1184 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1185 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1186 /* GPIO-15 IN as ~ACK, rest as OUT */
1187 cx_write(MC417_OEN, 0x00001000);
1188 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1189 cx_write(MC417_RWD, 0x0000c300);
1190 /* enable irq */
1191 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1192 break;
2074dffa 1193 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1194 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1195 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1196 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1197 case CX23885_BOARD_HAUPPAUGE_HVR1210:
d099becb 1198 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
6b926eca
MK		 1199 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1200 /* GPIO-9 Demod reset */
2074dffa
ST		 1201
1202 /* Put the parts into reset and back */
d099becb
MK		 1203 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1204 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
2074dffa
ST		 1205 cx23885_gpio_clear(dev, GPIO_9);
1206 mdelay(20);
1207 cx23885_gpio_set(dev, GPIO_9);
1208 break;
493b7127 1209 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 1210 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
87988753 1211 case CX23885_BOARD_MYGICA_X8507:
8e069bb9 1212 /* GPIO-0 (0)Analog / (1)Digital TV */
493b7127 1213 /* GPIO-1 reset XC5000 */
2365b2d3 1214 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
8e069bb9
DW		 1215 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1216 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
493b7127 1217 mdelay(100);
8e069bb9 1218 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
493b7127
DW		 1219 mdelay(100);
1220 break;
ea5697fe
DW		 1221 case CX23885_BOARD_MYGICA_X8558PRO:
1222 /* GPIO-0 reset first ATBM8830 */
1223 /* GPIO-1 reset second ATBM8830 */
1224 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1225 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1226 mdelay(100);
1227 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1228 mdelay(100);
1229 break;
13697380 1230 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1231 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1232 /* GPIO-0 656_CLK */
1233 /* GPIO-1 656_D0 */
1234 /* GPIO-2 Wake# */
1235 /* GPIO-3-10 cx23417 data0-7 */
1236 /* GPIO-11-14 cx23417 addr0-3 */
1237 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1238 /* GPIO-19 IR_RX */
1239 /* GPIO-20 C_IR_TX */
1240 /* GPIO-21 I2S DAT */
1241 /* GPIO-22 I2S WCLK */
1242 /* GPIO-23 I2S BCLK */
1243 /* ALT GPIO: EXP GPIO LATCH */
1244
1245 /* CX23417 GPIO's */
1246 /* GPIO-14 S5H1411/CX24228 Reset */
1247 /* GPIO-13 EEPROM write protect */
1248 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1249
1250 /* Put the demod into reset and protect the eeprom */
1251 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1252 mdelay(100);
1253
1254 /* Bring the demod out of reset */
1255 mc417_gpio_set(dev, GPIO_14);
1256 mdelay(100);
1257
1258 /* CX24228 GPIO */
1259 /* Connected to IF / Mux */
1260 break;
9028f58f
AC		 1261 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1262 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1263 break;
78db8547
IL		 1264 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1265 /* GPIO-0 ~INT in
1266 GPIO-1 TMS out
1267 GPIO-2 ~reset chips out
1268 GPIO-3 to GPIO-10 data/addr for CA in/out
1269 GPIO-11 ~CS out
1270 GPIO-12 ADDR out
1271 GPIO-13 ~WR out
1272 GPIO-14 ~RD out
1273 GPIO-15 ~RDY in
1274 GPIO-16 TCK out
1275 GPIO-17 TDO in
1276 GPIO-18 TDI out
1277 */
1278 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1279 /* GPIO-0 as INT, reset & TMS low */
1280 cx_clear(GP0_IO, 0x00010006);
1281 mdelay(100);/* reset delay */
1282 cx_set(GP0_IO, 0x00000004); /* reset high */
1283 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1284 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1285 cx_write(MC417_OEN, 0x00005000);
1286 /* ~RD, ~WR high; ADDR low; ~CS high */
1287 cx_write(MC417_RWD, 0x00000d00);
1288 /* enable irq */
1289 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1290 break;
a6a3f140
ST		 1291 }
1292}
1293
1294int cx23885_ir_init(struct cx23885_dev *dev)
1295{
98d109f9 1296 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
81f287da
AW		 1297 {
1298 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1299 .pin = CX23885_PIN_IR_RX_GPIO19,
1300 .function = CX23885_PAD_IR_RX,
1301 .value = 0,
1302 .strength = CX25840_PIN_DRIVE_MEDIUM,
1303 }, {
1304 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1305 .pin = CX23885_PIN_IR_TX_GPIO20,
1306 .function = CX23885_PAD_IR_TX,
1307 .value = 0,
1308 .strength = CX25840_PIN_DRIVE_MEDIUM,
1309 }
1310 };
98d109f9
AW		 1311 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1312
1313 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1314 {
1315 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1316 .pin = CX23885_PIN_IR_RX_GPIO19,
1317 .function = CX23885_PAD_IR_RX,
1318 .value = 0,
1319 .strength = CX25840_PIN_DRIVE_MEDIUM,
1320 }
1321 };
1322 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
81f287da
AW		 1323
1324 struct v4l2_subdev_ir_parameters params;
29f8a0a5 1325 int ret = 0;
a6a3f140 1326 switch (dev->board) {
07b4a835 1327 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1328 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 1329 case CX23885_BOARD_HAUPPAUGE_HVR1800:
b3ea0166 1330 case CX23885_BOARD_HAUPPAUGE_HVR1200:
66762373 1331 case CX23885_BOARD_HAUPPAUGE_HVR1400:
d099becb 1332 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1333 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1334 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1335 case CX23885_BOARD_HAUPPAUGE_HVR1210:
a6a3f140
ST		 1336 /* FIXME: Implement me */
1337 break;
9b3d8ecc
AW		 1338 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1339 ret = cx23888_ir_probe(dev);
1340 if (ret)
1341 break;
1342 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1343 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1344 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1345 break;
29f8a0a5 1346 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1347 case CX23885_BOARD_HAUPPAUGE_HVR1290:
29f8a0a5
AW		 1348 ret = cx23888_ir_probe(dev);
1349 if (ret)
1350 break;
1351 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
81f287da 1352 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
98d109f9 1353 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
81f287da
AW		 1354 /*
1355 * For these boards we need to invert the Tx output via the
1356 * IR controller to have the LED off while idle
1357 */
1358 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1359 params.enable = false;
1360 params.shutdown = false;
1361 params.invert_level = true;
1362 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1363 params.shutdown = true;
1364 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
29f8a0a5 1365 break;
98d109f9 1366 case CX23885_BOARD_TEVII_S470:
fa647f24
AW		 1367 if (!enable_885_ir)
1368 break;
98d109f9
AW		 1369 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1370 if (dev->sd_ir == NULL) {
1371 ret = -ENODEV;
1372 break;
1373 }
1374 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1375 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
98d109f9
AW		 1376 break;
1377 case CX23885_BOARD_HAUPPAUGE_HVR1250:
fa647f24
AW		 1378 if (!enable_885_ir)
1379 break;
98d109f9
AW		 1380 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1381 if (dev->sd_ir == NULL) {
1382 ret = -ENODEV;
1383 break;
1384 }
1385 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1386 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
98d109f9 1387 break;
12886871
ST		 1388 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1389 request_module("ir-kbd-i2c");
1390 break;
a6a3f140
ST		 1391 }
1392
29f8a0a5 1393 return ret;
a6a3f140
ST		 1394}
1395
f59ad611
AW		 1396void cx23885_ir_fini(struct cx23885_dev *dev)
1397{
1398 switch (dev->board) {
9b3d8ecc 1399 case CX23885_BOARD_HAUPPAUGE_HVR1270:
f59ad611 1400 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1401 case CX23885_BOARD_HAUPPAUGE_HVR1290:
dbe83a3b 1402 cx23885_irq_remove(dev, PCI_MSK_IR);
f59ad611
AW		 1403 cx23888_ir_remove(dev);
1404 dev->sd_ir = NULL;
1405 break;
98d109f9
AW		 1406 case CX23885_BOARD_TEVII_S470:
1407 case CX23885_BOARD_HAUPPAUGE_HVR1250:
dbe83a3b 1408 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
98d109f9
AW		 1409 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1410 dev->sd_ir = NULL;
1411 break;
f59ad611
AW		 1412 }
1413}
1414
78db8547
IL		 1415int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1416{
1417 int data;
1418 int tdo = 0;
1419 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1420 /*TMS*/
1421 data = ((cx_read(GP0_IO)) & (~0x00000002));
1422 data |= (tms ? 0x00020002 : 0x00020000);
1423 cx_write(GP0_IO, data);
1424
1425 /*TDI*/
1426 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1427 data |= (tdi ? 0x00008000 : 0);
1428 cx_write(MC417_RWD, data);
1429 if (read_tdo)
1430 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1431
1432 cx_write(MC417_RWD, data | 0x00002000);
1433 udelay(1);
1434 /*TCK*/
1435 cx_write(MC417_RWD, data);
1436
1437 return tdo;
1438}
1439
f59ad611
AW		 1440void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1441{
1442 switch (dev->board) {
9b3d8ecc 1443 case CX23885_BOARD_HAUPPAUGE_HVR1270:
f59ad611 1444 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1445 case CX23885_BOARD_HAUPPAUGE_HVR1290:
dbe83a3b
AW		 1446 if (dev->sd_ir)
1447 cx23885_irq_add_enable(dev, PCI_MSK_IR);
f59ad611 1448 break;
98d109f9
AW		 1449 case CX23885_BOARD_TEVII_S470:
1450 case CX23885_BOARD_HAUPPAUGE_HVR1250:
dbe83a3b
AW		 1451 if (dev->sd_ir)
1452 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
98d109f9 1453 break;
f59ad611
AW		 1454 }
1455}
1456
d19770e5
ST		 1457void cx23885_card_setup(struct cx23885_dev *dev)
1458{
a6a3f140
ST		 1459 struct cx23885_tsport *ts1 = &dev->ts1;
1460 struct cx23885_tsport *ts2 = &dev->ts2;
1461
d19770e5
ST		 1462 static u8 eeprom[256];
1463
1464 if (dev->i2c_bus[0].i2c_rc == 0) {
1465 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
44a6481d
MK		 1466 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1467 eeprom, sizeof(eeprom));
d19770e5
ST		 1468 }
1469
1470 switch (dev->board) {
a77743bc 1471 case CX23885_BOARD_HAUPPAUGE_HVR1250:
ebbeb460
AW		 1472 if (dev->i2c_bus[0].i2c_rc == 0) {
1473 if (eeprom[0x80] != 0x84)
1474 hauppauge_eeprom(dev, eeprom+0xc0);
1475 else
1476 hauppauge_eeprom(dev, eeprom+0x80);
1477 }
1478 break;
07b4a835 1479 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1480 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
66762373 1481 case CX23885_BOARD_HAUPPAUGE_HVR1400:
c88133ec
ST		 1482 if (dev->i2c_bus[0].i2c_rc == 0)
1483 hauppauge_eeprom(dev, eeprom+0x80);
1484 break;
d19770e5
ST		 1485 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1486 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1487 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1488 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2074dffa 1489 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1490 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1491 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1492 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1493 case CX23885_BOARD_HAUPPAUGE_HVR1210:
13697380 1494 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1495 case CX23885_BOARD_HAUPPAUGE_HVR1290:
d19770e5 1496 if (dev->i2c_bus[0].i2c_rc == 0)
c88133ec 1497 hauppauge_eeprom(dev, eeprom+0xc0);
d19770e5
ST		 1498 break;
1499 }
a6a3f140
ST		 1500
1501 switch (dev->board) {
335377b7 1502 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 1503 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
335377b7
MK		 1504 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1505 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1506 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1507 /* break omitted intentionally */
a6a3f140
ST		 1508 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1509 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1510 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1511 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1512 break;
35045137 1513 case CX23885_BOARD_HAUPPAUGE_HVR1850:
a589b665
ST		 1514 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1515 /* Defaults for VID B - Analog encoder */
1516 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1517 ts1->gen_ctrl_val = 0x10e;
1518 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1519 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1520
1521 /* APB_TSVALERR_POL (active low)*/
1522 ts1->vld_misc_val = 0x2000;
1523 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
35045137 1524 cx_write(0x130184, 0xc);
a589b665
ST		 1525
1526 /* Defaults for VID C */
1527 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1528 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1529 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
96318d0c
IL		 1530 break;
1531 case CX23885_BOARD_TBS_6920:
09ea33e5
IL		 1532 ts1->gen_ctrl_val = 0x4; /* Parallel */
1533 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1534 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1535 break;
1536 case CX23885_BOARD_TEVII_S470:
7b134e85 1537 case CX23885_BOARD_TEVII_S471:
c9b8b04b 1538 case CX23885_BOARD_DVBWORLD_2005:
96318d0c
IL		 1539 ts1->gen_ctrl_val = 0x5; /* Parallel */
1540 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1541 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
a589b665 1542 break;
5a23b076 1543 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
78db8547 1544 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
722c90eb 1545 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
5a23b076
IL		 1546 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1547 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1548 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1549 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1550 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1551 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1552 break;
493b7127 1553 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 1554 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
493b7127
DW		 1555 ts1->gen_ctrl_val = 0x5; /* Parallel */
1556 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1557 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1558 break;
ea5697fe
DW		 1559 case CX23885_BOARD_MYGICA_X8558PRO:
1560 ts1->gen_ctrl_val = 0x5; /* Parallel */
1561 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1562 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1563 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1564 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1565 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1566 break;
a6a3f140 1567 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 1568 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1569 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 1570 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1571 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1572 case CX23885_BOARD_HAUPPAUGE_HVR1700:
66762373 1573 case CX23885_BOARD_HAUPPAUGE_HVR1400:
4c56b04a 1574 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1575 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1576 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2074dffa 1577 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1578 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1579 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1580 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1581 case CX23885_BOARD_HAUPPAUGE_HVR1210:
34e383dd 1582 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
aee0b24c 1583 case CX23885_BOARD_HAUPPAUGE_HVR1290:
9028f58f 1584 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
a6a3f140
ST		 1585 default:
1586 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1587 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1588 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1589 }
1590
ce89cfb4
ST		 1591 /* Certain boards support analog, or require the avcore to be
1592 * loaded, ensure this happens.
1593 */
1594 switch (dev->board) {
fa647f24 1595 case CX23885_BOARD_TEVII_S470:
fa647f24
AW		 1596 /* Currently only enabled for the integrated IR controller */
1597 if (!enable_885_ir)
1598 break;
d214ddc8 1599 case CX23885_BOARD_HAUPPAUGE_HVR1250:
ce89cfb4
ST		 1600 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1601 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1602 case CX23885_BOARD_HAUPPAUGE_HVR1700:
4c56b04a 1603 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1604 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1605 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
5a23b076 1606 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
78db8547 1607 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
34e383dd 1608 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0ac60acb
DH		 1609 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1610 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
9b3d8ecc 1611 case CX23885_BOARD_HAUPPAUGE_HVR1270:
c6b7053b 1612 case CX23885_BOARD_HAUPPAUGE_HVR1850:
bc1548ad
DW		 1613 case CX23885_BOARD_MYGICA_X8506:
1614 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
aee0b24c 1615 case CX23885_BOARD_HAUPPAUGE_HVR1290:
0b32d65c 1616 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
9028f58f 1617 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
18d64476 1618 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2cb9ccd4 1619 case CX23885_BOARD_MPX885:
87988753 1620 case CX23885_BOARD_MYGICA_X8507:
722c90eb 1621 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
e6574f2f
HV		 1622 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1623 &dev->i2c_bus[2].i2c_adap,
9a1f8b34 1624 "cx25840", 0x88 >> 1, NULL);
d6b1850d
AW		 1625 if (dev->sd_cx25840) {
1626 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1627 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1628 }
ce89cfb4
ST		 1629 break;
1630 }
5a23b076
IL		 1631
1632 /* AUX-PLL 27MHz CLK */
1633 switch (dev->board) {
1634 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1635 netup_initialize(dev);
1636 break;
78db8547
IL		 1637 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1638 int ret;
1639 const struct firmware *fw;
1640 const char *filename = "dvb-netup-altera-01.fw";
1641 char *action = "configure";
b8f0d306 1642 static struct netup_card_info cinfo;
78db8547
IL		 1643 struct altera_config netup_config = {
1644 .dev = dev,
1645 .action = action,
1646 .jtag_io = netup_jtag_io,
1647 };
1648
1649 netup_initialize(dev);
1650
b8f0d306 1651 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
2d12421d
AO		 1652 if (netup_card_rev)
1653 cinfo.rev = netup_card_rev;
1654
b8f0d306
AO		 1655 switch (cinfo.rev) {
1656 case 0x4:
1657 filename = "dvb-netup-altera-04.fw";
1658 break;
1659 default:
1660 filename = "dvb-netup-altera-01.fw";
1661 break;
1662 }
1663 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1664 cinfo.rev, filename);
1665
78db8547
IL		 1666 ret = request_firmware(&fw, filename, &dev->pci->dev);
1667 if (ret != 0)
1668 printk(KERN_ERR "did not find the firmware file. (%s) "
1669 "Please see linux/Documentation/dvb/ for more details "
1670 "on firmware-problems.", filename);
1671 else
1672 altera_init(&netup_config, fw);
1673
3f84a4e1 1674 release_firmware(fw);
78db8547
IL		 1675 break;
1676 }
5a23b076 1677 }
d19770e5
ST		 1678}
1679
1680/* ------------------------------------------------------------------ */
Linux kernel - Deliverables
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