V4L/DVB (11768): cx23885: add ATSC/QAM tuning support for Hauppauge WinTV-HVR1270
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-cards.c
CommitLineData
d19770e5
ST
1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
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5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
7b888014 26#include <media/cx25840.h>
d19770e5
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27
28#include "cx23885.h"
90a71b1c 29#include "tuner-xc2028.h"
5a23b076 30#include "netup-init.h"
d19770e5
ST
31
32/* ------------------------------------------------------------------ */
33/* board config info */
34
35struct cx23885_board cx23885_boards[] = {
36 [CX23885_BOARD_UNKNOWN] = {
37 .name = "UNKNOWN/GENERIC",
c7712613
ST
38 /* Ensure safe default for unknown boards */
39 .clk_freq = 0,
d19770e5
ST
40 .input = {{
41 .type = CX23885_VMUX_COMPOSITE1,
42 .vmux = 0,
9c8ced51 43 }, {
d19770e5
ST
44 .type = CX23885_VMUX_COMPOSITE2,
45 .vmux = 1,
9c8ced51 46 }, {
d19770e5
ST
47 .type = CX23885_VMUX_COMPOSITE3,
48 .vmux = 2,
9c8ced51 49 }, {
d19770e5
ST
50 .type = CX23885_VMUX_COMPOSITE4,
51 .vmux = 3,
9c8ced51 52 } },
d19770e5
ST
53 },
54 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
55 .name = "Hauppauge WinTV-HVR1800lp",
d19770e5
ST
56 .portc = CX23885_MPEG_DVB,
57 .input = {{
58 .type = CX23885_VMUX_TELEVISION,
59 .vmux = 0,
60 .gpio0 = 0xff00,
9c8ced51 61 }, {
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ST
62 .type = CX23885_VMUX_DEBUG,
63 .vmux = 0,
64 .gpio0 = 0xff01,
9c8ced51 65 }, {
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ST
66 .type = CX23885_VMUX_COMPOSITE1,
67 .vmux = 1,
68 .gpio0 = 0xff02,
9c8ced51 69 }, {
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70 .type = CX23885_VMUX_SVIDEO,
71 .vmux = 2,
72 .gpio0 = 0xff02,
9c8ced51 73 } },
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ST
74 },
75 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
76 .name = "Hauppauge WinTV-HVR1800",
7b888014 77 .porta = CX23885_ANALOG_VIDEO,
a589b665 78 .portb = CX23885_MPEG_ENCODER,
d19770e5 79 .portc = CX23885_MPEG_DVB,
7b888014
ST
80 .tuner_type = TUNER_PHILIPS_TDA8290,
81 .tuner_addr = 0x42, /* 0x84 >> 1 */
d19770e5
ST
82 .input = {{
83 .type = CX23885_VMUX_TELEVISION,
7b888014
ST
84 .vmux = CX25840_VIN7_CH3 |
85 CX25840_VIN5_CH2 |
86 CX25840_VIN2_CH1,
87 .gpio0 = 0,
9c8ced51 88 }, {
d19770e5 89 .type = CX23885_VMUX_COMPOSITE1,
7b888014
ST
90 .vmux = CX25840_VIN7_CH3 |
91 CX25840_VIN4_CH2 |
92 CX25840_VIN6_CH1,
93 .gpio0 = 0,
9c8ced51 94 }, {
d19770e5 95 .type = CX23885_VMUX_SVIDEO,
7b888014
ST
96 .vmux = CX25840_VIN7_CH3 |
97 CX25840_VIN4_CH2 |
98 CX25840_VIN8_CH1 |
99 CX25840_SVIDEO_ON,
100 .gpio0 = 0,
9c8ced51 101 } },
d19770e5 102 },
a77743bc
ST
103 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
104 .name = "Hauppauge WinTV-HVR1250",
105 .portc = CX23885_MPEG_DVB,
106 .input = {{
107 .type = CX23885_VMUX_TELEVISION,
108 .vmux = 0,
109 .gpio0 = 0xff00,
9c8ced51 110 }, {
a77743bc
ST
111 .type = CX23885_VMUX_DEBUG,
112 .vmux = 0,
113 .gpio0 = 0xff01,
9c8ced51 114 }, {
a77743bc
ST
115 .type = CX23885_VMUX_COMPOSITE1,
116 .vmux = 1,
117 .gpio0 = 0xff02,
9c8ced51 118 }, {
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ST
119 .type = CX23885_VMUX_SVIDEO,
120 .vmux = 2,
121 .gpio0 = 0xff02,
9c8ced51 122 } },
a77743bc 123 },
9bc37caa
MK
124 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
125 .name = "DViCO FusionHDTV5 Express",
a6a3f140 126 .portb = CX23885_MPEG_DVB,
9bc37caa 127 },
d1987d55
ST
128 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
129 .name = "Hauppauge WinTV-HVR1500Q",
130 .portc = CX23885_MPEG_DVB,
131 },
07b4a835
MK
132 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
133 .name = "Hauppauge WinTV-HVR1500",
134 .portc = CX23885_MPEG_DVB,
135 },
b3ea0166
ST
136 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
137 .name = "Hauppauge WinTV-HVR1200",
138 .portc = CX23885_MPEG_DVB,
139 },
a780a31c
ST
140 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
141 .name = "Hauppauge WinTV-HVR1700",
142 .portc = CX23885_MPEG_DVB,
143 },
66762373
ST
144 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
145 .name = "Hauppauge WinTV-HVR1400",
146 .portc = CX23885_MPEG_DVB,
147 },
335377b7
MK
148 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
149 .name = "DViCO FusionHDTV7 Dual Express",
aaadeac8 150 .portb = CX23885_MPEG_DVB,
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MK
151 .portc = CX23885_MPEG_DVB,
152 },
aef2d186
ST
153 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
154 .name = "DViCO FusionHDTV DVB-T Dual Express",
155 .portb = CX23885_MPEG_DVB,
156 .portc = CX23885_MPEG_DVB,
157 },
4c56b04a
ST
158 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
159 .name = "Leadtek Winfast PxDVR3200 H",
160 .portc = CX23885_MPEG_DVB,
161 },
9bb1b7e8
IL
162 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
163 .name = "Compro VideoMate E650F",
164 .portc = CX23885_MPEG_DVB,
165 },
96318d0c
IL
166 [CX23885_BOARD_TBS_6920] = {
167 .name = "TurboSight TBS 6920",
168 .portb = CX23885_MPEG_DVB,
169 },
579943f5
IL
170 [CX23885_BOARD_TEVII_S470] = {
171 .name = "TeVii S470",
172 .portb = CX23885_MPEG_DVB,
173 },
c9b8b04b
IL
174 [CX23885_BOARD_DVBWORLD_2005] = {
175 .name = "DVBWorld DVB-S2 2005",
176 .portb = CX23885_MPEG_DVB,
177 },
5a23b076
IL
178 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
179 .cimax = 1,
180 .name = "NetUP Dual DVB-S2 CI",
181 .portb = CX23885_MPEG_DVB,
182 .portc = CX23885_MPEG_DVB,
183 },
2074dffa
ST
184 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
185 .name = "Hauppauge WinTV-HVR1270",
a5dbf457 186 .portc = CX23885_MPEG_DVB,
2074dffa 187 },
d19770e5
ST
188};
189const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
190
191/* ------------------------------------------------------------------ */
192/* PCI subsystem IDs */
193
194struct cx23885_subid cx23885_subids[] = {
195 {
196 .subvendor = 0x0070,
197 .subdevice = 0x3400,
198 .card = CX23885_BOARD_UNKNOWN,
9c8ced51 199 }, {
d19770e5
ST
200 .subvendor = 0x0070,
201 .subdevice = 0x7600,
202 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
9c8ced51 203 }, {
d19770e5
ST
204 .subvendor = 0x0070,
205 .subdevice = 0x7800,
206 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 207 }, {
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ST
208 .subvendor = 0x0070,
209 .subdevice = 0x7801,
210 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 211 }, {
6ccb8cfb
MK
212 .subvendor = 0x0070,
213 .subdevice = 0x7809,
214 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 215 }, {
a77743bc
ST
216 .subvendor = 0x0070,
217 .subdevice = 0x7911,
218 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
9c8ced51 219 }, {
9bc37caa
MK
220 .subvendor = 0x18ac,
221 .subdevice = 0xd500,
222 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
9c8ced51 223 }, {
b00fff0b
MK
224 .subvendor = 0x0070,
225 .subdevice = 0x7790,
226 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 227 }, {
d1987d55
ST
228 .subvendor = 0x0070,
229 .subdevice = 0x7797,
230 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 231 }, {
b00fff0b
MK
232 .subvendor = 0x0070,
233 .subdevice = 0x7710,
234 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
9c8ced51 235 }, {
07b4a835
MK
236 .subvendor = 0x0070,
237 .subdevice = 0x7717,
238 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
b3ea0166
ST
239 }, {
240 .subvendor = 0x0070,
241 .subdevice = 0x71d1,
242 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
3c3852cd
MK
243 }, {
244 .subvendor = 0x0070,
245 .subdevice = 0x71d3,
246 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
a780a31c
ST
247 }, {
248 .subvendor = 0x0070,
249 .subdevice = 0x8101,
250 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
66762373
ST
251 }, {
252 .subvendor = 0x0070,
253 .subdevice = 0x8010,
254 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
9c8ced51 255 }, {
335377b7
MK
256 .subvendor = 0x18ac,
257 .subdevice = 0xd618,
258 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
9c8ced51 259 }, {
aef2d186
ST
260 .subvendor = 0x18ac,
261 .subdevice = 0xdb78,
262 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
4c56b04a
ST
263 }, {
264 .subvendor = 0x107d,
265 .subdevice = 0x6681,
266 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
9bb1b7e8
IL
267 }, {
268 .subvendor = 0x185b,
269 .subdevice = 0xe800,
270 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
96318d0c
IL
271 }, {
272 .subvendor = 0x6920,
273 .subdevice = 0x8888,
274 .card = CX23885_BOARD_TBS_6920,
579943f5
IL
275 }, {
276 .subvendor = 0xd470,
277 .subdevice = 0x9022,
278 .card = CX23885_BOARD_TEVII_S470,
c9b8b04b
IL
279 }, {
280 .subvendor = 0x0001,
281 .subdevice = 0x2005,
282 .card = CX23885_BOARD_DVBWORLD_2005,
5a23b076
IL
283 }, {
284 .subvendor = 0x1b55,
285 .subdevice = 0x2a2c,
286 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
2074dffa
ST
287 }, {
288 .subvendor = 0x0070,
289 .subdevice = 0x2211,
290 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
d19770e5
ST
291 },
292};
293const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
294
295void cx23885_card_list(struct cx23885_dev *dev)
296{
297 int i;
298
299 if (0 == dev->pci->subsystem_vendor &&
300 0 == dev->pci->subsystem_device) {
9c8ced51
ST
301 printk(KERN_INFO
302 "%s: Board has no valid PCIe Subsystem ID and can't\n"
303 "%s: be autodetected. Pass card=<n> insmod option\n"
304 "%s: to workaround that. Redirect complaints to the\n"
305 "%s: vendor of the TV card. Best regards,\n"
d19770e5
ST
306 "%s: -- tux\n",
307 dev->name, dev->name, dev->name, dev->name, dev->name);
308 } else {
9c8ced51
ST
309 printk(KERN_INFO
310 "%s: Your board isn't known (yet) to the driver.\n"
311 "%s: Try to pick one of the existing card configs via\n"
d19770e5
ST
312 "%s: card=<n> insmod option. Updating to the latest\n"
313 "%s: version might help as well.\n",
314 dev->name, dev->name, dev->name, dev->name);
315 }
9c8ced51 316 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
d19770e5
ST
317 dev->name);
318 for (i = 0; i < cx23885_bcount; i++)
9c8ced51 319 printk(KERN_INFO "%s: card=%d -> %s\n",
d19770e5
ST
320 dev->name, i, cx23885_boards[i].name);
321}
322
323static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
324{
325 struct tveeprom tv;
326
9c8ced51
ST
327 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
328 eeprom_data);
d19770e5 329
d19770e5 330 /* Make sure we support the board model */
9c8ced51 331 switch (tv.model) {
36396c89
MK
332 case 71009:
333 /* WinTV-HVR1200 (PCIe, Retail, full height)
334 * DVB-T and basic analog */
335 case 71359:
336 /* WinTV-HVR1200 (PCIe, OEM, half height)
337 * DVB-T and basic analog */
338 case 71439:
339 /* WinTV-HVR1200 (PCIe, OEM, half height)
340 * DVB-T and basic analog */
341 case 71449:
342 /* WinTV-HVR1200 (PCIe, OEM, full height)
343 * DVB-T and basic analog */
344 case 71939:
345 /* WinTV-HVR1200 (PCIe, OEM, half height)
346 * DVB-T and basic analog */
347 case 71949:
348 /* WinTV-HVR1200 (PCIe, OEM, full height)
349 * DVB-T and basic analog */
350 case 71959:
351 /* WinTV-HVR1200 (PCIe, OEM, full height)
352 * DVB-T and basic analog */
353 case 71979:
354 /* WinTV-HVR1200 (PCIe, OEM, half height)
355 * DVB-T and basic analog */
356 case 71999:
357 /* WinTV-HVR1200 (PCIe, OEM, full height)
358 * DVB-T and basic analog */
9c8ced51
ST
359 case 76601:
360 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
361 channel ATSC and MPEG2 HW Encoder */
362 case 77001:
363 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
364 and Basic analog */
365 case 77011:
366 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
367 and Basic analog */
368 case 77041:
369 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
370 and Basic analog */
371 case 77051:
372 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
373 and Basic analog */
374 case 78011:
375 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
376 Dual channel ATSC and MPEG2 HW Encoder */
377 case 78501:
378 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
379 Dual channel ATSC and MPEG2 HW Encoder */
380 case 78521:
381 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
382 Dual channel ATSC and MPEG2 HW Encoder */
383 case 78531:
384 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
385 Dual channel ATSC and MPEG2 HW Encoder */
386 case 78631:
387 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
388 Dual channel ATSC and MPEG2 HW Encoder */
389 case 79001:
390 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
391 ATSC and Basic analog */
392 case 79101:
393 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
394 ATSC and Basic analog */
395 case 79561:
396 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
397 ATSC and Basic analog */
398 case 79571:
399 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
400 ATSC and Basic analog */
401 case 79671:
402 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
403 ATSC and Basic analog */
66762373
ST
404 case 80019:
405 /* WinTV-HVR1400 (Express Card, Retail, IR,
406 * DVB-T and Basic analog */
36396c89
MK
407 case 81509:
408 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
409 * DVB-T and MPEG2 HW Encoder */
a780a31c 410 case 81519:
36396c89 411 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
a780a31c 412 * DVB-T and MPEG2 HW Encoder */
d19770e5
ST
413 break;
414 default:
9c8ced51
ST
415 printk(KERN_WARNING "%s: warning: unknown hauppauge model #%d\n",
416 dev->name, tv.model);
d19770e5
ST
417 break;
418 }
419
420 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
421 dev->name, tv.model);
422}
423
d7cba043 424int cx23885_tuner_callback(void *priv, int component, int command, int arg)
8c70017f 425{
89ce2216
ST
426 struct cx23885_tsport *port = priv;
427 struct cx23885_dev *dev = port->dev;
6df51690
ST
428 u32 bitmask = 0;
429
89ce2216
ST
430 if (command == XC2028_RESET_CLK)
431 return 0;
432
6df51690
ST
433 if (command != 0) {
434 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
435 __func__, command);
436 return -EINVAL;
437 }
8c70017f 438
9c8ced51 439 switch (dev->board) {
90a71b1c
ST
440 case CX23885_BOARD_HAUPPAUGE_HVR1400:
441 case CX23885_BOARD_HAUPPAUGE_HVR1500:
8c70017f 442 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
4c56b04a 443 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 444 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
90a71b1c 445 /* Tuner Reset Command */
4c56b04a 446 bitmask = 0x04;
6df51690
ST
447 break;
448 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 449 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
4c56b04a
ST
450 /* Two identical tuners on two different i2c buses,
451 * we need to reset the correct gpio. */
d4dc673d 452 if (port->nr == 1)
4c56b04a 453 bitmask = 0x01;
d4dc673d 454 else if (port->nr == 2)
4c56b04a 455 bitmask = 0x04;
8c70017f
ST
456 break;
457 }
458
6df51690
ST
459 if (bitmask) {
460 /* Drive the tuner into reset and back out */
461 cx_clear(GP0_IO, bitmask);
462 mdelay(200);
463 cx_set(GP0_IO, bitmask);
464 }
465
466 return 0;
8c70017f 467}
73c993a8 468
a6a3f140
ST
469void cx23885_gpio_setup(struct cx23885_dev *dev)
470{
9c8ced51 471 switch (dev->board) {
a6a3f140
ST
472 case CX23885_BOARD_HAUPPAUGE_HVR1250:
473 /* GPIO-0 cx24227 demodulator reset */
474 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
475 break;
07b4a835
MK
476 case CX23885_BOARD_HAUPPAUGE_HVR1500:
477 /* GPIO-0 cx24227 demodulator */
478 /* GPIO-2 xc3028 tuner */
479
480 /* Put the parts into reset */
481 cx_set(GP0_IO, 0x00050000);
482 cx_clear(GP0_IO, 0x00000005);
483 msleep(5);
484
485 /* Bring the parts out of reset */
486 cx_set(GP0_IO, 0x00050005);
487 break;
d1987d55
ST
488 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
489 /* GPIO-0 cx24227 demodulator reset */
490 /* GPIO-2 xc5000 tuner reset */
491 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
492 break;
a6a3f140
ST
493 case CX23885_BOARD_HAUPPAUGE_HVR1800:
494 /* GPIO-0 656_CLK */
495 /* GPIO-1 656_D0 */
496 /* GPIO-2 8295A Reset */
497 /* GPIO-3-10 cx23417 data0-7 */
498 /* GPIO-11-14 cx23417 addr0-3 */
499 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
500 /* GPIO-19 IR_RX */
3ba71d21 501
a589b665
ST
502 /* CX23417 GPIO's */
503 /* EIO15 Zilog Reset */
504 /* EIO14 S5H1409/CX24227 Reset */
505
5206d6ec
ST
506 /* Force the TDA8295A into reset and back */
507 cx_set(GP0_IO, 0x00040004);
508 mdelay(20);
509 cx_clear(GP0_IO, 0x00000004);
510 mdelay(20);
511 cx_set(GP0_IO, 0x00040004);
512 mdelay(20);
a6a3f140 513 break;
b3ea0166
ST
514 case CX23885_BOARD_HAUPPAUGE_HVR1200:
515 /* GPIO-0 tda10048 demodulator reset */
516 /* GPIO-2 tda18271 tuner reset */
517
a780a31c
ST
518 /* Put the parts into reset and back */
519 cx_set(GP0_IO, 0x00050000);
520 mdelay(20);
521 cx_clear(GP0_IO, 0x00000005);
522 mdelay(20);
523 cx_set(GP0_IO, 0x00050005);
524 break;
525 case CX23885_BOARD_HAUPPAUGE_HVR1700:
526 /* GPIO-0 TDA10048 demodulator reset */
527 /* GPIO-2 TDA8295A Reset */
528 /* GPIO-3-10 cx23417 data0-7 */
529 /* GPIO-11-14 cx23417 addr0-3 */
530 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
531
532 /* The following GPIO's are on the interna AVCore (cx25840) */
533 /* GPIO-19 IR_RX */
534 /* GPIO-20 IR_TX 416/DVBT Select */
535 /* GPIO-21 IIS DAT */
536 /* GPIO-22 IIS WCLK */
537 /* GPIO-23 IIS BCLK */
538
66762373
ST
539 /* Put the parts into reset and back */
540 cx_set(GP0_IO, 0x00050000);
541 mdelay(20);
542 cx_clear(GP0_IO, 0x00000005);
543 mdelay(20);
544 cx_set(GP0_IO, 0x00050005);
545 break;
546 case CX23885_BOARD_HAUPPAUGE_HVR1400:
547 /* GPIO-0 Dibcom7000p demodulator reset */
548 /* GPIO-2 xc3028L tuner reset */
549 /* GPIO-13 LED */
550
b3ea0166
ST
551 /* Put the parts into reset and back */
552 cx_set(GP0_IO, 0x00050000);
553 mdelay(20);
554 cx_clear(GP0_IO, 0x00000005);
555 mdelay(20);
556 cx_set(GP0_IO, 0x00050005);
557 break;
1ecc5aed
ST
558 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
559 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
560 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
561 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
562 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
563
aef2d186
ST
564 /* Put the parts into reset and back */
565 cx_set(GP0_IO, 0x000f0000);
566 mdelay(20);
567 cx_clear(GP0_IO, 0x0000000f);
568 mdelay(20);
569 cx_set(GP0_IO, 0x000f000f);
570 break;
571 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
572 /* GPIO-0 portb xc3028 reset */
573 /* GPIO-1 portb zl10353 reset */
574 /* GPIO-2 portc xc3028 reset */
575 /* GPIO-3 portc zl10353 reset */
576
1ecc5aed
ST
577 /* Put the parts into reset and back */
578 cx_set(GP0_IO, 0x000f0000);
579 mdelay(20);
580 cx_clear(GP0_IO, 0x0000000f);
581 mdelay(20);
582 cx_set(GP0_IO, 0x000f000f);
583 break;
4c56b04a 584 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 585 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
4c56b04a
ST
586 /* GPIO-2 xc3028 tuner reset */
587
588 /* The following GPIO's are on the internal AVCore (cx25840) */
589 /* GPIO-? zl10353 demod reset */
590
591 /* Put the parts into reset and back */
592 cx_set(GP0_IO, 0x00040000);
593 mdelay(20);
594 cx_clear(GP0_IO, 0x00000004);
595 mdelay(20);
596 cx_set(GP0_IO, 0x00040004);
597 break;
96318d0c 598 case CX23885_BOARD_TBS_6920:
579943f5 599 case CX23885_BOARD_TEVII_S470:
96318d0c
IL
600 cx_write(MC417_CTL, 0x00000036);
601 cx_write(MC417_OEN, 0x00001000);
602 cx_write(MC417_RWD, 0x00001800);
603 break;
5a23b076
IL
604 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
605 /* GPIO-0 INTA from CiMax1
606 GPIO-1 INTB from CiMax2
607 GPIO-2 reset chips
608 GPIO-3 to GPIO-10 data/addr for CA
609 GPIO-11 ~CS0 to CiMax1
610 GPIO-12 ~CS1 to CiMax2
611 GPIO-13 ADL0 load LSB addr
612 GPIO-14 ADL1 load MSB addr
613 GPIO-15 ~RDY from CiMax
614 GPIO-17 ~RD to CiMax
615 GPIO-18 ~WR to CiMax
616 */
617 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
618 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
619 cx_clear(GP0_IO, 0x00030004);
620 mdelay(100);/* reset delay */
621 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
622 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
623 /* GPIO-15 IN as ~ACK, rest as OUT */
624 cx_write(MC417_OEN, 0x00001000);
625 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
626 cx_write(MC417_RWD, 0x0000c300);
627 /* enable irq */
628 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
629 break;
2074dffa
ST
630 case CX23885_BOARD_HAUPPAUGE_HVR1270:
631 /* GPIO-6 I2C Gate which can isolate the 3305 from the bus */
632 /* GPIO-9 LG3305 reset */
633
634 /* Put the parts into reset and back */
635 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6, 1);
636 cx23885_gpio_set(dev, GPIO_9 | GPIO_6);
637 cx23885_gpio_clear(dev, GPIO_9);
638 mdelay(20);
639 cx23885_gpio_set(dev, GPIO_9);
640 break;
a6a3f140
ST
641 }
642}
643
644int cx23885_ir_init(struct cx23885_dev *dev)
645{
646 switch (dev->board) {
647 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 648 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 649 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 650 case CX23885_BOARD_HAUPPAUGE_HVR1800:
b3ea0166 651 case CX23885_BOARD_HAUPPAUGE_HVR1200:
66762373 652 case CX23885_BOARD_HAUPPAUGE_HVR1400:
2074dffa 653 case CX23885_BOARD_HAUPPAUGE_HVR1270:
a6a3f140
ST
654 /* FIXME: Implement me */
655 break;
12886871
ST
656 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
657 request_module("ir-kbd-i2c");
658 break;
a6a3f140
ST
659 }
660
661 return 0;
662}
663
d19770e5
ST
664void cx23885_card_setup(struct cx23885_dev *dev)
665{
a6a3f140
ST
666 struct cx23885_tsport *ts1 = &dev->ts1;
667 struct cx23885_tsport *ts2 = &dev->ts2;
668
d19770e5
ST
669 static u8 eeprom[256];
670
671 if (dev->i2c_bus[0].i2c_rc == 0) {
672 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
44a6481d
MK
673 tveeprom_read(&dev->i2c_bus[0].i2c_client,
674 eeprom, sizeof(eeprom));
d19770e5
ST
675 }
676
677 switch (dev->board) {
a77743bc 678 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 679 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 680 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
66762373 681 case CX23885_BOARD_HAUPPAUGE_HVR1400:
c88133ec
ST
682 if (dev->i2c_bus[0].i2c_rc == 0)
683 hauppauge_eeprom(dev, eeprom+0x80);
684 break;
d19770e5
ST
685 case CX23885_BOARD_HAUPPAUGE_HVR1800:
686 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 687 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 688 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2074dffa 689 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d19770e5 690 if (dev->i2c_bus[0].i2c_rc == 0)
c88133ec 691 hauppauge_eeprom(dev, eeprom+0xc0);
d19770e5
ST
692 break;
693 }
a6a3f140
ST
694
695 switch (dev->board) {
335377b7 696 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 697 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
335377b7
MK
698 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
699 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
700 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
701 /* break omitted intentionally */
a6a3f140
ST
702 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
703 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
704 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
705 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
706 break;
a589b665
ST
707 case CX23885_BOARD_HAUPPAUGE_HVR1800:
708 /* Defaults for VID B - Analog encoder */
709 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
710 ts1->gen_ctrl_val = 0x10e;
711 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
712 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
713
714 /* APB_TSVALERR_POL (active low)*/
715 ts1->vld_misc_val = 0x2000;
716 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
717
718 /* Defaults for VID C */
719 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
720 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
721 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
96318d0c 722 break;
579943f5 723 case CX23885_BOARD_TEVII_S470:
96318d0c 724 case CX23885_BOARD_TBS_6920:
c9b8b04b 725 case CX23885_BOARD_DVBWORLD_2005:
96318d0c
IL
726 ts1->gen_ctrl_val = 0x5; /* Parallel */
727 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
728 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
a589b665 729 break;
5a23b076
IL
730 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
731 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
732 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
733 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
734 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
735 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
736 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
737 break;
a6a3f140 738 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 739 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 740 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 741 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 742 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 743 case CX23885_BOARD_HAUPPAUGE_HVR1700:
66762373 744 case CX23885_BOARD_HAUPPAUGE_HVR1400:
4c56b04a 745 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 746 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2074dffa 747 case CX23885_BOARD_HAUPPAUGE_HVR1270:
a6a3f140
ST
748 default:
749 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
750 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
751 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
752 }
753
ce89cfb4
ST
754 /* Certain boards support analog, or require the avcore to be
755 * loaded, ensure this happens.
756 */
757 switch (dev->board) {
758 case CX23885_BOARD_HAUPPAUGE_HVR1800:
759 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
760 case CX23885_BOARD_HAUPPAUGE_HVR1700:
4c56b04a 761 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 762 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
5a23b076 763 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
e6574f2f
HV
764 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
765 &dev->i2c_bus[2].i2c_adap,
0d5a19f1 766 "cx25840", "cx25840", 0x88 >> 1);
cc26b076 767 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
ce89cfb4
ST
768 break;
769 }
5a23b076
IL
770
771 /* AUX-PLL 27MHz CLK */
772 switch (dev->board) {
773 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
774 netup_initialize(dev);
775 break;
776 }
d19770e5
ST
777}
778
779/* ------------------------------------------------------------------ */
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