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V4L/DVB: cx23885: Add a v4l2_subdev group id for the CX2388[578] integrated AV core
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-cards.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
7b888014 26#include <media/cx25840.h>
d19770e5
ST		 27
28#include "cx23885.h"
90a71b1c 29#include "tuner-xc2028.h"
5a23b076 30#include "netup-init.h"
29f8a0a5 31#include "cx23888-ir.h"
d19770e5
ST		 32
33/* ------------------------------------------------------------------ */
34/* board config info */
35
36struct cx23885_board cx23885_boards[] = {
37 [CX23885_BOARD_UNKNOWN] = {
38 .name = "UNKNOWN/GENERIC",
c7712613
ST		 39 /* Ensure safe default for unknown boards */
40 .clk_freq = 0,
d19770e5
ST		 41 .input = {{
42 .type = CX23885_VMUX_COMPOSITE1,
43 .vmux = 0,
9c8ced51 44 }, {
d19770e5
ST		 45 .type = CX23885_VMUX_COMPOSITE2,
46 .vmux = 1,
9c8ced51 47 }, {
d19770e5
ST		 48 .type = CX23885_VMUX_COMPOSITE3,
49 .vmux = 2,
9c8ced51 50 }, {
d19770e5
ST		 51 .type = CX23885_VMUX_COMPOSITE4,
52 .vmux = 3,
9c8ced51 53 } },
d19770e5
ST		 54 },
55 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
56 .name = "Hauppauge WinTV-HVR1800lp",
d19770e5
ST		 57 .portc = CX23885_MPEG_DVB,
58 .input = {{
59 .type = CX23885_VMUX_TELEVISION,
60 .vmux = 0,
61 .gpio0 = 0xff00,
9c8ced51 62 }, {
d19770e5
ST		 63 .type = CX23885_VMUX_DEBUG,
64 .vmux = 0,
65 .gpio0 = 0xff01,
9c8ced51 66 }, {
d19770e5
ST		 67 .type = CX23885_VMUX_COMPOSITE1,
68 .vmux = 1,
69 .gpio0 = 0xff02,
9c8ced51 70 }, {
d19770e5
ST		 71 .type = CX23885_VMUX_SVIDEO,
72 .vmux = 2,
73 .gpio0 = 0xff02,
9c8ced51 74 } },
d19770e5
ST		 75 },
76 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
77 .name = "Hauppauge WinTV-HVR1800",
7b888014 78 .porta = CX23885_ANALOG_VIDEO,
a589b665 79 .portb = CX23885_MPEG_ENCODER,
d19770e5 80 .portc = CX23885_MPEG_DVB,
7b888014
ST		 81 .tuner_type = TUNER_PHILIPS_TDA8290,
82 .tuner_addr = 0x42, /* 0x84 >> 1 */
d19770e5
ST		 83 .input = {{
84 .type = CX23885_VMUX_TELEVISION,
7b888014
ST		 85 .vmux = CX25840_VIN7_CH3 |
86 CX25840_VIN5_CH2 |
87 CX25840_VIN2_CH1,
88 .gpio0 = 0,
9c8ced51 89 }, {
d19770e5 90 .type = CX23885_VMUX_COMPOSITE1,
7b888014
ST		 91 .vmux = CX25840_VIN7_CH3 |
92 CX25840_VIN4_CH2 |
93 CX25840_VIN6_CH1,
94 .gpio0 = 0,
9c8ced51 95 }, {
d19770e5 96 .type = CX23885_VMUX_SVIDEO,
7b888014
ST		 97 .vmux = CX25840_VIN7_CH3 |
98 CX25840_VIN4_CH2 |
99 CX25840_VIN8_CH1 |
100 CX25840_SVIDEO_ON,
101 .gpio0 = 0,
9c8ced51 102 } },
d19770e5 103 },
a77743bc
ST		 104 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
105 .name = "Hauppauge WinTV-HVR1250",
106 .portc = CX23885_MPEG_DVB,
107 .input = {{
108 .type = CX23885_VMUX_TELEVISION,
109 .vmux = 0,
110 .gpio0 = 0xff00,
9c8ced51 111 }, {
a77743bc
ST		 112 .type = CX23885_VMUX_DEBUG,
113 .vmux = 0,
114 .gpio0 = 0xff01,
9c8ced51 115 }, {
a77743bc
ST		 116 .type = CX23885_VMUX_COMPOSITE1,
117 .vmux = 1,
118 .gpio0 = 0xff02,
9c8ced51 119 }, {
a77743bc
ST		 120 .type = CX23885_VMUX_SVIDEO,
121 .vmux = 2,
122 .gpio0 = 0xff02,
9c8ced51 123 } },
a77743bc 124 },
9bc37caa
MK		 125 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
126 .name = "DViCO FusionHDTV5 Express",
a6a3f140 127 .portb = CX23885_MPEG_DVB,
9bc37caa 128 },
d1987d55
ST		 129 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
130 .name = "Hauppauge WinTV-HVR1500Q",
131 .portc = CX23885_MPEG_DVB,
132 },
07b4a835
MK		 133 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
134 .name = "Hauppauge WinTV-HVR1500",
135 .portc = CX23885_MPEG_DVB,
136 },
b3ea0166
ST		 137 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
138 .name = "Hauppauge WinTV-HVR1200",
139 .portc = CX23885_MPEG_DVB,
140 },
a780a31c
ST		 141 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
142 .name = "Hauppauge WinTV-HVR1700",
143 .portc = CX23885_MPEG_DVB,
144 },
66762373
ST		 145 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
146 .name = "Hauppauge WinTV-HVR1400",
147 .portc = CX23885_MPEG_DVB,
148 },
335377b7
MK		 149 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
150 .name = "DViCO FusionHDTV7 Dual Express",
aaadeac8 151 .portb = CX23885_MPEG_DVB,
335377b7
MK		 152 .portc = CX23885_MPEG_DVB,
153 },
aef2d186
ST		 154 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
155 .name = "DViCO FusionHDTV DVB-T Dual Express",
156 .portb = CX23885_MPEG_DVB,
157 .portc = CX23885_MPEG_DVB,
158 },
4c56b04a
ST		 159 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
160 .name = "Leadtek Winfast PxDVR3200 H",
161 .portc = CX23885_MPEG_DVB,
162 },
9bb1b7e8
IL		 163 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
164 .name = "Compro VideoMate E650F",
165 .portc = CX23885_MPEG_DVB,
166 },
96318d0c
IL		 167 [CX23885_BOARD_TBS_6920] = {
168 .name = "TurboSight TBS 6920",
169 .portb = CX23885_MPEG_DVB,
170 },
579943f5
IL		 171 [CX23885_BOARD_TEVII_S470] = {
172 .name = "TeVii S470",
173 .portb = CX23885_MPEG_DVB,
174 },
c9b8b04b
IL		 175 [CX23885_BOARD_DVBWORLD_2005] = {
176 .name = "DVBWorld DVB-S2 2005",
177 .portb = CX23885_MPEG_DVB,
178 },
5a23b076
IL		 179 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
180 .cimax = 1,
181 .name = "NetUP Dual DVB-S2 CI",
182 .portb = CX23885_MPEG_DVB,
183 .portc = CX23885_MPEG_DVB,
184 },
2074dffa
ST		 185 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
186 .name = "Hauppauge WinTV-HVR1270",
a5dbf457 187 .portc = CX23885_MPEG_DVB,
2074dffa 188 },
d099becb
MK		 189 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
190 .name = "Hauppauge WinTV-HVR1275",
191 .portc = CX23885_MPEG_DVB,
192 },
19bc5796
MK		 193 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
194 .name = "Hauppauge WinTV-HVR1255",
195 .portc = CX23885_MPEG_DVB,
196 },
6b926eca
MK		 197 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
198 .name = "Hauppauge WinTV-HVR1210",
199 .portc = CX23885_MPEG_DVB,
200 },
493b7127
DW		 201 [CX23885_BOARD_MYGICA_X8506] = {
202 .name = "Mygica X8506 DMB-TH",
6f0d8c02
DW		 203 .tuner_type = TUNER_XC5000,
204 .tuner_addr = 0x61,
bc1548ad 205 .porta = CX23885_ANALOG_VIDEO,
493b7127 206 .portb = CX23885_MPEG_DVB,
bc1548ad 207 .input = {
6f0d8c02
DW		 208 {
209 .type = CX23885_VMUX_TELEVISION,
210 .vmux = CX25840_COMPOSITE2,
211 },
bc1548ad
DW		 212 {
213 .type = CX23885_VMUX_COMPOSITE1,
214 .vmux = CX25840_COMPOSITE8,
215 },
216 {
217 .type = CX23885_VMUX_SVIDEO,
218 .vmux = CX25840_SVIDEO_LUMA3 |
219 CX25840_SVIDEO_CHROMA4,
220 },
221 {
222 .type = CX23885_VMUX_COMPONENT,
223 .vmux = CX25840_COMPONENT_ON |
224 CX25840_VIN1_CH1 |
225 CX25840_VIN6_CH2 |
226 CX25840_VIN7_CH3,
227 },
228 },
493b7127 229 },
2365b2d3
DW		 230 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
231 .name = "Magic-Pro ProHDTV Extreme 2",
6f0d8c02
DW		 232 .tuner_type = TUNER_XC5000,
233 .tuner_addr = 0x61,
bc1548ad 234 .porta = CX23885_ANALOG_VIDEO,
2365b2d3 235 .portb = CX23885_MPEG_DVB,
bc1548ad 236 .input = {
6f0d8c02
DW		 237 {
238 .type = CX23885_VMUX_TELEVISION,
239 .vmux = CX25840_COMPOSITE2,
240 },
bc1548ad
DW		 241 {
242 .type = CX23885_VMUX_COMPOSITE1,
243 .vmux = CX25840_COMPOSITE8,
244 },
245 {
246 .type = CX23885_VMUX_SVIDEO,
247 .vmux = CX25840_SVIDEO_LUMA3 |
248 CX25840_SVIDEO_CHROMA4,
249 },
250 {
251 .type = CX23885_VMUX_COMPONENT,
252 .vmux = CX25840_COMPONENT_ON |
253 CX25840_VIN1_CH1 |
254 CX25840_VIN6_CH2 |
255 CX25840_VIN7_CH3,
256 },
257 },
2365b2d3 258 },
13697380
ST		 259 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
260 .name = "Hauppauge WinTV-HVR1850",
261 .portb = CX23885_MPEG_ENCODER,
262 .portc = CX23885_MPEG_DVB,
263 },
34e383dd
VG		 264 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
265 .name = "Compro VideoMate E800",
266 .portc = CX23885_MPEG_DVB,
267 },
aee0b24c
MK		 268 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
269 .name = "Hauppauge WinTV-HVR1290",
270 .portc = CX23885_MPEG_DVB,
271 },
ea5697fe
DW		 272 [CX23885_BOARD_MYGICA_X8558PRO] = {
273 .name = "Mygica X8558 PRO DMB-TH",
274 .portb = CX23885_MPEG_DVB,
275 .portc = CX23885_MPEG_DVB,
276 },
0b32d65c
KK		 277 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
278 .name = "LEADTEK WinFast PxTV1200",
279 .porta = CX23885_ANALOG_VIDEO,
280 .tuner_type = TUNER_XC2028,
281 .tuner_addr = 0x61,
282 .input = {{
283 .type = CX23885_VMUX_TELEVISION,
284 .vmux = CX25840_VIN2_CH1 |
285 CX25840_VIN5_CH2 |
286 CX25840_NONE0_CH3,
287 }, {
288 .type = CX23885_VMUX_COMPOSITE1,
289 .vmux = CX25840_COMPOSITE1,
290 }, {
291 .type = CX23885_VMUX_SVIDEO,
292 .vmux = CX25840_SVIDEO_LUMA3 |
293 CX25840_SVIDEO_CHROMA4,
294 }, {
295 .type = CX23885_VMUX_COMPONENT,
296 .vmux = CX25840_VIN7_CH1 |
297 CX25840_VIN6_CH2 |
298 CX25840_VIN8_CH3 |
299 CX25840_COMPONENT_ON,
300 } },
301 },
d19770e5
ST		 302};
303const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
304
305/* ------------------------------------------------------------------ */
306/* PCI subsystem IDs */
307
308struct cx23885_subid cx23885_subids[] = {
309 {
310 .subvendor = 0x0070,
311 .subdevice = 0x3400,
312 .card = CX23885_BOARD_UNKNOWN,
9c8ced51 313 }, {
d19770e5
ST		 314 .subvendor = 0x0070,
315 .subdevice = 0x7600,
316 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
9c8ced51 317 }, {
d19770e5
ST		 318 .subvendor = 0x0070,
319 .subdevice = 0x7800,
320 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 321 }, {
d19770e5
ST		 322 .subvendor = 0x0070,
323 .subdevice = 0x7801,
324 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 325 }, {
6ccb8cfb
MK		 326 .subvendor = 0x0070,
327 .subdevice = 0x7809,
328 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 329 }, {
a77743bc
ST		 330 .subvendor = 0x0070,
331 .subdevice = 0x7911,
332 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
9c8ced51 333 }, {
9bc37caa
MK		 334 .subvendor = 0x18ac,
335 .subdevice = 0xd500,
336 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
9c8ced51 337 }, {
b00fff0b
MK		 338 .subvendor = 0x0070,
339 .subdevice = 0x7790,
340 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 341 }, {
d1987d55
ST		 342 .subvendor = 0x0070,
343 .subdevice = 0x7797,
344 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 345 }, {
b00fff0b
MK		 346 .subvendor = 0x0070,
347 .subdevice = 0x7710,
348 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
9c8ced51 349 }, {
07b4a835
MK		 350 .subvendor = 0x0070,
351 .subdevice = 0x7717,
352 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
b3ea0166
ST		 353 }, {
354 .subvendor = 0x0070,
355 .subdevice = 0x71d1,
356 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
3c3852cd
MK		 357 }, {
358 .subvendor = 0x0070,
359 .subdevice = 0x71d3,
360 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
a780a31c
ST		 361 }, {
362 .subvendor = 0x0070,
363 .subdevice = 0x8101,
364 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
66762373
ST		 365 }, {
366 .subvendor = 0x0070,
367 .subdevice = 0x8010,
368 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
9c8ced51 369 }, {
335377b7
MK		 370 .subvendor = 0x18ac,
371 .subdevice = 0xd618,
372 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
9c8ced51 373 }, {
aef2d186
ST		 374 .subvendor = 0x18ac,
375 .subdevice = 0xdb78,
376 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
4c56b04a
ST		 377 }, {
378 .subvendor = 0x107d,
379 .subdevice = 0x6681,
380 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
9bb1b7e8
IL		 381 }, {
382 .subvendor = 0x185b,
383 .subdevice = 0xe800,
384 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
96318d0c
IL		 385 }, {
386 .subvendor = 0x6920,
387 .subdevice = 0x8888,
388 .card = CX23885_BOARD_TBS_6920,
579943f5
IL		 389 }, {
390 .subvendor = 0xd470,
391 .subdevice = 0x9022,
392 .card = CX23885_BOARD_TEVII_S470,
c9b8b04b
IL		 393 }, {
394 .subvendor = 0x0001,
395 .subdevice = 0x2005,
396 .card = CX23885_BOARD_DVBWORLD_2005,
5a23b076
IL		 397 }, {
398 .subvendor = 0x1b55,
399 .subdevice = 0x2a2c,
400 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
2074dffa
ST		 401 }, {
402 .subvendor = 0x0070,
403 .subdevice = 0x2211,
404 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
d099becb
MK		 405 }, {
406 .subvendor = 0x0070,
407 .subdevice = 0x2215,
408 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
7d7b5284
MK		 409 }, {
410 .subvendor = 0x0070,
411 .subdevice = 0x221d,
412 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
19bc5796
MK		 413 }, {
414 .subvendor = 0x0070,
415 .subdevice = 0x2251,
416 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
7d7b5284
MK		 417 }, {
418 .subvendor = 0x0070,
419 .subdevice = 0x2259,
420 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
6b926eca
MK		 421 }, {
422 .subvendor = 0x0070,
423 .subdevice = 0x2291,
424 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
425 }, {
426 .subvendor = 0x0070,
427 .subdevice = 0x2295,
428 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
7d7b5284
MK		 429 }, {
430 .subvendor = 0x0070,
431 .subdevice = 0x2299,
432 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
433 }, {
434 .subvendor = 0x0070,
435 .subdevice = 0x229d,
436 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
437 }, {
438 .subvendor = 0x0070,
439 .subdevice = 0x22f0,
440 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
441 }, {
442 .subvendor = 0x0070,
443 .subdevice = 0x22f1,
444 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
445 }, {
446 .subvendor = 0x0070,
447 .subdevice = 0x22f2,
448 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
449 }, {
450 .subvendor = 0x0070,
451 .subdevice = 0x22f3,
452 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
453 }, {
454 .subvendor = 0x0070,
455 .subdevice = 0x22f4,
456 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
457 }, {
458 .subvendor = 0x0070,
459 .subdevice = 0x22f5,
460 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
493b7127
DW		 461 }, {
462 .subvendor = 0x14f1,
463 .subdevice = 0x8651,
464 .card = CX23885_BOARD_MYGICA_X8506,
2365b2d3
DW		 465 }, {
466 .subvendor = 0x14f1,
467 .subdevice = 0x8657,
468 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
13697380
ST		 469 }, {
470 .subvendor = 0x0070,
471 .subdevice = 0x8541,
472 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
34e383dd
VG		 473 }, {
474 .subvendor = 0x1858,
475 .subdevice = 0xe800,
476 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
aee0b24c
MK		 477 }, {
478 .subvendor = 0x0070,
479 .subdevice = 0x8551,
480 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
ea5697fe
DW		 481 }, {
482 .subvendor = 0x14f1,
483 .subdevice = 0x8578,
484 .card = CX23885_BOARD_MYGICA_X8558PRO,
0b32d65c
KK		 485 }, {
486 .subvendor = 0x107d,
487 .subdevice = 0x6f22,
488 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
d19770e5
ST		 489 },
490};
491const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
492
493void cx23885_card_list(struct cx23885_dev *dev)
494{
495 int i;
496
497 if (0 == dev->pci->subsystem_vendor &&
498 0 == dev->pci->subsystem_device) {
9c8ced51
ST		 499 printk(KERN_INFO
500 "%s: Board has no valid PCIe Subsystem ID and can't\n"
501 "%s: be autodetected. Pass card=<n> insmod option\n"
502 "%s: to workaround that. Redirect complaints to the\n"
503 "%s: vendor of the TV card. Best regards,\n"
d19770e5
ST		 504 "%s: -- tux\n",
505 dev->name, dev->name, dev->name, dev->name, dev->name);
506 } else {
9c8ced51
ST		 507 printk(KERN_INFO
508 "%s: Your board isn't known (yet) to the driver.\n"
509 "%s: Try to pick one of the existing card configs via\n"
d19770e5
ST		 510 "%s: card=<n> insmod option. Updating to the latest\n"
511 "%s: version might help as well.\n",
512 dev->name, dev->name, dev->name, dev->name);
513 }
9c8ced51 514 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
d19770e5
ST		 515 dev->name);
516 for (i = 0; i < cx23885_bcount; i++)
9c8ced51 517 printk(KERN_INFO "%s: card=%d -> %s\n",
d19770e5
ST		 518 dev->name, i, cx23885_boards[i].name);
519}
520
521static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
522{
523 struct tveeprom tv;
524
9c8ced51
ST		 525 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
526 eeprom_data);
d19770e5 527
d19770e5 528 /* Make sure we support the board model */
9c8ced51 529 switch (tv.model) {
5308cf09
MK		 530 case 22001:
531 /* WinTV-HVR1270 (PCIe, Retail, half height)
532 * ATSC/QAM and basic analog, IR Blast */
533 case 22009:
534 /* WinTV-HVR1210 (PCIe, Retail, half height)
535 * DVB-T and basic analog, IR Blast */
536 case 22011:
537 /* WinTV-HVR1270 (PCIe, Retail, half height)
538 * ATSC/QAM and basic analog, IR Recv */
539 case 22019:
540 /* WinTV-HVR1210 (PCIe, Retail, half height)
541 * DVB-T and basic analog, IR Recv */
542 case 22021:
543 /* WinTV-HVR1275 (PCIe, Retail, half height)
544 * ATSC/QAM and basic analog, IR Recv */
545 case 22029:
546 /* WinTV-HVR1210 (PCIe, Retail, half height)
547 * DVB-T and basic analog, IR Recv */
548 case 22101:
549 /* WinTV-HVR1270 (PCIe, Retail, full height)
550 * ATSC/QAM and basic analog, IR Blast */
551 case 22109:
552 /* WinTV-HVR1210 (PCIe, Retail, full height)
553 * DVB-T and basic analog, IR Blast */
554 case 22111:
555 /* WinTV-HVR1270 (PCIe, Retail, full height)
556 * ATSC/QAM and basic analog, IR Recv */
557 case 22119:
558 /* WinTV-HVR1210 (PCIe, Retail, full height)
559 * DVB-T and basic analog, IR Recv */
560 case 22121:
561 /* WinTV-HVR1275 (PCIe, Retail, full height)
562 * ATSC/QAM and basic analog, IR Recv */
563 case 22129:
564 /* WinTV-HVR1210 (PCIe, Retail, full height)
565 * DVB-T and basic analog, IR Recv */
36396c89
MK		 566 case 71009:
567 /* WinTV-HVR1200 (PCIe, Retail, full height)
568 * DVB-T and basic analog */
569 case 71359:
570 /* WinTV-HVR1200 (PCIe, OEM, half height)
571 * DVB-T and basic analog */
572 case 71439:
573 /* WinTV-HVR1200 (PCIe, OEM, half height)
574 * DVB-T and basic analog */
575 case 71449:
576 /* WinTV-HVR1200 (PCIe, OEM, full height)
577 * DVB-T and basic analog */
578 case 71939:
579 /* WinTV-HVR1200 (PCIe, OEM, half height)
580 * DVB-T and basic analog */
581 case 71949:
582 /* WinTV-HVR1200 (PCIe, OEM, full height)
583 * DVB-T and basic analog */
584 case 71959:
585 /* WinTV-HVR1200 (PCIe, OEM, full height)
586 * DVB-T and basic analog */
587 case 71979:
588 /* WinTV-HVR1200 (PCIe, OEM, half height)
589 * DVB-T and basic analog */
590 case 71999:
591 /* WinTV-HVR1200 (PCIe, OEM, full height)
592 * DVB-T and basic analog */
9c8ced51
ST		 593 case 76601:
594 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
595 channel ATSC and MPEG2 HW Encoder */
596 case 77001:
597 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
598 and Basic analog */
599 case 77011:
600 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
601 and Basic analog */
602 case 77041:
603 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
604 and Basic analog */
605 case 77051:
606 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
607 and Basic analog */
608 case 78011:
609 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
610 Dual channel ATSC and MPEG2 HW Encoder */
611 case 78501:
612 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
613 Dual channel ATSC and MPEG2 HW Encoder */
614 case 78521:
615 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
616 Dual channel ATSC and MPEG2 HW Encoder */
617 case 78531:
618 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
619 Dual channel ATSC and MPEG2 HW Encoder */
620 case 78631:
621 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
622 Dual channel ATSC and MPEG2 HW Encoder */
623 case 79001:
624 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
625 ATSC and Basic analog */
626 case 79101:
627 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
628 ATSC and Basic analog */
ebbeb460
AW		 629 case 79501:
630 /* WinTV-HVR1250 (PCIe, No IR, half height,
631 ATSC [at least] and Basic analog) */
9c8ced51
ST		 632 case 79561:
633 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
634 ATSC and Basic analog */
635 case 79571:
636 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
637 ATSC and Basic analog */
638 case 79671:
639 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
640 ATSC and Basic analog */
66762373
ST		 641 case 80019:
642 /* WinTV-HVR1400 (Express Card, Retail, IR,
643 * DVB-T and Basic analog */
36396c89
MK		 644 case 81509:
645 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
646 * DVB-T and MPEG2 HW Encoder */
a780a31c 647 case 81519:
36396c89 648 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
a780a31c 649 * DVB-T and MPEG2 HW Encoder */
d19770e5 650 break;
13697380 651 case 85021:
73a5f419 652 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
13697380
ST		 653 Dual channel ATSC and MPEG2 HW Encoder */
654 break;
73a5f419
MK		 655 case 85721:
656 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
657 Dual channel ATSC and Basic analog */
658 break;
d19770e5 659 default:
13697380
ST		 660 printk(KERN_WARNING "%s: warning: "
661 "unknown hauppauge model #%d\n",
9c8ced51 662 dev->name, tv.model);
d19770e5
ST		 663 break;
664 }
665
666 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
667 dev->name, tv.model);
668}
669
d7cba043 670int cx23885_tuner_callback(void *priv, int component, int command, int arg)
8c70017f 671{
89ce2216
ST		 672 struct cx23885_tsport *port = priv;
673 struct cx23885_dev *dev = port->dev;
6df51690
ST		 674 u32 bitmask = 0;
675
89ce2216
ST		 676 if (command == XC2028_RESET_CLK)
677 return 0;
678
6df51690
ST		 679 if (command != 0) {
680 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
681 __func__, command);
682 return -EINVAL;
683 }
8c70017f 684
9c8ced51 685 switch (dev->board) {
90a71b1c
ST		 686 case CX23885_BOARD_HAUPPAUGE_HVR1400:
687 case CX23885_BOARD_HAUPPAUGE_HVR1500:
8c70017f 688 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
4c56b04a 689 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 690 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 691 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 692 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
90a71b1c 693 /* Tuner Reset Command */
4c56b04a 694 bitmask = 0x04;
6df51690
ST		 695 break;
696 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 697 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
4c56b04a
ST		 698 /* Two identical tuners on two different i2c buses,
699 * we need to reset the correct gpio. */
d4dc673d 700 if (port->nr == 1)
4c56b04a 701 bitmask = 0x01;
d4dc673d 702 else if (port->nr == 2)
4c56b04a 703 bitmask = 0x04;
8c70017f
ST		 704 break;
705 }
706
6df51690
ST		 707 if (bitmask) {
708 /* Drive the tuner into reset and back out */
709 cx_clear(GP0_IO, bitmask);
710 mdelay(200);
711 cx_set(GP0_IO, bitmask);
712 }
713
714 return 0;
8c70017f 715}
73c993a8 716
a6a3f140
ST		 717void cx23885_gpio_setup(struct cx23885_dev *dev)
718{
9c8ced51 719 switch (dev->board) {
a6a3f140
ST		 720 case CX23885_BOARD_HAUPPAUGE_HVR1250:
721 /* GPIO-0 cx24227 demodulator reset */
722 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
723 break;
07b4a835
MK		 724 case CX23885_BOARD_HAUPPAUGE_HVR1500:
725 /* GPIO-0 cx24227 demodulator */
726 /* GPIO-2 xc3028 tuner */
727
728 /* Put the parts into reset */
729 cx_set(GP0_IO, 0x00050000);
730 cx_clear(GP0_IO, 0x00000005);
731 msleep(5);
732
733 /* Bring the parts out of reset */
734 cx_set(GP0_IO, 0x00050005);
735 break;
d1987d55
ST		 736 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
737 /* GPIO-0 cx24227 demodulator reset */
738 /* GPIO-2 xc5000 tuner reset */
739 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
740 break;
a6a3f140
ST		 741 case CX23885_BOARD_HAUPPAUGE_HVR1800:
742 /* GPIO-0 656_CLK */
743 /* GPIO-1 656_D0 */
744 /* GPIO-2 8295A Reset */
745 /* GPIO-3-10 cx23417 data0-7 */
746 /* GPIO-11-14 cx23417 addr0-3 */
747 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
748 /* GPIO-19 IR_RX */
3ba71d21 749
a589b665
ST		 750 /* CX23417 GPIO's */
751 /* EIO15 Zilog Reset */
752 /* EIO14 S5H1409/CX24227 Reset */
f659c513
ST		 753 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
754
755 /* Put the demod into reset and protect the eeprom */
756 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
757 mdelay(100);
758
759 /* Bring the demod and blaster out of reset */
760 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
761 mdelay(100);
a589b665 762
5206d6ec 763 /* Force the TDA8295A into reset and back */
21ff3e4f
ST		 764 cx23885_gpio_enable(dev, GPIO_2, 1);
765 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 766 mdelay(20);
21ff3e4f 767 cx23885_gpio_clear(dev, GPIO_2);
5206d6ec 768 mdelay(20);
21ff3e4f 769 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 770 mdelay(20);
a6a3f140 771 break;
b3ea0166
ST		 772 case CX23885_BOARD_HAUPPAUGE_HVR1200:
773 /* GPIO-0 tda10048 demodulator reset */
774 /* GPIO-2 tda18271 tuner reset */
775
a780a31c
ST		 776 /* Put the parts into reset and back */
777 cx_set(GP0_IO, 0x00050000);
778 mdelay(20);
779 cx_clear(GP0_IO, 0x00000005);
780 mdelay(20);
781 cx_set(GP0_IO, 0x00050005);
782 break;
783 case CX23885_BOARD_HAUPPAUGE_HVR1700:
784 /* GPIO-0 TDA10048 demodulator reset */
785 /* GPIO-2 TDA8295A Reset */
786 /* GPIO-3-10 cx23417 data0-7 */
787 /* GPIO-11-14 cx23417 addr0-3 */
788 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
789
790 /* The following GPIO's are on the interna AVCore (cx25840) */
791 /* GPIO-19 IR_RX */
792 /* GPIO-20 IR_TX 416/DVBT Select */
793 /* GPIO-21 IIS DAT */
794 /* GPIO-22 IIS WCLK */
795 /* GPIO-23 IIS BCLK */
796
66762373
ST		 797 /* Put the parts into reset and back */
798 cx_set(GP0_IO, 0x00050000);
799 mdelay(20);
800 cx_clear(GP0_IO, 0x00000005);
801 mdelay(20);
802 cx_set(GP0_IO, 0x00050005);
803 break;
804 case CX23885_BOARD_HAUPPAUGE_HVR1400:
805 /* GPIO-0 Dibcom7000p demodulator reset */
806 /* GPIO-2 xc3028L tuner reset */
807 /* GPIO-13 LED */
808
b3ea0166
ST		 809 /* Put the parts into reset and back */
810 cx_set(GP0_IO, 0x00050000);
811 mdelay(20);
812 cx_clear(GP0_IO, 0x00000005);
813 mdelay(20);
814 cx_set(GP0_IO, 0x00050005);
815 break;
1ecc5aed
ST		 816 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
817 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
818 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
819 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
820 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
821
aef2d186
ST		 822 /* Put the parts into reset and back */
823 cx_set(GP0_IO, 0x000f0000);
824 mdelay(20);
825 cx_clear(GP0_IO, 0x0000000f);
826 mdelay(20);
827 cx_set(GP0_IO, 0x000f000f);
828 break;
829 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
830 /* GPIO-0 portb xc3028 reset */
831 /* GPIO-1 portb zl10353 reset */
832 /* GPIO-2 portc xc3028 reset */
833 /* GPIO-3 portc zl10353 reset */
834
1ecc5aed
ST		 835 /* Put the parts into reset and back */
836 cx_set(GP0_IO, 0x000f0000);
837 mdelay(20);
838 cx_clear(GP0_IO, 0x0000000f);
839 mdelay(20);
840 cx_set(GP0_IO, 0x000f000f);
841 break;
4c56b04a 842 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 843 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 844 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 845 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
4c56b04a
ST		 846 /* GPIO-2 xc3028 tuner reset */
847
848 /* The following GPIO's are on the internal AVCore (cx25840) */
849 /* GPIO-? zl10353 demod reset */
850
851 /* Put the parts into reset and back */
852 cx_set(GP0_IO, 0x00040000);
853 mdelay(20);
854 cx_clear(GP0_IO, 0x00000004);
855 mdelay(20);
856 cx_set(GP0_IO, 0x00040004);
857 break;
96318d0c
IL		 858 case CX23885_BOARD_TBS_6920:
859 cx_write(MC417_CTL, 0x00000036);
860 cx_write(MC417_OEN, 0x00001000);
09ea33e5
IL		 861 cx_set(MC417_RWD, 0x00000002);
862 mdelay(200);
863 cx_clear(MC417_RWD, 0x00000800);
864 mdelay(200);
865 cx_set(MC417_RWD, 0x00000800);
866 mdelay(200);
96318d0c 867 break;
5a23b076
IL		 868 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
869 /* GPIO-0 INTA from CiMax1
870 GPIO-1 INTB from CiMax2
871 GPIO-2 reset chips
872 GPIO-3 to GPIO-10 data/addr for CA
873 GPIO-11 ~CS0 to CiMax1
874 GPIO-12 ~CS1 to CiMax2
875 GPIO-13 ADL0 load LSB addr
876 GPIO-14 ADL1 load MSB addr
877 GPIO-15 ~RDY from CiMax
878 GPIO-17 ~RD to CiMax
879 GPIO-18 ~WR to CiMax
880 */
881 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
882 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
883 cx_clear(GP0_IO, 0x00030004);
884 mdelay(100);/* reset delay */
885 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
886 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
887 /* GPIO-15 IN as ~ACK, rest as OUT */
888 cx_write(MC417_OEN, 0x00001000);
889 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
890 cx_write(MC417_RWD, 0x0000c300);
891 /* enable irq */
892 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
893 break;
2074dffa 894 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 895 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 896 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 897 case CX23885_BOARD_HAUPPAUGE_HVR1210:
d099becb 898 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
6b926eca
MK		 899 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
900 /* GPIO-9 Demod reset */
2074dffa
ST		 901
902 /* Put the parts into reset and back */
d099becb
MK		 903 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
904 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
2074dffa
ST		 905 cx23885_gpio_clear(dev, GPIO_9);
906 mdelay(20);
907 cx23885_gpio_set(dev, GPIO_9);
908 break;
493b7127 909 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 910 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
8e069bb9 911 /* GPIO-0 (0)Analog / (1)Digital TV */
493b7127 912 /* GPIO-1 reset XC5000 */
2365b2d3 913 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
8e069bb9
DW		 914 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
915 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
493b7127 916 mdelay(100);
8e069bb9 917 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
493b7127
DW		 918 mdelay(100);
919 break;
ea5697fe
DW		 920 case CX23885_BOARD_MYGICA_X8558PRO:
921 /* GPIO-0 reset first ATBM8830 */
922 /* GPIO-1 reset second ATBM8830 */
923 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
924 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
925 mdelay(100);
926 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
927 mdelay(100);
928 break;
13697380 929 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 930 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 931 /* GPIO-0 656_CLK */
932 /* GPIO-1 656_D0 */
933 /* GPIO-2 Wake# */
934 /* GPIO-3-10 cx23417 data0-7 */
935 /* GPIO-11-14 cx23417 addr0-3 */
936 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
937 /* GPIO-19 IR_RX */
938 /* GPIO-20 C_IR_TX */
939 /* GPIO-21 I2S DAT */
940 /* GPIO-22 I2S WCLK */
941 /* GPIO-23 I2S BCLK */
942 /* ALT GPIO: EXP GPIO LATCH */
943
944 /* CX23417 GPIO's */
945 /* GPIO-14 S5H1411/CX24228 Reset */
946 /* GPIO-13 EEPROM write protect */
947 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
948
949 /* Put the demod into reset and protect the eeprom */
950 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
951 mdelay(100);
952
953 /* Bring the demod out of reset */
954 mc417_gpio_set(dev, GPIO_14);
955 mdelay(100);
956
957 /* CX24228 GPIO */
958 /* Connected to IF / Mux */
959 break;
a6a3f140
ST		 960 }
961}
962
963int cx23885_ir_init(struct cx23885_dev *dev)
964{
81f287da
AW		 965 static struct v4l2_subdev_io_pin_config ir_pin_cfg[] = {
966 {
967 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
968 .pin = CX23885_PIN_IR_RX_GPIO19,
969 .function = CX23885_PAD_IR_RX,
970 .value = 0,
971 .strength = CX25840_PIN_DRIVE_MEDIUM,
972 }, {
973 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
974 .pin = CX23885_PIN_IR_TX_GPIO20,
975 .function = CX23885_PAD_IR_TX,
976 .value = 0,
977 .strength = CX25840_PIN_DRIVE_MEDIUM,
978 }
979 };
980 const size_t ir_pin_cfg_count = ARRAY_SIZE(ir_pin_cfg);
981
982 struct v4l2_subdev_ir_parameters params;
29f8a0a5 983 int ret = 0;
a6a3f140
ST		 984 switch (dev->board) {
985 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 986 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 987 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 988 case CX23885_BOARD_HAUPPAUGE_HVR1800:
b3ea0166 989 case CX23885_BOARD_HAUPPAUGE_HVR1200:
66762373 990 case CX23885_BOARD_HAUPPAUGE_HVR1400:
2074dffa 991 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 992 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 993 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 994 case CX23885_BOARD_HAUPPAUGE_HVR1210:
a6a3f140
ST		 995 /* FIXME: Implement me */
996 break;
29f8a0a5 997 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 998 case CX23885_BOARD_HAUPPAUGE_HVR1290:
29f8a0a5
AW		 999 ret = cx23888_ir_probe(dev);
1000 if (ret)
1001 break;
1002 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
81f287da
AW		 1003 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1004 ir_pin_cfg_count, ir_pin_cfg);
f59ad611 1005 dev->pci_irqmask |= PCI_MSK_IR;
81f287da
AW		 1006 /*
1007 * For these boards we need to invert the Tx output via the
1008 * IR controller to have the LED off while idle
1009 */
1010 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1011 params.enable = false;
1012 params.shutdown = false;
1013 params.invert_level = true;
1014 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1015 params.shutdown = true;
1016 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
29f8a0a5 1017 break;
12886871
ST		 1018 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1019 request_module("ir-kbd-i2c");
1020 break;
a6a3f140
ST		 1021 }
1022
29f8a0a5 1023 return ret;
a6a3f140
ST		 1024}
1025
f59ad611
AW		 1026void cx23885_ir_fini(struct cx23885_dev *dev)
1027{
1028 switch (dev->board) {
1029 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1030 case CX23885_BOARD_HAUPPAUGE_HVR1290:
f59ad611
AW		 1031 dev->pci_irqmask &= ~PCI_MSK_IR;
1032 cx_clear(PCI_INT_MSK, PCI_MSK_IR);
1033 cx23888_ir_remove(dev);
1034 dev->sd_ir = NULL;
1035 break;
1036 }
1037}
1038
1039void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1040{
1041 switch (dev->board) {
1042 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1043 case CX23885_BOARD_HAUPPAUGE_HVR1290:
f59ad611
AW		 1044 if (dev->sd_ir && (dev->pci_irqmask & PCI_MSK_IR))
1045 cx_set(PCI_INT_MSK, PCI_MSK_IR);
1046 break;
1047 }
1048}
1049
d19770e5
ST		 1050void cx23885_card_setup(struct cx23885_dev *dev)
1051{
a6a3f140
ST		 1052 struct cx23885_tsport *ts1 = &dev->ts1;
1053 struct cx23885_tsport *ts2 = &dev->ts2;
1054
d19770e5
ST		 1055 static u8 eeprom[256];
1056
1057 if (dev->i2c_bus[0].i2c_rc == 0) {
1058 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
44a6481d
MK		 1059 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1060 eeprom, sizeof(eeprom));
d19770e5
ST		 1061 }
1062
1063 switch (dev->board) {
a77743bc 1064 case CX23885_BOARD_HAUPPAUGE_HVR1250:
ebbeb460
AW		 1065 if (dev->i2c_bus[0].i2c_rc == 0) {
1066 if (eeprom[0x80] != 0x84)
1067 hauppauge_eeprom(dev, eeprom+0xc0);
1068 else
1069 hauppauge_eeprom(dev, eeprom+0x80);
1070 }
1071 break;
07b4a835 1072 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1073 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
66762373 1074 case CX23885_BOARD_HAUPPAUGE_HVR1400:
c88133ec
ST		 1075 if (dev->i2c_bus[0].i2c_rc == 0)
1076 hauppauge_eeprom(dev, eeprom+0x80);
1077 break;
d19770e5
ST		 1078 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1079 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1080 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1081 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2074dffa 1082 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1083 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1084 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 1085 case CX23885_BOARD_HAUPPAUGE_HVR1210:
13697380 1086 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1087 case CX23885_BOARD_HAUPPAUGE_HVR1290:
d19770e5 1088 if (dev->i2c_bus[0].i2c_rc == 0)
c88133ec 1089 hauppauge_eeprom(dev, eeprom+0xc0);
d19770e5
ST		 1090 break;
1091 }
a6a3f140
ST		 1092
1093 switch (dev->board) {
335377b7 1094 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 1095 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
335377b7
MK		 1096 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1097 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1098 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1099 /* break omitted intentionally */
a6a3f140
ST		 1100 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1101 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1102 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1103 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1104 break;
a589b665
ST		 1105 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1106 /* Defaults for VID B - Analog encoder */
1107 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1108 ts1->gen_ctrl_val = 0x10e;
1109 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1110 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1111
1112 /* APB_TSVALERR_POL (active low)*/
1113 ts1->vld_misc_val = 0x2000;
1114 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1115
1116 /* Defaults for VID C */
1117 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1118 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1119 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
96318d0c
IL		 1120 break;
1121 case CX23885_BOARD_TBS_6920:
09ea33e5
IL		 1122 ts1->gen_ctrl_val = 0x4; /* Parallel */
1123 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1124 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1125 break;
1126 case CX23885_BOARD_TEVII_S470:
c9b8b04b 1127 case CX23885_BOARD_DVBWORLD_2005:
96318d0c
IL		 1128 ts1->gen_ctrl_val = 0x5; /* Parallel */
1129 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1130 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
a589b665 1131 break;
5a23b076
IL		 1132 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1133 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1134 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1135 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1136 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1137 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1138 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1139 break;
493b7127 1140 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 1141 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
493b7127
DW		 1142 ts1->gen_ctrl_val = 0x5; /* Parallel */
1143 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1144 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1145 break;
ea5697fe
DW		 1146 case CX23885_BOARD_MYGICA_X8558PRO:
1147 ts1->gen_ctrl_val = 0x5; /* Parallel */
1148 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1149 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1150 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1151 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1152 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1153 break;
a6a3f140 1154 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 1155 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1156 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 1157 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1158 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1159 case CX23885_BOARD_HAUPPAUGE_HVR1700:
66762373 1160 case CX23885_BOARD_HAUPPAUGE_HVR1400:
4c56b04a 1161 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 1162 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2074dffa 1163 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1164 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1165 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 1166 case CX23885_BOARD_HAUPPAUGE_HVR1210:
13697380 1167 case CX23885_BOARD_HAUPPAUGE_HVR1850:
34e383dd 1168 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
aee0b24c 1169 case CX23885_BOARD_HAUPPAUGE_HVR1290:
a6a3f140
ST		 1170 default:
1171 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1172 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1173 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1174 }
1175
ce89cfb4
ST		 1176 /* Certain boards support analog, or require the avcore to be
1177 * loaded, ensure this happens.
1178 */
1179 switch (dev->board) {
1180 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1181 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1182 case CX23885_BOARD_HAUPPAUGE_HVR1700:
4c56b04a 1183 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 1184 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
5a23b076 1185 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
34e383dd 1186 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
c6b7053b 1187 case CX23885_BOARD_HAUPPAUGE_HVR1850:
bc1548ad
DW		 1188 case CX23885_BOARD_MYGICA_X8506:
1189 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
aee0b24c 1190 case CX23885_BOARD_HAUPPAUGE_HVR1290:
0b32d65c 1191 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
e6574f2f
HV		 1192 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1193 &dev->i2c_bus[2].i2c_adap,
53dacb15 1194 "cx25840", "cx25840", 0x88 >> 1, NULL);
d6b1850d
AW		 1195 if (dev->sd_cx25840) {
1196 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1197 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1198 }
ce89cfb4
ST		 1199 break;
1200 }
5a23b076
IL		 1201
1202 /* AUX-PLL 27MHz CLK */
1203 switch (dev->board) {
1204 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1205 netup_initialize(dev);
1206 break;
1207 }
d19770e5
ST		 1208}
1209
1210/* ------------------------------------------------------------------ */
Linux kernel - Deliverables
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