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[media] Don't OOPS if videobuf_dvb_get_frontend return NULL
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-cards.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
7b888014 26#include <media/cx25840.h>
78db8547 27#include <linux/firmware.h>
d19770e5 28
e2d4dc5a 29#include "../../../staging/altera-stapl/altera.h"
d19770e5 30#include "cx23885.h"
90a71b1c 31#include "tuner-xc2028.h"
b8f0d306 32#include "netup-eeprom.h"
5a23b076 33#include "netup-init.h"
78db8547 34#include "altera-ci.h"
0cf8af57 35#include "xc4000.h"
78db8547 36#include "xc5000.h"
29f8a0a5 37#include "cx23888-ir.h"
d19770e5 38
fa647f24
AW		 39static unsigned int enable_885_ir;
40module_param(enable_885_ir, int, 0644);
41MODULE_PARM_DESC(enable_885_ir,
42 "Enable integrated IR controller for supported\n"
43 "\t\t CX2388[57] boards that are wired for it:\n"
44 "\t\t\tHVR-1250 (reported safe)\n"
45 "\t\t\tTeVii S470 (reported unsafe)\n"
46 "\t\t This can cause an interrupt storm with some cards.\n"
47 "\t\t Default: 0 [Disabled]");
48
d19770e5
ST		 49/* ------------------------------------------------------------------ */
50/* board config info */
51
52struct cx23885_board cx23885_boards[] = {
53 [CX23885_BOARD_UNKNOWN] = {
54 .name = "UNKNOWN/GENERIC",
c7712613
ST		 55 /* Ensure safe default for unknown boards */
56 .clk_freq = 0,
d19770e5
ST		 57 .input = {{
58 .type = CX23885_VMUX_COMPOSITE1,
59 .vmux = 0,
9c8ced51 60 }, {
d19770e5
ST		 61 .type = CX23885_VMUX_COMPOSITE2,
62 .vmux = 1,
9c8ced51 63 }, {
d19770e5
ST		 64 .type = CX23885_VMUX_COMPOSITE3,
65 .vmux = 2,
9c8ced51 66 }, {
d19770e5
ST		 67 .type = CX23885_VMUX_COMPOSITE4,
68 .vmux = 3,
9c8ced51 69 } },
d19770e5
ST		 70 },
71 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
72 .name = "Hauppauge WinTV-HVR1800lp",
d19770e5
ST		 73 .portc = CX23885_MPEG_DVB,
74 .input = {{
75 .type = CX23885_VMUX_TELEVISION,
76 .vmux = 0,
77 .gpio0 = 0xff00,
9c8ced51 78 }, {
d19770e5
ST		 79 .type = CX23885_VMUX_DEBUG,
80 .vmux = 0,
81 .gpio0 = 0xff01,
9c8ced51 82 }, {
d19770e5
ST		 83 .type = CX23885_VMUX_COMPOSITE1,
84 .vmux = 1,
85 .gpio0 = 0xff02,
9c8ced51 86 }, {
d19770e5
ST		 87 .type = CX23885_VMUX_SVIDEO,
88 .vmux = 2,
89 .gpio0 = 0xff02,
9c8ced51 90 } },
d19770e5
ST		 91 },
92 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
93 .name = "Hauppauge WinTV-HVR1800",
7b888014 94 .porta = CX23885_ANALOG_VIDEO,
a589b665 95 .portb = CX23885_MPEG_ENCODER,
d19770e5 96 .portc = CX23885_MPEG_DVB,
7b888014
ST		 97 .tuner_type = TUNER_PHILIPS_TDA8290,
98 .tuner_addr = 0x42, /* 0x84 >> 1 */
557f48d5 99 .tuner_bus = 1,
d19770e5
ST		 100 .input = {{
101 .type = CX23885_VMUX_TELEVISION,
7b888014
ST		 102 .vmux = CX25840_VIN7_CH3 |
103 CX25840_VIN5_CH2 |
104 CX25840_VIN2_CH1,
105 .gpio0 = 0,
9c8ced51 106 }, {
d19770e5 107 .type = CX23885_VMUX_COMPOSITE1,
7b888014
ST		 108 .vmux = CX25840_VIN7_CH3 |
109 CX25840_VIN4_CH2 |
110 CX25840_VIN6_CH1,
111 .gpio0 = 0,
9c8ced51 112 }, {
d19770e5 113 .type = CX23885_VMUX_SVIDEO,
7b888014
ST		 114 .vmux = CX25840_VIN7_CH3 |
115 CX25840_VIN4_CH2 |
116 CX25840_VIN8_CH1 |
117 CX25840_SVIDEO_ON,
118 .gpio0 = 0,
9c8ced51 119 } },
d19770e5 120 },
a77743bc
ST		 121 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
122 .name = "Hauppauge WinTV-HVR1250",
123 .portc = CX23885_MPEG_DVB,
124 .input = {{
125 .type = CX23885_VMUX_TELEVISION,
126 .vmux = 0,
127 .gpio0 = 0xff00,
9c8ced51 128 }, {
a77743bc
ST		 129 .type = CX23885_VMUX_DEBUG,
130 .vmux = 0,
131 .gpio0 = 0xff01,
9c8ced51 132 }, {
a77743bc
ST		 133 .type = CX23885_VMUX_COMPOSITE1,
134 .vmux = 1,
135 .gpio0 = 0xff02,
9c8ced51 136 }, {
a77743bc
ST		 137 .type = CX23885_VMUX_SVIDEO,
138 .vmux = 2,
139 .gpio0 = 0xff02,
9c8ced51 140 } },
a77743bc 141 },
9bc37caa
MK		 142 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
143 .name = "DViCO FusionHDTV5 Express",
a6a3f140 144 .portb = CX23885_MPEG_DVB,
9bc37caa 145 },
d1987d55
ST		 146 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
147 .name = "Hauppauge WinTV-HVR1500Q",
148 .portc = CX23885_MPEG_DVB,
149 },
07b4a835
MK		 150 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
151 .name = "Hauppauge WinTV-HVR1500",
152 .portc = CX23885_MPEG_DVB,
153 },
b3ea0166
ST		 154 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
155 .name = "Hauppauge WinTV-HVR1200",
156 .portc = CX23885_MPEG_DVB,
157 },
a780a31c
ST		 158 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
159 .name = "Hauppauge WinTV-HVR1700",
160 .portc = CX23885_MPEG_DVB,
161 },
66762373
ST		 162 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
163 .name = "Hauppauge WinTV-HVR1400",
164 .portc = CX23885_MPEG_DVB,
165 },
335377b7
MK		 166 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
167 .name = "DViCO FusionHDTV7 Dual Express",
aaadeac8 168 .portb = CX23885_MPEG_DVB,
335377b7
MK		 169 .portc = CX23885_MPEG_DVB,
170 },
aef2d186
ST		 171 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
172 .name = "DViCO FusionHDTV DVB-T Dual Express",
173 .portb = CX23885_MPEG_DVB,
174 .portc = CX23885_MPEG_DVB,
175 },
4c56b04a
ST		 176 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
177 .name = "Leadtek Winfast PxDVR3200 H",
178 .portc = CX23885_MPEG_DVB,
179 },
0cf8af57 180 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
181 .name = "Leadtek Winfast PxDVR3200 H XC4000",
182 .porta = CX23885_ANALOG_VIDEO,
183 .portc = CX23885_MPEG_DVB,
184 .tuner_type = TUNER_XC4000,
185 .tuner_addr = 0x61,
186 .radio_type = TUNER_XC4000,
187 .radio_addr = 0x61,
188 .input = {{
189 .type = CX23885_VMUX_TELEVISION,
190 .vmux = CX25840_VIN2_CH1 |
191 CX25840_VIN5_CH2 |
192 CX25840_NONE0_CH3,
193 }, {
194 .type = CX23885_VMUX_COMPOSITE1,
195 .vmux = CX25840_COMPOSITE1,
196 }, {
197 .type = CX23885_VMUX_SVIDEO,
198 .vmux = CX25840_SVIDEO_LUMA3 |
199 CX25840_SVIDEO_CHROMA4,
200 }, {
201 .type = CX23885_VMUX_COMPONENT,
202 .vmux = CX25840_VIN7_CH1 |
203 CX25840_VIN6_CH2 |
204 CX25840_VIN8_CH3 |
205 CX25840_COMPONENT_ON,
206 } },
207 },
9bb1b7e8
IL		 208 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
209 .name = "Compro VideoMate E650F",
210 .portc = CX23885_MPEG_DVB,
211 },
96318d0c
IL		 212 [CX23885_BOARD_TBS_6920] = {
213 .name = "TurboSight TBS 6920",
214 .portb = CX23885_MPEG_DVB,
215 },
579943f5
IL		 216 [CX23885_BOARD_TEVII_S470] = {
217 .name = "TeVii S470",
218 .portb = CX23885_MPEG_DVB,
219 },
c9b8b04b
IL		 220 [CX23885_BOARD_DVBWORLD_2005] = {
221 .name = "DVBWorld DVB-S2 2005",
222 .portb = CX23885_MPEG_DVB,
223 },
5a23b076 224 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
78db8547 225 .ci_type = 1,
5a23b076
IL		 226 .name = "NetUP Dual DVB-S2 CI",
227 .portb = CX23885_MPEG_DVB,
228 .portc = CX23885_MPEG_DVB,
229 },
2074dffa
ST		 230 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
231 .name = "Hauppauge WinTV-HVR1270",
a5dbf457 232 .portc = CX23885_MPEG_DVB,
2074dffa 233 },
d099becb
MK		 234 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
235 .name = "Hauppauge WinTV-HVR1275",
236 .portc = CX23885_MPEG_DVB,
237 },
19bc5796
MK		 238 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
239 .name = "Hauppauge WinTV-HVR1255",
240 .portc = CX23885_MPEG_DVB,
241 },
6b926eca
MK		 242 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
243 .name = "Hauppauge WinTV-HVR1210",
244 .portc = CX23885_MPEG_DVB,
245 },
493b7127
DW		 246 [CX23885_BOARD_MYGICA_X8506] = {
247 .name = "Mygica X8506 DMB-TH",
6f0d8c02
DW		 248 .tuner_type = TUNER_XC5000,
249 .tuner_addr = 0x61,
557f48d5 250 .tuner_bus = 1,
bc1548ad 251 .porta = CX23885_ANALOG_VIDEO,
493b7127 252 .portb = CX23885_MPEG_DVB,
bc1548ad 253 .input = {
6f0d8c02
DW		 254 {
255 .type = CX23885_VMUX_TELEVISION,
256 .vmux = CX25840_COMPOSITE2,
257 },
bc1548ad
DW		 258 {
259 .type = CX23885_VMUX_COMPOSITE1,
260 .vmux = CX25840_COMPOSITE8,
261 },
262 {
263 .type = CX23885_VMUX_SVIDEO,
264 .vmux = CX25840_SVIDEO_LUMA3 |
265 CX25840_SVIDEO_CHROMA4,
266 },
267 {
268 .type = CX23885_VMUX_COMPONENT,
269 .vmux = CX25840_COMPONENT_ON |
270 CX25840_VIN1_CH1 |
271 CX25840_VIN6_CH2 |
272 CX25840_VIN7_CH3,
273 },
274 },
493b7127 275 },
2365b2d3
DW		 276 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
277 .name = "Magic-Pro ProHDTV Extreme 2",
6f0d8c02
DW		 278 .tuner_type = TUNER_XC5000,
279 .tuner_addr = 0x61,
557f48d5 280 .tuner_bus = 1,
bc1548ad 281 .porta = CX23885_ANALOG_VIDEO,
2365b2d3 282 .portb = CX23885_MPEG_DVB,
bc1548ad 283 .input = {
6f0d8c02
DW		 284 {
285 .type = CX23885_VMUX_TELEVISION,
286 .vmux = CX25840_COMPOSITE2,
287 },
bc1548ad
DW		 288 {
289 .type = CX23885_VMUX_COMPOSITE1,
290 .vmux = CX25840_COMPOSITE8,
291 },
292 {
293 .type = CX23885_VMUX_SVIDEO,
294 .vmux = CX25840_SVIDEO_LUMA3 |
295 CX25840_SVIDEO_CHROMA4,
296 },
297 {
298 .type = CX23885_VMUX_COMPONENT,
299 .vmux = CX25840_COMPONENT_ON |
300 CX25840_VIN1_CH1 |
301 CX25840_VIN6_CH2 |
302 CX25840_VIN7_CH3,
303 },
304 },
2365b2d3 305 },
13697380
ST		 306 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
307 .name = "Hauppauge WinTV-HVR1850",
308 .portb = CX23885_MPEG_ENCODER,
309 .portc = CX23885_MPEG_DVB,
310 },
34e383dd
VG		 311 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
312 .name = "Compro VideoMate E800",
313 .portc = CX23885_MPEG_DVB,
314 },
aee0b24c
MK		 315 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
316 .name = "Hauppauge WinTV-HVR1290",
317 .portc = CX23885_MPEG_DVB,
318 },
ea5697fe
DW		 319 [CX23885_BOARD_MYGICA_X8558PRO] = {
320 .name = "Mygica X8558 PRO DMB-TH",
321 .portb = CX23885_MPEG_DVB,
322 .portc = CX23885_MPEG_DVB,
323 },
0b32d65c
KK		 324 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
325 .name = "LEADTEK WinFast PxTV1200",
326 .porta = CX23885_ANALOG_VIDEO,
327 .tuner_type = TUNER_XC2028,
328 .tuner_addr = 0x61,
557f48d5 329 .tuner_bus = 1,
0b32d65c
KK		 330 .input = {{
331 .type = CX23885_VMUX_TELEVISION,
332 .vmux = CX25840_VIN2_CH1 |
333 CX25840_VIN5_CH2 |
334 CX25840_NONE0_CH3,
335 }, {
336 .type = CX23885_VMUX_COMPOSITE1,
337 .vmux = CX25840_COMPOSITE1,
338 }, {
339 .type = CX23885_VMUX_SVIDEO,
340 .vmux = CX25840_SVIDEO_LUMA3 |
341 CX25840_SVIDEO_CHROMA4,
342 }, {
343 .type = CX23885_VMUX_COMPONENT,
344 .vmux = CX25840_VIN7_CH1 |
345 CX25840_VIN6_CH2 |
346 CX25840_VIN8_CH3 |
347 CX25840_COMPONENT_ON,
348 } },
349 },
9028f58f
AC		 350 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
351 .name = "GoTView X5 3D Hybrid",
352 .tuner_type = TUNER_XC5000,
353 .tuner_addr = 0x64,
557f48d5 354 .tuner_bus = 1,
9028f58f
AC		 355 .porta = CX23885_ANALOG_VIDEO,
356 .portb = CX23885_MPEG_DVB,
357 .input = {{
358 .type = CX23885_VMUX_TELEVISION,
359 .vmux = CX25840_VIN2_CH1 |
360 CX25840_VIN5_CH2,
361 .gpio0 = 0x02,
362 }, {
363 .type = CX23885_VMUX_COMPOSITE1,
364 .vmux = CX23885_VMUX_COMPOSITE1,
365 }, {
366 .type = CX23885_VMUX_SVIDEO,
367 .vmux = CX25840_SVIDEO_LUMA3 |
368 CX25840_SVIDEO_CHROMA4,
369 } },
370 },
78db8547
IL		 371 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
372 .ci_type = 2,
373 .name = "NetUP Dual DVB-T/C-CI RF",
374 .porta = CX23885_ANALOG_VIDEO,
375 .portb = CX23885_MPEG_DVB,
376 .portc = CX23885_MPEG_DVB,
10d0dcd7
IL		 377 .num_fds_portb = 2,
378 .num_fds_portc = 2,
78db8547
IL		 379 .tuner_type = TUNER_XC5000,
380 .tuner_addr = 0x64,
381 .input = { {
382 .type = CX23885_VMUX_TELEVISION,
383 .vmux = CX25840_COMPOSITE1,
384 } },
385 },
d19770e5
ST		 386};
387const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
388
389/* ------------------------------------------------------------------ */
390/* PCI subsystem IDs */
391
392struct cx23885_subid cx23885_subids[] = {
393 {
394 .subvendor = 0x0070,
395 .subdevice = 0x3400,
396 .card = CX23885_BOARD_UNKNOWN,
9c8ced51 397 }, {
d19770e5
ST		 398 .subvendor = 0x0070,
399 .subdevice = 0x7600,
400 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
9c8ced51 401 }, {
d19770e5
ST		 402 .subvendor = 0x0070,
403 .subdevice = 0x7800,
404 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 405 }, {
d19770e5
ST		 406 .subvendor = 0x0070,
407 .subdevice = 0x7801,
408 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 409 }, {
6ccb8cfb
MK		 410 .subvendor = 0x0070,
411 .subdevice = 0x7809,
412 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 413 }, {
a77743bc
ST		 414 .subvendor = 0x0070,
415 .subdevice = 0x7911,
416 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
9c8ced51 417 }, {
9bc37caa
MK		 418 .subvendor = 0x18ac,
419 .subdevice = 0xd500,
420 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
9c8ced51 421 }, {
b00fff0b
MK		 422 .subvendor = 0x0070,
423 .subdevice = 0x7790,
424 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 425 }, {
d1987d55
ST		 426 .subvendor = 0x0070,
427 .subdevice = 0x7797,
428 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 429 }, {
b00fff0b
MK		 430 .subvendor = 0x0070,
431 .subdevice = 0x7710,
432 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
9c8ced51 433 }, {
07b4a835
MK		 434 .subvendor = 0x0070,
435 .subdevice = 0x7717,
436 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
b3ea0166
ST		 437 }, {
438 .subvendor = 0x0070,
439 .subdevice = 0x71d1,
440 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
3c3852cd
MK		 441 }, {
442 .subvendor = 0x0070,
443 .subdevice = 0x71d3,
444 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
a780a31c
ST		 445 }, {
446 .subvendor = 0x0070,
447 .subdevice = 0x8101,
448 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
66762373
ST		 449 }, {
450 .subvendor = 0x0070,
451 .subdevice = 0x8010,
452 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
9c8ced51 453 }, {
335377b7
MK		 454 .subvendor = 0x18ac,
455 .subdevice = 0xd618,
456 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
9c8ced51 457 }, {
aef2d186
ST		 458 .subvendor = 0x18ac,
459 .subdevice = 0xdb78,
460 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
4c56b04a
ST		 461 }, {
462 .subvendor = 0x107d,
463 .subdevice = 0x6681,
464 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
0cf8af57 465 }, {
466 .subvendor = 0x107d,
467 .subdevice = 0x6f39,
468 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
9bb1b7e8
IL		 469 }, {
470 .subvendor = 0x185b,
471 .subdevice = 0xe800,
472 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
96318d0c
IL		 473 }, {
474 .subvendor = 0x6920,
475 .subdevice = 0x8888,
476 .card = CX23885_BOARD_TBS_6920,
579943f5
IL		 477 }, {
478 .subvendor = 0xd470,
479 .subdevice = 0x9022,
480 .card = CX23885_BOARD_TEVII_S470,
c9b8b04b
IL		 481 }, {
482 .subvendor = 0x0001,
483 .subdevice = 0x2005,
484 .card = CX23885_BOARD_DVBWORLD_2005,
5a23b076
IL		 485 }, {
486 .subvendor = 0x1b55,
487 .subdevice = 0x2a2c,
488 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
2074dffa
ST		 489 }, {
490 .subvendor = 0x0070,
491 .subdevice = 0x2211,
492 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
d099becb
MK		 493 }, {
494 .subvendor = 0x0070,
495 .subdevice = 0x2215,
496 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
7d7b5284
MK		 497 }, {
498 .subvendor = 0x0070,
499 .subdevice = 0x221d,
500 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
19bc5796
MK		 501 }, {
502 .subvendor = 0x0070,
503 .subdevice = 0x2251,
504 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
7d7b5284
MK		 505 }, {
506 .subvendor = 0x0070,
507 .subdevice = 0x2259,
508 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
6b926eca
MK		 509 }, {
510 .subvendor = 0x0070,
511 .subdevice = 0x2291,
512 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
513 }, {
514 .subvendor = 0x0070,
515 .subdevice = 0x2295,
516 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
7d7b5284
MK		 517 }, {
518 .subvendor = 0x0070,
519 .subdevice = 0x2299,
520 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
521 }, {
522 .subvendor = 0x0070,
523 .subdevice = 0x229d,
524 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
525 }, {
526 .subvendor = 0x0070,
527 .subdevice = 0x22f0,
528 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
529 }, {
530 .subvendor = 0x0070,
531 .subdevice = 0x22f1,
532 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
533 }, {
534 .subvendor = 0x0070,
535 .subdevice = 0x22f2,
536 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
537 }, {
538 .subvendor = 0x0070,
539 .subdevice = 0x22f3,
540 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
541 }, {
542 .subvendor = 0x0070,
543 .subdevice = 0x22f4,
544 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
545 }, {
546 .subvendor = 0x0070,
547 .subdevice = 0x22f5,
548 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
493b7127
DW		 549 }, {
550 .subvendor = 0x14f1,
551 .subdevice = 0x8651,
552 .card = CX23885_BOARD_MYGICA_X8506,
2365b2d3
DW		 553 }, {
554 .subvendor = 0x14f1,
555 .subdevice = 0x8657,
556 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
13697380
ST		 557 }, {
558 .subvendor = 0x0070,
559 .subdevice = 0x8541,
560 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
34e383dd
VG		 561 }, {
562 .subvendor = 0x1858,
563 .subdevice = 0xe800,
564 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
aee0b24c
MK		 565 }, {
566 .subvendor = 0x0070,
567 .subdevice = 0x8551,
568 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
ea5697fe
DW		 569 }, {
570 .subvendor = 0x14f1,
571 .subdevice = 0x8578,
572 .card = CX23885_BOARD_MYGICA_X8558PRO,
0b32d65c
KK		 573 }, {
574 .subvendor = 0x107d,
575 .subdevice = 0x6f22,
576 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
9028f58f
AC		 577 }, {
578 .subvendor = 0x5654,
579 .subdevice = 0x2390,
580 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
78db8547
IL		 581 }, {
582 .subvendor = 0x1b55,
583 .subdevice = 0xe2e4,
584 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
d19770e5
ST		 585 },
586};
587const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
588
589void cx23885_card_list(struct cx23885_dev *dev)
590{
591 int i;
592
593 if (0 == dev->pci->subsystem_vendor &&
594 0 == dev->pci->subsystem_device) {
9c8ced51
ST		 595 printk(KERN_INFO
596 "%s: Board has no valid PCIe Subsystem ID and can't\n"
597 "%s: be autodetected. Pass card=<n> insmod option\n"
598 "%s: to workaround that. Redirect complaints to the\n"
599 "%s: vendor of the TV card. Best regards,\n"
d19770e5
ST		 600 "%s: -- tux\n",
601 dev->name, dev->name, dev->name, dev->name, dev->name);
602 } else {
9c8ced51
ST		 603 printk(KERN_INFO
604 "%s: Your board isn't known (yet) to the driver.\n"
605 "%s: Try to pick one of the existing card configs via\n"
d19770e5
ST		 606 "%s: card=<n> insmod option. Updating to the latest\n"
607 "%s: version might help as well.\n",
608 dev->name, dev->name, dev->name, dev->name);
609 }
9c8ced51 610 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
d19770e5
ST		 611 dev->name);
612 for (i = 0; i < cx23885_bcount; i++)
9c8ced51 613 printk(KERN_INFO "%s: card=%d -> %s\n",
d19770e5
ST		 614 dev->name, i, cx23885_boards[i].name);
615}
616
617static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
618{
619 struct tveeprom tv;
620
9c8ced51
ST		 621 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
622 eeprom_data);
d19770e5 623
d19770e5 624 /* Make sure we support the board model */
9c8ced51 625 switch (tv.model) {
5308cf09
MK		 626 case 22001:
627 /* WinTV-HVR1270 (PCIe, Retail, half height)
628 * ATSC/QAM and basic analog, IR Blast */
629 case 22009:
630 /* WinTV-HVR1210 (PCIe, Retail, half height)
631 * DVB-T and basic analog, IR Blast */
632 case 22011:
633 /* WinTV-HVR1270 (PCIe, Retail, half height)
634 * ATSC/QAM and basic analog, IR Recv */
635 case 22019:
636 /* WinTV-HVR1210 (PCIe, Retail, half height)
637 * DVB-T and basic analog, IR Recv */
638 case 22021:
639 /* WinTV-HVR1275 (PCIe, Retail, half height)
640 * ATSC/QAM and basic analog, IR Recv */
641 case 22029:
642 /* WinTV-HVR1210 (PCIe, Retail, half height)
643 * DVB-T and basic analog, IR Recv */
644 case 22101:
645 /* WinTV-HVR1270 (PCIe, Retail, full height)
646 * ATSC/QAM and basic analog, IR Blast */
647 case 22109:
648 /* WinTV-HVR1210 (PCIe, Retail, full height)
649 * DVB-T and basic analog, IR Blast */
650 case 22111:
651 /* WinTV-HVR1270 (PCIe, Retail, full height)
652 * ATSC/QAM and basic analog, IR Recv */
653 case 22119:
654 /* WinTV-HVR1210 (PCIe, Retail, full height)
655 * DVB-T and basic analog, IR Recv */
656 case 22121:
657 /* WinTV-HVR1275 (PCIe, Retail, full height)
658 * ATSC/QAM and basic analog, IR Recv */
659 case 22129:
660 /* WinTV-HVR1210 (PCIe, Retail, full height)
661 * DVB-T and basic analog, IR Recv */
36396c89
MK		 662 case 71009:
663 /* WinTV-HVR1200 (PCIe, Retail, full height)
664 * DVB-T and basic analog */
665 case 71359:
666 /* WinTV-HVR1200 (PCIe, OEM, half height)
667 * DVB-T and basic analog */
668 case 71439:
669 /* WinTV-HVR1200 (PCIe, OEM, half height)
670 * DVB-T and basic analog */
671 case 71449:
672 /* WinTV-HVR1200 (PCIe, OEM, full height)
673 * DVB-T and basic analog */
674 case 71939:
675 /* WinTV-HVR1200 (PCIe, OEM, half height)
676 * DVB-T and basic analog */
677 case 71949:
678 /* WinTV-HVR1200 (PCIe, OEM, full height)
679 * DVB-T and basic analog */
680 case 71959:
681 /* WinTV-HVR1200 (PCIe, OEM, full height)
682 * DVB-T and basic analog */
683 case 71979:
684 /* WinTV-HVR1200 (PCIe, OEM, half height)
685 * DVB-T and basic analog */
686 case 71999:
687 /* WinTV-HVR1200 (PCIe, OEM, full height)
688 * DVB-T and basic analog */
9c8ced51
ST		 689 case 76601:
690 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
691 channel ATSC and MPEG2 HW Encoder */
692 case 77001:
693 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
694 and Basic analog */
695 case 77011:
696 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
697 and Basic analog */
698 case 77041:
699 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
700 and Basic analog */
701 case 77051:
702 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
703 and Basic analog */
704 case 78011:
705 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
706 Dual channel ATSC and MPEG2 HW Encoder */
707 case 78501:
708 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
709 Dual channel ATSC and MPEG2 HW Encoder */
710 case 78521:
711 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
712 Dual channel ATSC and MPEG2 HW Encoder */
713 case 78531:
714 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
715 Dual channel ATSC and MPEG2 HW Encoder */
716 case 78631:
717 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
718 Dual channel ATSC and MPEG2 HW Encoder */
719 case 79001:
720 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
721 ATSC and Basic analog */
722 case 79101:
723 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
724 ATSC and Basic analog */
ebbeb460
AW		 725 case 79501:
726 /* WinTV-HVR1250 (PCIe, No IR, half height,
727 ATSC [at least] and Basic analog) */
9c8ced51
ST		 728 case 79561:
729 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
730 ATSC and Basic analog */
731 case 79571:
732 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
733 ATSC and Basic analog */
734 case 79671:
735 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
736 ATSC and Basic analog */
66762373
ST		 737 case 80019:
738 /* WinTV-HVR1400 (Express Card, Retail, IR,
739 * DVB-T and Basic analog */
36396c89
MK		 740 case 81509:
741 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
742 * DVB-T and MPEG2 HW Encoder */
a780a31c 743 case 81519:
36396c89 744 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
a780a31c 745 * DVB-T and MPEG2 HW Encoder */
d19770e5 746 break;
13697380 747 case 85021:
73a5f419 748 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
13697380
ST		 749 Dual channel ATSC and MPEG2 HW Encoder */
750 break;
73a5f419
MK		 751 case 85721:
752 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
753 Dual channel ATSC and Basic analog */
754 break;
d19770e5 755 default:
13697380
ST		 756 printk(KERN_WARNING "%s: warning: "
757 "unknown hauppauge model #%d\n",
9c8ced51 758 dev->name, tv.model);
d19770e5
ST		 759 break;
760 }
761
762 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
763 dev->name, tv.model);
764}
765
d7cba043 766int cx23885_tuner_callback(void *priv, int component, int command, int arg)
8c70017f 767{
89ce2216
ST		 768 struct cx23885_tsport *port = priv;
769 struct cx23885_dev *dev = port->dev;
6df51690
ST		 770 u32 bitmask = 0;
771
89ce2216
ST		 772 if (command == XC2028_RESET_CLK)
773 return 0;
774
6df51690
ST		 775 if (command != 0) {
776 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
777 __func__, command);
778 return -EINVAL;
779 }
8c70017f 780
9c8ced51 781 switch (dev->board) {
90a71b1c
ST		 782 case CX23885_BOARD_HAUPPAUGE_HVR1400:
783 case CX23885_BOARD_HAUPPAUGE_HVR1500:
8c70017f 784 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
4c56b04a 785 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 786 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 787 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 788 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 789 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
90a71b1c 790 /* Tuner Reset Command */
4c56b04a 791 bitmask = 0x04;
6df51690
ST		 792 break;
793 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 794 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
4c56b04a
ST		 795 /* Two identical tuners on two different i2c buses,
796 * we need to reset the correct gpio. */
d4dc673d 797 if (port->nr == 1)
4c56b04a 798 bitmask = 0x01;
d4dc673d 799 else if (port->nr == 2)
4c56b04a 800 bitmask = 0x04;
8c70017f 801 break;
9028f58f
AC		 802 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
803 /* Tuner Reset Command */
804 bitmask = 0x02;
805 break;
78db8547
IL		 806 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
807 altera_ci_tuner_reset(dev, port->nr);
808 break;
8c70017f
ST		 809 }
810
6df51690
ST		 811 if (bitmask) {
812 /* Drive the tuner into reset and back out */
813 cx_clear(GP0_IO, bitmask);
814 mdelay(200);
815 cx_set(GP0_IO, bitmask);
816 }
817
818 return 0;
8c70017f 819}
73c993a8 820
a6a3f140
ST		 821void cx23885_gpio_setup(struct cx23885_dev *dev)
822{
9c8ced51 823 switch (dev->board) {
a6a3f140
ST		 824 case CX23885_BOARD_HAUPPAUGE_HVR1250:
825 /* GPIO-0 cx24227 demodulator reset */
826 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
827 break;
07b4a835
MK		 828 case CX23885_BOARD_HAUPPAUGE_HVR1500:
829 /* GPIO-0 cx24227 demodulator */
830 /* GPIO-2 xc3028 tuner */
831
832 /* Put the parts into reset */
833 cx_set(GP0_IO, 0x00050000);
834 cx_clear(GP0_IO, 0x00000005);
835 msleep(5);
836
837 /* Bring the parts out of reset */
838 cx_set(GP0_IO, 0x00050005);
839 break;
d1987d55
ST		 840 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
841 /* GPIO-0 cx24227 demodulator reset */
842 /* GPIO-2 xc5000 tuner reset */
843 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
844 break;
a6a3f140
ST		 845 case CX23885_BOARD_HAUPPAUGE_HVR1800:
846 /* GPIO-0 656_CLK */
847 /* GPIO-1 656_D0 */
848 /* GPIO-2 8295A Reset */
849 /* GPIO-3-10 cx23417 data0-7 */
850 /* GPIO-11-14 cx23417 addr0-3 */
851 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
852 /* GPIO-19 IR_RX */
3ba71d21 853
a589b665
ST		 854 /* CX23417 GPIO's */
855 /* EIO15 Zilog Reset */
856 /* EIO14 S5H1409/CX24227 Reset */
f659c513
ST		 857 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
858
859 /* Put the demod into reset and protect the eeprom */
860 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
861 mdelay(100);
862
863 /* Bring the demod and blaster out of reset */
864 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
865 mdelay(100);
a589b665 866
5206d6ec 867 /* Force the TDA8295A into reset and back */
21ff3e4f
ST		 868 cx23885_gpio_enable(dev, GPIO_2, 1);
869 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 870 mdelay(20);
21ff3e4f 871 cx23885_gpio_clear(dev, GPIO_2);
5206d6ec 872 mdelay(20);
21ff3e4f 873 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 874 mdelay(20);
a6a3f140 875 break;
b3ea0166
ST		 876 case CX23885_BOARD_HAUPPAUGE_HVR1200:
877 /* GPIO-0 tda10048 demodulator reset */
878 /* GPIO-2 tda18271 tuner reset */
879
a780a31c
ST		 880 /* Put the parts into reset and back */
881 cx_set(GP0_IO, 0x00050000);
882 mdelay(20);
883 cx_clear(GP0_IO, 0x00000005);
884 mdelay(20);
885 cx_set(GP0_IO, 0x00050005);
886 break;
887 case CX23885_BOARD_HAUPPAUGE_HVR1700:
888 /* GPIO-0 TDA10048 demodulator reset */
889 /* GPIO-2 TDA8295A Reset */
890 /* GPIO-3-10 cx23417 data0-7 */
891 /* GPIO-11-14 cx23417 addr0-3 */
892 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
893
894 /* The following GPIO's are on the interna AVCore (cx25840) */
895 /* GPIO-19 IR_RX */
896 /* GPIO-20 IR_TX 416/DVBT Select */
897 /* GPIO-21 IIS DAT */
898 /* GPIO-22 IIS WCLK */
899 /* GPIO-23 IIS BCLK */
900
66762373
ST		 901 /* Put the parts into reset and back */
902 cx_set(GP0_IO, 0x00050000);
903 mdelay(20);
904 cx_clear(GP0_IO, 0x00000005);
905 mdelay(20);
906 cx_set(GP0_IO, 0x00050005);
907 break;
908 case CX23885_BOARD_HAUPPAUGE_HVR1400:
909 /* GPIO-0 Dibcom7000p demodulator reset */
910 /* GPIO-2 xc3028L tuner reset */
911 /* GPIO-13 LED */
912
b3ea0166
ST		 913 /* Put the parts into reset and back */
914 cx_set(GP0_IO, 0x00050000);
915 mdelay(20);
916 cx_clear(GP0_IO, 0x00000005);
917 mdelay(20);
918 cx_set(GP0_IO, 0x00050005);
919 break;
1ecc5aed
ST		 920 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
921 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
922 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
923 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
924 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
925
aef2d186
ST		 926 /* Put the parts into reset and back */
927 cx_set(GP0_IO, 0x000f0000);
928 mdelay(20);
929 cx_clear(GP0_IO, 0x0000000f);
930 mdelay(20);
931 cx_set(GP0_IO, 0x000f000f);
932 break;
933 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
934 /* GPIO-0 portb xc3028 reset */
935 /* GPIO-1 portb zl10353 reset */
936 /* GPIO-2 portc xc3028 reset */
937 /* GPIO-3 portc zl10353 reset */
938
1ecc5aed
ST		 939 /* Put the parts into reset and back */
940 cx_set(GP0_IO, 0x000f0000);
941 mdelay(20);
942 cx_clear(GP0_IO, 0x0000000f);
943 mdelay(20);
944 cx_set(GP0_IO, 0x000f000f);
945 break;
4c56b04a 946 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 947 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 948 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 949 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 950 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
4c56b04a
ST		 951 /* GPIO-2 xc3028 tuner reset */
952
953 /* The following GPIO's are on the internal AVCore (cx25840) */
954 /* GPIO-? zl10353 demod reset */
955
956 /* Put the parts into reset and back */
957 cx_set(GP0_IO, 0x00040000);
958 mdelay(20);
959 cx_clear(GP0_IO, 0x00000004);
960 mdelay(20);
961 cx_set(GP0_IO, 0x00040004);
962 break;
96318d0c
IL		 963 case CX23885_BOARD_TBS_6920:
964 cx_write(MC417_CTL, 0x00000036);
965 cx_write(MC417_OEN, 0x00001000);
09ea33e5
IL		 966 cx_set(MC417_RWD, 0x00000002);
967 mdelay(200);
968 cx_clear(MC417_RWD, 0x00000800);
969 mdelay(200);
970 cx_set(MC417_RWD, 0x00000800);
971 mdelay(200);
96318d0c 972 break;
5a23b076
IL		 973 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
974 /* GPIO-0 INTA from CiMax1
975 GPIO-1 INTB from CiMax2
976 GPIO-2 reset chips
977 GPIO-3 to GPIO-10 data/addr for CA
978 GPIO-11 ~CS0 to CiMax1
979 GPIO-12 ~CS1 to CiMax2
980 GPIO-13 ADL0 load LSB addr
981 GPIO-14 ADL1 load MSB addr
982 GPIO-15 ~RDY from CiMax
983 GPIO-17 ~RD to CiMax
984 GPIO-18 ~WR to CiMax
985 */
986 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
987 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
988 cx_clear(GP0_IO, 0x00030004);
989 mdelay(100);/* reset delay */
990 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
991 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
992 /* GPIO-15 IN as ~ACK, rest as OUT */
993 cx_write(MC417_OEN, 0x00001000);
994 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
995 cx_write(MC417_RWD, 0x0000c300);
996 /* enable irq */
997 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
998 break;
2074dffa 999 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1000 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1001 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 1002 case CX23885_BOARD_HAUPPAUGE_HVR1210:
d099becb 1003 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
6b926eca
MK		 1004 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1005 /* GPIO-9 Demod reset */
2074dffa
ST		 1006
1007 /* Put the parts into reset and back */
d099becb
MK		 1008 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1009 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
2074dffa
ST		 1010 cx23885_gpio_clear(dev, GPIO_9);
1011 mdelay(20);
1012 cx23885_gpio_set(dev, GPIO_9);
1013 break;
493b7127 1014 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 1015 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
8e069bb9 1016 /* GPIO-0 (0)Analog / (1)Digital TV */
493b7127 1017 /* GPIO-1 reset XC5000 */
2365b2d3 1018 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
8e069bb9
DW		 1019 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1020 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
493b7127 1021 mdelay(100);
8e069bb9 1022 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
493b7127
DW		 1023 mdelay(100);
1024 break;
ea5697fe
DW		 1025 case CX23885_BOARD_MYGICA_X8558PRO:
1026 /* GPIO-0 reset first ATBM8830 */
1027 /* GPIO-1 reset second ATBM8830 */
1028 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1029 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1030 mdelay(100);
1031 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1032 mdelay(100);
1033 break;
13697380 1034 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1035 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1036 /* GPIO-0 656_CLK */
1037 /* GPIO-1 656_D0 */
1038 /* GPIO-2 Wake# */
1039 /* GPIO-3-10 cx23417 data0-7 */
1040 /* GPIO-11-14 cx23417 addr0-3 */
1041 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1042 /* GPIO-19 IR_RX */
1043 /* GPIO-20 C_IR_TX */
1044 /* GPIO-21 I2S DAT */
1045 /* GPIO-22 I2S WCLK */
1046 /* GPIO-23 I2S BCLK */
1047 /* ALT GPIO: EXP GPIO LATCH */
1048
1049 /* CX23417 GPIO's */
1050 /* GPIO-14 S5H1411/CX24228 Reset */
1051 /* GPIO-13 EEPROM write protect */
1052 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1053
1054 /* Put the demod into reset and protect the eeprom */
1055 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1056 mdelay(100);
1057
1058 /* Bring the demod out of reset */
1059 mc417_gpio_set(dev, GPIO_14);
1060 mdelay(100);
1061
1062 /* CX24228 GPIO */
1063 /* Connected to IF / Mux */
1064 break;
9028f58f
AC		 1065 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1066 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1067 break;
78db8547
IL		 1068 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1069 /* GPIO-0 ~INT in
1070 GPIO-1 TMS out
1071 GPIO-2 ~reset chips out
1072 GPIO-3 to GPIO-10 data/addr for CA in/out
1073 GPIO-11 ~CS out
1074 GPIO-12 ADDR out
1075 GPIO-13 ~WR out
1076 GPIO-14 ~RD out
1077 GPIO-15 ~RDY in
1078 GPIO-16 TCK out
1079 GPIO-17 TDO in
1080 GPIO-18 TDI out
1081 */
1082 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1083 /* GPIO-0 as INT, reset & TMS low */
1084 cx_clear(GP0_IO, 0x00010006);
1085 mdelay(100);/* reset delay */
1086 cx_set(GP0_IO, 0x00000004); /* reset high */
1087 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1088 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1089 cx_write(MC417_OEN, 0x00005000);
1090 /* ~RD, ~WR high; ADDR low; ~CS high */
1091 cx_write(MC417_RWD, 0x00000d00);
1092 /* enable irq */
1093 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1094 break;
a6a3f140
ST		 1095 }
1096}
1097
1098int cx23885_ir_init(struct cx23885_dev *dev)
1099{
98d109f9 1100 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
81f287da
AW		 1101 {
1102 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1103 .pin = CX23885_PIN_IR_RX_GPIO19,
1104 .function = CX23885_PAD_IR_RX,
1105 .value = 0,
1106 .strength = CX25840_PIN_DRIVE_MEDIUM,
1107 }, {
1108 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1109 .pin = CX23885_PIN_IR_TX_GPIO20,
1110 .function = CX23885_PAD_IR_TX,
1111 .value = 0,
1112 .strength = CX25840_PIN_DRIVE_MEDIUM,
1113 }
1114 };
98d109f9
AW		 1115 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1116
1117 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1118 {
1119 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1120 .pin = CX23885_PIN_IR_RX_GPIO19,
1121 .function = CX23885_PAD_IR_RX,
1122 .value = 0,
1123 .strength = CX25840_PIN_DRIVE_MEDIUM,
1124 }
1125 };
1126 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
81f287da
AW		 1127
1128 struct v4l2_subdev_ir_parameters params;
29f8a0a5 1129 int ret = 0;
a6a3f140 1130 switch (dev->board) {
07b4a835 1131 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1132 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 1133 case CX23885_BOARD_HAUPPAUGE_HVR1800:
b3ea0166 1134 case CX23885_BOARD_HAUPPAUGE_HVR1200:
66762373 1135 case CX23885_BOARD_HAUPPAUGE_HVR1400:
d099becb 1136 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1137 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 1138 case CX23885_BOARD_HAUPPAUGE_HVR1210:
a6a3f140
ST		 1139 /* FIXME: Implement me */
1140 break;
9b3d8ecc
AW		 1141 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1142 ret = cx23888_ir_probe(dev);
1143 if (ret)
1144 break;
1145 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1146 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1147 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1148 break;
29f8a0a5 1149 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1150 case CX23885_BOARD_HAUPPAUGE_HVR1290:
29f8a0a5
AW		 1151 ret = cx23888_ir_probe(dev);
1152 if (ret)
1153 break;
1154 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
81f287da 1155 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
98d109f9 1156 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
81f287da
AW		 1157 /*
1158 * For these boards we need to invert the Tx output via the
1159 * IR controller to have the LED off while idle
1160 */
1161 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1162 params.enable = false;
1163 params.shutdown = false;
1164 params.invert_level = true;
1165 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1166 params.shutdown = true;
1167 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
29f8a0a5 1168 break;
98d109f9 1169 case CX23885_BOARD_TEVII_S470:
fa647f24
AW		 1170 if (!enable_885_ir)
1171 break;
98d109f9
AW		 1172 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1173 if (dev->sd_ir == NULL) {
1174 ret = -ENODEV;
1175 break;
1176 }
1177 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1178 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
98d109f9
AW		 1179 break;
1180 case CX23885_BOARD_HAUPPAUGE_HVR1250:
fa647f24
AW		 1181 if (!enable_885_ir)
1182 break;
98d109f9
AW		 1183 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1184 if (dev->sd_ir == NULL) {
1185 ret = -ENODEV;
1186 break;
1187 }
1188 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1189 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
98d109f9 1190 break;
12886871
ST		 1191 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1192 request_module("ir-kbd-i2c");
1193 break;
a6a3f140
ST		 1194 }
1195
29f8a0a5 1196 return ret;
a6a3f140
ST		 1197}
1198
f59ad611
AW		 1199void cx23885_ir_fini(struct cx23885_dev *dev)
1200{
1201 switch (dev->board) {
9b3d8ecc 1202 case CX23885_BOARD_HAUPPAUGE_HVR1270:
f59ad611 1203 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1204 case CX23885_BOARD_HAUPPAUGE_HVR1290:
dbe83a3b 1205 cx23885_irq_remove(dev, PCI_MSK_IR);
f59ad611
AW		 1206 cx23888_ir_remove(dev);
1207 dev->sd_ir = NULL;
1208 break;
98d109f9
AW		 1209 case CX23885_BOARD_TEVII_S470:
1210 case CX23885_BOARD_HAUPPAUGE_HVR1250:
dbe83a3b 1211 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
98d109f9
AW		 1212 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1213 dev->sd_ir = NULL;
1214 break;
f59ad611
AW		 1215 }
1216}
1217
78db8547
IL		 1218int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1219{
1220 int data;
1221 int tdo = 0;
1222 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1223 /*TMS*/
1224 data = ((cx_read(GP0_IO)) & (~0x00000002));
1225 data |= (tms ? 0x00020002 : 0x00020000);
1226 cx_write(GP0_IO, data);
1227
1228 /*TDI*/
1229 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1230 data |= (tdi ? 0x00008000 : 0);
1231 cx_write(MC417_RWD, data);
1232 if (read_tdo)
1233 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1234
1235 cx_write(MC417_RWD, data | 0x00002000);
1236 udelay(1);
1237 /*TCK*/
1238 cx_write(MC417_RWD, data);
1239
1240 return tdo;
1241}
1242
f59ad611
AW		 1243void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1244{
1245 switch (dev->board) {
9b3d8ecc 1246 case CX23885_BOARD_HAUPPAUGE_HVR1270:
f59ad611 1247 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1248 case CX23885_BOARD_HAUPPAUGE_HVR1290:
dbe83a3b
AW		 1249 if (dev->sd_ir)
1250 cx23885_irq_add_enable(dev, PCI_MSK_IR);
f59ad611 1251 break;
98d109f9
AW		 1252 case CX23885_BOARD_TEVII_S470:
1253 case CX23885_BOARD_HAUPPAUGE_HVR1250:
dbe83a3b
AW		 1254 if (dev->sd_ir)
1255 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
98d109f9 1256 break;
f59ad611
AW		 1257 }
1258}
1259
d19770e5
ST		 1260void cx23885_card_setup(struct cx23885_dev *dev)
1261{
a6a3f140
ST		 1262 struct cx23885_tsport *ts1 = &dev->ts1;
1263 struct cx23885_tsport *ts2 = &dev->ts2;
1264
d19770e5
ST		 1265 static u8 eeprom[256];
1266
1267 if (dev->i2c_bus[0].i2c_rc == 0) {
1268 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
44a6481d
MK		 1269 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1270 eeprom, sizeof(eeprom));
d19770e5
ST		 1271 }
1272
1273 switch (dev->board) {
a77743bc 1274 case CX23885_BOARD_HAUPPAUGE_HVR1250:
ebbeb460
AW		 1275 if (dev->i2c_bus[0].i2c_rc == 0) {
1276 if (eeprom[0x80] != 0x84)
1277 hauppauge_eeprom(dev, eeprom+0xc0);
1278 else
1279 hauppauge_eeprom(dev, eeprom+0x80);
1280 }
1281 break;
07b4a835 1282 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1283 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
66762373 1284 case CX23885_BOARD_HAUPPAUGE_HVR1400:
c88133ec
ST		 1285 if (dev->i2c_bus[0].i2c_rc == 0)
1286 hauppauge_eeprom(dev, eeprom+0x80);
1287 break;
d19770e5
ST		 1288 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1289 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1290 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1291 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2074dffa 1292 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1293 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1294 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 1295 case CX23885_BOARD_HAUPPAUGE_HVR1210:
13697380 1296 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1297 case CX23885_BOARD_HAUPPAUGE_HVR1290:
d19770e5 1298 if (dev->i2c_bus[0].i2c_rc == 0)
c88133ec 1299 hauppauge_eeprom(dev, eeprom+0xc0);
d19770e5
ST		 1300 break;
1301 }
a6a3f140
ST		 1302
1303 switch (dev->board) {
335377b7 1304 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 1305 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
335377b7
MK		 1306 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1307 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1308 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1309 /* break omitted intentionally */
a6a3f140
ST		 1310 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1311 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1312 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1313 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1314 break;
a589b665
ST		 1315 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1316 /* Defaults for VID B - Analog encoder */
1317 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1318 ts1->gen_ctrl_val = 0x10e;
1319 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1320 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1321
1322 /* APB_TSVALERR_POL (active low)*/
1323 ts1->vld_misc_val = 0x2000;
1324 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1325
1326 /* Defaults for VID C */
1327 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1328 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1329 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
96318d0c
IL		 1330 break;
1331 case CX23885_BOARD_TBS_6920:
09ea33e5
IL		 1332 ts1->gen_ctrl_val = 0x4; /* Parallel */
1333 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1334 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1335 break;
1336 case CX23885_BOARD_TEVII_S470:
c9b8b04b 1337 case CX23885_BOARD_DVBWORLD_2005:
96318d0c
IL		 1338 ts1->gen_ctrl_val = 0x5; /* Parallel */
1339 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1340 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
a589b665 1341 break;
5a23b076 1342 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
78db8547 1343 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
5a23b076
IL		 1344 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1345 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1346 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1347 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1348 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1349 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1350 break;
493b7127 1351 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 1352 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
493b7127
DW		 1353 ts1->gen_ctrl_val = 0x5; /* Parallel */
1354 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1355 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1356 break;
ea5697fe
DW		 1357 case CX23885_BOARD_MYGICA_X8558PRO:
1358 ts1->gen_ctrl_val = 0x5; /* Parallel */
1359 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1360 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1361 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1362 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1363 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1364 break;
a6a3f140 1365 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 1366 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1367 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 1368 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1369 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1370 case CX23885_BOARD_HAUPPAUGE_HVR1700:
66762373 1371 case CX23885_BOARD_HAUPPAUGE_HVR1400:
4c56b04a 1372 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1373 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1374 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2074dffa 1375 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1376 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1377 case CX23885_BOARD_HAUPPAUGE_HVR1255:
6b926eca 1378 case CX23885_BOARD_HAUPPAUGE_HVR1210:
13697380 1379 case CX23885_BOARD_HAUPPAUGE_HVR1850:
34e383dd 1380 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
aee0b24c 1381 case CX23885_BOARD_HAUPPAUGE_HVR1290:
9028f58f 1382 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
a6a3f140
ST		 1383 default:
1384 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1385 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1386 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1387 }
1388
ce89cfb4
ST		 1389 /* Certain boards support analog, or require the avcore to be
1390 * loaded, ensure this happens.
1391 */
1392 switch (dev->board) {
fa647f24
AW		 1393 case CX23885_BOARD_TEVII_S470:
1394 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1395 /* Currently only enabled for the integrated IR controller */
1396 if (!enable_885_ir)
1397 break;
ce89cfb4
ST		 1398 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1399 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1400 case CX23885_BOARD_HAUPPAUGE_HVR1700:
4c56b04a 1401 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1402 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1403 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
5a23b076 1404 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
78db8547 1405 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
34e383dd 1406 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
9b3d8ecc 1407 case CX23885_BOARD_HAUPPAUGE_HVR1270:
c6b7053b 1408 case CX23885_BOARD_HAUPPAUGE_HVR1850:
bc1548ad
DW		 1409 case CX23885_BOARD_MYGICA_X8506:
1410 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
aee0b24c 1411 case CX23885_BOARD_HAUPPAUGE_HVR1290:
0b32d65c 1412 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
9028f58f 1413 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
e6574f2f
HV		 1414 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1415 &dev->i2c_bus[2].i2c_adap,
9a1f8b34 1416 "cx25840", 0x88 >> 1, NULL);
d6b1850d
AW		 1417 if (dev->sd_cx25840) {
1418 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1419 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1420 }
ce89cfb4
ST		 1421 break;
1422 }
5a23b076
IL		 1423
1424 /* AUX-PLL 27MHz CLK */
1425 switch (dev->board) {
1426 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1427 netup_initialize(dev);
1428 break;
78db8547
IL		 1429 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1430 int ret;
1431 const struct firmware *fw;
1432 const char *filename = "dvb-netup-altera-01.fw";
1433 char *action = "configure";
b8f0d306 1434 static struct netup_card_info cinfo;
78db8547
IL		 1435 struct altera_config netup_config = {
1436 .dev = dev,
1437 .action = action,
1438 .jtag_io = netup_jtag_io,
1439 };
1440
1441 netup_initialize(dev);
1442
b8f0d306
AO		 1443 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1444 switch (cinfo.rev) {
1445 case 0x4:
1446 filename = "dvb-netup-altera-04.fw";
1447 break;
1448 default:
1449 filename = "dvb-netup-altera-01.fw";
1450 break;
1451 }
1452 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1453 cinfo.rev, filename);
1454
78db8547
IL		 1455 ret = request_firmware(&fw, filename, &dev->pci->dev);
1456 if (ret != 0)
1457 printk(KERN_ERR "did not find the firmware file. (%s) "
1458 "Please see linux/Documentation/dvb/ for more details "
1459 "on firmware-problems.", filename);
1460 else
1461 altera_init(&netup_config, fw);
1462
3f84a4e1 1463 release_firmware(fw);
78db8547
IL		 1464 break;
1465 }
5a23b076 1466 }
d19770e5
ST		 1467}
1468
1469/* ------------------------------------------------------------------ */
Linux kernel - Deliverables
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