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V4L/DVB (8466): cx23885: Bugfix - DVB Transport cards using DVB port VIDB/TS1 did...
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-core.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kmod.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <asm/div64.h>
32
33#include "cx23885.h"
34
35MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37MODULE_LICENSE("GPL");
38
4513fc69 39static unsigned int debug;
d19770e5
ST		 40module_param(debug,int,0644);
41MODULE_PARM_DESC(debug,"enable debug messages");
42
43static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44module_param_array(card, int, NULL, 0444);
45MODULE_PARM_DESC(card,"card type");
46
4513fc69
ST		 47#define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
50 } while (0)
d19770e5
ST		 51
52static unsigned int cx23885_devcount;
53
54static DEFINE_MUTEX(devlist);
7b888014 55LIST_HEAD(cx23885_devlist);
d19770e5
ST		 56
57#define NO_SYNC_LINE (-1U)
58
d19770e5
ST		 59/* FIXME, these allocations will change when
60 * analog arrives. The be reviewed.
61 * CX23887 Assumptions
62 * 1 line = 16 bytes of CDT
63 * cmds size = 80
64 * cdt size = 16 * linesize
65 * iqsize = 64
66 * maxlines = 6
67 *
68 * Address Space:
69 * 0x00000000 0x00008fff FIFO clusters
70 * 0x00010000 0x000104af Channel Management Data Structures
71 * 0x000104b0 0x000104ff Free
72 * 0x00010500 0x000108bf 15 channels * iqsize
73 * 0x000108c0 0x000108ff Free
74 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
75 * 15 channels * (iqsize + (maxlines * linesize))
76 * 0x00010ea0 0x00010xxx Free
77 */
78
39e75cfe 79static struct sram_channel cx23887_sram_channels[] = {
d19770e5 80 [SRAM_CH01] = {
69ad6e56
ST		 81 .name = "VID A",
82 .cmds_start = 0x10000,
83 .ctrl_start = 0x105b0,
84 .cdt = 0x107b0,
85 .fifo_start = 0x40,
86 .fifo_size = 0x2800,
d19770e5
ST		 87 .ptr1_reg = DMA1_PTR1,
88 .ptr2_reg = DMA1_PTR2,
89 .cnt1_reg = DMA1_CNT1,
90 .cnt2_reg = DMA1_CNT2,
91 },
92 [SRAM_CH02] = {
93 .name = "ch2",
94 .cmds_start = 0x0,
95 .ctrl_start = 0x0,
96 .cdt = 0x0,
97 .fifo_start = 0x0,
98 .fifo_size = 0x0,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
103 },
104 [SRAM_CH03] = {
69ad6e56
ST		 105 .name = "TS1 B",
106 .cmds_start = 0x100A0,
28901ab6
ST		 107 .ctrl_start = 0x10670,
108 .cdt = 0x10810,
69ad6e56
ST		 109 .fifo_start = 0x5000,
110 .fifo_size = 0x1000,
d19770e5
ST		 111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
115 },
116 [SRAM_CH04] = {
117 .name = "ch4",
118 .cmds_start = 0x0,
119 .ctrl_start = 0x0,
120 .cdt = 0x0,
121 .fifo_start = 0x0,
122 .fifo_size = 0x0,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
127 },
128 [SRAM_CH05] = {
129 .name = "ch5",
130 .cmds_start = 0x0,
131 .ctrl_start = 0x0,
132 .cdt = 0x0,
133 .fifo_start = 0x0,
134 .fifo_size = 0x0,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
139 },
140 [SRAM_CH06] = {
141 .name = "TS2 C",
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10680,
3bd40659 144 .cdt = 0x108d0,
d19770e5
ST		 145 .fifo_start = 0x6000,
146 .fifo_size = 0x1000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
151 },
152 [SRAM_CH07] = {
153 .name = "ch7",
154 .cmds_start = 0x0,
155 .ctrl_start = 0x0,
156 .cdt = 0x0,
157 .fifo_start = 0x0,
158 .fifo_size = 0x0,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
163 },
164 [SRAM_CH08] = {
165 .name = "ch8",
166 .cmds_start = 0x0,
167 .ctrl_start = 0x0,
168 .cdt = 0x0,
169 .fifo_start = 0x0,
170 .fifo_size = 0x0,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 },
176 [SRAM_CH09] = {
177 .name = "ch9",
178 .cmds_start = 0x0,
179 .ctrl_start = 0x0,
180 .cdt = 0x0,
181 .fifo_start = 0x0,
182 .fifo_size = 0x0,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
187 },
188};
189
190static int cx23885_risc_decode(u32 risc)
191{
192 static char *instr[16] = {
b1b81f1d
ST		 193 [RISC_SYNC >> 28] = "sync",
194 [RISC_WRITE >> 28] = "write",
195 [RISC_WRITEC >> 28] = "writec",
196 [RISC_READ >> 28] = "read",
197 [RISC_READC >> 28] = "readc",
198 [RISC_JUMP >> 28] = "jump",
199 [RISC_SKIP >> 28] = "skip",
200 [RISC_WRITERM >> 28] = "writerm",
201 [RISC_WRITECM >> 28] = "writecm",
202 [RISC_WRITECR >> 28] = "writecr",
d19770e5
ST		 203 };
204 static int incr[16] = {
b1b81f1d
ST		 205 [RISC_WRITE >> 28] = 3,
206 [RISC_JUMP >> 28] = 3,
207 [RISC_SKIP >> 28] = 1,
208 [RISC_SYNC >> 28] = 1,
209 [RISC_WRITERM >> 28] = 3,
210 [RISC_WRITECM >> 28] = 3,
211 [RISC_WRITECR >> 28] = 4,
d19770e5
ST		 212 };
213 static char *bits[] = {
214 "12", "13", "14", "resync",
215 "cnt0", "cnt1", "18", "19",
216 "20", "21", "22", "23",
217 "irq1", "irq2", "eol", "sol",
218 };
219 int i;
220
221 printk("0x%08x [ %s", risc,
222 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
44a6481d 223 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
d19770e5 224 if (risc & (1 << (i + 12)))
44a6481d 225 printk(" %s", bits[i]);
d19770e5
ST		 226 printk(" count=%d ]\n", risc & 0xfff);
227 return incr[risc >> 28] ? incr[risc >> 28] : 1;
228}
229
7b888014 230void cx23885_wakeup(struct cx23885_tsport *port,
39e75cfe 231 struct cx23885_dmaqueue *q, u32 count)
d19770e5
ST		 232{
233 struct cx23885_dev *dev = port->dev;
234 struct cx23885_buffer *buf;
235 int bc;
236
237 for (bc = 0;; bc++) {
238 if (list_empty(&q->active))
239 break;
240 buf = list_entry(q->active.next,
241 struct cx23885_buffer, vb.queue);
2e52f215 242
d19770e5
ST		 243 /* count comes from the hw and is is 16bit wide --
244 * this trick handles wrap-arounds correctly for
245 * up to 32767 buffers in flight... */
246 if ((s16) (count - buf->count) < 0)
247 break;
2e52f215 248
d19770e5 249 do_gettimeofday(&buf->vb.ts);
44a6481d 250 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
d19770e5 251 count, buf->count);
0fc0686e 252 buf->vb.state = VIDEOBUF_DONE;
d19770e5
ST		 253 list_del(&buf->vb.queue);
254 wake_up(&buf->vb.done);
255 }
256 if (list_empty(&q->active)) {
257 del_timer(&q->timeout);
258 } else {
44a6481d 259 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 260 }
261 if (bc != 1)
44a6481d 262 printk("%s: %d buffers handled (should be 1)\n",
22b4e64f 263 __func__, bc);
d19770e5 264}
d19770e5 265
7b888014 266int cx23885_sram_channel_setup(struct cx23885_dev *dev,
39e75cfe
AB		 267 struct sram_channel *ch,
268 unsigned int bpl, u32 risc)
d19770e5 269{
44a6481d 270 unsigned int i, lines;
d19770e5
ST		 271 u32 cdt;
272
273 if (ch->cmds_start == 0)
274 {
22b4e64f 275 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
44a6481d 276 ch->name);
d19770e5
ST		 277 cx_write(ch->ptr1_reg, 0);
278 cx_write(ch->ptr2_reg, 0);
279 cx_write(ch->cnt2_reg, 0);
280 cx_write(ch->cnt1_reg, 0);
281 return 0;
282 } else {
22b4e64f 283 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
44a6481d 284 ch->name);
d19770e5
ST		 285 }
286
287 bpl = (bpl + 7) & ~7; /* alignment */
288 cdt = ch->cdt;
289 lines = ch->fifo_size / bpl;
290 if (lines > 6)
291 lines = 6;
292 BUG_ON(lines < 2);
293
86ecc027
AV		 294 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
295 cx_write(8 + 4, 8);
296 cx_write(8 + 8, 0);
d19770e5
ST		 297
298 /* write CDT */
299 for (i = 0; i < lines; i++) {
22b4e64f 300 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
44a6481d 301 ch->fifo_start + bpl*i);
d19770e5
ST		 302 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
303 cx_write(cdt + 16*i + 4, 0);
304 cx_write(cdt + 16*i + 8, 0);
305 cx_write(cdt + 16*i + 12, 0);
306 }
307
308 /* write CMDS */
309 if (ch->jumponly)
310 cx_write(ch->cmds_start + 0, 8);
311 else
312 cx_write(ch->cmds_start + 0, risc);
313 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
314 cx_write(ch->cmds_start + 8, cdt);
315 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
316 cx_write(ch->cmds_start + 16, ch->ctrl_start);
317 if (ch->jumponly)
318 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
319 else
320 cx_write(ch->cmds_start + 20, 64 >> 2);
321 for (i = 24; i < 80; i += 4)
322 cx_write(ch->cmds_start + i, 0);
323
324 /* fill registers */
325 cx_write(ch->ptr1_reg, ch->fifo_start);
326 cx_write(ch->ptr2_reg, cdt);
327 cx_write(ch->cnt2_reg, (lines*16) >> 3);
328 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
329
e133be0f
ST		 330 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
331 dev->bridge,
d19770e5
ST		 332 ch->name,
333 bpl,
334 lines);
335
336 return 0;
337}
338
7b888014 339void cx23885_sram_channel_dump(struct cx23885_dev *dev,
39e75cfe 340 struct sram_channel *ch)
d19770e5
ST		 341{
342 static char *name[] = {
343 "init risc lo",
344 "init risc hi",
345 "cdt base",
346 "cdt size",
347 "iq base",
348 "iq size",
349 "risc pc lo",
350 "risc pc hi",
351 "iq wr ptr",
352 "iq rd ptr",
353 "cdt current",
354 "pci target lo",
355 "pci target hi",
356 "line / byte",
357 };
358 u32 risc;
44a6481d 359 unsigned int i, j, n;
d19770e5
ST		 360
361 printk("%s: %s - dma channel status dump\n",
362 dev->name, ch->name);
363 for (i = 0; i < ARRAY_SIZE(name); i++)
364 printk("%s: cmds: %-15s: 0x%08x\n",
365 dev->name, name[i],
366 cx_read(ch->cmds_start + 4*i));
367
368 for (i = 0; i < 4; i++) {
44a6481d 369 risc = cx_read(ch->cmds_start + 4 * (i + 14));
d19770e5
ST		 370 printk("%s: risc%d: ", dev->name, i);
371 cx23885_risc_decode(risc);
372 }
373 for (i = 0; i < (64 >> 2); i += n) {
44a6481d
MK		 374 risc = cx_read(ch->ctrl_start + 4 * i);
375 /* No consideration for bits 63-32 */
376
377 printk("%s: (0x%08x) iq %x: ", dev->name,
378 ch->ctrl_start + 4 * i, i);
d19770e5
ST		 379 n = cx23885_risc_decode(risc);
380 for (j = 1; j < n; j++) {
44a6481d 381 risc = cx_read(ch->ctrl_start + 4 * (i + j));
d19770e5
ST		 382 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
383 dev->name, i+j, risc, j);
384 }
385 }
386
387 printk("%s: fifo: 0x%08x -> 0x%x\n",
388 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
389 printk("%s: ctrl: 0x%08x -> 0x%x\n",
44a6481d 390 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
d19770e5
ST		 391 printk("%s: ptr1_reg: 0x%08x\n",
392 dev->name, cx_read(ch->ptr1_reg));
393 printk("%s: ptr2_reg: 0x%08x\n",
394 dev->name, cx_read(ch->ptr2_reg));
395 printk("%s: cnt1_reg: 0x%08x\n",
396 dev->name, cx_read(ch->cnt1_reg));
397 printk("%s: cnt2_reg: 0x%08x\n",
398 dev->name, cx_read(ch->cnt2_reg));
399}
400
39e75cfe
AB		 401static void cx23885_risc_disasm(struct cx23885_tsport *port,
402 struct btcx_riscmem *risc)
d19770e5
ST		 403{
404 struct cx23885_dev *dev = port->dev;
44a6481d 405 unsigned int i, j, n;
d19770e5
ST		 406
407 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
408 dev->name, risc->cpu, (unsigned long)risc->dma);
409 for (i = 0; i < (risc->size >> 2); i += n) {
410 printk("%s: %04d: ", dev->name, i);
86ecc027 411 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
d19770e5
ST		 412 for (j = 1; j < n; j++)
413 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
44a6481d 414 dev->name, i + j, risc->cpu[i + j], j);
86ecc027 415 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
d19770e5
ST		 416 break;
417 }
418}
419
39e75cfe 420static void cx23885_shutdown(struct cx23885_dev *dev)
d19770e5
ST		 421{
422 /* disable RISC controller */
423 cx_write(DEV_CNTRL2, 0);
424
425 /* Disable all IR activity */
426 cx_write(IR_CNTRL_REG, 0);
427
428 /* Disable Video A/B activity */
429 cx_write(VID_A_DMA_CTL, 0);
430 cx_write(VID_B_DMA_CTL, 0);
431 cx_write(VID_C_DMA_CTL, 0);
432
433 /* Disable Audio activity */
434 cx_write(AUD_INT_DMA_CTL, 0);
435 cx_write(AUD_EXT_DMA_CTL, 0);
436
437 /* Disable Serial port */
438 cx_write(UART_CTL, 0);
439
440 /* Disable Interrupts */
441 cx_write(PCI_INT_MSK, 0);
442 cx_write(VID_A_INT_MSK, 0);
443 cx_write(VID_B_INT_MSK, 0);
444 cx_write(VID_C_INT_MSK, 0);
445 cx_write(AUDIO_INT_INT_MSK, 0);
446 cx_write(AUDIO_EXT_INT_MSK, 0);
447
448}
449
39e75cfe 450static void cx23885_reset(struct cx23885_dev *dev)
d19770e5 451{
22b4e64f 452 dprintk(1, "%s()\n", __func__);
d19770e5
ST		 453
454 cx23885_shutdown(dev);
455
456 cx_write(PCI_INT_STAT, 0xffffffff);
457 cx_write(VID_A_INT_STAT, 0xffffffff);
458 cx_write(VID_B_INT_STAT, 0xffffffff);
459 cx_write(VID_C_INT_STAT, 0xffffffff);
460 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
461 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
462 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
ecda5966 463 cx_write(PAD_CTRL, 0x00500300);
d19770e5
ST		 464
465 mdelay(100);
466
7b888014
ST		 467 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
468 720*4, 0);
469 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
470 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
471 188*4, 0);
472 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
473 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
474 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
475 188*4, 0);
476 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
477 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
478 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
d19770e5 479
a6a3f140 480 cx23885_gpio_setup(dev);
d19770e5
ST		 481}
482
483
484static int cx23885_pci_quirks(struct cx23885_dev *dev)
485{
22b4e64f 486 dprintk(1, "%s()\n", __func__);
d19770e5 487
2df9a4c2
ST		 488 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
489 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
490 * occur on the cx23887 bridge.
491 */
4823e9ee 492 if(dev->bridge == CX23885_BRIDGE_885)
d19770e5 493 cx_clear(RDR_TLCTL0, 1 << 4);
4823e9ee 494
d19770e5
ST		 495 return 0;
496}
497
498static int get_resources(struct cx23885_dev *dev)
499{
500 if (request_mem_region(pci_resource_start(dev->pci,0),
44a6481d
MK		 501 pci_resource_len(dev->pci,0),
502 dev->name))
d19770e5
ST		 503 return 0;
504
505 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
506 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
507
508 return -EBUSY;
509}
510
511static void cx23885_timeout(unsigned long data);
7b888014 512int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
39e75cfe 513 u32 reg, u32 mask, u32 value);
d19770e5 514
a6a3f140 515static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
d19770e5 516{
22b4e64f 517 dprintk(1, "%s(portno=%d)\n", __func__, portno);
a6a3f140
ST		 518
519 /* Transport bus init dma queue - Common settings */
520 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
521 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
b1b81f1d
ST		 522 port->vld_misc_val = 0x0;
523 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
a6a3f140
ST		 524
525 spin_lock_init(&port->slock);
526 port->dev = dev;
527 port->nr = portno;
528
529 INIT_LIST_HEAD(&port->mpegq.active);
530 INIT_LIST_HEAD(&port->mpegq.queued);
531 port->mpegq.timeout.function = cx23885_timeout;
532 port->mpegq.timeout.data = (unsigned long)port;
533 init_timer(&port->mpegq.timeout);
534
535 switch(portno) {
536 case 1:
537 port->reg_gpcnt = VID_B_GPCNT;
538 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
539 port->reg_dma_ctl = VID_B_DMA_CTL;
540 port->reg_lngth = VID_B_LNGTH;
541 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
542 port->reg_gen_ctrl = VID_B_GEN_CTL;
543 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
544 port->reg_sop_status = VID_B_SOP_STATUS;
545 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
546 port->reg_vld_misc = VID_B_VLD_MISC;
547 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
548 port->reg_src_sel = VID_B_SRC_SEL;
549 port->reg_ts_int_msk = VID_B_INT_MSK;
b1b81f1d 550 port->reg_ts_int_stat = VID_B_INT_STAT;
a6a3f140
ST		 551 port->sram_chno = SRAM_CH03; /* VID_B */
552 port->pci_irqmask = 0x02; /* VID_B bit1 */
553 break;
554 case 2:
555 port->reg_gpcnt = VID_C_GPCNT;
556 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
557 port->reg_dma_ctl = VID_C_DMA_CTL;
558 port->reg_lngth = VID_C_LNGTH;
559 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
560 port->reg_gen_ctrl = VID_C_GEN_CTL;
561 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
562 port->reg_sop_status = VID_C_SOP_STATUS;
563 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
564 port->reg_vld_misc = VID_C_VLD_MISC;
565 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
566 port->reg_src_sel = 0;
567 port->reg_ts_int_msk = VID_C_INT_MSK;
568 port->reg_ts_int_stat = VID_C_INT_STAT;
569 port->sram_chno = SRAM_CH06; /* VID_C */
570 port->pci_irqmask = 0x04; /* VID_C bit2 */
d19770e5 571 break;
a6a3f140
ST		 572 default:
573 BUG();
d19770e5
ST		 574 }
575
a6a3f140
ST		 576 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
577 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
578
d19770e5
ST		 579 return 0;
580}
581
0ac5881a
ST		 582static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
583{
584 switch (cx_read(RDR_CFG2) & 0xff) {
585 case 0x00:
586 /* cx23885 */
587 dev->hwrevision = 0xa0;
588 break;
589 case 0x01:
590 /* CX23885-12Z */
591 dev->hwrevision = 0xa1;
592 break;
593 case 0x02:
594 /* CX23885-13Z */
595 dev->hwrevision = 0xb0;
596 break;
597 case 0x03:
598 /* CX23888-22Z */
599 dev->hwrevision = 0xc0;
600 break;
601 case 0x0e:
602 /* CX23887-15Z */
603 dev->hwrevision = 0xc0;
604 case 0x0f:
605 /* CX23887-14Z */
606 dev->hwrevision = 0xb1;
607 break;
608 default:
609 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
22b4e64f 610 __func__, dev->hwrevision);
0ac5881a
ST		 611 }
612 if (dev->hwrevision)
613 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
22b4e64f 614 __func__, dev->hwrevision);
0ac5881a
ST		 615 else
616 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
22b4e64f 617 __func__, dev->hwrevision);
0ac5881a
ST		 618}
619
d19770e5
ST		 620static int cx23885_dev_setup(struct cx23885_dev *dev)
621{
622 int i;
623
624 mutex_init(&dev->lock);
625
626 atomic_inc(&dev->refcount);
627
628 dev->nr = cx23885_devcount++;
31c8cc97 629 dev->sram_channels = cx23887_sram_channels;
579f1163
ST		 630 sprintf(dev->name, "cx23885[%d]", dev->nr);
631
632 mutex_lock(&devlist);
633 list_add_tail(&dev->devlist, &cx23885_devlist);
634 mutex_unlock(&devlist);
635
636 /* Configure the internal memory */
637 if(dev->pci->device == 0x8880) {
638 dev->bridge = CX23885_BRIDGE_887;
c7712613
ST		 639 /* Apply a sensible clock frequency for the PCIe bridge */
640 dev->clk_freq = 25000000;
579f1163
ST		 641 } else
642 if(dev->pci->device == 0x8852) {
643 dev->bridge = CX23885_BRIDGE_885;
c7712613
ST		 644 /* Apply a sensible clock frequency for the PCIe bridge */
645 dev->clk_freq = 28000000;
579f1163
ST		 646 } else
647 BUG();
648
649 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
22b4e64f 650 __func__, dev->bridge);
579f1163
ST		 651
652 /* board config */
653 dev->board = UNSET;
654 if (card[dev->nr] < cx23885_bcount)
655 dev->board = card[dev->nr];
656 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
657 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
658 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
659 dev->board = cx23885_subids[i].card;
660 if (UNSET == dev->board) {
661 dev->board = CX23885_BOARD_UNKNOWN;
662 cx23885_card_list(dev);
663 }
664
c7712613
ST		 665 /* If the user specific a clk freq override, apply it */
666 if (cx23885_boards[dev->board].clk_freq > 0)
667 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
668
d19770e5
ST		 669 dev->pci_bus = dev->pci->bus->number;
670 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
671 dev->pci_irqmask = 0x001f00;
672
673 /* External Master 1 Bus */
674 dev->i2c_bus[0].nr = 0;
675 dev->i2c_bus[0].dev = dev;
676 dev->i2c_bus[0].reg_stat = I2C1_STAT;
677 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
678 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
679 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
680 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
681 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
682
683 /* External Master 2 Bus */
684 dev->i2c_bus[1].nr = 1;
685 dev->i2c_bus[1].dev = dev;
686 dev->i2c_bus[1].reg_stat = I2C2_STAT;
687 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
688 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
689 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
690 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
691 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
692
693 /* Internal Master 3 Bus */
694 dev->i2c_bus[2].nr = 2;
695 dev->i2c_bus[2].dev = dev;
696 dev->i2c_bus[2].reg_stat = I2C3_STAT;
697 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
a2129af5 698 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
d19770e5
ST		 699 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
700 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
701 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
702
b1b81f1d
ST		 703 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
704 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
a6a3f140 705 cx23885_init_tsport(dev, &dev->ts1, 1);
579f1163 706
b1b81f1d
ST		 707 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
708 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
a6a3f140 709 cx23885_init_tsport(dev, &dev->ts2, 2);
d19770e5 710
d19770e5
ST		 711 if (get_resources(dev) < 0) {
712 printk(KERN_ERR "CORE %s No more PCIe resources for "
44a6481d
MK		 713 "subsystem: %04x:%04x\n",
714 dev->name, dev->pci->subsystem_vendor,
715 dev->pci->subsystem_device);
d19770e5
ST		 716
717 cx23885_devcount--;
fcf94c89 718 return -ENODEV;
d19770e5
ST		 719 }
720
d19770e5
ST		 721 /* PCIe stuff */
722 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
44a6481d 723 pci_resource_len(dev->pci,0));
d19770e5
ST		 724
725 dev->bmmio = (u8 __iomem *)dev->lmmio;
726
d19770e5 727 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
44a6481d
MK		 728 dev->name, dev->pci->subsystem_vendor,
729 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
730 dev->board, card[dev->nr] == dev->board ?
731 "insmod option" : "autodetected");
d19770e5 732
4823e9ee
ST		 733 cx23885_pci_quirks(dev);
734
7b888014
ST		 735 /* Assume some sensible defaults */
736 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
737 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
738 dev->radio_type = cx23885_boards[dev->board].radio_type;
739 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
740
741 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
22b4e64f 742 __func__, dev->tuner_type, dev->tuner_addr);
7b888014 743 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
22b4e64f 744 __func__, dev->radio_type, dev->radio_addr);
7b888014 745
d19770e5
ST		 746 /* init hardware */
747 cx23885_reset(dev);
748
749 cx23885_i2c_register(&dev->i2c_bus[0]);
750 cx23885_i2c_register(&dev->i2c_bus[1]);
751 cx23885_i2c_register(&dev->i2c_bus[2]);
d19770e5 752 cx23885_card_setup(dev);
ce89cfb4 753 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
d19770e5
ST		 754 cx23885_ir_init(dev);
755
7b888014
ST		 756 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
757 if (cx23885_video_register(dev) < 0) {
758 printk(KERN_ERR "%s() Failed to register analog "
22b4e64f 759 "video adapters on VID_A\n", __func__);
7b888014
ST		 760 }
761 }
762
763 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
a6a3f140
ST		 764 if (cx23885_dvb_register(&dev->ts1) < 0) {
765 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
22b4e64f 766 __func__);
a6a3f140 767 }
b1b81f1d
ST		 768 } else
769 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
770 if (cx23885_417_register(dev) < 0) {
771 printk(KERN_ERR
772 "%s() Failed to register 417 on VID_B\n",
773 __func__);
774 }
579f1163
ST		 775 }
776
7b888014 777 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
a6a3f140 778 if (cx23885_dvb_register(&dev->ts2) < 0) {
b1b81f1d
ST		 779 printk(KERN_ERR
780 "%s() Failed to register dvb on VID_C\n",
781 __func__);
782 }
783 } else
784 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
785 if (cx23885_417_register(dev) < 0) {
786 printk(KERN_ERR
787 "%s() Failed to register 417 on VID_C\n",
22b4e64f 788 __func__);
a6a3f140 789 }
d19770e5
ST		 790 }
791
0ac5881a
ST		 792 cx23885_dev_checkrevision(dev);
793
d19770e5 794 return 0;
d19770e5
ST		 795}
796
39e75cfe 797static void cx23885_dev_unregister(struct cx23885_dev *dev)
d19770e5
ST		 798{
799 release_mem_region(pci_resource_start(dev->pci,0),
800 pci_resource_len(dev->pci,0));
801
802 if (!atomic_dec_and_test(&dev->refcount))
803 return;
804
7b888014
ST		 805 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
806 cx23885_video_unregister(dev);
807
b1b81f1d 808 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
a6a3f140
ST		 809 cx23885_dvb_unregister(&dev->ts1);
810
b1b81f1d
ST		 811 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
812 cx23885_417_unregister(dev);
813
814 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
a6a3f140
ST		 815 cx23885_dvb_unregister(&dev->ts2);
816
b1b81f1d
ST		 817 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
818 cx23885_417_unregister(dev);
819
d19770e5
ST		 820 cx23885_i2c_unregister(&dev->i2c_bus[2]);
821 cx23885_i2c_unregister(&dev->i2c_bus[1]);
822 cx23885_i2c_unregister(&dev->i2c_bus[0]);
823
824 iounmap(dev->lmmio);
825}
826
d8eaa58b 827static __le32* cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
44a6481d
MK		 828 unsigned int offset, u32 sync_line,
829 unsigned int bpl, unsigned int padding,
830 unsigned int lines)
d19770e5
ST		 831{
832 struct scatterlist *sg;
44a6481d 833 unsigned int line, todo;
d19770e5
ST		 834
835 /* sync instruction */
836 if (sync_line != NO_SYNC_LINE)
837 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
838
839 /* scan lines */
840 sg = sglist;
841 for (line = 0; line < lines; line++) {
842 while (offset && offset >= sg_dma_len(sg)) {
843 offset -= sg_dma_len(sg);
844 sg++;
845 }
846 if (bpl <= sg_dma_len(sg)-offset) {
847 /* fits into current chunk */
848 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
849 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
850 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
851 offset+=bpl;
852 } else {
853 /* scanline needs to be split */
854 todo = bpl;
855 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
856 (sg_dma_len(sg)-offset));
857 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
858 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
859 todo -= (sg_dma_len(sg)-offset);
860 offset = 0;
861 sg++;
862 while (todo > sg_dma_len(sg)) {
863 *(rp++)=cpu_to_le32(RISC_WRITE|
864 sg_dma_len(sg));
865 *(rp++)=cpu_to_le32(sg_dma_address(sg));
866 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
867 todo -= sg_dma_len(sg);
868 sg++;
869 }
870 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
871 *(rp++)=cpu_to_le32(sg_dma_address(sg));
872 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
873 offset += todo;
874 }
875 offset += padding;
876 }
877
878 return rp;
879}
880
7b888014
ST		 881int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
882 struct scatterlist *sglist, unsigned int top_offset,
883 unsigned int bottom_offset, unsigned int bpl,
884 unsigned int padding, unsigned int lines)
885{
886 u32 instructions, fields;
d8eaa58b 887 __le32 *rp;
7b888014
ST		 888 int rc;
889
890 fields = 0;
891 if (UNSET != top_offset)
892 fields++;
893 if (UNSET != bottom_offset)
894 fields++;
895
896 /* estimate risc mem: worst case is one write per page border +
897 one write per scan line + syncs + jump (all 2 dwords). Padding
898 can cause next bpl to start close to a page border. First DMA
899 region may be smaller than PAGE_SIZE */
900 /* write and jump need and extra dword */
901 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
902 instructions += 2;
903 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
904 return rc;
905
906 /* write risc instructions */
907 rp = risc->cpu;
908 if (UNSET != top_offset)
909 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
910 bpl, padding, lines);
911 if (UNSET != bottom_offset)
912 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
913 bpl, padding, lines);
914
915 /* save pointer to jmp instruction address */
916 risc->jmp = rp;
917 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
918 return 0;
919}
d19770e5 920
39e75cfe
AB		 921static int cx23885_risc_databuffer(struct pci_dev *pci,
922 struct btcx_riscmem *risc,
923 struct scatterlist *sglist,
924 unsigned int bpl,
925 unsigned int lines)
d19770e5
ST		 926{
927 u32 instructions;
d8eaa58b 928 __le32 *rp;
d19770e5
ST		 929 int rc;
930
931 /* estimate risc mem: worst case is one write per page border +
932 one write per scan line + syncs + jump (all 2 dwords). Here
933 there is no padding and no sync. First DMA region may be smaller
934 than PAGE_SIZE */
935 /* Jump and write need an extra dword */
936 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
937 instructions += 1;
938
d19770e5
ST		 939 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
940 return rc;
941
942 /* write risc instructions */
943 rp = risc->cpu;
944 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
945
946 /* save pointer to jmp instruction address */
947 risc->jmp = rp;
948 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
949 return 0;
950}
951
7b888014 952int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
39e75cfe 953 u32 reg, u32 mask, u32 value)
d19770e5 954{
d8eaa58b 955 __le32 *rp;
d19770e5
ST		 956 int rc;
957
958 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
959 return rc;
960
961 /* write risc instructions */
962 rp = risc->cpu;
d19770e5
ST		 963 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
964 *(rp++) = cpu_to_le32(reg);
965 *(rp++) = cpu_to_le32(value);
966 *(rp++) = cpu_to_le32(mask);
967 *(rp++) = cpu_to_le32(RISC_JUMP);
968 *(rp++) = cpu_to_le32(risc->dma);
969 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
970 return 0;
971}
972
973void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
974{
409d84f8
TP		 975 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
976
d19770e5 977 BUG_ON(in_interrupt());
44a6481d 978 videobuf_waiton(&buf->vb, 0, 0);
409d84f8
TP		 979 videobuf_dma_unmap(q, dma);
980 videobuf_dma_free(dma);
a920e42f 981 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
0fc0686e 982 buf->vb.state = VIDEOBUF_NEEDS_INIT;
d19770e5
ST		 983}
984
7b888014
ST		 985static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
986{
987 struct cx23885_dev *dev = port->dev;
988
22b4e64f
HH		 989 dprintk(1, "%s() Register Dump\n", __func__);
990 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
7b888014 991 cx_read(DEV_CNTRL2));
22b4e64f 992 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
7b888014 993 cx_read(PCI_INT_MSK));
22b4e64f 994 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
7b888014 995 cx_read(AUDIO_INT_INT_MSK));
22b4e64f 996 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
7b888014 997 cx_read(AUD_INT_DMA_CTL));
22b4e64f 998 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
7b888014 999 cx_read(AUDIO_EXT_INT_MSK));
22b4e64f 1000 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
7b888014 1001 cx_read(AUD_EXT_DMA_CTL));
22b4e64f 1002 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
7b888014 1003 cx_read(PAD_CTRL));
22b4e64f 1004 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
7b888014 1005 cx_read(ALT_PIN_OUT_SEL));
22b4e64f 1006 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
7b888014 1007 cx_read(GPIO2));
22b4e64f 1008 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
7b888014 1009 port->reg_gpcnt, cx_read(port->reg_gpcnt));
22b4e64f 1010 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
7b888014 1011 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
22b4e64f 1012 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
7b888014 1013 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
22b4e64f 1014 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
7b888014 1015 port->reg_src_sel, cx_read(port->reg_src_sel));
22b4e64f 1016 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
7b888014 1017 port->reg_lngth, cx_read(port->reg_lngth));
22b4e64f 1018 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
7b888014 1019 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
22b4e64f 1020 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
7b888014 1021 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
22b4e64f 1022 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
7b888014 1023 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
22b4e64f 1024 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
7b888014 1025 port->reg_sop_status, cx_read(port->reg_sop_status));
22b4e64f 1026 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
7b888014 1027 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
22b4e64f 1028 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
7b888014 1029 port->reg_vld_misc, cx_read(port->reg_vld_misc));
22b4e64f 1030 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
7b888014 1031 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
22b4e64f 1032 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
7b888014
ST		 1033 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1034}
1035
d19770e5 1036static int cx23885_start_dma(struct cx23885_tsport *port,
44a6481d
MK		 1037 struct cx23885_dmaqueue *q,
1038 struct cx23885_buffer *buf)
d19770e5
ST		 1039{
1040 struct cx23885_dev *dev = port->dev;
a589b665 1041 u32 reg;
d19770e5 1042
22b4e64f 1043 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
44a6481d 1044 buf->vb.width, buf->vb.height, buf->vb.field);
d19770e5 1045
d19770e5
ST		 1046 /* setup fifo + format */
1047 cx23885_sram_channel_setup(dev,
44a6481d
MK		 1048 &dev->sram_channels[ port->sram_chno ],
1049 port->ts_packet_size, buf->risc.dma);
3328e4fb 1050 if(debug > 5) {
d19770e5 1051 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
d19770e5 1052 cx23885_risc_disasm(port, &buf->risc);
3328e4fb 1053 }
d19770e5
ST		 1054
1055 /* write TS length to chip */
1056 cx_write(port->reg_lngth, buf->vb.width);
1057
661c7e44
ST		 1058 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1059 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1060 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
22b4e64f 1061 __func__,
661c7e44
ST		 1062 cx23885_boards[dev->board].portb,
1063 cx23885_boards[dev->board].portc );
d19770e5
ST		 1064 return -EINVAL;
1065 }
1066
a589b665
ST		 1067 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1068 cx23885_av_clk(dev, 0);
1069
d19770e5
ST		 1070 udelay(100);
1071
579f1163
ST		 1072 /* If the port supports SRC SELECT, configure it */
1073 if(port->reg_src_sel)
1074 cx_write(port->reg_src_sel, port->src_sel_val);
1075
b1b81f1d 1076 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
d19770e5 1077 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
b1b81f1d 1078 cx_write(port->reg_vld_misc, port->vld_misc_val);
d19770e5
ST		 1079 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1080 udelay(100);
1081
579f1163 1082 // NOTE: this is 2 (reserved) for portb, does it matter?
d19770e5
ST		 1083 /* reset counter to zero */
1084 cx_write(port->reg_gpcnt_ctl, 3);
1085 q->count = 1;
1086
52ce27bf
ST		 1087 /* Set VIDB pins to input */
1088 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1089 reg = cx_read(PAD_CTRL);
1090 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1091 cx_write(PAD_CTRL, reg);
1092 }
1093
1094 /* Set VIDC pins to input */
1095 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1096 reg = cx_read(PAD_CTRL);
1097 reg &= ~0x4; /* Clear TS2_SOP_OE */
1098 cx_write(PAD_CTRL, reg);
1099 }
1100
1101 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
a589b665
ST		 1102
1103 reg = cx_read(PAD_CTRL);
1104 reg = reg & ~0x1; /* Clear TS1_OE */
1105
1106 /* FIXME, bit 2 writing here is questionable */
1107 /* set TS1_SOP_OE and TS1_OE_HI */
1108 reg = reg | 0xa;
1109 cx_write(PAD_CTRL, reg);
1110
1111 /* FIXME and these two registers should be documented. */
1112 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1113 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1114 }
1115
e133be0f 1116 switch(dev->bridge) {
d19770e5 1117 case CX23885_BRIDGE_885:
3bd40659 1118 case CX23885_BRIDGE_887:
d19770e5 1119 /* enable irqs */
22b4e64f 1120 dprintk(1, "%s() enabling TS int's and DMA\n", __func__ );
d19770e5
ST		 1121 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1122 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1123 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1124 break;
d19770e5 1125 default:
579f1163 1126 BUG();
d19770e5
ST		 1127 }
1128
d19770e5
ST		 1129 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1130
a589b665
ST		 1131 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1132 cx23885_av_clk(dev, 1);
1133
7b888014
ST		 1134 if (debug > 4)
1135 cx23885_tsport_reg_dump(port);
1136
d19770e5
ST		 1137 return 0;
1138}
1139
1140static int cx23885_stop_dma(struct cx23885_tsport *port)
1141{
1142 struct cx23885_dev *dev = port->dev;
a589b665
ST		 1143 u32 reg;
1144
22b4e64f 1145 dprintk(1, "%s()\n", __func__);
d19770e5
ST		 1146
1147 /* Stop interrupts and DMA */
1148 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1149 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1150
52ce27bf 1151 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
a589b665
ST		 1152
1153 reg = cx_read(PAD_CTRL);
1154
1155 /* Set TS1_OE */
1156 reg = reg | 0x1;
1157
1158 /* clear TS1_SOP_OE and TS1_OE_HI */
1159 reg = reg & ~0xa;
1160 cx_write(PAD_CTRL, reg);
1161 cx_write(port->reg_src_sel, 0);
1162 cx_write(port->reg_gen_ctrl, 8);
1163
1164 }
1165
1166 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1167 cx23885_av_clk(dev, 0);
1168
d19770e5
ST		 1169 return 0;
1170}
1171
7b888014 1172int cx23885_restart_queue(struct cx23885_tsport *port,
d19770e5
ST		 1173 struct cx23885_dmaqueue *q)
1174{
1175 struct cx23885_dev *dev = port->dev;
1176 struct cx23885_buffer *buf;
d19770e5 1177
22b4e64f 1178 dprintk(5, "%s()\n", __func__);
d19770e5
ST		 1179 if (list_empty(&q->active))
1180 {
44a6481d
MK		 1181 struct cx23885_buffer *prev;
1182 prev = NULL;
d19770e5 1183
22b4e64f 1184 dprintk(5, "%s() queue is empty\n", __func__);
d19770e5 1185
44a6481d
MK		 1186 for (;;) {
1187 if (list_empty(&q->queued))
1188 return 0;
1189 buf = list_entry(q->queued.next, struct cx23885_buffer,
1190 vb.queue);
1191 if (NULL == prev) {
1192 list_del(&buf->vb.queue);
1193 list_add_tail(&buf->vb.queue, &q->active);
1194 cx23885_start_dma(port, q, buf);
0fc0686e 1195 buf->vb.state = VIDEOBUF_ACTIVE;
44a6481d
MK		 1196 buf->count = q->count++;
1197 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1198 dprintk(5, "[%p/%d] restart_queue - first active\n",
1199 buf, buf->vb.i);
1200
1201 } else if (prev->vb.width == buf->vb.width &&
1202 prev->vb.height == buf->vb.height &&
1203 prev->fmt == buf->fmt) {
1204 list_del(&buf->vb.queue);
1205 list_add_tail(&buf->vb.queue, &q->active);
0fc0686e 1206 buf->vb.state = VIDEOBUF_ACTIVE;
44a6481d
MK		 1207 buf->count = q->count++;
1208 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1209 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1210 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1211 buf, buf->vb.i);
1212 } else {
1213 return 0;
1214 }
1215 prev = buf;
1216 }
d19770e5
ST		 1217 return 0;
1218 }
1219
1220 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
44a6481d 1221 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
d19770e5
ST		 1222 buf, buf->vb.i);
1223 cx23885_start_dma(port, q, buf);
a991f44b 1224 list_for_each_entry(buf, &q->active, vb.queue)
d19770e5 1225 buf->count = q->count++;
44a6481d 1226 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 1227 return 0;
1228}
1229
1230/* ------------------------------------------------------------------ */
1231
1232int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1233 struct cx23885_buffer *buf, enum v4l2_field field)
1234{
1235 struct cx23885_dev *dev = port->dev;
1236 int size = port->ts_packet_size * port->ts_packet_count;
1237 int rc;
1238
22b4e64f 1239 dprintk(1, "%s: %p\n", __func__, buf);
d19770e5
ST		 1240 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1241 return -EINVAL;
1242
0fc0686e 1243 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
d19770e5
ST		 1244 buf->vb.width = port->ts_packet_size;
1245 buf->vb.height = port->ts_packet_count;
1246 buf->vb.size = size;
1247 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1248
44a6481d 1249 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
d19770e5
ST		 1250 goto fail;
1251 cx23885_risc_databuffer(dev->pci, &buf->risc,
409d84f8
TP		 1252 videobuf_to_dma(&buf->vb)->sglist,
1253 buf->vb.width, buf->vb.height);
d19770e5 1254 }
0fc0686e 1255 buf->vb.state = VIDEOBUF_PREPARED;
d19770e5
ST		 1256 return 0;
1257
1258 fail:
44a6481d 1259 cx23885_free_buffer(q, buf);
d19770e5
ST		 1260 return rc;
1261}
1262
1263void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1264{
1265 struct cx23885_buffer *prev;
1266 struct cx23885_dev *dev = port->dev;
1267 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1268
1269 /* add jump to stopper */
1270 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1271 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1272 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1273
1274 if (list_empty(&cx88q->active)) {
1275 dprintk( 1, "queue is empty - first active\n" );
44a6481d 1276 list_add_tail(&buf->vb.queue, &cx88q->active);
d19770e5 1277 cx23885_start_dma(port, cx88q, buf);
0fc0686e 1278 buf->vb.state = VIDEOBUF_ACTIVE;
d19770e5 1279 buf->count = cx88q->count++;
44a6481d
MK		 1280 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1281 dprintk(1, "[%p/%d] %s - first active\n",
22b4e64f 1282 buf, buf->vb.i, __func__);
d19770e5
ST		 1283 } else {
1284 dprintk( 1, "queue is not empty - append to active\n" );
44a6481d
MK		 1285 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1286 vb.queue);
1287 list_add_tail(&buf->vb.queue, &cx88q->active);
0fc0686e 1288 buf->vb.state = VIDEOBUF_ACTIVE;
d19770e5
ST		 1289 buf->count = cx88q->count++;
1290 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1291 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1292 dprintk( 1, "[%p/%d] %s - append to active\n",
22b4e64f 1293 buf, buf->vb.i, __func__);
d19770e5
ST		 1294 }
1295}
1296
1297/* ----------------------------------------------------------- */
1298
44a6481d
MK		 1299static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1300 int restart)
d19770e5
ST		 1301{
1302 struct cx23885_dev *dev = port->dev;
1303 struct cx23885_dmaqueue *q = &port->mpegq;
1304 struct cx23885_buffer *buf;
1305 unsigned long flags;
1306
44a6481d 1307 spin_lock_irqsave(&port->slock, flags);
d19770e5 1308 while (!list_empty(&q->active)) {
44a6481d
MK		 1309 buf = list_entry(q->active.next, struct cx23885_buffer,
1310 vb.queue);
d19770e5 1311 list_del(&buf->vb.queue);
0fc0686e 1312 buf->vb.state = VIDEOBUF_ERROR;
d19770e5 1313 wake_up(&buf->vb.done);
44a6481d 1314 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
d19770e5
ST		 1315 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1316 }
44a6481d 1317 if (restart) {
d19770e5
ST		 1318 dprintk(1, "restarting queue\n" );
1319 cx23885_restart_queue(port, q);
1320 }
44a6481d 1321 spin_unlock_irqrestore(&port->slock, flags);
d19770e5
ST		 1322}
1323
b1b81f1d
ST		 1324void cx23885_cancel_buffers(struct cx23885_tsport *port)
1325{
1326 struct cx23885_dev *dev = port->dev;
1327 struct cx23885_dmaqueue *q = &port->mpegq;
1328
1329 dprintk(1, "%s()\n", __FUNCTION__);
1330 del_timer_sync(&q->timeout);
1331 cx23885_stop_dma(port);
1332 do_cancel_buffers(port, "cancel", 0);
1333}
d19770e5
ST		 1334
1335static void cx23885_timeout(unsigned long data)
1336{
1337 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1338 struct cx23885_dev *dev = port->dev;
1339
22b4e64f 1340 dprintk(1, "%s()\n",__func__);
d19770e5
ST		 1341
1342 if (debug > 5)
d19770e5 1343 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
3328e4fb 1344
d19770e5
ST		 1345 cx23885_stop_dma(port);
1346 do_cancel_buffers(port, "timeout", 1);
1347}
1348
b1b81f1d
ST		 1349int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1350{
1351 /* FIXME: port1 assumption here. */
1352 struct cx23885_tsport *port = &dev->ts1;
1353 int count = 0;
1354 int handled = 0;
1355
1356 if (status == 0)
1357 return handled;
1358
1359 count = cx_read(port->reg_gpcnt);
1360 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1361 status, cx_read(port->reg_ts_int_msk), count);
1362
1363 if ((status & VID_B_MSK_BAD_PKT) ||
1364 (status & VID_B_MSK_OPC_ERR) ||
1365 (status & VID_B_MSK_VBI_OPC_ERR) ||
1366 (status & VID_B_MSK_SYNC) ||
1367 (status & VID_B_MSK_VBI_SYNC) ||
1368 (status & VID_B_MSK_OF) ||
1369 (status & VID_B_MSK_VBI_OF)) {
1370 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1371 "= 0x%x\n", dev->name, status);
1372 if (status & VID_B_MSK_BAD_PKT)
1373 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1374 if (status & VID_B_MSK_OPC_ERR)
1375 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1376 if (status & VID_B_MSK_VBI_OPC_ERR)
1377 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1378 if (status & VID_B_MSK_SYNC)
1379 dprintk(1, " VID_B_MSK_SYNC\n");
1380 if (status & VID_B_MSK_VBI_SYNC)
1381 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1382 if (status & VID_B_MSK_OF)
1383 dprintk(1, " VID_B_MSK_OF\n");
1384 if (status & VID_B_MSK_VBI_OF)
1385 dprintk(1, " VID_B_MSK_VBI_OF\n");
1386
1387 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1388 cx23885_sram_channel_dump(dev,
1389 &dev->sram_channels[port->sram_chno]);
1390 cx23885_417_check_encoder(dev);
1391 } else if (status & VID_B_MSK_RISCI1) {
1392 dprintk(7, " VID_B_MSK_RISCI1\n");
1393 spin_lock(&port->slock);
1394 cx23885_wakeup(port, &port->mpegq, count);
1395 spin_unlock(&port->slock);
1396 } else if (status & VID_B_MSK_RISCI2) {
1397 dprintk(7, " VID_B_MSK_RISCI2\n");
1398 spin_lock(&port->slock);
1399 cx23885_restart_queue(port, &port->mpegq);
1400 spin_unlock(&port->slock);
1401 }
1402 if (status) {
1403 cx_write(port->reg_ts_int_stat, status);
1404 handled = 1;
1405 }
1406
1407 return handled;
1408}
1409
a6a3f140
ST		 1410static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1411{
1412 struct cx23885_dev *dev = port->dev;
1413 int handled = 0;
1414 u32 count;
1415
b1b81f1d
ST		 1416 if ((status & VID_BC_MSK_OPC_ERR) ||
1417 (status & VID_BC_MSK_BAD_PKT) ||
1418 (status & VID_BC_MSK_SYNC) ||
1419 (status & VID_BC_MSK_OF))
a6a3f140
ST		 1420 {
1421 if (status & VID_BC_MSK_OPC_ERR)
1422 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1423 if (status & VID_BC_MSK_BAD_PKT)
1424 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1425 if (status & VID_BC_MSK_SYNC)
1426 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
1427 if (status & VID_BC_MSK_OF)
1428 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
1429
1430 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1431
1432 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
b1b81f1d
ST		 1433 cx23885_sram_channel_dump(dev,
1434 &dev->sram_channels[port->sram_chno]);
a6a3f140
ST		 1435
1436 } else if (status & VID_BC_MSK_RISCI1) {
1437
1438 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1439
1440 spin_lock(&port->slock);
1441 count = cx_read(port->reg_gpcnt);
1442 cx23885_wakeup(port, &port->mpegq, count);
1443 spin_unlock(&port->slock);
1444
1445 } else if (status & VID_BC_MSK_RISCI2) {
1446
1447 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1448
1449 spin_lock(&port->slock);
1450 cx23885_restart_queue(port, &port->mpegq);
1451 spin_unlock(&port->slock);
1452
1453 }
1454 if (status) {
1455 cx_write(port->reg_ts_int_stat, status);
1456 handled = 1;
1457 }
1458
1459 return handled;
1460}
1461
03121f05 1462static irqreturn_t cx23885_irq(int irq, void *dev_id)
d19770e5
ST		 1463{
1464 struct cx23885_dev *dev = dev_id;
a6a3f140
ST		 1465 struct cx23885_tsport *ts1 = &dev->ts1;
1466 struct cx23885_tsport *ts2 = &dev->ts2;
d19770e5 1467 u32 pci_status, pci_mask;
7b888014 1468 u32 vida_status, vida_mask;
6f074abb 1469 u32 ts1_status, ts1_mask;
d19770e5 1470 u32 ts2_status, ts2_mask;
7b888014 1471 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
d19770e5
ST		 1472
1473 pci_status = cx_read(PCI_INT_STAT);
1474 pci_mask = cx_read(PCI_INT_MSK);
7b888014
ST		 1475 vida_status = cx_read(VID_A_INT_STAT);
1476 vida_mask = cx_read(VID_A_INT_MSK);
6f074abb
ST		 1477 ts1_status = cx_read(VID_B_INT_STAT);
1478 ts1_mask = cx_read(VID_B_INT_MSK);
d19770e5
ST		 1479 ts2_status = cx_read(VID_C_INT_STAT);
1480 ts2_mask = cx_read(VID_C_INT_MSK);
1481
6f074abb 1482 if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
d19770e5
ST		 1483 goto out;
1484
7b888014 1485 vida_count = cx_read(VID_A_GPCNT);
a6a3f140
ST		 1486 ts1_count = cx_read(ts1->reg_gpcnt);
1487 ts2_count = cx_read(ts2->reg_gpcnt);
7b888014
ST		 1488 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1489 pci_status, pci_mask);
1490 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1491 vida_status, vida_mask, vida_count);
1492 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1493 ts1_status, ts1_mask, ts1_count);
1494 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1495 ts2_status, ts2_mask, ts2_count);
d19770e5
ST		 1496
1497 if ( (pci_status & PCI_MSK_RISC_RD) ||
44a6481d
MK		 1498 (pci_status & PCI_MSK_RISC_WR) ||
1499 (pci_status & PCI_MSK_AL_RD) ||
1500 (pci_status & PCI_MSK_AL_WR) ||
1501 (pci_status & PCI_MSK_APB_DMA) ||
1502 (pci_status & PCI_MSK_VID_C) ||
1503 (pci_status & PCI_MSK_VID_B) ||
1504 (pci_status & PCI_MSK_VID_A) ||
1505 (pci_status & PCI_MSK_AUD_INT) ||
1506 (pci_status & PCI_MSK_AUD_EXT) )
d19770e5
ST		 1507 {
1508
1509 if (pci_status & PCI_MSK_RISC_RD)
1510 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1511 if (pci_status & PCI_MSK_RISC_WR)
1512 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1513 if (pci_status & PCI_MSK_AL_RD)
1514 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1515 if (pci_status & PCI_MSK_AL_WR)
1516 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1517 if (pci_status & PCI_MSK_APB_DMA)
1518 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1519 if (pci_status & PCI_MSK_VID_C)
1520 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1521 if (pci_status & PCI_MSK_VID_B)
1522 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1523 if (pci_status & PCI_MSK_VID_A)
1524 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1525 if (pci_status & PCI_MSK_AUD_INT)
1526 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1527 if (pci_status & PCI_MSK_AUD_EXT)
1528 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1529
1530 }
1531
7b888014
ST		 1532 if (ts1_status) {
1533 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1534 handled += cx23885_irq_ts(ts1, ts1_status);
b1b81f1d
ST		 1535 else
1536 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1537 handled += cx23885_irq_417(dev, ts1_status);
7b888014
ST		 1538 }
1539
1540 if (ts2_status) {
1541 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1542 handled += cx23885_irq_ts(ts2, ts2_status);
b1b81f1d
ST		 1543 else
1544 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1545 handled += cx23885_irq_417(dev, ts2_status);
7b888014 1546 }
6f074abb 1547
7b888014
ST		 1548 if (vida_status)
1549 handled += cx23885_video_irq(dev, vida_status);
6f074abb
ST		 1550
1551 if (handled)
1552 cx_write(PCI_INT_STAT, pci_status);
d19770e5
ST		 1553out:
1554 return IRQ_RETVAL(handled);
1555}
1556
1557static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
44a6481d 1558 const struct pci_device_id *pci_id)
d19770e5
ST		 1559{
1560 struct cx23885_dev *dev;
1561 int err;
1562
44a6481d 1563 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
d19770e5
ST		 1564 if (NULL == dev)
1565 return -ENOMEM;
1566
1567 /* pci init */
1568 dev->pci = pci_dev;
1569 if (pci_enable_device(pci_dev)) {
1570 err = -EIO;
1571 goto fail_free;
1572 }
1573
1574 if (cx23885_dev_setup(dev) < 0) {
1575 err = -EINVAL;
1576 goto fail_free;
1577 }
1578
1579 /* print pci info */
1580 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1581 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1582 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1583 "latency: %d, mmio: 0x%llx\n", dev->name,
1584 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
a589b665
ST		 1585 dev->pci_lat,
1586 (unsigned long long)pci_resource_start(pci_dev, 0));
d19770e5
ST		 1587
1588 pci_set_master(pci_dev);
1589 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1590 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1591 err = -EIO;
1592 goto fail_irq;
1593 }
1594
44a6481d
MK		 1595 err = request_irq(pci_dev->irq, cx23885_irq,
1596 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
d19770e5
ST		 1597 if (err < 0) {
1598 printk(KERN_ERR "%s: can't get IRQ %d\n",
1599 dev->name, pci_dev->irq);
1600 goto fail_irq;
1601 }
1602
1603 pci_set_drvdata(pci_dev, dev);
1604 return 0;
1605
1606fail_irq:
1607 cx23885_dev_unregister(dev);
1608fail_free:
1609 kfree(dev);
1610 return err;
1611}
1612
1613static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1614{
1615 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1616
1617 cx23885_shutdown(dev);
1618
1619 pci_disable_device(pci_dev);
1620
1621 /* unregister stuff */
1622 free_irq(pci_dev->irq, dev);
1623 pci_set_drvdata(pci_dev, NULL);
1624
1625 mutex_lock(&devlist);
1626 list_del(&dev->devlist);
1627 mutex_unlock(&devlist);
1628
1629 cx23885_dev_unregister(dev);
1630 kfree(dev);
1631}
1632
1633static struct pci_device_id cx23885_pci_tbl[] = {
1634 {
1635 /* CX23885 */
1636 .vendor = 0x14f1,
1637 .device = 0x8852,
1638 .subvendor = PCI_ANY_ID,
1639 .subdevice = PCI_ANY_ID,
1640 },{
1641 /* CX23887 Rev 2 */
1642 .vendor = 0x14f1,
1643 .device = 0x8880,
1644 .subvendor = PCI_ANY_ID,
1645 .subdevice = PCI_ANY_ID,
1646 },{
1647 /* --- end of list --- */
1648 }
1649};
1650MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1651
1652static struct pci_driver cx23885_pci_driver = {
1653 .name = "cx23885",
1654 .id_table = cx23885_pci_tbl,
1655 .probe = cx23885_initdev,
1656 .remove = __devexit_p(cx23885_finidev),
1657 /* TODO */
1658 .suspend = NULL,
1659 .resume = NULL,
1660};
1661
1662static int cx23885_init(void)
1663{
1664 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
047646bf
ST		 1665 (CX23885_VERSION_CODE >> 16) & 0xff,
1666 (CX23885_VERSION_CODE >> 8) & 0xff,
1667 CX23885_VERSION_CODE & 0xff);
d19770e5
ST		 1668#ifdef SNAPSHOT
1669 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1670 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1671#endif
1672 return pci_register_driver(&cx23885_pci_driver);
1673}
1674
1675static void cx23885_fini(void)
1676{
1677 pci_unregister_driver(&cx23885_pci_driver);
1678}
1679
1680module_init(cx23885_init);
1681module_exit(cx23885_fini);
1682
1683/* ----------------------------------------------------------- */
1684/*
1685 * Local variables:
1686 * c-basic-offset: 8
1687 * End:
1688 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1689 */
Linux kernel - Deliverables
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