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V4L/DVB (9230): cx23885: MFE related OOPS fix
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-core.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kmod.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <asm/div64.h>
32
33#include "cx23885.h"
34
35MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
6d897616 36MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
d19770e5
ST		 37MODULE_LICENSE("GPL");
38
4513fc69 39static unsigned int debug;
d19770e5
ST		 40module_param(debug,int,0644);
41MODULE_PARM_DESC(debug,"enable debug messages");
42
43static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44module_param_array(card, int, NULL, 0444);
45MODULE_PARM_DESC(card,"card type");
46
4513fc69
ST		 47#define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
50 } while (0)
d19770e5
ST		 51
52static unsigned int cx23885_devcount;
53
54static DEFINE_MUTEX(devlist);
7b888014 55LIST_HEAD(cx23885_devlist);
d19770e5
ST		 56
57#define NO_SYNC_LINE (-1U)
58
d19770e5
ST		 59/* FIXME, these allocations will change when
60 * analog arrives. The be reviewed.
61 * CX23887 Assumptions
62 * 1 line = 16 bytes of CDT
63 * cmds size = 80
64 * cdt size = 16 * linesize
65 * iqsize = 64
66 * maxlines = 6
67 *
68 * Address Space:
69 * 0x00000000 0x00008fff FIFO clusters
70 * 0x00010000 0x000104af Channel Management Data Structures
71 * 0x000104b0 0x000104ff Free
72 * 0x00010500 0x000108bf 15 channels * iqsize
73 * 0x000108c0 0x000108ff Free
74 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
75 * 15 channels * (iqsize + (maxlines * linesize))
76 * 0x00010ea0 0x00010xxx Free
77 */
78
7e994302 79static struct sram_channel cx23885_sram_channels[] = {
d19770e5 80 [SRAM_CH01] = {
69ad6e56
ST		 81 .name = "VID A",
82 .cmds_start = 0x10000,
d8d12b43
ST		 83 .ctrl_start = 0x10380,
84 .cdt = 0x104c0,
69ad6e56
ST		 85 .fifo_start = 0x40,
86 .fifo_size = 0x2800,
d19770e5
ST		 87 .ptr1_reg = DMA1_PTR1,
88 .ptr2_reg = DMA1_PTR2,
89 .cnt1_reg = DMA1_CNT1,
90 .cnt2_reg = DMA1_CNT2,
91 },
92 [SRAM_CH02] = {
93 .name = "ch2",
94 .cmds_start = 0x0,
95 .ctrl_start = 0x0,
96 .cdt = 0x0,
97 .fifo_start = 0x0,
98 .fifo_size = 0x0,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
103 },
104 [SRAM_CH03] = {
69ad6e56
ST		 105 .name = "TS1 B",
106 .cmds_start = 0x100A0,
d8d12b43
ST		 107 .ctrl_start = 0x10400,
108 .cdt = 0x10580,
69ad6e56
ST		 109 .fifo_start = 0x5000,
110 .fifo_size = 0x1000,
d19770e5
ST		 111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
115 },
116 [SRAM_CH04] = {
117 .name = "ch4",
118 .cmds_start = 0x0,
119 .ctrl_start = 0x0,
120 .cdt = 0x0,
121 .fifo_start = 0x0,
122 .fifo_size = 0x0,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
127 },
128 [SRAM_CH05] = {
129 .name = "ch5",
130 .cmds_start = 0x0,
131 .ctrl_start = 0x0,
132 .cdt = 0x0,
133 .fifo_start = 0x0,
134 .fifo_size = 0x0,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
139 },
140 [SRAM_CH06] = {
141 .name = "TS2 C",
142 .cmds_start = 0x10140,
d8d12b43
ST		 143 .ctrl_start = 0x10440,
144 .cdt = 0x105e0,
d19770e5
ST		 145 .fifo_start = 0x6000,
146 .fifo_size = 0x1000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
151 },
152 [SRAM_CH07] = {
153 .name = "ch7",
154 .cmds_start = 0x0,
155 .ctrl_start = 0x0,
156 .cdt = 0x0,
157 .fifo_start = 0x0,
158 .fifo_size = 0x0,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
163 },
164 [SRAM_CH08] = {
165 .name = "ch8",
166 .cmds_start = 0x0,
167 .ctrl_start = 0x0,
168 .cdt = 0x0,
169 .fifo_start = 0x0,
170 .fifo_size = 0x0,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 },
176 [SRAM_CH09] = {
177 .name = "ch9",
178 .cmds_start = 0x0,
179 .ctrl_start = 0x0,
180 .cdt = 0x0,
181 .fifo_start = 0x0,
182 .fifo_size = 0x0,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
187 },
188};
189
7e994302
ST		 190static struct sram_channel cx23887_sram_channels[] = {
191 [SRAM_CH01] = {
192 .name = "VID A",
193 .cmds_start = 0x10000,
194 .ctrl_start = 0x105b0,
195 .cdt = 0x107b0,
196 .fifo_start = 0x40,
197 .fifo_size = 0x2800,
198 .ptr1_reg = DMA1_PTR1,
199 .ptr2_reg = DMA1_PTR2,
200 .cnt1_reg = DMA1_CNT1,
201 .cnt2_reg = DMA1_CNT2,
202 },
203 [SRAM_CH02] = {
204 .name = "ch2",
205 .cmds_start = 0x0,
206 .ctrl_start = 0x0,
207 .cdt = 0x0,
208 .fifo_start = 0x0,
209 .fifo_size = 0x0,
210 .ptr1_reg = DMA2_PTR1,
211 .ptr2_reg = DMA2_PTR2,
212 .cnt1_reg = DMA2_CNT1,
213 .cnt2_reg = DMA2_CNT2,
214 },
215 [SRAM_CH03] = {
216 .name = "TS1 B",
217 .cmds_start = 0x100A0,
218 .ctrl_start = 0x10630,
219 .cdt = 0x10870,
220 .fifo_start = 0x5000,
221 .fifo_size = 0x1000,
222 .ptr1_reg = DMA3_PTR1,
223 .ptr2_reg = DMA3_PTR2,
224 .cnt1_reg = DMA3_CNT1,
225 .cnt2_reg = DMA3_CNT2,
226 },
227 [SRAM_CH04] = {
228 .name = "ch4",
229 .cmds_start = 0x0,
230 .ctrl_start = 0x0,
231 .cdt = 0x0,
232 .fifo_start = 0x0,
233 .fifo_size = 0x0,
234 .ptr1_reg = DMA4_PTR1,
235 .ptr2_reg = DMA4_PTR2,
236 .cnt1_reg = DMA4_CNT1,
237 .cnt2_reg = DMA4_CNT2,
238 },
239 [SRAM_CH05] = {
240 .name = "ch5",
241 .cmds_start = 0x0,
242 .ctrl_start = 0x0,
243 .cdt = 0x0,
244 .fifo_start = 0x0,
245 .fifo_size = 0x0,
246 .ptr1_reg = DMA5_PTR1,
247 .ptr2_reg = DMA5_PTR2,
248 .cnt1_reg = DMA5_CNT1,
249 .cnt2_reg = DMA5_CNT2,
250 },
251 [SRAM_CH06] = {
252 .name = "TS2 C",
253 .cmds_start = 0x10140,
254 .ctrl_start = 0x10670,
255 .cdt = 0x108d0,
256 .fifo_start = 0x6000,
257 .fifo_size = 0x1000,
258 .ptr1_reg = DMA5_PTR1,
259 .ptr2_reg = DMA5_PTR2,
260 .cnt1_reg = DMA5_CNT1,
261 .cnt2_reg = DMA5_CNT2,
262 },
263 [SRAM_CH07] = {
264 .name = "ch7",
265 .cmds_start = 0x0,
266 .ctrl_start = 0x0,
267 .cdt = 0x0,
268 .fifo_start = 0x0,
269 .fifo_size = 0x0,
270 .ptr1_reg = DMA6_PTR1,
271 .ptr2_reg = DMA6_PTR2,
272 .cnt1_reg = DMA6_CNT1,
273 .cnt2_reg = DMA6_CNT2,
274 },
275 [SRAM_CH08] = {
276 .name = "ch8",
277 .cmds_start = 0x0,
278 .ctrl_start = 0x0,
279 .cdt = 0x0,
280 .fifo_start = 0x0,
281 .fifo_size = 0x0,
282 .ptr1_reg = DMA7_PTR1,
283 .ptr2_reg = DMA7_PTR2,
284 .cnt1_reg = DMA7_CNT1,
285 .cnt2_reg = DMA7_CNT2,
286 },
287 [SRAM_CH09] = {
288 .name = "ch9",
289 .cmds_start = 0x0,
290 .ctrl_start = 0x0,
291 .cdt = 0x0,
292 .fifo_start = 0x0,
293 .fifo_size = 0x0,
294 .ptr1_reg = DMA8_PTR1,
295 .ptr2_reg = DMA8_PTR2,
296 .cnt1_reg = DMA8_CNT1,
297 .cnt2_reg = DMA8_CNT2,
298 },
299};
300
d19770e5
ST		 301static int cx23885_risc_decode(u32 risc)
302{
303 static char *instr[16] = {
b1b81f1d
ST		 304 [RISC_SYNC >> 28] = "sync",
305 [RISC_WRITE >> 28] = "write",
306 [RISC_WRITEC >> 28] = "writec",
307 [RISC_READ >> 28] = "read",
308 [RISC_READC >> 28] = "readc",
309 [RISC_JUMP >> 28] = "jump",
310 [RISC_SKIP >> 28] = "skip",
311 [RISC_WRITERM >> 28] = "writerm",
312 [RISC_WRITECM >> 28] = "writecm",
313 [RISC_WRITECR >> 28] = "writecr",
d19770e5
ST		 314 };
315 static int incr[16] = {
b1b81f1d
ST		 316 [RISC_WRITE >> 28] = 3,
317 [RISC_JUMP >> 28] = 3,
318 [RISC_SKIP >> 28] = 1,
319 [RISC_SYNC >> 28] = 1,
320 [RISC_WRITERM >> 28] = 3,
321 [RISC_WRITECM >> 28] = 3,
322 [RISC_WRITECR >> 28] = 4,
d19770e5
ST		 323 };
324 static char *bits[] = {
325 "12", "13", "14", "resync",
326 "cnt0", "cnt1", "18", "19",
327 "20", "21", "22", "23",
328 "irq1", "irq2", "eol", "sol",
329 };
330 int i;
331
332 printk("0x%08x [ %s", risc,
333 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
44a6481d 334 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
d19770e5 335 if (risc & (1 << (i + 12)))
44a6481d 336 printk(" %s", bits[i]);
d19770e5
ST		 337 printk(" count=%d ]\n", risc & 0xfff);
338 return incr[risc >> 28] ? incr[risc >> 28] : 1;
339}
340
7b888014 341void cx23885_wakeup(struct cx23885_tsport *port,
39e75cfe 342 struct cx23885_dmaqueue *q, u32 count)
d19770e5
ST		 343{
344 struct cx23885_dev *dev = port->dev;
345 struct cx23885_buffer *buf;
346 int bc;
347
348 for (bc = 0;; bc++) {
349 if (list_empty(&q->active))
350 break;
351 buf = list_entry(q->active.next,
352 struct cx23885_buffer, vb.queue);
2e52f215 353
d19770e5
ST		 354 /* count comes from the hw and is is 16bit wide --
355 * this trick handles wrap-arounds correctly for
356 * up to 32767 buffers in flight... */
357 if ((s16) (count - buf->count) < 0)
358 break;
2e52f215 359
d19770e5 360 do_gettimeofday(&buf->vb.ts);
44a6481d 361 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
d19770e5 362 count, buf->count);
0fc0686e 363 buf->vb.state = VIDEOBUF_DONE;
d19770e5
ST		 364 list_del(&buf->vb.queue);
365 wake_up(&buf->vb.done);
366 }
367 if (list_empty(&q->active)) {
368 del_timer(&q->timeout);
369 } else {
44a6481d 370 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 371 }
372 if (bc != 1)
44a6481d 373 printk("%s: %d buffers handled (should be 1)\n",
22b4e64f 374 __func__, bc);
d19770e5 375}
d19770e5 376
7b888014 377int cx23885_sram_channel_setup(struct cx23885_dev *dev,
39e75cfe
AB		 378 struct sram_channel *ch,
379 unsigned int bpl, u32 risc)
d19770e5 380{
44a6481d 381 unsigned int i, lines;
d19770e5
ST		 382 u32 cdt;
383
384 if (ch->cmds_start == 0)
385 {
22b4e64f 386 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
44a6481d 387 ch->name);
d19770e5
ST		 388 cx_write(ch->ptr1_reg, 0);
389 cx_write(ch->ptr2_reg, 0);
390 cx_write(ch->cnt2_reg, 0);
391 cx_write(ch->cnt1_reg, 0);
392 return 0;
393 } else {
22b4e64f 394 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
44a6481d 395 ch->name);
d19770e5
ST		 396 }
397
398 bpl = (bpl + 7) & ~7; /* alignment */
399 cdt = ch->cdt;
400 lines = ch->fifo_size / bpl;
401 if (lines > 6)
402 lines = 6;
403 BUG_ON(lines < 2);
404
86ecc027
AV		 405 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
406 cx_write(8 + 4, 8);
407 cx_write(8 + 8, 0);
d19770e5
ST		 408
409 /* write CDT */
410 for (i = 0; i < lines; i++) {
22b4e64f 411 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
44a6481d 412 ch->fifo_start + bpl*i);
d19770e5
ST		 413 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
414 cx_write(cdt + 16*i + 4, 0);
415 cx_write(cdt + 16*i + 8, 0);
416 cx_write(cdt + 16*i + 12, 0);
417 }
418
419 /* write CMDS */
420 if (ch->jumponly)
421 cx_write(ch->cmds_start + 0, 8);
422 else
423 cx_write(ch->cmds_start + 0, risc);
424 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
425 cx_write(ch->cmds_start + 8, cdt);
426 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
427 cx_write(ch->cmds_start + 16, ch->ctrl_start);
428 if (ch->jumponly)
429 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
430 else
431 cx_write(ch->cmds_start + 20, 64 >> 2);
432 for (i = 24; i < 80; i += 4)
433 cx_write(ch->cmds_start + i, 0);
434
435 /* fill registers */
436 cx_write(ch->ptr1_reg, ch->fifo_start);
437 cx_write(ch->ptr2_reg, cdt);
438 cx_write(ch->cnt2_reg, (lines*16) >> 3);
439 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
440
e133be0f
ST		 441 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
442 dev->bridge,
d19770e5
ST		 443 ch->name,
444 bpl,
445 lines);
446
447 return 0;
448}
449
7b888014 450void cx23885_sram_channel_dump(struct cx23885_dev *dev,
39e75cfe 451 struct sram_channel *ch)
d19770e5
ST		 452{
453 static char *name[] = {
454 "init risc lo",
455 "init risc hi",
456 "cdt base",
457 "cdt size",
458 "iq base",
459 "iq size",
460 "risc pc lo",
461 "risc pc hi",
462 "iq wr ptr",
463 "iq rd ptr",
464 "cdt current",
465 "pci target lo",
466 "pci target hi",
467 "line / byte",
468 };
469 u32 risc;
44a6481d 470 unsigned int i, j, n;
d19770e5
ST		 471
472 printk("%s: %s - dma channel status dump\n",
473 dev->name, ch->name);
474 for (i = 0; i < ARRAY_SIZE(name); i++)
475 printk("%s: cmds: %-15s: 0x%08x\n",
476 dev->name, name[i],
477 cx_read(ch->cmds_start + 4*i));
478
479 for (i = 0; i < 4; i++) {
44a6481d 480 risc = cx_read(ch->cmds_start + 4 * (i + 14));
d19770e5
ST		 481 printk("%s: risc%d: ", dev->name, i);
482 cx23885_risc_decode(risc);
483 }
484 for (i = 0; i < (64 >> 2); i += n) {
44a6481d
MK		 485 risc = cx_read(ch->ctrl_start + 4 * i);
486 /* No consideration for bits 63-32 */
487
488 printk("%s: (0x%08x) iq %x: ", dev->name,
489 ch->ctrl_start + 4 * i, i);
d19770e5
ST		 490 n = cx23885_risc_decode(risc);
491 for (j = 1; j < n; j++) {
44a6481d 492 risc = cx_read(ch->ctrl_start + 4 * (i + j));
d19770e5
ST		 493 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
494 dev->name, i+j, risc, j);
495 }
496 }
497
498 printk("%s: fifo: 0x%08x -> 0x%x\n",
499 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
500 printk("%s: ctrl: 0x%08x -> 0x%x\n",
44a6481d 501 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
d19770e5
ST		 502 printk("%s: ptr1_reg: 0x%08x\n",
503 dev->name, cx_read(ch->ptr1_reg));
504 printk("%s: ptr2_reg: 0x%08x\n",
505 dev->name, cx_read(ch->ptr2_reg));
506 printk("%s: cnt1_reg: 0x%08x\n",
507 dev->name, cx_read(ch->cnt1_reg));
508 printk("%s: cnt2_reg: 0x%08x\n",
509 dev->name, cx_read(ch->cnt2_reg));
510}
511
39e75cfe
AB		 512static void cx23885_risc_disasm(struct cx23885_tsport *port,
513 struct btcx_riscmem *risc)
d19770e5
ST		 514{
515 struct cx23885_dev *dev = port->dev;
44a6481d 516 unsigned int i, j, n;
d19770e5
ST		 517
518 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
519 dev->name, risc->cpu, (unsigned long)risc->dma);
520 for (i = 0; i < (risc->size >> 2); i += n) {
521 printk("%s: %04d: ", dev->name, i);
86ecc027 522 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
d19770e5
ST		 523 for (j = 1; j < n; j++)
524 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
44a6481d 525 dev->name, i + j, risc->cpu[i + j], j);
86ecc027 526 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
d19770e5
ST		 527 break;
528 }
529}
530
39e75cfe 531static void cx23885_shutdown(struct cx23885_dev *dev)
d19770e5
ST		 532{
533 /* disable RISC controller */
534 cx_write(DEV_CNTRL2, 0);
535
536 /* Disable all IR activity */
537 cx_write(IR_CNTRL_REG, 0);
538
539 /* Disable Video A/B activity */
540 cx_write(VID_A_DMA_CTL, 0);
541 cx_write(VID_B_DMA_CTL, 0);
542 cx_write(VID_C_DMA_CTL, 0);
543
544 /* Disable Audio activity */
545 cx_write(AUD_INT_DMA_CTL, 0);
546 cx_write(AUD_EXT_DMA_CTL, 0);
547
548 /* Disable Serial port */
549 cx_write(UART_CTL, 0);
550
551 /* Disable Interrupts */
552 cx_write(PCI_INT_MSK, 0);
553 cx_write(VID_A_INT_MSK, 0);
554 cx_write(VID_B_INT_MSK, 0);
555 cx_write(VID_C_INT_MSK, 0);
556 cx_write(AUDIO_INT_INT_MSK, 0);
557 cx_write(AUDIO_EXT_INT_MSK, 0);
558
559}
560
39e75cfe 561static void cx23885_reset(struct cx23885_dev *dev)
d19770e5 562{
22b4e64f 563 dprintk(1, "%s()\n", __func__);
d19770e5
ST		 564
565 cx23885_shutdown(dev);
566
567 cx_write(PCI_INT_STAT, 0xffffffff);
568 cx_write(VID_A_INT_STAT, 0xffffffff);
569 cx_write(VID_B_INT_STAT, 0xffffffff);
570 cx_write(VID_C_INT_STAT, 0xffffffff);
571 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
572 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
573 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
ecda5966 574 cx_write(PAD_CTRL, 0x00500300);
d19770e5
ST		 575
576 mdelay(100);
577
7b888014
ST		 578 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
579 720*4, 0);
580 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
581 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
582 188*4, 0);
583 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
584 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
585 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
586 188*4, 0);
587 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
588 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
589 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
d19770e5 590
a6a3f140 591 cx23885_gpio_setup(dev);
d19770e5
ST		 592}
593
594
595static int cx23885_pci_quirks(struct cx23885_dev *dev)
596{
22b4e64f 597 dprintk(1, "%s()\n", __func__);
d19770e5 598
2df9a4c2
ST		 599 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
600 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
601 * occur on the cx23887 bridge.
602 */
4823e9ee 603 if(dev->bridge == CX23885_BRIDGE_885)
d19770e5 604 cx_clear(RDR_TLCTL0, 1 << 4);
4823e9ee 605
d19770e5
ST		 606 return 0;
607}
608
609static int get_resources(struct cx23885_dev *dev)
610{
611 if (request_mem_region(pci_resource_start(dev->pci,0),
44a6481d
MK		 612 pci_resource_len(dev->pci,0),
613 dev->name))
d19770e5
ST		 614 return 0;
615
616 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
617 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
618
619 return -EBUSY;
620}
621
622static void cx23885_timeout(unsigned long data);
7b888014 623int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
39e75cfe 624 u32 reg, u32 mask, u32 value);
d19770e5 625
a6a3f140 626static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
d19770e5 627{
22b4e64f 628 dprintk(1, "%s(portno=%d)\n", __func__, portno);
a6a3f140
ST		 629
630 /* Transport bus init dma queue - Common settings */
631 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
632 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
b1b81f1d
ST		 633 port->vld_misc_val = 0x0;
634 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
a6a3f140
ST		 635
636 spin_lock_init(&port->slock);
637 port->dev = dev;
638 port->nr = portno;
639
640 INIT_LIST_HEAD(&port->mpegq.active);
641 INIT_LIST_HEAD(&port->mpegq.queued);
642 port->mpegq.timeout.function = cx23885_timeout;
643 port->mpegq.timeout.data = (unsigned long)port;
644 init_timer(&port->mpegq.timeout);
645
d782ffa2
ST		 646 mutex_init(&port->frontends.lock);
647 INIT_LIST_HEAD(&port->frontends.frontend.felist);
648 port->frontends.active_fe_id = 0;
649
a6a3f140
ST		 650 switch(portno) {
651 case 1:
652 port->reg_gpcnt = VID_B_GPCNT;
653 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
654 port->reg_dma_ctl = VID_B_DMA_CTL;
655 port->reg_lngth = VID_B_LNGTH;
656 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
657 port->reg_gen_ctrl = VID_B_GEN_CTL;
658 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
659 port->reg_sop_status = VID_B_SOP_STATUS;
660 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
661 port->reg_vld_misc = VID_B_VLD_MISC;
662 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
663 port->reg_src_sel = VID_B_SRC_SEL;
664 port->reg_ts_int_msk = VID_B_INT_MSK;
b1b81f1d 665 port->reg_ts_int_stat = VID_B_INT_STAT;
a6a3f140
ST		 666 port->sram_chno = SRAM_CH03; /* VID_B */
667 port->pci_irqmask = 0x02; /* VID_B bit1 */
668 break;
669 case 2:
670 port->reg_gpcnt = VID_C_GPCNT;
671 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
672 port->reg_dma_ctl = VID_C_DMA_CTL;
673 port->reg_lngth = VID_C_LNGTH;
674 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
675 port->reg_gen_ctrl = VID_C_GEN_CTL;
676 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
677 port->reg_sop_status = VID_C_SOP_STATUS;
678 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
679 port->reg_vld_misc = VID_C_VLD_MISC;
680 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
681 port->reg_src_sel = 0;
682 port->reg_ts_int_msk = VID_C_INT_MSK;
683 port->reg_ts_int_stat = VID_C_INT_STAT;
684 port->sram_chno = SRAM_CH06; /* VID_C */
685 port->pci_irqmask = 0x04; /* VID_C bit2 */
d19770e5 686 break;
a6a3f140
ST		 687 default:
688 BUG();
d19770e5
ST		 689 }
690
a6a3f140
ST		 691 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
692 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
693
d19770e5
ST		 694 return 0;
695}
696
0ac5881a
ST		 697static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
698{
699 switch (cx_read(RDR_CFG2) & 0xff) {
700 case 0x00:
701 /* cx23885 */
702 dev->hwrevision = 0xa0;
703 break;
704 case 0x01:
705 /* CX23885-12Z */
706 dev->hwrevision = 0xa1;
707 break;
708 case 0x02:
709 /* CX23885-13Z */
710 dev->hwrevision = 0xb0;
711 break;
712 case 0x03:
713 /* CX23888-22Z */
714 dev->hwrevision = 0xc0;
715 break;
716 case 0x0e:
717 /* CX23887-15Z */
718 dev->hwrevision = 0xc0;
719 case 0x0f:
720 /* CX23887-14Z */
721 dev->hwrevision = 0xb1;
722 break;
723 default:
724 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
22b4e64f 725 __func__, dev->hwrevision);
0ac5881a
ST		 726 }
727 if (dev->hwrevision)
728 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
22b4e64f 729 __func__, dev->hwrevision);
0ac5881a
ST		 730 else
731 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
22b4e64f 732 __func__, dev->hwrevision);
0ac5881a
ST		 733}
734
d19770e5
ST		 735static int cx23885_dev_setup(struct cx23885_dev *dev)
736{
737 int i;
738
739 mutex_init(&dev->lock);
740
741 atomic_inc(&dev->refcount);
742
743 dev->nr = cx23885_devcount++;
579f1163
ST		 744 sprintf(dev->name, "cx23885[%d]", dev->nr);
745
746 mutex_lock(&devlist);
747 list_add_tail(&dev->devlist, &cx23885_devlist);
748 mutex_unlock(&devlist);
749
750 /* Configure the internal memory */
751 if(dev->pci->device == 0x8880) {
752 dev->bridge = CX23885_BRIDGE_887;
c7712613
ST		 753 /* Apply a sensible clock frequency for the PCIe bridge */
754 dev->clk_freq = 25000000;
7e994302 755 dev->sram_channels = cx23887_sram_channels;
579f1163
ST		 756 } else
757 if(dev->pci->device == 0x8852) {
758 dev->bridge = CX23885_BRIDGE_885;
c7712613
ST		 759 /* Apply a sensible clock frequency for the PCIe bridge */
760 dev->clk_freq = 28000000;
7e994302 761 dev->sram_channels = cx23885_sram_channels;
579f1163
ST		 762 } else
763 BUG();
764
765 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
22b4e64f 766 __func__, dev->bridge);
579f1163
ST		 767
768 /* board config */
769 dev->board = UNSET;
770 if (card[dev->nr] < cx23885_bcount)
771 dev->board = card[dev->nr];
772 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
773 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
774 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
775 dev->board = cx23885_subids[i].card;
776 if (UNSET == dev->board) {
777 dev->board = CX23885_BOARD_UNKNOWN;
778 cx23885_card_list(dev);
779 }
780
c7712613
ST		 781 /* If the user specific a clk freq override, apply it */
782 if (cx23885_boards[dev->board].clk_freq > 0)
783 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
784
d19770e5
ST		 785 dev->pci_bus = dev->pci->bus->number;
786 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
787 dev->pci_irqmask = 0x001f00;
788
789 /* External Master 1 Bus */
790 dev->i2c_bus[0].nr = 0;
791 dev->i2c_bus[0].dev = dev;
792 dev->i2c_bus[0].reg_stat = I2C1_STAT;
793 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
794 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
795 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
796 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
797 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
798
799 /* External Master 2 Bus */
800 dev->i2c_bus[1].nr = 1;
801 dev->i2c_bus[1].dev = dev;
802 dev->i2c_bus[1].reg_stat = I2C2_STAT;
803 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
804 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
805 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
806 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
807 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
808
809 /* Internal Master 3 Bus */
810 dev->i2c_bus[2].nr = 2;
811 dev->i2c_bus[2].dev = dev;
812 dev->i2c_bus[2].reg_stat = I2C3_STAT;
813 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
a2129af5 814 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
d19770e5
ST		 815 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
816 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
817 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
818
b1b81f1d
ST		 819 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
820 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
a6a3f140 821 cx23885_init_tsport(dev, &dev->ts1, 1);
579f1163 822
b1b81f1d
ST		 823 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
824 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
a6a3f140 825 cx23885_init_tsport(dev, &dev->ts2, 2);
d19770e5 826
d19770e5
ST		 827 if (get_resources(dev) < 0) {
828 printk(KERN_ERR "CORE %s No more PCIe resources for "
44a6481d
MK		 829 "subsystem: %04x:%04x\n",
830 dev->name, dev->pci->subsystem_vendor,
831 dev->pci->subsystem_device);
d19770e5
ST		 832
833 cx23885_devcount--;
fcf94c89 834 return -ENODEV;
d19770e5
ST		 835 }
836
d19770e5
ST		 837 /* PCIe stuff */
838 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
44a6481d 839 pci_resource_len(dev->pci,0));
d19770e5
ST		 840
841 dev->bmmio = (u8 __iomem *)dev->lmmio;
842
d19770e5 843 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
44a6481d
MK		 844 dev->name, dev->pci->subsystem_vendor,
845 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
846 dev->board, card[dev->nr] == dev->board ?
847 "insmod option" : "autodetected");
d19770e5 848
4823e9ee
ST		 849 cx23885_pci_quirks(dev);
850
7b888014
ST		 851 /* Assume some sensible defaults */
852 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
853 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
854 dev->radio_type = cx23885_boards[dev->board].radio_type;
855 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
856
857 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
22b4e64f 858 __func__, dev->tuner_type, dev->tuner_addr);
7b888014 859 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
22b4e64f 860 __func__, dev->radio_type, dev->radio_addr);
7b888014 861
d19770e5
ST		 862 /* init hardware */
863 cx23885_reset(dev);
864
865 cx23885_i2c_register(&dev->i2c_bus[0]);
866 cx23885_i2c_register(&dev->i2c_bus[1]);
867 cx23885_i2c_register(&dev->i2c_bus[2]);
d19770e5 868 cx23885_card_setup(dev);
ce89cfb4 869 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
d19770e5
ST		 870 cx23885_ir_init(dev);
871
7b888014
ST		 872 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
873 if (cx23885_video_register(dev) < 0) {
874 printk(KERN_ERR "%s() Failed to register analog "
22b4e64f 875 "video adapters on VID_A\n", __func__);
7b888014
ST		 876 }
877 }
878
879 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
a6a3f140
ST		 880 if (cx23885_dvb_register(&dev->ts1) < 0) {
881 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
22b4e64f 882 __func__);
a6a3f140 883 }
b1b81f1d
ST		 884 } else
885 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
886 if (cx23885_417_register(dev) < 0) {
887 printk(KERN_ERR
888 "%s() Failed to register 417 on VID_B\n",
889 __func__);
890 }
579f1163
ST		 891 }
892
7b888014 893 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
a6a3f140 894 if (cx23885_dvb_register(&dev->ts2) < 0) {
b1b81f1d
ST		 895 printk(KERN_ERR
896 "%s() Failed to register dvb on VID_C\n",
897 __func__);
898 }
899 } else
900 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
901 if (cx23885_417_register(dev) < 0) {
902 printk(KERN_ERR
903 "%s() Failed to register 417 on VID_C\n",
22b4e64f 904 __func__);
a6a3f140 905 }
d19770e5
ST		 906 }
907
0ac5881a
ST		 908 cx23885_dev_checkrevision(dev);
909
d19770e5 910 return 0;
d19770e5
ST		 911}
912
39e75cfe 913static void cx23885_dev_unregister(struct cx23885_dev *dev)
d19770e5
ST		 914{
915 release_mem_region(pci_resource_start(dev->pci,0),
916 pci_resource_len(dev->pci,0));
917
918 if (!atomic_dec_and_test(&dev->refcount))
919 return;
920
7b888014
ST		 921 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
922 cx23885_video_unregister(dev);
923
b1b81f1d 924 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
a6a3f140
ST		 925 cx23885_dvb_unregister(&dev->ts1);
926
b1b81f1d
ST		 927 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
928 cx23885_417_unregister(dev);
929
930 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
a6a3f140
ST		 931 cx23885_dvb_unregister(&dev->ts2);
932
b1b81f1d
ST		 933 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
934 cx23885_417_unregister(dev);
935
d19770e5
ST		 936 cx23885_i2c_unregister(&dev->i2c_bus[2]);
937 cx23885_i2c_unregister(&dev->i2c_bus[1]);
938 cx23885_i2c_unregister(&dev->i2c_bus[0]);
939
940 iounmap(dev->lmmio);
941}
942
d8eaa58b 943static __le32* cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
44a6481d
MK		 944 unsigned int offset, u32 sync_line,
945 unsigned int bpl, unsigned int padding,
946 unsigned int lines)
d19770e5
ST		 947{
948 struct scatterlist *sg;
44a6481d 949 unsigned int line, todo;
d19770e5
ST		 950
951 /* sync instruction */
952 if (sync_line != NO_SYNC_LINE)
953 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
954
955 /* scan lines */
956 sg = sglist;
957 for (line = 0; line < lines; line++) {
958 while (offset && offset >= sg_dma_len(sg)) {
959 offset -= sg_dma_len(sg);
960 sg++;
961 }
962 if (bpl <= sg_dma_len(sg)-offset) {
963 /* fits into current chunk */
964 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
965 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
966 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
967 offset+=bpl;
968 } else {
969 /* scanline needs to be split */
970 todo = bpl;
971 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
972 (sg_dma_len(sg)-offset));
973 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
974 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
975 todo -= (sg_dma_len(sg)-offset);
976 offset = 0;
977 sg++;
978 while (todo > sg_dma_len(sg)) {
979 *(rp++)=cpu_to_le32(RISC_WRITE|
980 sg_dma_len(sg));
981 *(rp++)=cpu_to_le32(sg_dma_address(sg));
982 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
983 todo -= sg_dma_len(sg);
984 sg++;
985 }
986 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
987 *(rp++)=cpu_to_le32(sg_dma_address(sg));
988 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
989 offset += todo;
990 }
991 offset += padding;
992 }
993
994 return rp;
995}
996
7b888014
ST		 997int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
998 struct scatterlist *sglist, unsigned int top_offset,
999 unsigned int bottom_offset, unsigned int bpl,
1000 unsigned int padding, unsigned int lines)
1001{
1002 u32 instructions, fields;
d8eaa58b 1003 __le32 *rp;
7b888014
ST		 1004 int rc;
1005
1006 fields = 0;
1007 if (UNSET != top_offset)
1008 fields++;
1009 if (UNSET != bottom_offset)
1010 fields++;
1011
1012 /* estimate risc mem: worst case is one write per page border +
1013 one write per scan line + syncs + jump (all 2 dwords). Padding
1014 can cause next bpl to start close to a page border. First DMA
1015 region may be smaller than PAGE_SIZE */
1016 /* write and jump need and extra dword */
1017 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1018 instructions += 2;
1019 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1020 return rc;
1021
1022 /* write risc instructions */
1023 rp = risc->cpu;
1024 if (UNSET != top_offset)
1025 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1026 bpl, padding, lines);
1027 if (UNSET != bottom_offset)
1028 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1029 bpl, padding, lines);
1030
1031 /* save pointer to jmp instruction address */
1032 risc->jmp = rp;
1033 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1034 return 0;
1035}
d19770e5 1036
39e75cfe
AB		 1037static int cx23885_risc_databuffer(struct pci_dev *pci,
1038 struct btcx_riscmem *risc,
1039 struct scatterlist *sglist,
1040 unsigned int bpl,
1041 unsigned int lines)
d19770e5
ST		 1042{
1043 u32 instructions;
d8eaa58b 1044 __le32 *rp;
d19770e5
ST		 1045 int rc;
1046
1047 /* estimate risc mem: worst case is one write per page border +
1048 one write per scan line + syncs + jump (all 2 dwords). Here
1049 there is no padding and no sync. First DMA region may be smaller
1050 than PAGE_SIZE */
1051 /* Jump and write need an extra dword */
1052 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1053 instructions += 1;
1054
d19770e5
ST		 1055 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1056 return rc;
1057
1058 /* write risc instructions */
1059 rp = risc->cpu;
1060 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1061
1062 /* save pointer to jmp instruction address */
1063 risc->jmp = rp;
1064 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1065 return 0;
1066}
1067
7b888014 1068int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
39e75cfe 1069 u32 reg, u32 mask, u32 value)
d19770e5 1070{
d8eaa58b 1071 __le32 *rp;
d19770e5
ST		 1072 int rc;
1073
1074 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
1075 return rc;
1076
1077 /* write risc instructions */
1078 rp = risc->cpu;
d19770e5
ST		 1079 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
1080 *(rp++) = cpu_to_le32(reg);
1081 *(rp++) = cpu_to_le32(value);
1082 *(rp++) = cpu_to_le32(mask);
1083 *(rp++) = cpu_to_le32(RISC_JUMP);
1084 *(rp++) = cpu_to_le32(risc->dma);
1085 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1086 return 0;
1087}
1088
1089void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1090{
409d84f8
TP		 1091 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1092
d19770e5 1093 BUG_ON(in_interrupt());
44a6481d 1094 videobuf_waiton(&buf->vb, 0, 0);
409d84f8
TP		 1095 videobuf_dma_unmap(q, dma);
1096 videobuf_dma_free(dma);
a920e42f 1097 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
0fc0686e 1098 buf->vb.state = VIDEOBUF_NEEDS_INIT;
d19770e5
ST		 1099}
1100
7b888014
ST		 1101static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1102{
1103 struct cx23885_dev *dev = port->dev;
1104
22b4e64f
HH		 1105 dprintk(1, "%s() Register Dump\n", __func__);
1106 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
7b888014 1107 cx_read(DEV_CNTRL2));
22b4e64f 1108 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
7b888014 1109 cx_read(PCI_INT_MSK));
22b4e64f 1110 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
7b888014 1111 cx_read(AUDIO_INT_INT_MSK));
22b4e64f 1112 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
7b888014 1113 cx_read(AUD_INT_DMA_CTL));
22b4e64f 1114 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
7b888014 1115 cx_read(AUDIO_EXT_INT_MSK));
22b4e64f 1116 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
7b888014 1117 cx_read(AUD_EXT_DMA_CTL));
22b4e64f 1118 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
7b888014 1119 cx_read(PAD_CTRL));
22b4e64f 1120 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
7b888014 1121 cx_read(ALT_PIN_OUT_SEL));
22b4e64f 1122 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
7b888014 1123 cx_read(GPIO2));
22b4e64f 1124 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
7b888014 1125 port->reg_gpcnt, cx_read(port->reg_gpcnt));
22b4e64f 1126 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
7b888014 1127 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
22b4e64f 1128 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
7b888014 1129 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
7b913908
ST		 1130 if (port->reg_src_sel)
1131 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1132 port->reg_src_sel, cx_read(port->reg_src_sel));
22b4e64f 1133 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
7b888014 1134 port->reg_lngth, cx_read(port->reg_lngth));
22b4e64f 1135 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
7b888014 1136 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
22b4e64f 1137 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
7b888014 1138 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
22b4e64f 1139 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
7b888014 1140 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
22b4e64f 1141 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
7b888014 1142 port->reg_sop_status, cx_read(port->reg_sop_status));
22b4e64f 1143 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
7b888014 1144 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
22b4e64f 1145 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
7b888014 1146 port->reg_vld_misc, cx_read(port->reg_vld_misc));
22b4e64f 1147 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
7b888014 1148 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
22b4e64f 1149 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
7b888014
ST		 1150 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1151}
1152
d19770e5 1153static int cx23885_start_dma(struct cx23885_tsport *port,
44a6481d
MK		 1154 struct cx23885_dmaqueue *q,
1155 struct cx23885_buffer *buf)
d19770e5
ST		 1156{
1157 struct cx23885_dev *dev = port->dev;
a589b665 1158 u32 reg;
d19770e5 1159
22b4e64f 1160 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
44a6481d 1161 buf->vb.width, buf->vb.height, buf->vb.field);
d19770e5 1162
d8d12b43
ST		 1163 /* Stop the fifo and risc engine for this port */
1164 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1165
d19770e5
ST		 1166 /* setup fifo + format */
1167 cx23885_sram_channel_setup(dev,
44a6481d
MK		 1168 &dev->sram_channels[ port->sram_chno ],
1169 port->ts_packet_size, buf->risc.dma);
3328e4fb 1170 if(debug > 5) {
d19770e5 1171 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
d19770e5 1172 cx23885_risc_disasm(port, &buf->risc);
3328e4fb 1173 }
d19770e5
ST		 1174
1175 /* write TS length to chip */
1176 cx_write(port->reg_lngth, buf->vb.width);
1177
661c7e44
ST		 1178 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1179 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1180 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
22b4e64f 1181 __func__,
661c7e44
ST		 1182 cx23885_boards[dev->board].portb,
1183 cx23885_boards[dev->board].portc );
d19770e5
ST		 1184 return -EINVAL;
1185 }
1186
a589b665
ST		 1187 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1188 cx23885_av_clk(dev, 0);
1189
d19770e5
ST		 1190 udelay(100);
1191
579f1163
ST		 1192 /* If the port supports SRC SELECT, configure it */
1193 if(port->reg_src_sel)
1194 cx_write(port->reg_src_sel, port->src_sel_val);
1195
b1b81f1d 1196 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
d19770e5 1197 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
b1b81f1d 1198 cx_write(port->reg_vld_misc, port->vld_misc_val);
d19770e5
ST		 1199 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1200 udelay(100);
1201
579f1163 1202 // NOTE: this is 2 (reserved) for portb, does it matter?
d19770e5
ST		 1203 /* reset counter to zero */
1204 cx_write(port->reg_gpcnt_ctl, 3);
1205 q->count = 1;
1206
52ce27bf
ST		 1207 /* Set VIDB pins to input */
1208 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1209 reg = cx_read(PAD_CTRL);
1210 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1211 cx_write(PAD_CTRL, reg);
1212 }
1213
1214 /* Set VIDC pins to input */
1215 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1216 reg = cx_read(PAD_CTRL);
1217 reg &= ~0x4; /* Clear TS2_SOP_OE */
1218 cx_write(PAD_CTRL, reg);
1219 }
1220
1221 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
a589b665
ST		 1222
1223 reg = cx_read(PAD_CTRL);
1224 reg = reg & ~0x1; /* Clear TS1_OE */
1225
1226 /* FIXME, bit 2 writing here is questionable */
1227 /* set TS1_SOP_OE and TS1_OE_HI */
1228 reg = reg | 0xa;
1229 cx_write(PAD_CTRL, reg);
1230
1231 /* FIXME and these two registers should be documented. */
1232 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1233 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1234 }
1235
e133be0f 1236 switch(dev->bridge) {
d19770e5 1237 case CX23885_BRIDGE_885:
3bd40659 1238 case CX23885_BRIDGE_887:
d19770e5 1239 /* enable irqs */
22b4e64f 1240 dprintk(1, "%s() enabling TS int's and DMA\n", __func__ );
d19770e5
ST		 1241 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1242 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1243 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1244 break;
d19770e5 1245 default:
579f1163 1246 BUG();
d19770e5
ST		 1247 }
1248
d19770e5
ST		 1249 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1250
a589b665
ST		 1251 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1252 cx23885_av_clk(dev, 1);
1253
7b888014
ST		 1254 if (debug > 4)
1255 cx23885_tsport_reg_dump(port);
1256
d19770e5
ST		 1257 return 0;
1258}
1259
1260static int cx23885_stop_dma(struct cx23885_tsport *port)
1261{
1262 struct cx23885_dev *dev = port->dev;
a589b665
ST		 1263 u32 reg;
1264
22b4e64f 1265 dprintk(1, "%s()\n", __func__);
d19770e5
ST		 1266
1267 /* Stop interrupts and DMA */
1268 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1269 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1270
52ce27bf 1271 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
a589b665
ST		 1272
1273 reg = cx_read(PAD_CTRL);
1274
1275 /* Set TS1_OE */
1276 reg = reg | 0x1;
1277
1278 /* clear TS1_SOP_OE and TS1_OE_HI */
1279 reg = reg & ~0xa;
1280 cx_write(PAD_CTRL, reg);
1281 cx_write(port->reg_src_sel, 0);
1282 cx_write(port->reg_gen_ctrl, 8);
1283
1284 }
1285
1286 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1287 cx23885_av_clk(dev, 0);
1288
d19770e5
ST		 1289 return 0;
1290}
1291
7b888014 1292int cx23885_restart_queue(struct cx23885_tsport *port,
d19770e5
ST		 1293 struct cx23885_dmaqueue *q)
1294{
1295 struct cx23885_dev *dev = port->dev;
1296 struct cx23885_buffer *buf;
d19770e5 1297
22b4e64f 1298 dprintk(5, "%s()\n", __func__);
d19770e5
ST		 1299 if (list_empty(&q->active))
1300 {
44a6481d
MK		 1301 struct cx23885_buffer *prev;
1302 prev = NULL;
d19770e5 1303
22b4e64f 1304 dprintk(5, "%s() queue is empty\n", __func__);
d19770e5 1305
44a6481d
MK		 1306 for (;;) {
1307 if (list_empty(&q->queued))
1308 return 0;
1309 buf = list_entry(q->queued.next, struct cx23885_buffer,
1310 vb.queue);
1311 if (NULL == prev) {
1312 list_del(&buf->vb.queue);
1313 list_add_tail(&buf->vb.queue, &q->active);
1314 cx23885_start_dma(port, q, buf);
0fc0686e 1315 buf->vb.state = VIDEOBUF_ACTIVE;
44a6481d
MK		 1316 buf->count = q->count++;
1317 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1318 dprintk(5, "[%p/%d] restart_queue - first active\n",
1319 buf, buf->vb.i);
1320
1321 } else if (prev->vb.width == buf->vb.width &&
1322 prev->vb.height == buf->vb.height &&
1323 prev->fmt == buf->fmt) {
1324 list_del(&buf->vb.queue);
1325 list_add_tail(&buf->vb.queue, &q->active);
0fc0686e 1326 buf->vb.state = VIDEOBUF_ACTIVE;
44a6481d
MK		 1327 buf->count = q->count++;
1328 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1329 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1330 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1331 buf, buf->vb.i);
1332 } else {
1333 return 0;
1334 }
1335 prev = buf;
1336 }
d19770e5
ST		 1337 return 0;
1338 }
1339
1340 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
44a6481d 1341 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
d19770e5
ST		 1342 buf, buf->vb.i);
1343 cx23885_start_dma(port, q, buf);
a991f44b 1344 list_for_each_entry(buf, &q->active, vb.queue)
d19770e5 1345 buf->count = q->count++;
44a6481d 1346 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 1347 return 0;
1348}
1349
1350/* ------------------------------------------------------------------ */
1351
1352int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1353 struct cx23885_buffer *buf, enum v4l2_field field)
1354{
1355 struct cx23885_dev *dev = port->dev;
1356 int size = port->ts_packet_size * port->ts_packet_count;
1357 int rc;
1358
22b4e64f 1359 dprintk(1, "%s: %p\n", __func__, buf);
d19770e5
ST		 1360 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1361 return -EINVAL;
1362
0fc0686e 1363 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
d19770e5
ST		 1364 buf->vb.width = port->ts_packet_size;
1365 buf->vb.height = port->ts_packet_count;
1366 buf->vb.size = size;
1367 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1368
44a6481d 1369 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
d19770e5
ST		 1370 goto fail;
1371 cx23885_risc_databuffer(dev->pci, &buf->risc,
409d84f8
TP		 1372 videobuf_to_dma(&buf->vb)->sglist,
1373 buf->vb.width, buf->vb.height);
d19770e5 1374 }
0fc0686e 1375 buf->vb.state = VIDEOBUF_PREPARED;
d19770e5
ST		 1376 return 0;
1377
1378 fail:
44a6481d 1379 cx23885_free_buffer(q, buf);
d19770e5
ST		 1380 return rc;
1381}
1382
1383void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1384{
1385 struct cx23885_buffer *prev;
1386 struct cx23885_dev *dev = port->dev;
1387 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1388
1389 /* add jump to stopper */
1390 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1391 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1392 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1393
1394 if (list_empty(&cx88q->active)) {
1395 dprintk( 1, "queue is empty - first active\n" );
44a6481d 1396 list_add_tail(&buf->vb.queue, &cx88q->active);
d19770e5 1397 cx23885_start_dma(port, cx88q, buf);
0fc0686e 1398 buf->vb.state = VIDEOBUF_ACTIVE;
d19770e5 1399 buf->count = cx88q->count++;
44a6481d
MK		 1400 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1401 dprintk(1, "[%p/%d] %s - first active\n",
22b4e64f 1402 buf, buf->vb.i, __func__);
d19770e5
ST		 1403 } else {
1404 dprintk( 1, "queue is not empty - append to active\n" );
44a6481d
MK		 1405 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1406 vb.queue);
1407 list_add_tail(&buf->vb.queue, &cx88q->active);
0fc0686e 1408 buf->vb.state = VIDEOBUF_ACTIVE;
d19770e5
ST		 1409 buf->count = cx88q->count++;
1410 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1411 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1412 dprintk( 1, "[%p/%d] %s - append to active\n",
22b4e64f 1413 buf, buf->vb.i, __func__);
d19770e5
ST		 1414 }
1415}
1416
1417/* ----------------------------------------------------------- */
1418
44a6481d
MK		 1419static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1420 int restart)
d19770e5
ST		 1421{
1422 struct cx23885_dev *dev = port->dev;
1423 struct cx23885_dmaqueue *q = &port->mpegq;
1424 struct cx23885_buffer *buf;
1425 unsigned long flags;
1426
44a6481d 1427 spin_lock_irqsave(&port->slock, flags);
d19770e5 1428 while (!list_empty(&q->active)) {
44a6481d
MK		 1429 buf = list_entry(q->active.next, struct cx23885_buffer,
1430 vb.queue);
d19770e5 1431 list_del(&buf->vb.queue);
0fc0686e 1432 buf->vb.state = VIDEOBUF_ERROR;
d19770e5 1433 wake_up(&buf->vb.done);
44a6481d 1434 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
d19770e5
ST		 1435 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1436 }
44a6481d 1437 if (restart) {
d19770e5
ST		 1438 dprintk(1, "restarting queue\n" );
1439 cx23885_restart_queue(port, q);
1440 }
44a6481d 1441 spin_unlock_irqrestore(&port->slock, flags);
d19770e5
ST		 1442}
1443
b1b81f1d
ST		 1444void cx23885_cancel_buffers(struct cx23885_tsport *port)
1445{
1446 struct cx23885_dev *dev = port->dev;
1447 struct cx23885_dmaqueue *q = &port->mpegq;
1448
26d2e854 1449 dprintk(1, "%s()\n", __func__);
b1b81f1d
ST		 1450 del_timer_sync(&q->timeout);
1451 cx23885_stop_dma(port);
1452 do_cancel_buffers(port, "cancel", 0);
1453}
d19770e5
ST		 1454
1455static void cx23885_timeout(unsigned long data)
1456{
1457 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1458 struct cx23885_dev *dev = port->dev;
1459
22b4e64f 1460 dprintk(1, "%s()\n",__func__);
d19770e5
ST		 1461
1462 if (debug > 5)
d19770e5 1463 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
3328e4fb 1464
d19770e5
ST		 1465 cx23885_stop_dma(port);
1466 do_cancel_buffers(port, "timeout", 1);
1467}
1468
b1b81f1d
ST		 1469int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1470{
1471 /* FIXME: port1 assumption here. */
1472 struct cx23885_tsport *port = &dev->ts1;
1473 int count = 0;
1474 int handled = 0;
1475
1476 if (status == 0)
1477 return handled;
1478
1479 count = cx_read(port->reg_gpcnt);
1480 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1481 status, cx_read(port->reg_ts_int_msk), count);
1482
1483 if ((status & VID_B_MSK_BAD_PKT) ||
1484 (status & VID_B_MSK_OPC_ERR) ||
1485 (status & VID_B_MSK_VBI_OPC_ERR) ||
1486 (status & VID_B_MSK_SYNC) ||
1487 (status & VID_B_MSK_VBI_SYNC) ||
1488 (status & VID_B_MSK_OF) ||
1489 (status & VID_B_MSK_VBI_OF)) {
1490 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1491 "= 0x%x\n", dev->name, status);
1492 if (status & VID_B_MSK_BAD_PKT)
1493 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1494 if (status & VID_B_MSK_OPC_ERR)
1495 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1496 if (status & VID_B_MSK_VBI_OPC_ERR)
1497 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1498 if (status & VID_B_MSK_SYNC)
1499 dprintk(1, " VID_B_MSK_SYNC\n");
1500 if (status & VID_B_MSK_VBI_SYNC)
1501 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1502 if (status & VID_B_MSK_OF)
1503 dprintk(1, " VID_B_MSK_OF\n");
1504 if (status & VID_B_MSK_VBI_OF)
1505 dprintk(1, " VID_B_MSK_VBI_OF\n");
1506
1507 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1508 cx23885_sram_channel_dump(dev,
1509 &dev->sram_channels[port->sram_chno]);
1510 cx23885_417_check_encoder(dev);
1511 } else if (status & VID_B_MSK_RISCI1) {
1512 dprintk(7, " VID_B_MSK_RISCI1\n");
1513 spin_lock(&port->slock);
1514 cx23885_wakeup(port, &port->mpegq, count);
1515 spin_unlock(&port->slock);
1516 } else if (status & VID_B_MSK_RISCI2) {
1517 dprintk(7, " VID_B_MSK_RISCI2\n");
1518 spin_lock(&port->slock);
1519 cx23885_restart_queue(port, &port->mpegq);
1520 spin_unlock(&port->slock);
1521 }
1522 if (status) {
1523 cx_write(port->reg_ts_int_stat, status);
1524 handled = 1;
1525 }
1526
1527 return handled;
1528}
1529
a6a3f140
ST		 1530static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1531{
1532 struct cx23885_dev *dev = port->dev;
1533 int handled = 0;
1534 u32 count;
1535
b1b81f1d
ST		 1536 if ((status & VID_BC_MSK_OPC_ERR) ||
1537 (status & VID_BC_MSK_BAD_PKT) ||
1538 (status & VID_BC_MSK_SYNC) ||
1539 (status & VID_BC_MSK_OF))
a6a3f140
ST		 1540 {
1541 if (status & VID_BC_MSK_OPC_ERR)
1542 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1543 if (status & VID_BC_MSK_BAD_PKT)
1544 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1545 if (status & VID_BC_MSK_SYNC)
1546 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
1547 if (status & VID_BC_MSK_OF)
1548 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
1549
1550 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1551
1552 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
b1b81f1d
ST		 1553 cx23885_sram_channel_dump(dev,
1554 &dev->sram_channels[port->sram_chno]);
a6a3f140
ST		 1555
1556 } else if (status & VID_BC_MSK_RISCI1) {
1557
1558 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1559
1560 spin_lock(&port->slock);
1561 count = cx_read(port->reg_gpcnt);
1562 cx23885_wakeup(port, &port->mpegq, count);
1563 spin_unlock(&port->slock);
1564
1565 } else if (status & VID_BC_MSK_RISCI2) {
1566
1567 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1568
1569 spin_lock(&port->slock);
1570 cx23885_restart_queue(port, &port->mpegq);
1571 spin_unlock(&port->slock);
1572
1573 }
1574 if (status) {
1575 cx_write(port->reg_ts_int_stat, status);
1576 handled = 1;
1577 }
1578
1579 return handled;
1580}
1581
03121f05 1582static irqreturn_t cx23885_irq(int irq, void *dev_id)
d19770e5
ST		 1583{
1584 struct cx23885_dev *dev = dev_id;
a6a3f140
ST		 1585 struct cx23885_tsport *ts1 = &dev->ts1;
1586 struct cx23885_tsport *ts2 = &dev->ts2;
d19770e5 1587 u32 pci_status, pci_mask;
7b888014 1588 u32 vida_status, vida_mask;
6f074abb 1589 u32 ts1_status, ts1_mask;
d19770e5 1590 u32 ts2_status, ts2_mask;
7b888014 1591 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
d19770e5
ST		 1592
1593 pci_status = cx_read(PCI_INT_STAT);
1594 pci_mask = cx_read(PCI_INT_MSK);
7b888014
ST		 1595 vida_status = cx_read(VID_A_INT_STAT);
1596 vida_mask = cx_read(VID_A_INT_MSK);
6f074abb
ST		 1597 ts1_status = cx_read(VID_B_INT_STAT);
1598 ts1_mask = cx_read(VID_B_INT_MSK);
d19770e5
ST		 1599 ts2_status = cx_read(VID_C_INT_STAT);
1600 ts2_mask = cx_read(VID_C_INT_MSK);
1601
6f074abb 1602 if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
d19770e5
ST		 1603 goto out;
1604
7b888014 1605 vida_count = cx_read(VID_A_GPCNT);
a6a3f140
ST		 1606 ts1_count = cx_read(ts1->reg_gpcnt);
1607 ts2_count = cx_read(ts2->reg_gpcnt);
7b888014
ST		 1608 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1609 pci_status, pci_mask);
1610 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1611 vida_status, vida_mask, vida_count);
1612 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1613 ts1_status, ts1_mask, ts1_count);
1614 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1615 ts2_status, ts2_mask, ts2_count);
d19770e5
ST		 1616
1617 if ( (pci_status & PCI_MSK_RISC_RD) ||
44a6481d
MK		 1618 (pci_status & PCI_MSK_RISC_WR) ||
1619 (pci_status & PCI_MSK_AL_RD) ||
1620 (pci_status & PCI_MSK_AL_WR) ||
1621 (pci_status & PCI_MSK_APB_DMA) ||
1622 (pci_status & PCI_MSK_VID_C) ||
1623 (pci_status & PCI_MSK_VID_B) ||
1624 (pci_status & PCI_MSK_VID_A) ||
1625 (pci_status & PCI_MSK_AUD_INT) ||
1626 (pci_status & PCI_MSK_AUD_EXT) )
d19770e5
ST		 1627 {
1628
1629 if (pci_status & PCI_MSK_RISC_RD)
1630 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1631 if (pci_status & PCI_MSK_RISC_WR)
1632 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1633 if (pci_status & PCI_MSK_AL_RD)
1634 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1635 if (pci_status & PCI_MSK_AL_WR)
1636 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1637 if (pci_status & PCI_MSK_APB_DMA)
1638 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1639 if (pci_status & PCI_MSK_VID_C)
1640 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1641 if (pci_status & PCI_MSK_VID_B)
1642 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1643 if (pci_status & PCI_MSK_VID_A)
1644 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1645 if (pci_status & PCI_MSK_AUD_INT)
1646 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1647 if (pci_status & PCI_MSK_AUD_EXT)
1648 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1649
1650 }
1651
7b888014
ST		 1652 if (ts1_status) {
1653 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1654 handled += cx23885_irq_ts(ts1, ts1_status);
b1b81f1d
ST		 1655 else
1656 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1657 handled += cx23885_irq_417(dev, ts1_status);
7b888014
ST		 1658 }
1659
1660 if (ts2_status) {
1661 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1662 handled += cx23885_irq_ts(ts2, ts2_status);
b1b81f1d
ST		 1663 else
1664 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1665 handled += cx23885_irq_417(dev, ts2_status);
7b888014 1666 }
6f074abb 1667
7b888014
ST		 1668 if (vida_status)
1669 handled += cx23885_video_irq(dev, vida_status);
6f074abb
ST		 1670
1671 if (handled)
1672 cx_write(PCI_INT_STAT, pci_status);
d19770e5
ST		 1673out:
1674 return IRQ_RETVAL(handled);
1675}
1676
1677static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
44a6481d 1678 const struct pci_device_id *pci_id)
d19770e5
ST		 1679{
1680 struct cx23885_dev *dev;
1681 int err;
1682
44a6481d 1683 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
d19770e5
ST		 1684 if (NULL == dev)
1685 return -ENOMEM;
1686
1687 /* pci init */
1688 dev->pci = pci_dev;
1689 if (pci_enable_device(pci_dev)) {
1690 err = -EIO;
1691 goto fail_free;
1692 }
1693
1694 if (cx23885_dev_setup(dev) < 0) {
1695 err = -EINVAL;
1696 goto fail_free;
1697 }
1698
1699 /* print pci info */
1700 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1701 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1702 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1703 "latency: %d, mmio: 0x%llx\n", dev->name,
1704 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
a589b665
ST		 1705 dev->pci_lat,
1706 (unsigned long long)pci_resource_start(pci_dev, 0));
d19770e5
ST		 1707
1708 pci_set_master(pci_dev);
1709 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1710 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1711 err = -EIO;
1712 goto fail_irq;
1713 }
1714
44a6481d
MK		 1715 err = request_irq(pci_dev->irq, cx23885_irq,
1716 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
d19770e5
ST		 1717 if (err < 0) {
1718 printk(KERN_ERR "%s: can't get IRQ %d\n",
1719 dev->name, pci_dev->irq);
1720 goto fail_irq;
1721 }
1722
1723 pci_set_drvdata(pci_dev, dev);
1724 return 0;
1725
1726fail_irq:
1727 cx23885_dev_unregister(dev);
1728fail_free:
1729 kfree(dev);
1730 return err;
1731}
1732
1733static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1734{
1735 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1736
1737 cx23885_shutdown(dev);
1738
1739 pci_disable_device(pci_dev);
1740
1741 /* unregister stuff */
1742 free_irq(pci_dev->irq, dev);
1743 pci_set_drvdata(pci_dev, NULL);
1744
1745 mutex_lock(&devlist);
1746 list_del(&dev->devlist);
1747 mutex_unlock(&devlist);
1748
1749 cx23885_dev_unregister(dev);
1750 kfree(dev);
1751}
1752
1753static struct pci_device_id cx23885_pci_tbl[] = {
1754 {
1755 /* CX23885 */
1756 .vendor = 0x14f1,
1757 .device = 0x8852,
1758 .subvendor = PCI_ANY_ID,
1759 .subdevice = PCI_ANY_ID,
1760 },{
1761 /* CX23887 Rev 2 */
1762 .vendor = 0x14f1,
1763 .device = 0x8880,
1764 .subvendor = PCI_ANY_ID,
1765 .subdevice = PCI_ANY_ID,
1766 },{
1767 /* --- end of list --- */
1768 }
1769};
1770MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1771
1772static struct pci_driver cx23885_pci_driver = {
1773 .name = "cx23885",
1774 .id_table = cx23885_pci_tbl,
1775 .probe = cx23885_initdev,
1776 .remove = __devexit_p(cx23885_finidev),
1777 /* TODO */
1778 .suspend = NULL,
1779 .resume = NULL,
1780};
1781
1782static int cx23885_init(void)
1783{
1784 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
047646bf
ST		 1785 (CX23885_VERSION_CODE >> 16) & 0xff,
1786 (CX23885_VERSION_CODE >> 8) & 0xff,
1787 CX23885_VERSION_CODE & 0xff);
d19770e5
ST		 1788#ifdef SNAPSHOT
1789 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1790 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1791#endif
1792 return pci_register_driver(&cx23885_pci_driver);
1793}
1794
1795static void cx23885_fini(void)
1796{
1797 pci_unregister_driver(&cx23885_pci_driver);
1798}
1799
1800module_init(cx23885_init);
1801module_exit(cx23885_fini);
1802
1803/* ----------------------------------------------------------- */
1804/*
1805 * Local variables:
1806 * c-basic-offset: 8
1807 * End:
1808 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1809 */
Linux kernel - Deliverables
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