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V4L/DVB (11879): Adds support for Leadtek WinFast DTV-1800H
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
ST		 44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076
IL		 47#include "stv0900.h"
48#include "stv6110.h"
49#include "lnbh24.h"
96318d0c 50#include "cx24116.h"
5a23b076
IL		 51#include "cimax2.h"
52#include "netup-eeprom.h"
53#include "netup-init.h"
a5dbf457 54#include "lgdt3305.h"
d19770e5 55
4513fc69 56static unsigned int debug;
d19770e5 57
4513fc69
ST		 58#define dprintk(level, fmt, arg...)\
59 do { if (debug >= level)\
60 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
61 } while (0)
d19770e5
ST		 62
63/* ------------------------------------------------------------------ */
64
3ba71d21
MK		 65static unsigned int alt_tuner;
66module_param(alt_tuner, int, 0644);
67MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
68
78e92006
JG		 69DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
70
3ba71d21
MK		 71/* ------------------------------------------------------------------ */
72
d19770e5
ST		 73static int dvb_buf_setup(struct videobuf_queue *q,
74 unsigned int *count, unsigned int *size)
75{
76 struct cx23885_tsport *port = q->priv_data;
77
78 port->ts_packet_size = 188 * 4;
79 port->ts_packet_count = 32;
80
81 *size = port->ts_packet_size * port->ts_packet_count;
82 *count = 32;
83 return 0;
84}
85
44a6481d
MK		 86static int dvb_buf_prepare(struct videobuf_queue *q,
87 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 88{
89 struct cx23885_tsport *port = q->priv_data;
9c8ced51 90 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 91}
92
93static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
94{
95 struct cx23885_tsport *port = q->priv_data;
9c8ced51 96 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 97}
98
44a6481d
MK		 99static void dvb_buf_release(struct videobuf_queue *q,
100 struct videobuf_buffer *vb)
d19770e5 101{
9c8ced51 102 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 103}
104
105static struct videobuf_queue_ops dvb_qops = {
106 .buf_setup = dvb_buf_setup,
107 .buf_prepare = dvb_buf_prepare,
108 .buf_queue = dvb_buf_queue,
109 .buf_release = dvb_buf_release,
110};
111
86184e06 112static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 113 .demod_address = 0x32 >> 1,
114 .output_mode = S5H1409_SERIAL_OUTPUT,
115 .gpio = S5H1409_GPIO_ON,
2b03238a 116 .qam_if = 44000,
fc959bef 117 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 118 .status_mode = S5H1409_DEMODLOCKING,
119 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 120};
121
b3ea0166
ST		 122static struct tda10048_config hauppauge_hvr1200_config = {
123 .demod_address = 0x10 >> 1,
124 .output_mode = TDA10048_SERIAL_OUTPUT,
125 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 126 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 127 .dtv6_if_freq_khz = TDA10048_IF_3300,
128 .dtv7_if_freq_khz = TDA10048_IF_3800,
129 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 130 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 131};
132
6b926eca
MK		 133static struct tda10048_config hauppauge_hvr1210_config = {
134 .demod_address = 0x10 >> 1,
135 .output_mode = TDA10048_SERIAL_OUTPUT,
136 .fwbulkwritelen = TDA10048_BULKWRITE_200,
137 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 138 .dtv6_if_freq_khz = TDA10048_IF_3300,
139 .dtv7_if_freq_khz = TDA10048_IF_3500,
140 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 141 .clk_freq_khz = TDA10048_CLK_16000,
142};
143
3ba71d21
MK		 144static struct s5h1409_config hauppauge_ezqam_config = {
145 .demod_address = 0x32 >> 1,
146 .output_mode = S5H1409_SERIAL_OUTPUT,
147 .gpio = S5H1409_GPIO_OFF,
148 .qam_if = 4000,
149 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 150 .status_mode = S5H1409_DEMODLOCKING,
151 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 152};
153
fc959bef 154static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 155 .demod_address = 0x32 >> 1,
156 .output_mode = S5H1409_SERIAL_OUTPUT,
157 .gpio = S5H1409_GPIO_OFF,
2b03238a 158 .qam_if = 44000,
fe475163 159 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 160 .status_mode = S5H1409_DEMODLOCKING,
161 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 162};
163
07b4a835
MK		 164static struct s5h1409_config hauppauge_hvr1500_config = {
165 .demod_address = 0x32 >> 1,
166 .output_mode = S5H1409_SERIAL_OUTPUT,
167 .gpio = S5H1409_GPIO_OFF,
168 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 169 .status_mode = S5H1409_DEMODLOCKING,
170 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 171};
172
86184e06 173static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 174 0x61
175};
176
9bc37caa
MK		 177static struct lgdt330x_config fusionhdtv_5_express = {
178 .demod_address = 0x0e,
179 .demod_chip = LGDT3303,
180 .serial_mpeg = 0x40,
181};
182
d1987d55
ST		 183static struct s5h1409_config hauppauge_hvr1500q_config = {
184 .demod_address = 0x32 >> 1,
185 .output_mode = S5H1409_SERIAL_OUTPUT,
186 .gpio = S5H1409_GPIO_ON,
187 .qam_if = 44000,
188 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 189 .status_mode = S5H1409_DEMODLOCKING,
190 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 191};
192
335377b7
MK		 193static struct s5h1409_config dvico_s5h1409_config = {
194 .demod_address = 0x32 >> 1,
195 .output_mode = S5H1409_SERIAL_OUTPUT,
196 .gpio = S5H1409_GPIO_ON,
197 .qam_if = 44000,
198 .inversion = S5H1409_INVERSION_OFF,
199 .status_mode = S5H1409_DEMODLOCKING,
200 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
201};
202
52b50450
MK		 203static struct s5h1411_config dvico_s5h1411_config = {
204 .output_mode = S5H1411_SERIAL_OUTPUT,
205 .gpio = S5H1411_GPIO_ON,
206 .qam_if = S5H1411_IF_44000,
207 .vsb_if = S5H1411_IF_44000,
208 .inversion = S5H1411_INVERSION_OFF,
209 .status_mode = S5H1411_DEMODLOCKING,
210 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
211};
212
19bc5796
MK		 213static struct s5h1411_config hcw_s5h1411_config = {
214 .output_mode = S5H1411_SERIAL_OUTPUT,
215 .gpio = S5H1411_GPIO_OFF,
216 .vsb_if = S5H1411_IF_44000,
217 .qam_if = S5H1411_IF_4000,
218 .inversion = S5H1411_INVERSION_ON,
219 .status_mode = S5H1411_DEMODLOCKING,
220 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
221};
222
d1987d55 223static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 224 .i2c_address = 0x61,
225 .if_khz = 5380,
d1987d55
ST		 226};
227
335377b7
MK		 228static struct xc5000_config dvico_xc5000_tunerconfig = {
229 .i2c_address = 0x64,
230 .if_khz = 5380,
335377b7
MK		 231};
232
4041f1a5
MK		 233static struct tda829x_config tda829x_no_probe = {
234 .probe_tuner = TDA829X_DONT_PROBE,
235};
236
f21e0d7f 237static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 238 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
239 .if_lvl = 6, .rfagc_top = 0x37 },
240 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
241 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 242};
243
244static struct tda18271_config hauppauge_tda18271_config = {
245 .std_map = &hauppauge_tda18271_std_map,
246 .gate = TDA18271_GATE_ANALOG,
247};
248
b3ea0166
ST		 249static struct tda18271_config hauppauge_hvr1200_tuner_config = {
250 .gate = TDA18271_GATE_ANALOG,
251};
252
6b926eca
MK		 253static struct tda18271_config hauppauge_hvr1210_tuner_config = {
254 .gate = TDA18271_GATE_DIGITAL,
255};
256
247bc540 257static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 258 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
259 .if_lvl = 1, .rfagc_top = 0x58 },
260 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
261 .if_lvl = 1, .rfagc_top = 0x58 },
262};
263
247bc540
MK		 264static struct tda18271_config hauppauge_hvr127x_config = {
265 .std_map = &hauppauge_hvr127x_std_map,
a5dbf457
MK		 266};
267
247bc540 268static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 269 .i2c_addr = 0x0e,
270 .mpeg_mode = LGDT3305_MPEG_SERIAL,
271 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
272 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
273 .deny_i2c_rptr = 1,
274 .spectral_inversion = 1,
275 .qam_if_khz = 4000,
276 .vsb_if_khz = 3250,
277};
278
b1721d0d 279static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 280 BAND_VHF | BAND_UHF, /* band_caps */
281
282 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
283 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
284 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
285 * P_agc_nb_est=2, P_agc_write=0
286 */
287 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
288 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
289
290 712, /* inv_gain */
291 21, /* time_stabiliz */
292
293 0, /* alpha_level */
294 118, /* thlock */
295
296 0, /* wbd_inv */
297 2867, /* wbd_ref */
298 0, /* wbd_sel */
299 2, /* wbd_alpha */
300
301 0, /* agc1_max */
302 0, /* agc1_min */
303 39718, /* agc2_max */
304 9930, /* agc2_min */
305 0, /* agc1_pt1 */
306 0, /* agc1_pt2 */
307 0, /* agc1_pt3 */
308 0, /* agc1_slope1 */
309 0, /* agc1_slope2 */
310 0, /* agc2_pt1 */
311 128, /* agc2_pt2 */
312 29, /* agc2_slope1 */
313 29, /* agc2_slope2 */
314
315 17, /* alpha_mant */
316 27, /* alpha_exp */
317 23, /* beta_mant */
318 51, /* beta_exp */
319
320 1, /* perform_agc_softsplit */
321};
322
323/* PLL Configuration for COFDM BW_MHz = 8.000000
324 * With external clock = 30.000000 */
b1721d0d 325static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 326 60000, /* internal */
327 30000, /* sampling */
328 1, /* pll_cfg: prediv */
329 8, /* pll_cfg: ratio */
330 3, /* pll_cfg: range */
331 1, /* pll_cfg: reset */
332 0, /* pll_cfg: bypass */
333 0, /* misc: refdiv */
334 0, /* misc: bypclk_div */
335 1, /* misc: IO_CLK_en_core */
336 1, /* misc: ADClkSrc */
337 0, /* misc: modulo */
338 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
339 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
340 20452225, /* timf */
341 30000000 /* xtal_hz */
342};
343
344static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
345 .output_mpeg2_in_188_bytes = 1,
346 .hostbus_diversity = 1,
347 .tuner_is_baseband = 0,
348 .update_lna = NULL,
349
350 .agc_config_count = 1,
351 .agc = &xc3028_agc_config,
352 .bw = &xc3028_bw_config,
353
354 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
355 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
356 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
357
358 .pwm_freq_div = 0,
359 .agc_control = NULL,
360 .spur_protect = 0,
361
362 .output_mode = OUTMODE_MPEG2_SERIAL,
363};
364
aef2d186
ST		 365static struct zl10353_config dvico_fusionhdtv_xc3028 = {
366 .demod_address = 0x0f,
367 .if2 = 45600,
368 .no_tuner = 1,
d4dc673d 369 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 370};
371
5a23b076
IL		 372static struct stv0900_config netup_stv0900_config = {
373 .demod_address = 0x68,
374 .xtal = 27000000,
375 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
376 .diseqc_mode = 2,/* 2/3 PWM */
377 .path1_mode = 2,/*Serial continues clock */
378 .path2_mode = 2,/*Serial continues clock */
379 .tun1_maddress = 0,/* 0x60 */
380 .tun2_maddress = 3,/* 0x63 */
381 .tun1_adc = 1,/* 1 Vpp */
382 .tun2_adc = 1,/* 1 Vpp */
383};
384
385static struct stv6110_config netup_stv6110_tunerconfig_a = {
386 .i2c_address = 0x60,
387 .mclk = 27000000,
388 .iq_wiring = 0,
389};
390
391static struct stv6110_config netup_stv6110_tunerconfig_b = {
392 .i2c_address = 0x63,
393 .mclk = 27000000,
394 .iq_wiring = 1,
395};
396
96318d0c
IL		 397static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
398{
399 struct cx23885_tsport *port = fe->dvb->priv;
400 struct cx23885_dev *dev = port->dev;
401
402 if (voltage == SEC_VOLTAGE_18)
403 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
404 else if (voltage == SEC_VOLTAGE_13)
405 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
406 else
407 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
408 return 0;
409}
410
411static struct cx24116_config tbs_cx24116_config = {
412 .demod_address = 0x05,
413};
414
579943f5
IL		 415static struct cx24116_config tevii_cx24116_config = {
416 .demod_address = 0x55,
417};
418
c9b8b04b
IL		 419static struct cx24116_config dvbworld_cx24116_config = {
420 .demod_address = 0x05,
421};
422
d19770e5
ST		 423static int dvb_register(struct cx23885_tsport *port)
424{
425 struct cx23885_dev *dev = port->dev;
f139fa71 426 struct cx23885_i2c *i2c_bus = NULL;
363c35fc 427 struct videobuf_dvb_frontend *fe0;
5a23b076 428 int ret;
363c35fc 429
f972e0bd 430 /* Get the first frontend */
92abe9ee 431 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 432 if (!fe0)
433 return -EINVAL;
d19770e5
ST		 434
435 /* init struct videobuf_dvb */
363c35fc 436 fe0->dvb.name = dev->name;
d19770e5
ST		 437
438 /* init frontend */
439 switch (dev->board) {
a77743bc 440 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 441 i2c_bus = &dev->i2c_bus[0];
363c35fc 442 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 443 &hauppauge_generic_config,
f139fa71 444 &i2c_bus->i2c_adap);
363c35fc
ST		 445 if (fe0->dvb.frontend != NULL) {
446 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 447 &i2c_bus->i2c_adap,
86184e06 448 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 449 }
450 break;
a5dbf457 451 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 452 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 453 i2c_bus = &dev->i2c_bus[0];
454 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 455 &hauppauge_lgdt3305_config,
a5dbf457
MK		 456 &i2c_bus->i2c_adap);
457 if (fe0->dvb.frontend != NULL) {
458 dvb_attach(tda18271_attach, fe0->dvb.frontend,
459 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 460 &hauppauge_hvr127x_config);
a5dbf457
MK		 461 }
462 break;
19bc5796
MK		 463 case CX23885_BOARD_HAUPPAUGE_HVR1255:
464 i2c_bus = &dev->i2c_bus[0];
465 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
466 &hcw_s5h1411_config,
467 &i2c_bus->i2c_adap);
468 if (fe0->dvb.frontend != NULL) {
469 dvb_attach(tda18271_attach, fe0->dvb.frontend,
470 0x60, &dev->i2c_bus[1].i2c_adap,
471 &hauppauge_tda18271_config);
472 }
473 break;
3ba71d21
MK		 474 case CX23885_BOARD_HAUPPAUGE_HVR1800:
475 i2c_bus = &dev->i2c_bus[0];
92abe9ee 476 switch (alt_tuner) {
3ba71d21 477 case 1:
363c35fc 478 fe0->dvb.frontend =
3ba71d21
MK		 479 dvb_attach(s5h1409_attach,
480 &hauppauge_ezqam_config,
481 &i2c_bus->i2c_adap);
363c35fc
ST		 482 if (fe0->dvb.frontend != NULL) {
483 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 484 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 485 &tda829x_no_probe);
363c35fc 486 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 487 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 488 &hauppauge_tda18271_config);
3ba71d21
MK		 489 }
490 break;
491 case 0:
492 default:
363c35fc 493 fe0->dvb.frontend =
3ba71d21
MK		 494 dvb_attach(s5h1409_attach,
495 &hauppauge_generic_config,
496 &i2c_bus->i2c_adap);
363c35fc
ST		 497 if (fe0->dvb.frontend != NULL)
498 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 499 &i2c_bus->i2c_adap,
500 &hauppauge_generic_tunerconfig, 0);
501 break;
502 }
503 break;
fc959bef 504 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 505 i2c_bus = &dev->i2c_bus[0];
363c35fc 506 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 507 &hauppauge_hvr1800lp_config,
f139fa71 508 &i2c_bus->i2c_adap);
363c35fc
ST		 509 if (fe0->dvb.frontend != NULL) {
510 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 511 &i2c_bus->i2c_adap,
fc959bef
ST		 512 &hauppauge_generic_tunerconfig, 0);
513 }
514 break;
9bc37caa 515 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 516 i2c_bus = &dev->i2c_bus[0];
363c35fc 517 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 518 &fusionhdtv_5_express,
f139fa71 519 &i2c_bus->i2c_adap);
363c35fc
ST		 520 if (fe0->dvb.frontend != NULL) {
521 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 522 &i2c_bus->i2c_adap, 0x61,
523 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 524 }
525 break;
d1987d55
ST		 526 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
527 i2c_bus = &dev->i2c_bus[1];
363c35fc 528 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 529 &hauppauge_hvr1500q_config,
530 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 531 if (fe0->dvb.frontend != NULL)
532 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 533 &i2c_bus->i2c_adap,
534 &hauppauge_hvr1500q_tunerconfig);
d1987d55 535 break;
07b4a835
MK		 536 case CX23885_BOARD_HAUPPAUGE_HVR1500:
537 i2c_bus = &dev->i2c_bus[1];
363c35fc 538 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 539 &hauppauge_hvr1500_config,
540 &dev->i2c_bus[0].i2c_adap);
363c35fc 541 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 542 struct dvb_frontend *fe;
543 struct xc2028_config cfg = {
544 .i2c_adap = &i2c_bus->i2c_adap,
545 .i2c_addr = 0x61,
07b4a835
MK		 546 };
547 static struct xc2028_ctrl ctl = {
ef80bfeb 548 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 549 .max_len = 64,
52c3d29c 550 .demod = XC3028_FE_OREN538,
07b4a835
MK		 551 };
552
553 fe = dvb_attach(xc2028_attach,
363c35fc 554 fe0->dvb.frontend, &cfg);
07b4a835
MK		 555 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
556 fe->ops.tuner_ops.set_config(fe, &ctl);
557 }
558 break;
b3ea0166 559 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 560 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 561 i2c_bus = &dev->i2c_bus[0];
363c35fc 562 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 563 &hauppauge_hvr1200_config,
564 &i2c_bus->i2c_adap);
363c35fc
ST		 565 if (fe0->dvb.frontend != NULL) {
566 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 567 &dev->i2c_bus[1].i2c_adap, 0x42,
568 &tda829x_no_probe);
363c35fc 569 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 570 0x60, &dev->i2c_bus[1].i2c_adap,
571 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 572 }
573 break;
574 case CX23885_BOARD_HAUPPAUGE_HVR1210:
575 i2c_bus = &dev->i2c_bus[0];
576 fe0->dvb.frontend = dvb_attach(tda10048_attach,
577 &hauppauge_hvr1210_config,
578 &i2c_bus->i2c_adap);
579 if (fe0->dvb.frontend != NULL) {
580 dvb_attach(tda18271_attach, fe0->dvb.frontend,
581 0x60, &dev->i2c_bus[1].i2c_adap,
582 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 583 }
584 break;
66762373
ST		 585 case CX23885_BOARD_HAUPPAUGE_HVR1400:
586 i2c_bus = &dev->i2c_bus[0];
363c35fc 587 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 588 &i2c_bus->i2c_adap,
589 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 590 if (fe0->dvb.frontend != NULL) {
66762373
ST		 591 struct dvb_frontend *fe;
592 struct xc2028_config cfg = {
593 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
594 .i2c_addr = 0x64,
66762373
ST		 595 };
596 static struct xc2028_ctrl ctl = {
ef80bfeb 597 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST		 598 .max_len = 64,
599 .demod = 5000,
9c8ced51
ST		 600 /* This is true for all demods with
601 v36 firmware? */
0975fc68 602 .type = XC2028_D2633,
66762373
ST		 603 };
604
605 fe = dvb_attach(xc2028_attach,
363c35fc 606 fe0->dvb.frontend, &cfg);
66762373
ST		 607 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
608 fe->ops.tuner_ops.set_config(fe, &ctl);
609 }
610 break;
335377b7
MK		 611 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
612 i2c_bus = &dev->i2c_bus[port->nr - 1];
613
363c35fc 614 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 615 &dvico_s5h1409_config,
616 &i2c_bus->i2c_adap);
363c35fc
ST		 617 if (fe0->dvb.frontend == NULL)
618 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 619 &dvico_s5h1411_config,
620 &i2c_bus->i2c_adap);
363c35fc
ST		 621 if (fe0->dvb.frontend != NULL)
622 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 623 &i2c_bus->i2c_adap,
624 &dvico_xc5000_tunerconfig);
335377b7 625 break;
aef2d186
ST		 626 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
627 i2c_bus = &dev->i2c_bus[port->nr - 1];
628
363c35fc 629 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 630 &dvico_fusionhdtv_xc3028,
631 &i2c_bus->i2c_adap);
363c35fc 632 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 633 struct dvb_frontend *fe;
634 struct xc2028_config cfg = {
635 .i2c_adap = &i2c_bus->i2c_adap,
636 .i2c_addr = 0x61,
aef2d186
ST		 637 };
638 static struct xc2028_ctrl ctl = {
ef80bfeb 639 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 640 .max_len = 64,
641 .demod = XC3028_FE_ZARLINK456,
642 };
643
363c35fc 644 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 645 &cfg);
646 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
647 fe->ops.tuner_ops.set_config(fe, &ctl);
648 }
649 break;
650 }
4c56b04a 651 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 652 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
4c56b04a
ST		 653 i2c_bus = &dev->i2c_bus[0];
654
363c35fc 655 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 656 &dvico_fusionhdtv_xc3028,
657 &i2c_bus->i2c_adap);
363c35fc 658 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 659 struct dvb_frontend *fe;
660 struct xc2028_config cfg = {
661 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
662 .i2c_addr = 0x61,
4c56b04a
ST		 663 };
664 static struct xc2028_ctrl ctl = {
ef80bfeb 665 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 666 .max_len = 64,
667 .demod = XC3028_FE_ZARLINK456,
668 };
669
363c35fc 670 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 671 &cfg);
672 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
673 fe->ops.tuner_ops.set_config(fe, &ctl);
674 }
96318d0c
IL		 675 break;
676 case CX23885_BOARD_TBS_6920:
677 i2c_bus = &dev->i2c_bus[0];
678
679 fe0->dvb.frontend = dvb_attach(cx24116_attach,
680 &tbs_cx24116_config,
681 &i2c_bus->i2c_adap);
682 if (fe0->dvb.frontend != NULL)
683 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
684
579943f5
IL		 685 break;
686 case CX23885_BOARD_TEVII_S470:
687 i2c_bus = &dev->i2c_bus[1];
688
689 fe0->dvb.frontend = dvb_attach(cx24116_attach,
690 &tevii_cx24116_config,
691 &i2c_bus->i2c_adap);
692 if (fe0->dvb.frontend != NULL)
693 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
694
4c56b04a 695 break;
c9b8b04b
IL		 696 case CX23885_BOARD_DVBWORLD_2005:
697 i2c_bus = &dev->i2c_bus[1];
698
699 fe0->dvb.frontend = dvb_attach(cx24116_attach,
700 &dvbworld_cx24116_config,
701 &i2c_bus->i2c_adap);
702 break;
5a23b076
IL		 703 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
704 i2c_bus = &dev->i2c_bus[0];
705 switch (port->nr) {
706 /* port B */
707 case 1:
708 fe0->dvb.frontend = dvb_attach(stv0900_attach,
709 &netup_stv0900_config,
710 &i2c_bus->i2c_adap, 0);
711 if (fe0->dvb.frontend != NULL) {
712 if (dvb_attach(stv6110_attach,
713 fe0->dvb.frontend,
714 &netup_stv6110_tunerconfig_a,
715 &i2c_bus->i2c_adap)) {
716 if (!dvb_attach(lnbh24_attach,
717 fe0->dvb.frontend,
718 &i2c_bus->i2c_adap,
719 LNBH24_PCL, 0, 0x09))
720 printk(KERN_ERR
721 "No LNBH24 found!\n");
722
723 }
724 }
725 break;
726 /* port C */
727 case 2:
728 fe0->dvb.frontend = dvb_attach(stv0900_attach,
729 &netup_stv0900_config,
730 &i2c_bus->i2c_adap, 1);
731 if (fe0->dvb.frontend != NULL) {
732 if (dvb_attach(stv6110_attach,
733 fe0->dvb.frontend,
734 &netup_stv6110_tunerconfig_b,
735 &i2c_bus->i2c_adap)) {
736 if (!dvb_attach(lnbh24_attach,
737 fe0->dvb.frontend,
738 &i2c_bus->i2c_adap,
739 LNBH24_PCL, 0, 0x0a))
740 printk(KERN_ERR
741 "No LNBH24 found!\n");
742
743 }
744 }
745 break;
746 }
747 break;
d19770e5 748 default:
9c8ced51
ST		 749 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
750 " isn't supported yet\n",
d19770e5
ST		 751 dev->name);
752 break;
753 }
363c35fc 754 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST		 755 printk(KERN_ERR "%s: frontend initialization failed\n",
756 dev->name);
d19770e5
ST		 757 return -1;
758 }
d7cba043 759 /* define general-purpose callback pointer */
363c35fc 760 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST		 761
762 /* Put the analog decoder in standby to keep it quiet */
7c9fc9d5 763 call_all(dev, tuner, s_standby);
d19770e5 764
363c35fc
ST		 765 if (fe0->dvb.frontend->ops.analog_ops.standby)
766 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 767
d19770e5 768 /* register everything */
5a23b076 769 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
59b1842d 770 &dev->pci->dev, adapter_nr, 0);
363c35fc 771
5a23b076
IL		 772 /* init CI & MAC */
773 switch (dev->board) {
774 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
775 static struct netup_card_info cinfo;
776
777 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
778 memcpy(port->frontends.adapter.proposed_mac,
779 cinfo.port[port->nr - 1].mac, 6);
780 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
781 "%02X:%02X:%02X:%02X:%02X:%02X\n",
782 port->nr,
783 port->frontends.adapter.proposed_mac[0],
784 port->frontends.adapter.proposed_mac[1],
785 port->frontends.adapter.proposed_mac[2],
786 port->frontends.adapter.proposed_mac[3],
787 port->frontends.adapter.proposed_mac[4],
788 port->frontends.adapter.proposed_mac[5]);
789
790 netup_ci_init(port);
791 break;
792 }
793 }
794
795 return ret;
d19770e5
ST		 796}
797
798int cx23885_dvb_register(struct cx23885_tsport *port)
799{
363c35fc
ST		 800
801 struct videobuf_dvb_frontend *fe0;
d19770e5 802 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 803 int err, i;
804
805 /* Here we need to allocate the correct number of frontends,
806 * as reflected in the cards struct. The reality is that currrently
807 * no cx23885 boards support this - yet. But, if we don't modify this
808 * code then the second frontend would never be allocated (later)
809 * and fail with error before the attach in dvb_register().
810 * Without these changes we risk an OOPS later. The changes here
811 * are for safety, and should provide a good foundation for the
812 * future addition of any multi-frontend cx23885 based boards.
813 */
814 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
815 port->num_frontends);
d19770e5 816
eb0c58bb 817 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 818 if (videobuf_dvb_alloc_frontend(
9c8ced51 819 &port->frontends, i) == NULL) {
eb0c58bb
ST		 820 printk(KERN_ERR "%s() failed to alloc\n", __func__);
821 return -ENOMEM;
822 }
823
824 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
825 if (!fe0)
826 err = -EINVAL;
363c35fc 827
eb0c58bb 828 dprintk(1, "%s\n", __func__);
9c8ced51 829 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 830 dev->board,
831 dev->name,
832 dev->pci_bus,
833 dev->pci_slot);
d19770e5 834
eb0c58bb 835 err = -ENODEV;
d19770e5 836
eb0c58bb
ST		 837 /* dvb stuff */
838 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 839 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
840 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
841 &dev->pci->dev, &port->slock,
44a6481d
MK		 842 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
843 sizeof(struct cx23885_buffer), port);
eb0c58bb 844 }
d19770e5
ST		 845 err = dvb_register(port);
846 if (err != 0)
9c8ced51
ST		 847 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
848 __func__, err);
d19770e5 849
d19770e5
ST		 850 return err;
851}
852
853int cx23885_dvb_unregister(struct cx23885_tsport *port)
854{
363c35fc
ST		 855 struct videobuf_dvb_frontend *fe0;
856
eb0c58bb
ST		 857 /* FIXME: in an error condition where the we have
858 * an expected number of frontends (attach problem)
859 * then this might not clean up correctly, if 1
860 * is invalid.
861 * This comment only applies to future boards IF they
862 * implement MFE support.
863 */
92abe9ee 864 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 865 if (fe0->dvb.frontend)
363c35fc 866 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 867
afd96668
HV		 868 switch (port->dev->board) {
869 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
870 netup_ci_exit(port);
871 break;
872 }
5a23b076 873
d19770e5
ST		 874 return 0;
875}
44a6481d 876
Linux kernel - Deliverables
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