[media] cx231xx: dereferencing NULL after allocation failure
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST
1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST
31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
ST
46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
5a23b076
IL
51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
5a23b076 54#include "cimax2.h"
493b7127 55#include "lgs8gxx.h"
5a23b076
IL
56#include "netup-eeprom.h"
57#include "netup-init.h"
a5dbf457 58#include "lgdt3305.h"
ea5697fe 59#include "atbm8830.h"
09ea33e5
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60#include "ds3000.h"
61#include "cx23885-f300.h"
78db8547
IL
62#include "altera-ci.h"
63#include "stv0367.h"
722c90eb
SR
64#include "drxk.h"
65#include "mt2063.h"
d19770e5 66
4513fc69 67static unsigned int debug;
d19770e5 68
4513fc69
ST
69#define dprintk(level, fmt, arg...)\
70 do { if (debug >= level)\
71 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
72 } while (0)
d19770e5
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73
74/* ------------------------------------------------------------------ */
75
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MK
76static unsigned int alt_tuner;
77module_param(alt_tuner, int, 0644);
78MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
79
78e92006
JG
80DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
81
3ba71d21
MK
82/* ------------------------------------------------------------------ */
83
d19770e5
ST
84static int dvb_buf_setup(struct videobuf_queue *q,
85 unsigned int *count, unsigned int *size)
86{
87 struct cx23885_tsport *port = q->priv_data;
88
89 port->ts_packet_size = 188 * 4;
90 port->ts_packet_count = 32;
91
92 *size = port->ts_packet_size * port->ts_packet_count;
93 *count = 32;
94 return 0;
95}
96
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97static int dvb_buf_prepare(struct videobuf_queue *q,
98 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST
99{
100 struct cx23885_tsport *port = q->priv_data;
9c8ced51 101 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST
102}
103
104static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
105{
106 struct cx23885_tsport *port = q->priv_data;
9c8ced51 107 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
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108}
109
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110static void dvb_buf_release(struct videobuf_queue *q,
111 struct videobuf_buffer *vb)
d19770e5 112{
9c8ced51 113 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST
114}
115
a7d44baa
MCC
116static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
117
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IL
118static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
119{
120 struct videobuf_dvb_frontends *f;
121 struct videobuf_dvb_frontend *fe;
122
123 f = &port->frontends;
124
125 if (f->gate <= 1) /* undefined or fe0 */
126 fe = videobuf_dvb_get_frontend(f, 1);
127 else
128 fe = videobuf_dvb_get_frontend(f, f->gate);
129
130 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
131 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
a7d44baa
MCC
132
133 /*
134 * FIXME: Improve this path to avoid calling the
135 * cx23885_dvb_set_frontend() every time it passes here.
136 */
137 cx23885_dvb_set_frontend(fe->dvb.frontend);
78db8547
IL
138}
139
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ST
140static struct videobuf_queue_ops dvb_qops = {
141 .buf_setup = dvb_buf_setup,
142 .buf_prepare = dvb_buf_prepare,
143 .buf_queue = dvb_buf_queue,
144 .buf_release = dvb_buf_release,
145};
146
86184e06 147static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST
148 .demod_address = 0x32 >> 1,
149 .output_mode = S5H1409_SERIAL_OUTPUT,
150 .gpio = S5H1409_GPIO_ON,
2b03238a 151 .qam_if = 44000,
fc959bef 152 .inversion = S5H1409_INVERSION_OFF,
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ST
153 .status_mode = S5H1409_DEMODLOCKING,
154 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST
155};
156
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ST
157static struct tda10048_config hauppauge_hvr1200_config = {
158 .demod_address = 0x10 >> 1,
159 .output_mode = TDA10048_SERIAL_OUTPUT,
160 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 161 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST
162 .dtv6_if_freq_khz = TDA10048_IF_3300,
163 .dtv7_if_freq_khz = TDA10048_IF_3800,
164 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 165 .clk_freq_khz = TDA10048_CLK_16000,
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ST
166};
167
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168static struct tda10048_config hauppauge_hvr1210_config = {
169 .demod_address = 0x10 >> 1,
170 .output_mode = TDA10048_SERIAL_OUTPUT,
171 .fwbulkwritelen = TDA10048_BULKWRITE_200,
172 .inversion = TDA10048_INVERSION_ON,
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173 .dtv6_if_freq_khz = TDA10048_IF_3300,
174 .dtv7_if_freq_khz = TDA10048_IF_3500,
175 .dtv8_if_freq_khz = TDA10048_IF_4000,
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176 .clk_freq_khz = TDA10048_CLK_16000,
177};
178
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179static struct s5h1409_config hauppauge_ezqam_config = {
180 .demod_address = 0x32 >> 1,
181 .output_mode = S5H1409_SERIAL_OUTPUT,
182 .gpio = S5H1409_GPIO_OFF,
183 .qam_if = 4000,
184 .inversion = S5H1409_INVERSION_ON,
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185 .status_mode = S5H1409_DEMODLOCKING,
186 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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187};
188
fc959bef 189static struct s5h1409_config hauppauge_hvr1800lp_config = {
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190 .demod_address = 0x32 >> 1,
191 .output_mode = S5H1409_SERIAL_OUTPUT,
192 .gpio = S5H1409_GPIO_OFF,
2b03238a 193 .qam_if = 44000,
fe475163 194 .inversion = S5H1409_INVERSION_OFF,
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195 .status_mode = S5H1409_DEMODLOCKING,
196 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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197};
198
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199static struct s5h1409_config hauppauge_hvr1500_config = {
200 .demod_address = 0x32 >> 1,
201 .output_mode = S5H1409_SERIAL_OUTPUT,
202 .gpio = S5H1409_GPIO_OFF,
203 .inversion = S5H1409_INVERSION_OFF,
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ST
204 .status_mode = S5H1409_DEMODLOCKING,
205 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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206};
207
86184e06 208static struct mt2131_config hauppauge_generic_tunerconfig = {
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ST
209 0x61
210};
211
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MK
212static struct lgdt330x_config fusionhdtv_5_express = {
213 .demod_address = 0x0e,
214 .demod_chip = LGDT3303,
215 .serial_mpeg = 0x40,
216};
217
d1987d55
ST
218static struct s5h1409_config hauppauge_hvr1500q_config = {
219 .demod_address = 0x32 >> 1,
220 .output_mode = S5H1409_SERIAL_OUTPUT,
221 .gpio = S5H1409_GPIO_ON,
222 .qam_if = 44000,
223 .inversion = S5H1409_INVERSION_OFF,
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224 .status_mode = S5H1409_DEMODLOCKING,
225 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
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226};
227
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228static struct s5h1409_config dvico_s5h1409_config = {
229 .demod_address = 0x32 >> 1,
230 .output_mode = S5H1409_SERIAL_OUTPUT,
231 .gpio = S5H1409_GPIO_ON,
232 .qam_if = 44000,
233 .inversion = S5H1409_INVERSION_OFF,
234 .status_mode = S5H1409_DEMODLOCKING,
235 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
236};
237
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MK
238static struct s5h1411_config dvico_s5h1411_config = {
239 .output_mode = S5H1411_SERIAL_OUTPUT,
240 .gpio = S5H1411_GPIO_ON,
241 .qam_if = S5H1411_IF_44000,
242 .vsb_if = S5H1411_IF_44000,
243 .inversion = S5H1411_INVERSION_OFF,
244 .status_mode = S5H1411_DEMODLOCKING,
245 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
246};
247
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248static struct s5h1411_config hcw_s5h1411_config = {
249 .output_mode = S5H1411_SERIAL_OUTPUT,
250 .gpio = S5H1411_GPIO_OFF,
251 .vsb_if = S5H1411_IF_44000,
252 .qam_if = S5H1411_IF_4000,
253 .inversion = S5H1411_INVERSION_ON,
254 .status_mode = S5H1411_DEMODLOCKING,
255 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
256};
257
d1987d55 258static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST
259 .i2c_address = 0x61,
260 .if_khz = 5380,
d1987d55
ST
261};
262
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263static struct xc5000_config dvico_xc5000_tunerconfig = {
264 .i2c_address = 0x64,
265 .if_khz = 5380,
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266};
267
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268static struct tda829x_config tda829x_no_probe = {
269 .probe_tuner = TDA829X_DONT_PROBE,
270};
271
f21e0d7f 272static struct tda18271_std_map hauppauge_tda18271_std_map = {
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MK
273 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
274 .if_lvl = 6, .rfagc_top = 0x37 },
275 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
276 .if_lvl = 6, .rfagc_top = 0x37 },
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MK
277};
278
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279static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
280 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
281 .if_lvl = 1, .rfagc_top = 0x37, },
282 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
283 .if_lvl = 1, .rfagc_top = 0x37, },
284 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
285 .if_lvl = 1, .rfagc_top = 0x37, },
286};
287
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MK
288static struct tda18271_config hauppauge_tda18271_config = {
289 .std_map = &hauppauge_tda18271_std_map,
290 .gate = TDA18271_GATE_ANALOG,
04a68baa 291 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK
292};
293
b3ea0166 294static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 295 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 296 .gate = TDA18271_GATE_ANALOG,
04a68baa 297 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST
298};
299
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MK
300static struct tda18271_config hauppauge_hvr1210_tuner_config = {
301 .gate = TDA18271_GATE_DIGITAL,
04a68baa 302 .output_opt = TDA18271_OUTPUT_LT_OFF,
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MK
303};
304
247bc540 305static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
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306 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
307 .if_lvl = 1, .rfagc_top = 0x58 },
308 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
309 .if_lvl = 1, .rfagc_top = 0x58 },
310};
311
247bc540
MK
312static struct tda18271_config hauppauge_hvr127x_config = {
313 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 314 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK
315};
316
247bc540 317static struct lgdt3305_config hauppauge_lgdt3305_config = {
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MK
318 .i2c_addr = 0x0e,
319 .mpeg_mode = LGDT3305_MPEG_SERIAL,
320 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
321 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
322 .deny_i2c_rptr = 1,
323 .spectral_inversion = 1,
324 .qam_if_khz = 4000,
325 .vsb_if_khz = 3250,
326};
327
b1721d0d 328static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST
329 BAND_VHF | BAND_UHF, /* band_caps */
330
331 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
332 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
333 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
334 * P_agc_nb_est=2, P_agc_write=0
335 */
336 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
337 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
338
339 712, /* inv_gain */
340 21, /* time_stabiliz */
341
342 0, /* alpha_level */
343 118, /* thlock */
344
345 0, /* wbd_inv */
346 2867, /* wbd_ref */
347 0, /* wbd_sel */
348 2, /* wbd_alpha */
349
350 0, /* agc1_max */
351 0, /* agc1_min */
352 39718, /* agc2_max */
353 9930, /* agc2_min */
354 0, /* agc1_pt1 */
355 0, /* agc1_pt2 */
356 0, /* agc1_pt3 */
357 0, /* agc1_slope1 */
358 0, /* agc1_slope2 */
359 0, /* agc2_pt1 */
360 128, /* agc2_pt2 */
361 29, /* agc2_slope1 */
362 29, /* agc2_slope2 */
363
364 17, /* alpha_mant */
365 27, /* alpha_exp */
366 23, /* beta_mant */
367 51, /* beta_exp */
368
369 1, /* perform_agc_softsplit */
370};
371
372/* PLL Configuration for COFDM BW_MHz = 8.000000
373 * With external clock = 30.000000 */
b1721d0d 374static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST
375 60000, /* internal */
376 30000, /* sampling */
377 1, /* pll_cfg: prediv */
378 8, /* pll_cfg: ratio */
379 3, /* pll_cfg: range */
380 1, /* pll_cfg: reset */
381 0, /* pll_cfg: bypass */
382 0, /* misc: refdiv */
383 0, /* misc: bypclk_div */
384 1, /* misc: IO_CLK_en_core */
385 1, /* misc: ADClkSrc */
386 0, /* misc: modulo */
387 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
388 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
389 20452225, /* timf */
390 30000000 /* xtal_hz */
391};
392
393static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
394 .output_mpeg2_in_188_bytes = 1,
395 .hostbus_diversity = 1,
396 .tuner_is_baseband = 0,
397 .update_lna = NULL,
398
399 .agc_config_count = 1,
400 .agc = &xc3028_agc_config,
401 .bw = &xc3028_bw_config,
402
403 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
404 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
405 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
406
407 .pwm_freq_div = 0,
408 .agc_control = NULL,
409 .spur_protect = 0,
410
411 .output_mode = OUTMODE_MPEG2_SERIAL,
412};
413
aef2d186
ST
414static struct zl10353_config dvico_fusionhdtv_xc3028 = {
415 .demod_address = 0x0f,
416 .if2 = 45600,
417 .no_tuner = 1,
d4dc673d 418 .disable_i2c_gate_ctrl = 1,
aef2d186
ST
419};
420
f867c3f4
IL
421static struct stv0900_reg stv0900_ts_regs[] = {
422 { R0900_TSGENERAL, 0x00 },
423 { R0900_P1_TSSPEED, 0x40 },
424 { R0900_P2_TSSPEED, 0x40 },
425 { R0900_P1_TSCFGM, 0xc0 },
426 { R0900_P2_TSCFGM, 0xc0 },
427 { R0900_P1_TSCFGH, 0xe0 },
428 { R0900_P2_TSCFGH, 0xe0 },
429 { R0900_P1_TSCFGL, 0x20 },
430 { R0900_P2_TSCFGL, 0x20 },
431 { 0xffff, 0xff }, /* terminate */
432};
433
5a23b076
IL
434static struct stv0900_config netup_stv0900_config = {
435 .demod_address = 0x68,
29372a8d 436 .demod_mode = 1, /* dual */
644c7ef0 437 .xtal = 8000000,
5a23b076
IL
438 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
439 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 440 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL
441 .tun1_maddress = 0,/* 0x60 */
442 .tun2_maddress = 3,/* 0x63 */
443 .tun1_adc = 1,/* 1 Vpp */
444 .tun2_adc = 1,/* 1 Vpp */
445};
446
447static struct stv6110_config netup_stv6110_tunerconfig_a = {
448 .i2c_address = 0x60,
644c7ef0
AO
449 .mclk = 16000000,
450 .clk_div = 1,
873688cd 451 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL
452};
453
454static struct stv6110_config netup_stv6110_tunerconfig_b = {
455 .i2c_address = 0x63,
644c7ef0
AO
456 .mclk = 16000000,
457 .clk_div = 1,
873688cd 458 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL
459};
460
96318d0c 461static struct cx24116_config tbs_cx24116_config = {
09ea33e5 462 .demod_address = 0x55,
96318d0c
IL
463};
464
09ea33e5
IL
465static struct ds3000_config tevii_ds3000_config = {
466 .demod_address = 0x68,
579943f5
IL
467};
468
c9b8b04b
IL
469static struct cx24116_config dvbworld_cx24116_config = {
470 .demod_address = 0x05,
471};
472
493b7127
DW
473static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
474 .prod = LGS8GXX_PROD_LGS8GL5,
475 .demod_address = 0x19,
476 .serial_ts = 0,
477 .ts_clk_pol = 1,
478 .ts_clk_gated = 1,
479 .if_clk_freq = 30400, /* 30.4 MHz */
480 .if_freq = 5380, /* 5.38 MHz */
481 .if_neg_center = 1,
482 .ext_adc = 0,
483 .adc_signed = 0,
484 .if_neg_edge = 0,
485};
486
487static struct xc5000_config mygica_x8506_xc5000_config = {
488 .i2c_address = 0x61,
489 .if_khz = 5380,
490};
491
a7d44baa 492static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 493{
a7d44baa 494 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK
495 struct cx23885_tsport *port = fe->dvb->priv;
496 struct cx23885_dev *dev = port->dev;
497
498 switch (dev->board) {
499 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 500 switch (p->modulation) {
f35b9e80
MK
501 case VSB_8:
502 cx23885_gpio_clear(dev, GPIO_5);
503 break;
504 case QAM_64:
505 case QAM_256:
506 default:
507 cx23885_gpio_set(dev, GPIO_5);
508 break;
509 }
510 break;
6f0d8c02
DW
511 case CX23885_BOARD_MYGICA_X8506:
512 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
513 /* Select Digital TV */
514 cx23885_gpio_set(dev, GPIO_0);
515 break;
f35b9e80 516 }
5bdd3962 517 return 0;
f35b9e80
MK
518}
519
2365b2d3
DW
520static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
521 .prod = LGS8GXX_PROD_LGS8G75,
522 .demod_address = 0x19,
523 .serial_ts = 0,
524 .ts_clk_pol = 1,
525 .ts_clk_gated = 1,
526 .if_clk_freq = 30400, /* 30.4 MHz */
527 .if_freq = 6500, /* 6.50 MHz */
528 .if_neg_center = 1,
529 .ext_adc = 0,
530 .adc_signed = 1,
531 .adc_vpp = 2, /* 1.6 Vpp */
532 .if_neg_edge = 1,
533};
534
535static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
536 .i2c_address = 0x61,
537 .if_khz = 6500,
538};
539
ea5697fe
DW
540static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
541 .prod = ATBM8830_PROD_8830,
542 .demod_address = 0x44,
543 .serial_ts = 0,
544 .ts_sampling_edge = 1,
545 .ts_clk_gated = 0,
546 .osc_clk_freq = 30400, /* in kHz */
547 .if_freq = 0, /* zero IF */
548 .zif_swap_iq = 1,
c245c75c
DW
549 .agc_min = 0x2E,
550 .agc_max = 0xFF,
551 .agc_hold_loop = 0,
ea5697fe
DW
552};
553
554static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
555 .i2c_address = 0x60,
556 .osc_clk = 20
557};
558
559static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
560 .prod = ATBM8830_PROD_8830,
561 .demod_address = 0x44,
562 .serial_ts = 1,
563 .ts_sampling_edge = 1,
564 .ts_clk_gated = 0,
565 .osc_clk_freq = 30400, /* in kHz */
566 .if_freq = 0, /* zero IF */
567 .zif_swap_iq = 1,
c245c75c
DW
568 .agc_min = 0x2E,
569 .agc_max = 0xFF,
570 .agc_hold_loop = 0,
ea5697fe
DW
571};
572
573static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
574 .i2c_address = 0x60,
575 .osc_clk = 20
576};
78db8547
IL
577static struct stv0367_config netup_stv0367_config[] = {
578 {
579 .demod_address = 0x1c,
580 .xtal = 27000000,
581 .if_khz = 4500,
582 .if_iq_mode = 0,
583 .ts_mode = 1,
584 .clk_pol = 0,
585 }, {
586 .demod_address = 0x1d,
587 .xtal = 27000000,
588 .if_khz = 4500,
589 .if_iq_mode = 0,
590 .ts_mode = 1,
591 .clk_pol = 0,
592 },
593};
594
595static struct xc5000_config netup_xc5000_config[] = {
596 {
597 .i2c_address = 0x61,
598 .if_khz = 4500,
599 }, {
600 .i2c_address = 0x64,
601 .if_khz = 4500,
602 },
603};
604
722c90eb
SR
605static struct drxk_config terratec_drxk_config[] = {
606 {
607 .adr = 0x29,
608 .no_i2c_bridge = 1,
609 }, {
610 .adr = 0x2a,
611 .no_i2c_bridge = 1,
612 },
613};
614
615static struct mt2063_config terratec_mt2063_config[] = {
616 {
617 .tuner_address = 0x60,
618 }, {
619 .tuner_address = 0x67,
620 },
621};
622
78db8547
IL
623int netup_altera_fpga_rw(void *device, int flag, int data, int read)
624{
625 struct cx23885_dev *dev = (struct cx23885_dev *)device;
626 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 627 uint32_t mem = 0;
78db8547 628
d164460f 629 mem = cx_read(MC417_RWD);
78db8547
IL
630 if (read)
631 cx_set(MC417_OEN, ALT_DATA);
632 else {
633 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL
634 mem &= ~ALT_DATA;
635 mem |= (data & ALT_DATA);
78db8547
IL
636 }
637
638 if (flag)
d164460f 639 mem |= ALT_AD_RG;
78db8547 640 else
d164460f 641 mem &= ~ALT_AD_RG;
78db8547 642
d164460f 643 mem &= ~ALT_CS;
78db8547 644 if (read)
d164460f 645 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 646 else
d164460f
AO
647 mem = (mem & ~ALT_WR) | ALT_RD;
648
649 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL
650
651 for (;;) {
652 mem = cx_read(MC417_RWD);
653 if ((mem & ALT_RDY) == 0)
654 break;
655 if (time_after(jiffies, timeout))
656 break;
657 udelay(1);
658 }
659
660 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
661 if (read)
662 return mem & ALT_DATA;
663
664 return 0;
665};
ea5697fe 666
d19770e5
ST
667static int dvb_register(struct cx23885_tsport *port)
668{
669 struct cx23885_dev *dev = port->dev;
493b7127 670 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL
671 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
672 int mfe_shared = 0; /* bus not shared by default */
5a23b076 673 int ret;
363c35fc 674
f972e0bd 675 /* Get the first frontend */
92abe9ee 676 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST
677 if (!fe0)
678 return -EINVAL;
d19770e5
ST
679
680 /* init struct videobuf_dvb */
363c35fc 681 fe0->dvb.name = dev->name;
d19770e5 682
78db8547
IL
683 /* multi-frontend gate control is undefined or defaults to fe0 */
684 port->frontends.gate = 0;
685
686 /* Sets the gate control callback to be used by i2c command calls */
687 port->gate_ctrl = cx23885_dvb_gate_ctrl;
688
d19770e5
ST
689 /* init frontend */
690 switch (dev->board) {
a77743bc 691 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 692 i2c_bus = &dev->i2c_bus[0];
363c35fc 693 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 694 &hauppauge_generic_config,
f139fa71 695 &i2c_bus->i2c_adap);
363c35fc
ST
696 if (fe0->dvb.frontend != NULL) {
697 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 698 &i2c_bus->i2c_adap,
86184e06 699 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST
700 }
701 break;
a5dbf457 702 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 703 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK
704 i2c_bus = &dev->i2c_bus[0];
705 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 706 &hauppauge_lgdt3305_config,
a5dbf457
MK
707 &i2c_bus->i2c_adap);
708 if (fe0->dvb.frontend != NULL) {
709 dvb_attach(tda18271_attach, fe0->dvb.frontend,
710 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 711 &hauppauge_hvr127x_config);
a5dbf457
MK
712 }
713 break;
19bc5796
MK
714 case CX23885_BOARD_HAUPPAUGE_HVR1255:
715 i2c_bus = &dev->i2c_bus[0];
716 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
717 &hcw_s5h1411_config,
718 &i2c_bus->i2c_adap);
719 if (fe0->dvb.frontend != NULL) {
720 dvb_attach(tda18271_attach, fe0->dvb.frontend,
721 0x60, &dev->i2c_bus[1].i2c_adap,
722 &hauppauge_tda18271_config);
723 }
724 break;
3ba71d21
MK
725 case CX23885_BOARD_HAUPPAUGE_HVR1800:
726 i2c_bus = &dev->i2c_bus[0];
92abe9ee 727 switch (alt_tuner) {
3ba71d21 728 case 1:
363c35fc 729 fe0->dvb.frontend =
3ba71d21
MK
730 dvb_attach(s5h1409_attach,
731 &hauppauge_ezqam_config,
732 &i2c_bus->i2c_adap);
363c35fc
ST
733 if (fe0->dvb.frontend != NULL) {
734 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 735 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 736 &tda829x_no_probe);
363c35fc 737 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 738 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 739 &hauppauge_tda18271_config);
3ba71d21
MK
740 }
741 break;
742 case 0:
743 default:
363c35fc 744 fe0->dvb.frontend =
3ba71d21
MK
745 dvb_attach(s5h1409_attach,
746 &hauppauge_generic_config,
747 &i2c_bus->i2c_adap);
363c35fc
ST
748 if (fe0->dvb.frontend != NULL)
749 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK
750 &i2c_bus->i2c_adap,
751 &hauppauge_generic_tunerconfig, 0);
752 break;
753 }
754 break;
fc959bef 755 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 756 i2c_bus = &dev->i2c_bus[0];
363c35fc 757 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 758 &hauppauge_hvr1800lp_config,
f139fa71 759 &i2c_bus->i2c_adap);
363c35fc
ST
760 if (fe0->dvb.frontend != NULL) {
761 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 762 &i2c_bus->i2c_adap,
fc959bef
ST
763 &hauppauge_generic_tunerconfig, 0);
764 }
765 break;
9bc37caa 766 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 767 i2c_bus = &dev->i2c_bus[0];
363c35fc 768 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 769 &fusionhdtv_5_express,
f139fa71 770 &i2c_bus->i2c_adap);
363c35fc
ST
771 if (fe0->dvb.frontend != NULL) {
772 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK
773 &i2c_bus->i2c_adap, 0x61,
774 TUNER_LG_TDVS_H06XF);
9bc37caa
MK
775 }
776 break;
d1987d55
ST
777 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
778 i2c_bus = &dev->i2c_bus[1];
363c35fc 779 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST
780 &hauppauge_hvr1500q_config,
781 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST
782 if (fe0->dvb.frontend != NULL)
783 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
784 &i2c_bus->i2c_adap,
785 &hauppauge_hvr1500q_tunerconfig);
d1987d55 786 break;
07b4a835
MK
787 case CX23885_BOARD_HAUPPAUGE_HVR1500:
788 i2c_bus = &dev->i2c_bus[1];
363c35fc 789 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK
790 &hauppauge_hvr1500_config,
791 &dev->i2c_bus[0].i2c_adap);
363c35fc 792 if (fe0->dvb.frontend != NULL) {
07b4a835
MK
793 struct dvb_frontend *fe;
794 struct xc2028_config cfg = {
795 .i2c_adap = &i2c_bus->i2c_adap,
796 .i2c_addr = 0x61,
07b4a835
MK
797 };
798 static struct xc2028_ctrl ctl = {
ef80bfeb 799 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 800 .max_len = 64,
52c3d29c 801 .demod = XC3028_FE_OREN538,
07b4a835
MK
802 };
803
804 fe = dvb_attach(xc2028_attach,
363c35fc 805 fe0->dvb.frontend, &cfg);
07b4a835
MK
806 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
807 fe->ops.tuner_ops.set_config(fe, &ctl);
808 }
809 break;
b3ea0166 810 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 811 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 812 i2c_bus = &dev->i2c_bus[0];
363c35fc 813 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST
814 &hauppauge_hvr1200_config,
815 &i2c_bus->i2c_adap);
363c35fc
ST
816 if (fe0->dvb.frontend != NULL) {
817 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST
818 &dev->i2c_bus[1].i2c_adap, 0x42,
819 &tda829x_no_probe);
363c35fc 820 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST
821 0x60, &dev->i2c_bus[1].i2c_adap,
822 &hauppauge_hvr1200_tuner_config);
6b926eca
MK
823 }
824 break;
825 case CX23885_BOARD_HAUPPAUGE_HVR1210:
826 i2c_bus = &dev->i2c_bus[0];
827 fe0->dvb.frontend = dvb_attach(tda10048_attach,
828 &hauppauge_hvr1210_config,
829 &i2c_bus->i2c_adap);
830 if (fe0->dvb.frontend != NULL) {
831 dvb_attach(tda18271_attach, fe0->dvb.frontend,
832 0x60, &dev->i2c_bus[1].i2c_adap,
833 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST
834 }
835 break;
66762373
ST
836 case CX23885_BOARD_HAUPPAUGE_HVR1400:
837 i2c_bus = &dev->i2c_bus[0];
363c35fc 838 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST
839 &i2c_bus->i2c_adap,
840 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 841 if (fe0->dvb.frontend != NULL) {
66762373
ST
842 struct dvb_frontend *fe;
843 struct xc2028_config cfg = {
844 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
845 .i2c_addr = 0x64,
66762373
ST
846 };
847 static struct xc2028_ctrl ctl = {
ef80bfeb 848 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 849 .max_len = 64,
9bed77ee 850 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST
851 /* This is true for all demods with
852 v36 firmware? */
0975fc68 853 .type = XC2028_D2633,
66762373
ST
854 };
855
856 fe = dvb_attach(xc2028_attach,
363c35fc 857 fe0->dvb.frontend, &cfg);
66762373
ST
858 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
859 fe->ops.tuner_ops.set_config(fe, &ctl);
860 }
861 break;
335377b7
MK
862 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
863 i2c_bus = &dev->i2c_bus[port->nr - 1];
864
363c35fc 865 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK
866 &dvico_s5h1409_config,
867 &i2c_bus->i2c_adap);
363c35fc
ST
868 if (fe0->dvb.frontend == NULL)
869 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK
870 &dvico_s5h1411_config,
871 &i2c_bus->i2c_adap);
363c35fc
ST
872 if (fe0->dvb.frontend != NULL)
873 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
874 &i2c_bus->i2c_adap,
875 &dvico_xc5000_tunerconfig);
335377b7 876 break;
aef2d186
ST
877 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
878 i2c_bus = &dev->i2c_bus[port->nr - 1];
879
363c35fc 880 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST
881 &dvico_fusionhdtv_xc3028,
882 &i2c_bus->i2c_adap);
363c35fc 883 if (fe0->dvb.frontend != NULL) {
aef2d186
ST
884 struct dvb_frontend *fe;
885 struct xc2028_config cfg = {
886 .i2c_adap = &i2c_bus->i2c_adap,
887 .i2c_addr = 0x61,
aef2d186
ST
888 };
889 static struct xc2028_ctrl ctl = {
ef80bfeb 890 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST
891 .max_len = 64,
892 .demod = XC3028_FE_ZARLINK456,
893 };
894
363c35fc 895 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST
896 &cfg);
897 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
898 fe->ops.tuner_ops.set_config(fe, &ctl);
899 }
900 break;
901 }
4c56b04a 902 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 903 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 904 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST
905 i2c_bus = &dev->i2c_bus[0];
906
363c35fc 907 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST
908 &dvico_fusionhdtv_xc3028,
909 &i2c_bus->i2c_adap);
363c35fc 910 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST
911 struct dvb_frontend *fe;
912 struct xc2028_config cfg = {
913 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
914 .i2c_addr = 0x61,
4c56b04a
ST
915 };
916 static struct xc2028_ctrl ctl = {
ef80bfeb 917 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST
918 .max_len = 64,
919 .demod = XC3028_FE_ZARLINK456,
920 };
921
363c35fc 922 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST
923 &cfg);
924 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
925 fe->ops.tuner_ops.set_config(fe, &ctl);
926 }
96318d0c 927 break;
0cf8af57 928 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
929 i2c_bus = &dev->i2c_bus[0];
930
931 fe0->dvb.frontend = dvb_attach(zl10353_attach,
932 &dvico_fusionhdtv_xc3028,
933 &i2c_bus->i2c_adap);
934 if (fe0->dvb.frontend != NULL) {
935 struct dvb_frontend *fe;
936 struct xc4000_config cfg = {
937 .i2c_address = 0x61,
938 .default_pm = 0,
939 .dvb_amplitude = 134,
940 .set_smoothedcvbs = 1,
941 .if_khz = 4560
942 };
943
944 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
945 &dev->i2c_bus[1].i2c_adap, &cfg);
946 }
947 break;
96318d0c 948 case CX23885_BOARD_TBS_6920:
09ea33e5 949 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL
950
951 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL
952 &tbs_cx24116_config,
953 &i2c_bus->i2c_adap);
96318d0c 954 if (fe0->dvb.frontend != NULL)
09ea33e5 955 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 956
579943f5
IL
957 break;
958 case CX23885_BOARD_TEVII_S470:
959 i2c_bus = &dev->i2c_bus[1];
960
09ea33e5
IL
961 fe0->dvb.frontend = dvb_attach(ds3000_attach,
962 &tevii_ds3000_config,
963 &i2c_bus->i2c_adap);
579943f5 964 if (fe0->dvb.frontend != NULL)
09ea33e5 965 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
579943f5 966
4c56b04a 967 break;
c9b8b04b
IL
968 case CX23885_BOARD_DVBWORLD_2005:
969 i2c_bus = &dev->i2c_bus[1];
970
971 fe0->dvb.frontend = dvb_attach(cx24116_attach,
972 &dvbworld_cx24116_config,
973 &i2c_bus->i2c_adap);
974 break;
5a23b076
IL
975 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
976 i2c_bus = &dev->i2c_bus[0];
977 switch (port->nr) {
978 /* port B */
979 case 1:
980 fe0->dvb.frontend = dvb_attach(stv0900_attach,
981 &netup_stv0900_config,
982 &i2c_bus->i2c_adap, 0);
983 if (fe0->dvb.frontend != NULL) {
984 if (dvb_attach(stv6110_attach,
985 fe0->dvb.frontend,
986 &netup_stv6110_tunerconfig_a,
987 &i2c_bus->i2c_adap)) {
988 if (!dvb_attach(lnbh24_attach,
989 fe0->dvb.frontend,
990 &i2c_bus->i2c_adap,
9329fb5b
AO
991 LNBH24_PCL | LNBH24_TTX,
992 LNBH24_TEN, 0x09))
5a23b076
IL
993 printk(KERN_ERR
994 "No LNBH24 found!\n");
995
996 }
997 }
998 break;
999 /* port C */
1000 case 2:
1001 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1002 &netup_stv0900_config,
1003 &i2c_bus->i2c_adap, 1);
1004 if (fe0->dvb.frontend != NULL) {
1005 if (dvb_attach(stv6110_attach,
1006 fe0->dvb.frontend,
1007 &netup_stv6110_tunerconfig_b,
1008 &i2c_bus->i2c_adap)) {
1009 if (!dvb_attach(lnbh24_attach,
1010 fe0->dvb.frontend,
1011 &i2c_bus->i2c_adap,
9329fb5b
AO
1012 LNBH24_PCL | LNBH24_TTX,
1013 LNBH24_TEN, 0x0a))
5a23b076
IL
1014 printk(KERN_ERR
1015 "No LNBH24 found!\n");
1016
1017 }
1018 }
1019 break;
1020 }
1021 break;
493b7127
DW
1022 case CX23885_BOARD_MYGICA_X8506:
1023 i2c_bus = &dev->i2c_bus[0];
1024 i2c_bus2 = &dev->i2c_bus[1];
1025 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1026 &mygica_x8506_lgs8gl5_config,
1027 &i2c_bus->i2c_adap);
1028 if (fe0->dvb.frontend != NULL) {
1029 dvb_attach(xc5000_attach,
1030 fe0->dvb.frontend,
1031 &i2c_bus2->i2c_adap,
1032 &mygica_x8506_xc5000_config);
1033 }
1034 break;
2365b2d3
DW
1035 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1036 i2c_bus = &dev->i2c_bus[0];
1037 i2c_bus2 = &dev->i2c_bus[1];
1038 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1039 &magicpro_prohdtve2_lgs8g75_config,
1040 &i2c_bus->i2c_adap);
1041 if (fe0->dvb.frontend != NULL) {
1042 dvb_attach(xc5000_attach,
1043 fe0->dvb.frontend,
1044 &i2c_bus2->i2c_adap,
1045 &magicpro_prohdtve2_xc5000_config);
1046 }
1047 break;
13697380 1048 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST
1049 i2c_bus = &dev->i2c_bus[0];
1050 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1051 &hcw_s5h1411_config,
1052 &i2c_bus->i2c_adap);
1053 if (fe0->dvb.frontend != NULL)
1054 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1055 0x60, &dev->i2c_bus[0].i2c_adap,
1056 &hauppauge_tda18271_config);
1057
1058 tda18271_attach(&dev->ts1.analog_fe,
1059 0x60, &dev->i2c_bus[1].i2c_adap,
1060 &hauppauge_tda18271_config);
1061
1062 break;
aee0b24c 1063 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST
1064 i2c_bus = &dev->i2c_bus[0];
1065 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1066 &hcw_s5h1411_config,
1067 &i2c_bus->i2c_adap);
1068 if (fe0->dvb.frontend != NULL)
1069 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1070 0x60, &dev->i2c_bus[0].i2c_adap,
1071 &hauppauge_tda18271_config);
1072 break;
ea5697fe
DW
1073 case CX23885_BOARD_MYGICA_X8558PRO:
1074 switch (port->nr) {
1075 /* port B */
1076 case 1:
1077 i2c_bus = &dev->i2c_bus[0];
1078 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1079 &mygica_x8558pro_atbm8830_cfg1,
1080 &i2c_bus->i2c_adap);
1081 if (fe0->dvb.frontend != NULL) {
1082 dvb_attach(max2165_attach,
1083 fe0->dvb.frontend,
1084 &i2c_bus->i2c_adap,
1085 &mygic_x8558pro_max2165_cfg1);
1086 }
1087 break;
1088 /* port C */
1089 case 2:
1090 i2c_bus = &dev->i2c_bus[1];
1091 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1092 &mygica_x8558pro_atbm8830_cfg2,
1093 &i2c_bus->i2c_adap);
1094 if (fe0->dvb.frontend != NULL) {
1095 dvb_attach(max2165_attach,
1096 fe0->dvb.frontend,
1097 &i2c_bus->i2c_adap,
1098 &mygic_x8558pro_max2165_cfg2);
1099 }
1100 break;
1101 }
1102 break;
78db8547
IL
1103 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1104 i2c_bus = &dev->i2c_bus[0];
1105 mfe_shared = 1;/* MFE */
1106 port->frontends.gate = 0;/* not clear for me yet */
1107 /* ports B, C */
1108 /* MFE frontend 1 DVB-T */
1109 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1110 &netup_stv0367_config[port->nr - 1],
1111 &i2c_bus->i2c_adap);
4174ebf5 1112 if (fe0->dvb.frontend != NULL) {
78db8547
IL
1113 if (NULL == dvb_attach(xc5000_attach,
1114 fe0->dvb.frontend,
1115 &i2c_bus->i2c_adap,
1116 &netup_xc5000_config[port->nr - 1]))
1117 goto frontend_detach;
4174ebf5
AO
1118 /* load xc5000 firmware */
1119 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1120 }
78db8547
IL
1121 /* MFE frontend 2 */
1122 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1123 if (fe1 == NULL)
1124 goto frontend_detach;
1125 /* DVB-C init */
1126 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1127 &netup_stv0367_config[port->nr - 1],
1128 &i2c_bus->i2c_adap);
1129 if (fe1->dvb.frontend != NULL) {
1130 fe1->dvb.frontend->id = 1;
1131 if (NULL == dvb_attach(xc5000_attach,
1132 fe1->dvb.frontend,
1133 &i2c_bus->i2c_adap,
1134 &netup_xc5000_config[port->nr - 1]))
1135 goto frontend_detach;
1136 }
1137 break;
722c90eb
SR
1138 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1139 i2c_bus = &dev->i2c_bus[0];
1140 i2c_bus2 = &dev->i2c_bus[1];
1141
1142 switch (port->nr) {
1143 /* port b */
1144 case 1:
1145 fe0->dvb.frontend = dvb_attach(drxk_attach,
1146 &terratec_drxk_config[0],
1147 &i2c_bus->i2c_adap);
1148 if (fe0->dvb.frontend != NULL) {
1149 if (!dvb_attach(mt2063_attach,
1150 fe0->dvb.frontend,
1151 &terratec_mt2063_config[0],
1152 &i2c_bus2->i2c_adap))
1153 goto frontend_detach;
1154 }
1155 break;
1156 /* port c */
1157 case 2:
1158 fe0->dvb.frontend = dvb_attach(drxk_attach,
1159 &terratec_drxk_config[1],
1160 &i2c_bus->i2c_adap);
1161 if (fe0->dvb.frontend != NULL) {
1162 if (!dvb_attach(mt2063_attach,
1163 fe0->dvb.frontend,
1164 &terratec_mt2063_config[1],
1165 &i2c_bus2->i2c_adap))
1166 goto frontend_detach;
1167 }
1168 break;
1169 }
1170 break;
d19770e5 1171 default:
9c8ced51
ST
1172 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1173 " isn't supported yet\n",
d19770e5
ST
1174 dev->name);
1175 break;
1176 }
78db8547
IL
1177
1178 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1179 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL
1180 dev->name);
1181 goto frontend_detach;
d19770e5 1182 }
78db8547 1183
d7cba043 1184 /* define general-purpose callback pointer */
363c35fc 1185 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL
1186 if (fe1)
1187 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1188#if 0
1189 /* Ensure all frontends negotiate bus access */
1190 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1191 if (fe1)
1192 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1193#endif
d19770e5
ST
1194
1195 /* Put the analog decoder in standby to keep it quiet */
622b828a 1196 call_all(dev, core, s_power, 0);
d19770e5 1197
363c35fc
ST
1198 if (fe0->dvb.frontend->ops.analog_ops.standby)
1199 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1200
d19770e5 1201 /* register everything */
5a23b076 1202 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
78db8547 1203 &dev->pci->dev, adapter_nr, mfe_shared,
a7d44baa 1204 NULL);
bee30192 1205 if (ret)
78db8547 1206 goto frontend_detach;
363c35fc 1207
5a23b076
IL
1208 /* init CI & MAC */
1209 switch (dev->board) {
1210 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1211 static struct netup_card_info cinfo;
1212
1213 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1214 memcpy(port->frontends.adapter.proposed_mac,
1215 cinfo.port[port->nr - 1].mac, 6);
be395157 1216 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1217 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL
1218
1219 netup_ci_init(port);
1220 break;
1221 }
78db8547
IL
1222 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1223 struct altera_ci_config netup_ci_cfg = {
1224 .dev = dev,/* magic number to identify*/
1225 .adapter = &port->frontends.adapter,/* for CI */
1226 .demux = &fe0->dvb.demux,/* for hw pid filter */
1227 .fpga_rw = netup_altera_fpga_rw,
1228 };
1229
1230 altera_ci_init(&netup_ci_cfg, port->nr);
1231 break;
1232 }
16bfdaa4
PG
1233 case CX23885_BOARD_TEVII_S470: {
1234 u8 eeprom[256]; /* 24C02 i2c eeprom */
1235
1236 if (port->nr != 1)
1237 break;
1238
1239 /* Read entire EEPROM */
1240 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1241 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1242 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG
1243 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1244 break;
1245 }
5a23b076
IL
1246 }
1247
1248 return ret;
78db8547
IL
1249
1250frontend_detach:
1251 port->gate_ctrl = NULL;
1252 videobuf_dvb_dealloc_frontends(&port->frontends);
1253 return -EINVAL;
d19770e5
ST
1254}
1255
1256int cx23885_dvb_register(struct cx23885_tsport *port)
1257{
363c35fc
ST
1258
1259 struct videobuf_dvb_frontend *fe0;
d19770e5 1260 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST
1261 int err, i;
1262
1263 /* Here we need to allocate the correct number of frontends,
af901ca1 1264 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST
1265 * no cx23885 boards support this - yet. But, if we don't modify this
1266 * code then the second frontend would never be allocated (later)
1267 * and fail with error before the attach in dvb_register().
1268 * Without these changes we risk an OOPS later. The changes here
1269 * are for safety, and should provide a good foundation for the
1270 * future addition of any multi-frontend cx23885 based boards.
1271 */
1272 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1273 port->num_frontends);
d19770e5 1274
eb0c58bb 1275 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1276 if (videobuf_dvb_alloc_frontend(
9c8ced51 1277 &port->frontends, i) == NULL) {
eb0c58bb
ST
1278 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1279 return -ENOMEM;
1280 }
1281
1282 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1283 if (!fe0)
1284 err = -EINVAL;
363c35fc 1285
eb0c58bb 1286 dprintk(1, "%s\n", __func__);
9c8ced51 1287 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST
1288 dev->board,
1289 dev->name,
1290 dev->pci_bus,
1291 dev->pci_slot);
d19770e5 1292
eb0c58bb 1293 err = -ENODEV;
d19770e5 1294
eb0c58bb
ST
1295 /* dvb stuff */
1296 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST
1297 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1298 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1299 &dev->pci->dev, &port->slock,
44a6481d 1300 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1301 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1302 }
d19770e5
ST
1303 err = dvb_register(port);
1304 if (err != 0)
9c8ced51
ST
1305 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1306 __func__, err);
d19770e5 1307
d19770e5
ST
1308 return err;
1309}
1310
1311int cx23885_dvb_unregister(struct cx23885_tsport *port)
1312{
363c35fc
ST
1313 struct videobuf_dvb_frontend *fe0;
1314
eb0c58bb
ST
1315 /* FIXME: in an error condition where the we have
1316 * an expected number of frontends (attach problem)
1317 * then this might not clean up correctly, if 1
1318 * is invalid.
1319 * This comment only applies to future boards IF they
1320 * implement MFE support.
1321 */
92abe9ee 1322 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1323 if (fe0 && fe0->dvb.frontend)
363c35fc 1324 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1325
afd96668
HV
1326 switch (port->dev->board) {
1327 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1328 netup_ci_exit(port);
1329 break;
78db8547
IL
1330 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1331 altera_ci_release(port->dev, port->nr);
1332 break;
afd96668 1333 }
5a23b076 1334
78db8547
IL
1335 port->gate_ctrl = NULL;
1336
d19770e5
ST
1337 return 0;
1338}
44a6481d 1339
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