V4L/DVB (11662): v4l2-ioctl: Clear buffer type specific trailing fields/padding
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
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1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
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5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
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31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
ST
44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076
IL
47#include "stv0900.h"
48#include "stv6110.h"
49#include "lnbh24.h"
96318d0c 50#include "cx24116.h"
5a23b076
IL
51#include "cimax2.h"
52#include "netup-eeprom.h"
53#include "netup-init.h"
d19770e5 54
4513fc69 55static unsigned int debug;
d19770e5 56
4513fc69
ST
57#define dprintk(level, fmt, arg...)\
58 do { if (debug >= level)\
59 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
60 } while (0)
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61
62/* ------------------------------------------------------------------ */
63
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64static unsigned int alt_tuner;
65module_param(alt_tuner, int, 0644);
66MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
67
78e92006
JG
68DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
69
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70/* ------------------------------------------------------------------ */
71
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72static int dvb_buf_setup(struct videobuf_queue *q,
73 unsigned int *count, unsigned int *size)
74{
75 struct cx23885_tsport *port = q->priv_data;
76
77 port->ts_packet_size = 188 * 4;
78 port->ts_packet_count = 32;
79
80 *size = port->ts_packet_size * port->ts_packet_count;
81 *count = 32;
82 return 0;
83}
84
44a6481d
MK
85static int dvb_buf_prepare(struct videobuf_queue *q,
86 struct videobuf_buffer *vb, enum v4l2_field field)
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ST
87{
88 struct cx23885_tsport *port = q->priv_data;
9c8ced51 89 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST
90}
91
92static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
93{
94 struct cx23885_tsport *port = q->priv_data;
9c8ced51 95 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
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96}
97
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98static void dvb_buf_release(struct videobuf_queue *q,
99 struct videobuf_buffer *vb)
d19770e5 100{
9c8ced51 101 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
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102}
103
104static struct videobuf_queue_ops dvb_qops = {
105 .buf_setup = dvb_buf_setup,
106 .buf_prepare = dvb_buf_prepare,
107 .buf_queue = dvb_buf_queue,
108 .buf_release = dvb_buf_release,
109};
110
86184e06 111static struct s5h1409_config hauppauge_generic_config = {
fc959bef
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112 .demod_address = 0x32 >> 1,
113 .output_mode = S5H1409_SERIAL_OUTPUT,
114 .gpio = S5H1409_GPIO_ON,
2b03238a 115 .qam_if = 44000,
fc959bef 116 .inversion = S5H1409_INVERSION_OFF,
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117 .status_mode = S5H1409_DEMODLOCKING,
118 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
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119};
120
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121static struct tda10048_config hauppauge_hvr1200_config = {
122 .demod_address = 0x10 >> 1,
123 .output_mode = TDA10048_SERIAL_OUTPUT,
124 .fwbulkwritelen = TDA10048_BULKWRITE_200,
125 .inversion = TDA10048_INVERSION_ON
126};
127
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128static struct s5h1409_config hauppauge_ezqam_config = {
129 .demod_address = 0x32 >> 1,
130 .output_mode = S5H1409_SERIAL_OUTPUT,
131 .gpio = S5H1409_GPIO_OFF,
132 .qam_if = 4000,
133 .inversion = S5H1409_INVERSION_ON,
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134 .status_mode = S5H1409_DEMODLOCKING,
135 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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136};
137
fc959bef 138static struct s5h1409_config hauppauge_hvr1800lp_config = {
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139 .demod_address = 0x32 >> 1,
140 .output_mode = S5H1409_SERIAL_OUTPUT,
141 .gpio = S5H1409_GPIO_OFF,
2b03238a 142 .qam_if = 44000,
fe475163 143 .inversion = S5H1409_INVERSION_OFF,
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144 .status_mode = S5H1409_DEMODLOCKING,
145 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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146};
147
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148static struct s5h1409_config hauppauge_hvr1500_config = {
149 .demod_address = 0x32 >> 1,
150 .output_mode = S5H1409_SERIAL_OUTPUT,
151 .gpio = S5H1409_GPIO_OFF,
152 .inversion = S5H1409_INVERSION_OFF,
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153 .status_mode = S5H1409_DEMODLOCKING,
154 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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155};
156
86184e06 157static struct mt2131_config hauppauge_generic_tunerconfig = {
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ST
158 0x61
159};
160
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161static struct lgdt330x_config fusionhdtv_5_express = {
162 .demod_address = 0x0e,
163 .demod_chip = LGDT3303,
164 .serial_mpeg = 0x40,
165};
166
d1987d55
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167static struct s5h1409_config hauppauge_hvr1500q_config = {
168 .demod_address = 0x32 >> 1,
169 .output_mode = S5H1409_SERIAL_OUTPUT,
170 .gpio = S5H1409_GPIO_ON,
171 .qam_if = 44000,
172 .inversion = S5H1409_INVERSION_OFF,
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173 .status_mode = S5H1409_DEMODLOCKING,
174 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
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175};
176
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177static struct s5h1409_config dvico_s5h1409_config = {
178 .demod_address = 0x32 >> 1,
179 .output_mode = S5H1409_SERIAL_OUTPUT,
180 .gpio = S5H1409_GPIO_ON,
181 .qam_if = 44000,
182 .inversion = S5H1409_INVERSION_OFF,
183 .status_mode = S5H1409_DEMODLOCKING,
184 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
185};
186
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187static struct s5h1411_config dvico_s5h1411_config = {
188 .output_mode = S5H1411_SERIAL_OUTPUT,
189 .gpio = S5H1411_GPIO_ON,
190 .qam_if = S5H1411_IF_44000,
191 .vsb_if = S5H1411_IF_44000,
192 .inversion = S5H1411_INVERSION_OFF,
193 .status_mode = S5H1411_DEMODLOCKING,
194 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
195};
196
d1987d55 197static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
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198 .i2c_address = 0x61,
199 .if_khz = 5380,
d1987d55
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200};
201
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202static struct xc5000_config dvico_xc5000_tunerconfig = {
203 .i2c_address = 0x64,
204 .if_khz = 5380,
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205};
206
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207static struct tda829x_config tda829x_no_probe = {
208 .probe_tuner = TDA829X_DONT_PROBE,
209};
210
f21e0d7f 211static struct tda18271_std_map hauppauge_tda18271_std_map = {
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212 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
213 .if_lvl = 6, .rfagc_top = 0x37 },
214 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
215 .if_lvl = 6, .rfagc_top = 0x37 },
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MK
216};
217
218static struct tda18271_config hauppauge_tda18271_config = {
219 .std_map = &hauppauge_tda18271_std_map,
220 .gate = TDA18271_GATE_ANALOG,
221};
222
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ST
223static struct tda18271_config hauppauge_hvr1200_tuner_config = {
224 .gate = TDA18271_GATE_ANALOG,
225};
226
b1721d0d 227static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST
228 BAND_VHF | BAND_UHF, /* band_caps */
229
230 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
231 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
232 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
233 * P_agc_nb_est=2, P_agc_write=0
234 */
235 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
236 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
237
238 712, /* inv_gain */
239 21, /* time_stabiliz */
240
241 0, /* alpha_level */
242 118, /* thlock */
243
244 0, /* wbd_inv */
245 2867, /* wbd_ref */
246 0, /* wbd_sel */
247 2, /* wbd_alpha */
248
249 0, /* agc1_max */
250 0, /* agc1_min */
251 39718, /* agc2_max */
252 9930, /* agc2_min */
253 0, /* agc1_pt1 */
254 0, /* agc1_pt2 */
255 0, /* agc1_pt3 */
256 0, /* agc1_slope1 */
257 0, /* agc1_slope2 */
258 0, /* agc2_pt1 */
259 128, /* agc2_pt2 */
260 29, /* agc2_slope1 */
261 29, /* agc2_slope2 */
262
263 17, /* alpha_mant */
264 27, /* alpha_exp */
265 23, /* beta_mant */
266 51, /* beta_exp */
267
268 1, /* perform_agc_softsplit */
269};
270
271/* PLL Configuration for COFDM BW_MHz = 8.000000
272 * With external clock = 30.000000 */
b1721d0d 273static struct dibx000_bandwidth_config xc3028_bw_config = {
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ST
274 60000, /* internal */
275 30000, /* sampling */
276 1, /* pll_cfg: prediv */
277 8, /* pll_cfg: ratio */
278 3, /* pll_cfg: range */
279 1, /* pll_cfg: reset */
280 0, /* pll_cfg: bypass */
281 0, /* misc: refdiv */
282 0, /* misc: bypclk_div */
283 1, /* misc: IO_CLK_en_core */
284 1, /* misc: ADClkSrc */
285 0, /* misc: modulo */
286 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
287 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
288 20452225, /* timf */
289 30000000 /* xtal_hz */
290};
291
292static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
293 .output_mpeg2_in_188_bytes = 1,
294 .hostbus_diversity = 1,
295 .tuner_is_baseband = 0,
296 .update_lna = NULL,
297
298 .agc_config_count = 1,
299 .agc = &xc3028_agc_config,
300 .bw = &xc3028_bw_config,
301
302 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
303 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
304 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
305
306 .pwm_freq_div = 0,
307 .agc_control = NULL,
308 .spur_protect = 0,
309
310 .output_mode = OUTMODE_MPEG2_SERIAL,
311};
312
aef2d186
ST
313static struct zl10353_config dvico_fusionhdtv_xc3028 = {
314 .demod_address = 0x0f,
315 .if2 = 45600,
316 .no_tuner = 1,
d4dc673d 317 .disable_i2c_gate_ctrl = 1,
aef2d186
ST
318};
319
5a23b076
IL
320static struct stv0900_config netup_stv0900_config = {
321 .demod_address = 0x68,
322 .xtal = 27000000,
323 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
324 .diseqc_mode = 2,/* 2/3 PWM */
325 .path1_mode = 2,/*Serial continues clock */
326 .path2_mode = 2,/*Serial continues clock */
327 .tun1_maddress = 0,/* 0x60 */
328 .tun2_maddress = 3,/* 0x63 */
329 .tun1_adc = 1,/* 1 Vpp */
330 .tun2_adc = 1,/* 1 Vpp */
331};
332
333static struct stv6110_config netup_stv6110_tunerconfig_a = {
334 .i2c_address = 0x60,
335 .mclk = 27000000,
336 .iq_wiring = 0,
337};
338
339static struct stv6110_config netup_stv6110_tunerconfig_b = {
340 .i2c_address = 0x63,
341 .mclk = 27000000,
342 .iq_wiring = 1,
343};
344
96318d0c
IL
345static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
346{
347 struct cx23885_tsport *port = fe->dvb->priv;
348 struct cx23885_dev *dev = port->dev;
349
350 if (voltage == SEC_VOLTAGE_18)
351 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
352 else if (voltage == SEC_VOLTAGE_13)
353 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
354 else
355 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
356 return 0;
357}
358
359static struct cx24116_config tbs_cx24116_config = {
360 .demod_address = 0x05,
361};
362
579943f5
IL
363static struct cx24116_config tevii_cx24116_config = {
364 .demod_address = 0x55,
365};
366
c9b8b04b
IL
367static struct cx24116_config dvbworld_cx24116_config = {
368 .demod_address = 0x05,
369};
370
d19770e5
ST
371static int dvb_register(struct cx23885_tsport *port)
372{
373 struct cx23885_dev *dev = port->dev;
f139fa71 374 struct cx23885_i2c *i2c_bus = NULL;
363c35fc 375 struct videobuf_dvb_frontend *fe0;
5a23b076 376 int ret;
363c35fc 377
f972e0bd 378 /* Get the first frontend */
92abe9ee 379 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST
380 if (!fe0)
381 return -EINVAL;
d19770e5
ST
382
383 /* init struct videobuf_dvb */
363c35fc 384 fe0->dvb.name = dev->name;
d19770e5
ST
385
386 /* init frontend */
387 switch (dev->board) {
a77743bc 388 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 389 i2c_bus = &dev->i2c_bus[0];
363c35fc 390 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 391 &hauppauge_generic_config,
f139fa71 392 &i2c_bus->i2c_adap);
363c35fc
ST
393 if (fe0->dvb.frontend != NULL) {
394 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 395 &i2c_bus->i2c_adap,
86184e06 396 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST
397 }
398 break;
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MK
399 case CX23885_BOARD_HAUPPAUGE_HVR1800:
400 i2c_bus = &dev->i2c_bus[0];
92abe9ee 401 switch (alt_tuner) {
3ba71d21 402 case 1:
363c35fc 403 fe0->dvb.frontend =
3ba71d21
MK
404 dvb_attach(s5h1409_attach,
405 &hauppauge_ezqam_config,
406 &i2c_bus->i2c_adap);
363c35fc
ST
407 if (fe0->dvb.frontend != NULL) {
408 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 409 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 410 &tda829x_no_probe);
363c35fc 411 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 412 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 413 &hauppauge_tda18271_config);
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414 }
415 break;
416 case 0:
417 default:
363c35fc 418 fe0->dvb.frontend =
3ba71d21
MK
419 dvb_attach(s5h1409_attach,
420 &hauppauge_generic_config,
421 &i2c_bus->i2c_adap);
363c35fc
ST
422 if (fe0->dvb.frontend != NULL)
423 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK
424 &i2c_bus->i2c_adap,
425 &hauppauge_generic_tunerconfig, 0);
426 break;
427 }
428 break;
fc959bef 429 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 430 i2c_bus = &dev->i2c_bus[0];
363c35fc 431 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 432 &hauppauge_hvr1800lp_config,
f139fa71 433 &i2c_bus->i2c_adap);
363c35fc
ST
434 if (fe0->dvb.frontend != NULL) {
435 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 436 &i2c_bus->i2c_adap,
fc959bef
ST
437 &hauppauge_generic_tunerconfig, 0);
438 }
439 break;
9bc37caa 440 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 441 i2c_bus = &dev->i2c_bus[0];
363c35fc 442 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 443 &fusionhdtv_5_express,
f139fa71 444 &i2c_bus->i2c_adap);
363c35fc
ST
445 if (fe0->dvb.frontend != NULL) {
446 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK
447 &i2c_bus->i2c_adap, 0x61,
448 TUNER_LG_TDVS_H06XF);
9bc37caa
MK
449 }
450 break;
d1987d55
ST
451 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
452 i2c_bus = &dev->i2c_bus[1];
363c35fc 453 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST
454 &hauppauge_hvr1500q_config,
455 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST
456 if (fe0->dvb.frontend != NULL)
457 dvb_attach(xc5000_attach, fe0->dvb.frontend,
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MK
458 &i2c_bus->i2c_adap,
459 &hauppauge_hvr1500q_tunerconfig);
d1987d55 460 break;
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MK
461 case CX23885_BOARD_HAUPPAUGE_HVR1500:
462 i2c_bus = &dev->i2c_bus[1];
363c35fc 463 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK
464 &hauppauge_hvr1500_config,
465 &dev->i2c_bus[0].i2c_adap);
363c35fc 466 if (fe0->dvb.frontend != NULL) {
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MK
467 struct dvb_frontend *fe;
468 struct xc2028_config cfg = {
469 .i2c_adap = &i2c_bus->i2c_adap,
470 .i2c_addr = 0x61,
07b4a835
MK
471 };
472 static struct xc2028_ctrl ctl = {
ef80bfeb 473 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 474 .max_len = 64,
33e53161 475 .scode_table = XC3028_FE_OREN538,
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MK
476 };
477
478 fe = dvb_attach(xc2028_attach,
363c35fc 479 fe0->dvb.frontend, &cfg);
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MK
480 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
481 fe->ops.tuner_ops.set_config(fe, &ctl);
482 }
483 break;
b3ea0166 484 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 485 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 486 i2c_bus = &dev->i2c_bus[0];
363c35fc 487 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST
488 &hauppauge_hvr1200_config,
489 &i2c_bus->i2c_adap);
363c35fc
ST
490 if (fe0->dvb.frontend != NULL) {
491 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST
492 &dev->i2c_bus[1].i2c_adap, 0x42,
493 &tda829x_no_probe);
363c35fc 494 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST
495 0x60, &dev->i2c_bus[1].i2c_adap,
496 &hauppauge_hvr1200_tuner_config);
497 }
498 break;
66762373
ST
499 case CX23885_BOARD_HAUPPAUGE_HVR1400:
500 i2c_bus = &dev->i2c_bus[0];
363c35fc 501 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST
502 &i2c_bus->i2c_adap,
503 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 504 if (fe0->dvb.frontend != NULL) {
66762373
ST
505 struct dvb_frontend *fe;
506 struct xc2028_config cfg = {
507 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
508 .i2c_addr = 0x64,
66762373
ST
509 };
510 static struct xc2028_ctrl ctl = {
ef80bfeb 511 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST
512 .max_len = 64,
513 .demod = 5000,
9c8ced51
ST
514 /* This is true for all demods with
515 v36 firmware? */
0975fc68 516 .type = XC2028_D2633,
66762373
ST
517 };
518
519 fe = dvb_attach(xc2028_attach,
363c35fc 520 fe0->dvb.frontend, &cfg);
66762373
ST
521 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
522 fe->ops.tuner_ops.set_config(fe, &ctl);
523 }
524 break;
335377b7
MK
525 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
526 i2c_bus = &dev->i2c_bus[port->nr - 1];
527
363c35fc 528 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK
529 &dvico_s5h1409_config,
530 &i2c_bus->i2c_adap);
363c35fc
ST
531 if (fe0->dvb.frontend == NULL)
532 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK
533 &dvico_s5h1411_config,
534 &i2c_bus->i2c_adap);
363c35fc
ST
535 if (fe0->dvb.frontend != NULL)
536 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
537 &i2c_bus->i2c_adap,
538 &dvico_xc5000_tunerconfig);
335377b7 539 break;
aef2d186
ST
540 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
541 i2c_bus = &dev->i2c_bus[port->nr - 1];
542
363c35fc 543 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST
544 &dvico_fusionhdtv_xc3028,
545 &i2c_bus->i2c_adap);
363c35fc 546 if (fe0->dvb.frontend != NULL) {
aef2d186
ST
547 struct dvb_frontend *fe;
548 struct xc2028_config cfg = {
549 .i2c_adap = &i2c_bus->i2c_adap,
550 .i2c_addr = 0x61,
aef2d186
ST
551 };
552 static struct xc2028_ctrl ctl = {
ef80bfeb 553 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST
554 .max_len = 64,
555 .demod = XC3028_FE_ZARLINK456,
556 };
557
363c35fc 558 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST
559 &cfg);
560 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
561 fe->ops.tuner_ops.set_config(fe, &ctl);
562 }
563 break;
564 }
4c56b04a 565 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 566 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
4c56b04a
ST
567 i2c_bus = &dev->i2c_bus[0];
568
363c35fc 569 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST
570 &dvico_fusionhdtv_xc3028,
571 &i2c_bus->i2c_adap);
363c35fc 572 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST
573 struct dvb_frontend *fe;
574 struct xc2028_config cfg = {
575 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
576 .i2c_addr = 0x61,
4c56b04a
ST
577 };
578 static struct xc2028_ctrl ctl = {
ef80bfeb 579 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST
580 .max_len = 64,
581 .demod = XC3028_FE_ZARLINK456,
582 };
583
363c35fc 584 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST
585 &cfg);
586 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
587 fe->ops.tuner_ops.set_config(fe, &ctl);
588 }
96318d0c
IL
589 break;
590 case CX23885_BOARD_TBS_6920:
591 i2c_bus = &dev->i2c_bus[0];
592
593 fe0->dvb.frontend = dvb_attach(cx24116_attach,
594 &tbs_cx24116_config,
595 &i2c_bus->i2c_adap);
596 if (fe0->dvb.frontend != NULL)
597 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
598
579943f5
IL
599 break;
600 case CX23885_BOARD_TEVII_S470:
601 i2c_bus = &dev->i2c_bus[1];
602
603 fe0->dvb.frontend = dvb_attach(cx24116_attach,
604 &tevii_cx24116_config,
605 &i2c_bus->i2c_adap);
606 if (fe0->dvb.frontend != NULL)
607 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
608
4c56b04a 609 break;
c9b8b04b
IL
610 case CX23885_BOARD_DVBWORLD_2005:
611 i2c_bus = &dev->i2c_bus[1];
612
613 fe0->dvb.frontend = dvb_attach(cx24116_attach,
614 &dvbworld_cx24116_config,
615 &i2c_bus->i2c_adap);
616 break;
5a23b076
IL
617 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
618 i2c_bus = &dev->i2c_bus[0];
619 switch (port->nr) {
620 /* port B */
621 case 1:
622 fe0->dvb.frontend = dvb_attach(stv0900_attach,
623 &netup_stv0900_config,
624 &i2c_bus->i2c_adap, 0);
625 if (fe0->dvb.frontend != NULL) {
626 if (dvb_attach(stv6110_attach,
627 fe0->dvb.frontend,
628 &netup_stv6110_tunerconfig_a,
629 &i2c_bus->i2c_adap)) {
630 if (!dvb_attach(lnbh24_attach,
631 fe0->dvb.frontend,
632 &i2c_bus->i2c_adap,
633 LNBH24_PCL, 0, 0x09))
634 printk(KERN_ERR
635 "No LNBH24 found!\n");
636
637 }
638 }
639 break;
640 /* port C */
641 case 2:
642 fe0->dvb.frontend = dvb_attach(stv0900_attach,
643 &netup_stv0900_config,
644 &i2c_bus->i2c_adap, 1);
645 if (fe0->dvb.frontend != NULL) {
646 if (dvb_attach(stv6110_attach,
647 fe0->dvb.frontend,
648 &netup_stv6110_tunerconfig_b,
649 &i2c_bus->i2c_adap)) {
650 if (!dvb_attach(lnbh24_attach,
651 fe0->dvb.frontend,
652 &i2c_bus->i2c_adap,
653 LNBH24_PCL, 0, 0x0a))
654 printk(KERN_ERR
655 "No LNBH24 found!\n");
656
657 }
658 }
659 break;
660 }
661 break;
d19770e5 662 default:
9c8ced51
ST
663 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
664 " isn't supported yet\n",
d19770e5
ST
665 dev->name);
666 break;
667 }
363c35fc 668 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST
669 printk(KERN_ERR "%s: frontend initialization failed\n",
670 dev->name);
d19770e5
ST
671 return -1;
672 }
d7cba043 673 /* define general-purpose callback pointer */
363c35fc 674 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST
675
676 /* Put the analog decoder in standby to keep it quiet */
7c9fc9d5 677 call_all(dev, tuner, s_standby);
d19770e5 678
363c35fc
ST
679 if (fe0->dvb.frontend->ops.analog_ops.standby)
680 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 681
d19770e5 682 /* register everything */
5a23b076 683 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
59b1842d 684 &dev->pci->dev, adapter_nr, 0);
363c35fc 685
5a23b076
IL
686 /* init CI & MAC */
687 switch (dev->board) {
688 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
689 static struct netup_card_info cinfo;
690
691 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
692 memcpy(port->frontends.adapter.proposed_mac,
693 cinfo.port[port->nr - 1].mac, 6);
694 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
695 "%02X:%02X:%02X:%02X:%02X:%02X\n",
696 port->nr,
697 port->frontends.adapter.proposed_mac[0],
698 port->frontends.adapter.proposed_mac[1],
699 port->frontends.adapter.proposed_mac[2],
700 port->frontends.adapter.proposed_mac[3],
701 port->frontends.adapter.proposed_mac[4],
702 port->frontends.adapter.proposed_mac[5]);
703
704 netup_ci_init(port);
705 break;
706 }
707 }
708
709 return ret;
d19770e5
ST
710}
711
712int cx23885_dvb_register(struct cx23885_tsport *port)
713{
363c35fc
ST
714
715 struct videobuf_dvb_frontend *fe0;
d19770e5 716 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST
717 int err, i;
718
719 /* Here we need to allocate the correct number of frontends,
720 * as reflected in the cards struct. The reality is that currrently
721 * no cx23885 boards support this - yet. But, if we don't modify this
722 * code then the second frontend would never be allocated (later)
723 * and fail with error before the attach in dvb_register().
724 * Without these changes we risk an OOPS later. The changes here
725 * are for safety, and should provide a good foundation for the
726 * future addition of any multi-frontend cx23885 based boards.
727 */
728 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
729 port->num_frontends);
d19770e5 730
eb0c58bb 731 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 732 if (videobuf_dvb_alloc_frontend(
9c8ced51 733 &port->frontends, i) == NULL) {
eb0c58bb
ST
734 printk(KERN_ERR "%s() failed to alloc\n", __func__);
735 return -ENOMEM;
736 }
737
738 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
739 if (!fe0)
740 err = -EINVAL;
363c35fc 741
eb0c58bb 742 dprintk(1, "%s\n", __func__);
9c8ced51 743 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST
744 dev->board,
745 dev->name,
746 dev->pci_bus,
747 dev->pci_slot);
d19770e5 748
eb0c58bb 749 err = -ENODEV;
d19770e5 750
eb0c58bb
ST
751 /* dvb stuff */
752 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST
753 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
754 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
755 &dev->pci->dev, &port->slock,
44a6481d
MK
756 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
757 sizeof(struct cx23885_buffer), port);
eb0c58bb 758 }
d19770e5
ST
759 err = dvb_register(port);
760 if (err != 0)
9c8ced51
ST
761 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
762 __func__, err);
d19770e5 763
d19770e5
ST
764 return err;
765}
766
767int cx23885_dvb_unregister(struct cx23885_tsport *port)
768{
363c35fc
ST
769 struct videobuf_dvb_frontend *fe0;
770
eb0c58bb
ST
771 /* FIXME: in an error condition where the we have
772 * an expected number of frontends (attach problem)
773 * then this might not clean up correctly, if 1
774 * is invalid.
775 * This comment only applies to future boards IF they
776 * implement MFE support.
777 */
92abe9ee 778 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 779 if (fe0->dvb.frontend)
363c35fc 780 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 781
afd96668
HV
782 switch (port->dev->board) {
783 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
784 netup_ci_exit(port);
785 break;
786 }
5a23b076 787
d19770e5
ST
788 return 0;
789}
44a6481d 790
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