V4L/DVB (13833): ir-core: some functions can be static
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
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1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
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5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
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31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
ea5697fe 41#include "max2165.h"
b3ea0166 42#include "tda10048.h"
07b4a835 43#include "tuner-xc2028.h"
827855d3 44#include "tuner-simple.h"
66762373
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45#include "dib7000p.h"
46#include "dibx000_common.h"
aef2d186 47#include "zl10353.h"
5a23b076 48#include "stv0900.h"
f867c3f4 49#include "stv0900_reg.h"
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50#include "stv6110.h"
51#include "lnbh24.h"
96318d0c 52#include "cx24116.h"
5a23b076 53#include "cimax2.h"
493b7127 54#include "lgs8gxx.h"
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55#include "netup-eeprom.h"
56#include "netup-init.h"
a5dbf457 57#include "lgdt3305.h"
ea5697fe 58#include "atbm8830.h"
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59#include "ds3000.h"
60#include "cx23885-f300.h"
d19770e5 61
4513fc69 62static unsigned int debug;
d19770e5 63
4513fc69
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64#define dprintk(level, fmt, arg...)\
65 do { if (debug >= level)\
66 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
67 } while (0)
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68
69/* ------------------------------------------------------------------ */
70
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71static unsigned int alt_tuner;
72module_param(alt_tuner, int, 0644);
73MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
74
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JG
75DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
76
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77/* ------------------------------------------------------------------ */
78
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79static int dvb_buf_setup(struct videobuf_queue *q,
80 unsigned int *count, unsigned int *size)
81{
82 struct cx23885_tsport *port = q->priv_data;
83
84 port->ts_packet_size = 188 * 4;
85 port->ts_packet_count = 32;
86
87 *size = port->ts_packet_size * port->ts_packet_count;
88 *count = 32;
89 return 0;
90}
91
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92static int dvb_buf_prepare(struct videobuf_queue *q,
93 struct videobuf_buffer *vb, enum v4l2_field field)
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94{
95 struct cx23885_tsport *port = q->priv_data;
9c8ced51 96 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
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97}
98
99static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
100{
101 struct cx23885_tsport *port = q->priv_data;
9c8ced51 102 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
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103}
104
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105static void dvb_buf_release(struct videobuf_queue *q,
106 struct videobuf_buffer *vb)
d19770e5 107{
9c8ced51 108 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
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109}
110
111static struct videobuf_queue_ops dvb_qops = {
112 .buf_setup = dvb_buf_setup,
113 .buf_prepare = dvb_buf_prepare,
114 .buf_queue = dvb_buf_queue,
115 .buf_release = dvb_buf_release,
116};
117
86184e06 118static struct s5h1409_config hauppauge_generic_config = {
fc959bef
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119 .demod_address = 0x32 >> 1,
120 .output_mode = S5H1409_SERIAL_OUTPUT,
121 .gpio = S5H1409_GPIO_ON,
2b03238a 122 .qam_if = 44000,
fc959bef 123 .inversion = S5H1409_INVERSION_OFF,
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124 .status_mode = S5H1409_DEMODLOCKING,
125 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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126};
127
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128static struct tda10048_config hauppauge_hvr1200_config = {
129 .demod_address = 0x10 >> 1,
130 .output_mode = TDA10048_SERIAL_OUTPUT,
131 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 132 .inversion = TDA10048_INVERSION_ON,
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133 .dtv6_if_freq_khz = TDA10048_IF_3300,
134 .dtv7_if_freq_khz = TDA10048_IF_3800,
135 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 136 .clk_freq_khz = TDA10048_CLK_16000,
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137};
138
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139static struct tda10048_config hauppauge_hvr1210_config = {
140 .demod_address = 0x10 >> 1,
141 .output_mode = TDA10048_SERIAL_OUTPUT,
142 .fwbulkwritelen = TDA10048_BULKWRITE_200,
143 .inversion = TDA10048_INVERSION_ON,
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144 .dtv6_if_freq_khz = TDA10048_IF_3300,
145 .dtv7_if_freq_khz = TDA10048_IF_3500,
146 .dtv8_if_freq_khz = TDA10048_IF_4000,
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147 .clk_freq_khz = TDA10048_CLK_16000,
148};
149
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150static struct s5h1409_config hauppauge_ezqam_config = {
151 .demod_address = 0x32 >> 1,
152 .output_mode = S5H1409_SERIAL_OUTPUT,
153 .gpio = S5H1409_GPIO_OFF,
154 .qam_if = 4000,
155 .inversion = S5H1409_INVERSION_ON,
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156 .status_mode = S5H1409_DEMODLOCKING,
157 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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158};
159
fc959bef 160static struct s5h1409_config hauppauge_hvr1800lp_config = {
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161 .demod_address = 0x32 >> 1,
162 .output_mode = S5H1409_SERIAL_OUTPUT,
163 .gpio = S5H1409_GPIO_OFF,
2b03238a 164 .qam_if = 44000,
fe475163 165 .inversion = S5H1409_INVERSION_OFF,
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166 .status_mode = S5H1409_DEMODLOCKING,
167 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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168};
169
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170static struct s5h1409_config hauppauge_hvr1500_config = {
171 .demod_address = 0x32 >> 1,
172 .output_mode = S5H1409_SERIAL_OUTPUT,
173 .gpio = S5H1409_GPIO_OFF,
174 .inversion = S5H1409_INVERSION_OFF,
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175 .status_mode = S5H1409_DEMODLOCKING,
176 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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177};
178
86184e06 179static struct mt2131_config hauppauge_generic_tunerconfig = {
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180 0x61
181};
182
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183static struct lgdt330x_config fusionhdtv_5_express = {
184 .demod_address = 0x0e,
185 .demod_chip = LGDT3303,
186 .serial_mpeg = 0x40,
187};
188
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189static struct s5h1409_config hauppauge_hvr1500q_config = {
190 .demod_address = 0x32 >> 1,
191 .output_mode = S5H1409_SERIAL_OUTPUT,
192 .gpio = S5H1409_GPIO_ON,
193 .qam_if = 44000,
194 .inversion = S5H1409_INVERSION_OFF,
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195 .status_mode = S5H1409_DEMODLOCKING,
196 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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197};
198
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199static struct s5h1409_config dvico_s5h1409_config = {
200 .demod_address = 0x32 >> 1,
201 .output_mode = S5H1409_SERIAL_OUTPUT,
202 .gpio = S5H1409_GPIO_ON,
203 .qam_if = 44000,
204 .inversion = S5H1409_INVERSION_OFF,
205 .status_mode = S5H1409_DEMODLOCKING,
206 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
207};
208
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209static struct s5h1411_config dvico_s5h1411_config = {
210 .output_mode = S5H1411_SERIAL_OUTPUT,
211 .gpio = S5H1411_GPIO_ON,
212 .qam_if = S5H1411_IF_44000,
213 .vsb_if = S5H1411_IF_44000,
214 .inversion = S5H1411_INVERSION_OFF,
215 .status_mode = S5H1411_DEMODLOCKING,
216 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
217};
218
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219static struct s5h1411_config hcw_s5h1411_config = {
220 .output_mode = S5H1411_SERIAL_OUTPUT,
221 .gpio = S5H1411_GPIO_OFF,
222 .vsb_if = S5H1411_IF_44000,
223 .qam_if = S5H1411_IF_4000,
224 .inversion = S5H1411_INVERSION_ON,
225 .status_mode = S5H1411_DEMODLOCKING,
226 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
227};
228
d1987d55 229static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
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230 .i2c_address = 0x61,
231 .if_khz = 5380,
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232};
233
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234static struct xc5000_config dvico_xc5000_tunerconfig = {
235 .i2c_address = 0x64,
236 .if_khz = 5380,
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237};
238
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239static struct tda829x_config tda829x_no_probe = {
240 .probe_tuner = TDA829X_DONT_PROBE,
241};
242
f21e0d7f 243static struct tda18271_std_map hauppauge_tda18271_std_map = {
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244 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
245 .if_lvl = 6, .rfagc_top = 0x37 },
246 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
247 .if_lvl = 6, .rfagc_top = 0x37 },
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248};
249
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250static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
251 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
252 .if_lvl = 1, .rfagc_top = 0x37, },
253 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
254 .if_lvl = 1, .rfagc_top = 0x37, },
255 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
256 .if_lvl = 1, .rfagc_top = 0x37, },
257};
258
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259static struct tda18271_config hauppauge_tda18271_config = {
260 .std_map = &hauppauge_tda18271_std_map,
261 .gate = TDA18271_GATE_ANALOG,
04a68baa 262 .output_opt = TDA18271_OUTPUT_LT_OFF,
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263};
264
b3ea0166 265static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 266 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 267 .gate = TDA18271_GATE_ANALOG,
04a68baa 268 .output_opt = TDA18271_OUTPUT_LT_OFF,
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ST
269};
270
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271static struct tda18271_config hauppauge_hvr1210_tuner_config = {
272 .gate = TDA18271_GATE_DIGITAL,
04a68baa 273 .output_opt = TDA18271_OUTPUT_LT_OFF,
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274};
275
247bc540 276static struct tda18271_std_map hauppauge_hvr127x_std_map = {
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277 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
278 .if_lvl = 1, .rfagc_top = 0x58 },
279 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
280 .if_lvl = 1, .rfagc_top = 0x58 },
281};
282
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283static struct tda18271_config hauppauge_hvr127x_config = {
284 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 285 .output_opt = TDA18271_OUTPUT_LT_OFF,
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286};
287
247bc540 288static struct lgdt3305_config hauppauge_lgdt3305_config = {
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289 .i2c_addr = 0x0e,
290 .mpeg_mode = LGDT3305_MPEG_SERIAL,
291 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
292 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
293 .deny_i2c_rptr = 1,
294 .spectral_inversion = 1,
295 .qam_if_khz = 4000,
296 .vsb_if_khz = 3250,
297};
298
b1721d0d 299static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST
300 BAND_VHF | BAND_UHF, /* band_caps */
301
302 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
303 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
304 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
305 * P_agc_nb_est=2, P_agc_write=0
306 */
307 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
308 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
309
310 712, /* inv_gain */
311 21, /* time_stabiliz */
312
313 0, /* alpha_level */
314 118, /* thlock */
315
316 0, /* wbd_inv */
317 2867, /* wbd_ref */
318 0, /* wbd_sel */
319 2, /* wbd_alpha */
320
321 0, /* agc1_max */
322 0, /* agc1_min */
323 39718, /* agc2_max */
324 9930, /* agc2_min */
325 0, /* agc1_pt1 */
326 0, /* agc1_pt2 */
327 0, /* agc1_pt3 */
328 0, /* agc1_slope1 */
329 0, /* agc1_slope2 */
330 0, /* agc2_pt1 */
331 128, /* agc2_pt2 */
332 29, /* agc2_slope1 */
333 29, /* agc2_slope2 */
334
335 17, /* alpha_mant */
336 27, /* alpha_exp */
337 23, /* beta_mant */
338 51, /* beta_exp */
339
340 1, /* perform_agc_softsplit */
341};
342
343/* PLL Configuration for COFDM BW_MHz = 8.000000
344 * With external clock = 30.000000 */
b1721d0d 345static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST
346 60000, /* internal */
347 30000, /* sampling */
348 1, /* pll_cfg: prediv */
349 8, /* pll_cfg: ratio */
350 3, /* pll_cfg: range */
351 1, /* pll_cfg: reset */
352 0, /* pll_cfg: bypass */
353 0, /* misc: refdiv */
354 0, /* misc: bypclk_div */
355 1, /* misc: IO_CLK_en_core */
356 1, /* misc: ADClkSrc */
357 0, /* misc: modulo */
358 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
359 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
360 20452225, /* timf */
361 30000000 /* xtal_hz */
362};
363
364static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
365 .output_mpeg2_in_188_bytes = 1,
366 .hostbus_diversity = 1,
367 .tuner_is_baseband = 0,
368 .update_lna = NULL,
369
370 .agc_config_count = 1,
371 .agc = &xc3028_agc_config,
372 .bw = &xc3028_bw_config,
373
374 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
375 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
376 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
377
378 .pwm_freq_div = 0,
379 .agc_control = NULL,
380 .spur_protect = 0,
381
382 .output_mode = OUTMODE_MPEG2_SERIAL,
383};
384
aef2d186
ST
385static struct zl10353_config dvico_fusionhdtv_xc3028 = {
386 .demod_address = 0x0f,
387 .if2 = 45600,
388 .no_tuner = 1,
d4dc673d 389 .disable_i2c_gate_ctrl = 1,
aef2d186
ST
390};
391
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IL
392static struct stv0900_reg stv0900_ts_regs[] = {
393 { R0900_TSGENERAL, 0x00 },
394 { R0900_P1_TSSPEED, 0x40 },
395 { R0900_P2_TSSPEED, 0x40 },
396 { R0900_P1_TSCFGM, 0xc0 },
397 { R0900_P2_TSCFGM, 0xc0 },
398 { R0900_P1_TSCFGH, 0xe0 },
399 { R0900_P2_TSCFGH, 0xe0 },
400 { R0900_P1_TSCFGL, 0x20 },
401 { R0900_P2_TSCFGL, 0x20 },
402 { 0xffff, 0xff }, /* terminate */
403};
404
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IL
405static struct stv0900_config netup_stv0900_config = {
406 .demod_address = 0x68,
29372a8d 407 .demod_mode = 1, /* dual */
644c7ef0 408 .xtal = 8000000,
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IL
409 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
410 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 411 .ts_config_regs = stv0900_ts_regs,
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IL
412 .tun1_maddress = 0,/* 0x60 */
413 .tun2_maddress = 3,/* 0x63 */
414 .tun1_adc = 1,/* 1 Vpp */
415 .tun2_adc = 1,/* 1 Vpp */
416};
417
418static struct stv6110_config netup_stv6110_tunerconfig_a = {
419 .i2c_address = 0x60,
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AO
420 .mclk = 16000000,
421 .clk_div = 1,
873688cd 422 .gain = 8, /* +16 dB - maximum gain */
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IL
423};
424
425static struct stv6110_config netup_stv6110_tunerconfig_b = {
426 .i2c_address = 0x63,
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AO
427 .mclk = 16000000,
428 .clk_div = 1,
873688cd 429 .gain = 8, /* +16 dB - maximum gain */
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IL
430};
431
96318d0c 432static struct cx24116_config tbs_cx24116_config = {
09ea33e5 433 .demod_address = 0x55,
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434};
435
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IL
436static struct ds3000_config tevii_ds3000_config = {
437 .demod_address = 0x68,
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438};
439
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IL
440static struct cx24116_config dvbworld_cx24116_config = {
441 .demod_address = 0x05,
442};
443
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DW
444static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
445 .prod = LGS8GXX_PROD_LGS8GL5,
446 .demod_address = 0x19,
447 .serial_ts = 0,
448 .ts_clk_pol = 1,
449 .ts_clk_gated = 1,
450 .if_clk_freq = 30400, /* 30.4 MHz */
451 .if_freq = 5380, /* 5.38 MHz */
452 .if_neg_center = 1,
453 .ext_adc = 0,
454 .adc_signed = 0,
455 .if_neg_edge = 0,
456};
457
458static struct xc5000_config mygica_x8506_xc5000_config = {
459 .i2c_address = 0x61,
460 .if_khz = 5380,
461};
462
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463static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
464 struct dvb_frontend_parameters *param)
465{
466 struct cx23885_tsport *port = fe->dvb->priv;
467 struct cx23885_dev *dev = port->dev;
468
469 switch (dev->board) {
470 case CX23885_BOARD_HAUPPAUGE_HVR1275:
471 switch (param->u.vsb.modulation) {
472 case VSB_8:
473 cx23885_gpio_clear(dev, GPIO_5);
474 break;
475 case QAM_64:
476 case QAM_256:
477 default:
478 cx23885_gpio_set(dev, GPIO_5);
479 break;
480 }
481 break;
6f0d8c02
DW
482 case CX23885_BOARD_MYGICA_X8506:
483 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
484 /* Select Digital TV */
485 cx23885_gpio_set(dev, GPIO_0);
486 break;
f35b9e80 487 }
5bdd3962 488 return 0;
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MK
489}
490
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MK
491static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
492 unsigned int cmd, void *parg,
493 unsigned int stage)
494{
495 int err = 0;
496
497 switch (stage) {
498 case DVB_FE_IOCTL_PRE:
499
500 switch (cmd) {
501 case FE_SET_FRONTEND:
502 err = cx23885_dvb_set_frontend(fe,
503 (struct dvb_frontend_parameters *) parg);
504 break;
505 }
506 break;
507
508 case DVB_FE_IOCTL_POST:
509 /* no post-ioctl handling required */
510 break;
511 }
512 return err;
513};
514
515
2365b2d3
DW
516static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
517 .prod = LGS8GXX_PROD_LGS8G75,
518 .demod_address = 0x19,
519 .serial_ts = 0,
520 .ts_clk_pol = 1,
521 .ts_clk_gated = 1,
522 .if_clk_freq = 30400, /* 30.4 MHz */
523 .if_freq = 6500, /* 6.50 MHz */
524 .if_neg_center = 1,
525 .ext_adc = 0,
526 .adc_signed = 1,
527 .adc_vpp = 2, /* 1.6 Vpp */
528 .if_neg_edge = 1,
529};
530
531static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
532 .i2c_address = 0x61,
533 .if_khz = 6500,
534};
535
ea5697fe
DW
536static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
537 .prod = ATBM8830_PROD_8830,
538 .demod_address = 0x44,
539 .serial_ts = 0,
540 .ts_sampling_edge = 1,
541 .ts_clk_gated = 0,
542 .osc_clk_freq = 30400, /* in kHz */
543 .if_freq = 0, /* zero IF */
544 .zif_swap_iq = 1,
545};
546
547static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
548 .i2c_address = 0x60,
549 .osc_clk = 20
550};
551
552static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
553 .prod = ATBM8830_PROD_8830,
554 .demod_address = 0x44,
555 .serial_ts = 1,
556 .ts_sampling_edge = 1,
557 .ts_clk_gated = 0,
558 .osc_clk_freq = 30400, /* in kHz */
559 .if_freq = 0, /* zero IF */
560 .zif_swap_iq = 1,
561};
562
563static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
564 .i2c_address = 0x60,
565 .osc_clk = 20
566};
567
d19770e5
ST
568static int dvb_register(struct cx23885_tsport *port)
569{
570 struct cx23885_dev *dev = port->dev;
493b7127 571 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
363c35fc 572 struct videobuf_dvb_frontend *fe0;
5a23b076 573 int ret;
363c35fc 574
f972e0bd 575 /* Get the first frontend */
92abe9ee 576 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST
577 if (!fe0)
578 return -EINVAL;
d19770e5
ST
579
580 /* init struct videobuf_dvb */
363c35fc 581 fe0->dvb.name = dev->name;
d19770e5
ST
582
583 /* init frontend */
584 switch (dev->board) {
a77743bc 585 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 586 i2c_bus = &dev->i2c_bus[0];
363c35fc 587 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 588 &hauppauge_generic_config,
f139fa71 589 &i2c_bus->i2c_adap);
363c35fc
ST
590 if (fe0->dvb.frontend != NULL) {
591 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 592 &i2c_bus->i2c_adap,
86184e06 593 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST
594 }
595 break;
a5dbf457 596 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 597 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK
598 i2c_bus = &dev->i2c_bus[0];
599 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 600 &hauppauge_lgdt3305_config,
a5dbf457
MK
601 &i2c_bus->i2c_adap);
602 if (fe0->dvb.frontend != NULL) {
603 dvb_attach(tda18271_attach, fe0->dvb.frontend,
604 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 605 &hauppauge_hvr127x_config);
a5dbf457
MK
606 }
607 break;
19bc5796
MK
608 case CX23885_BOARD_HAUPPAUGE_HVR1255:
609 i2c_bus = &dev->i2c_bus[0];
610 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
611 &hcw_s5h1411_config,
612 &i2c_bus->i2c_adap);
613 if (fe0->dvb.frontend != NULL) {
614 dvb_attach(tda18271_attach, fe0->dvb.frontend,
615 0x60, &dev->i2c_bus[1].i2c_adap,
616 &hauppauge_tda18271_config);
617 }
618 break;
3ba71d21
MK
619 case CX23885_BOARD_HAUPPAUGE_HVR1800:
620 i2c_bus = &dev->i2c_bus[0];
92abe9ee 621 switch (alt_tuner) {
3ba71d21 622 case 1:
363c35fc 623 fe0->dvb.frontend =
3ba71d21
MK
624 dvb_attach(s5h1409_attach,
625 &hauppauge_ezqam_config,
626 &i2c_bus->i2c_adap);
363c35fc
ST
627 if (fe0->dvb.frontend != NULL) {
628 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 629 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 630 &tda829x_no_probe);
363c35fc 631 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 632 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 633 &hauppauge_tda18271_config);
3ba71d21
MK
634 }
635 break;
636 case 0:
637 default:
363c35fc 638 fe0->dvb.frontend =
3ba71d21
MK
639 dvb_attach(s5h1409_attach,
640 &hauppauge_generic_config,
641 &i2c_bus->i2c_adap);
363c35fc
ST
642 if (fe0->dvb.frontend != NULL)
643 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK
644 &i2c_bus->i2c_adap,
645 &hauppauge_generic_tunerconfig, 0);
646 break;
647 }
648 break;
fc959bef 649 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 650 i2c_bus = &dev->i2c_bus[0];
363c35fc 651 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 652 &hauppauge_hvr1800lp_config,
f139fa71 653 &i2c_bus->i2c_adap);
363c35fc
ST
654 if (fe0->dvb.frontend != NULL) {
655 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 656 &i2c_bus->i2c_adap,
fc959bef
ST
657 &hauppauge_generic_tunerconfig, 0);
658 }
659 break;
9bc37caa 660 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 661 i2c_bus = &dev->i2c_bus[0];
363c35fc 662 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 663 &fusionhdtv_5_express,
f139fa71 664 &i2c_bus->i2c_adap);
363c35fc
ST
665 if (fe0->dvb.frontend != NULL) {
666 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK
667 &i2c_bus->i2c_adap, 0x61,
668 TUNER_LG_TDVS_H06XF);
9bc37caa
MK
669 }
670 break;
d1987d55
ST
671 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
672 i2c_bus = &dev->i2c_bus[1];
363c35fc 673 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST
674 &hauppauge_hvr1500q_config,
675 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST
676 if (fe0->dvb.frontend != NULL)
677 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
678 &i2c_bus->i2c_adap,
679 &hauppauge_hvr1500q_tunerconfig);
d1987d55 680 break;
07b4a835
MK
681 case CX23885_BOARD_HAUPPAUGE_HVR1500:
682 i2c_bus = &dev->i2c_bus[1];
363c35fc 683 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK
684 &hauppauge_hvr1500_config,
685 &dev->i2c_bus[0].i2c_adap);
363c35fc 686 if (fe0->dvb.frontend != NULL) {
07b4a835
MK
687 struct dvb_frontend *fe;
688 struct xc2028_config cfg = {
689 .i2c_adap = &i2c_bus->i2c_adap,
690 .i2c_addr = 0x61,
07b4a835
MK
691 };
692 static struct xc2028_ctrl ctl = {
ef80bfeb 693 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 694 .max_len = 64,
52c3d29c 695 .demod = XC3028_FE_OREN538,
07b4a835
MK
696 };
697
698 fe = dvb_attach(xc2028_attach,
363c35fc 699 fe0->dvb.frontend, &cfg);
07b4a835
MK
700 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
701 fe->ops.tuner_ops.set_config(fe, &ctl);
702 }
703 break;
b3ea0166 704 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 705 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 706 i2c_bus = &dev->i2c_bus[0];
363c35fc 707 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST
708 &hauppauge_hvr1200_config,
709 &i2c_bus->i2c_adap);
363c35fc
ST
710 if (fe0->dvb.frontend != NULL) {
711 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST
712 &dev->i2c_bus[1].i2c_adap, 0x42,
713 &tda829x_no_probe);
363c35fc 714 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST
715 0x60, &dev->i2c_bus[1].i2c_adap,
716 &hauppauge_hvr1200_tuner_config);
6b926eca
MK
717 }
718 break;
719 case CX23885_BOARD_HAUPPAUGE_HVR1210:
720 i2c_bus = &dev->i2c_bus[0];
721 fe0->dvb.frontend = dvb_attach(tda10048_attach,
722 &hauppauge_hvr1210_config,
723 &i2c_bus->i2c_adap);
724 if (fe0->dvb.frontend != NULL) {
725 dvb_attach(tda18271_attach, fe0->dvb.frontend,
726 0x60, &dev->i2c_bus[1].i2c_adap,
727 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST
728 }
729 break;
66762373
ST
730 case CX23885_BOARD_HAUPPAUGE_HVR1400:
731 i2c_bus = &dev->i2c_bus[0];
363c35fc 732 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST
733 &i2c_bus->i2c_adap,
734 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 735 if (fe0->dvb.frontend != NULL) {
66762373
ST
736 struct dvb_frontend *fe;
737 struct xc2028_config cfg = {
738 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
739 .i2c_addr = 0x64,
66762373
ST
740 };
741 static struct xc2028_ctrl ctl = {
ef80bfeb 742 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST
743 .max_len = 64,
744 .demod = 5000,
9c8ced51
ST
745 /* This is true for all demods with
746 v36 firmware? */
0975fc68 747 .type = XC2028_D2633,
66762373
ST
748 };
749
750 fe = dvb_attach(xc2028_attach,
363c35fc 751 fe0->dvb.frontend, &cfg);
66762373
ST
752 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
753 fe->ops.tuner_ops.set_config(fe, &ctl);
754 }
755 break;
335377b7
MK
756 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
757 i2c_bus = &dev->i2c_bus[port->nr - 1];
758
363c35fc 759 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK
760 &dvico_s5h1409_config,
761 &i2c_bus->i2c_adap);
363c35fc
ST
762 if (fe0->dvb.frontend == NULL)
763 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK
764 &dvico_s5h1411_config,
765 &i2c_bus->i2c_adap);
363c35fc
ST
766 if (fe0->dvb.frontend != NULL)
767 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
768 &i2c_bus->i2c_adap,
769 &dvico_xc5000_tunerconfig);
335377b7 770 break;
aef2d186
ST
771 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
772 i2c_bus = &dev->i2c_bus[port->nr - 1];
773
363c35fc 774 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST
775 &dvico_fusionhdtv_xc3028,
776 &i2c_bus->i2c_adap);
363c35fc 777 if (fe0->dvb.frontend != NULL) {
aef2d186
ST
778 struct dvb_frontend *fe;
779 struct xc2028_config cfg = {
780 .i2c_adap = &i2c_bus->i2c_adap,
781 .i2c_addr = 0x61,
aef2d186
ST
782 };
783 static struct xc2028_ctrl ctl = {
ef80bfeb 784 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST
785 .max_len = 64,
786 .demod = XC3028_FE_ZARLINK456,
787 };
788
363c35fc 789 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST
790 &cfg);
791 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
792 fe->ops.tuner_ops.set_config(fe, &ctl);
793 }
794 break;
795 }
4c56b04a 796 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 797 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 798 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST
799 i2c_bus = &dev->i2c_bus[0];
800
363c35fc 801 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST
802 &dvico_fusionhdtv_xc3028,
803 &i2c_bus->i2c_adap);
363c35fc 804 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST
805 struct dvb_frontend *fe;
806 struct xc2028_config cfg = {
807 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
808 .i2c_addr = 0x61,
4c56b04a
ST
809 };
810 static struct xc2028_ctrl ctl = {
ef80bfeb 811 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST
812 .max_len = 64,
813 .demod = XC3028_FE_ZARLINK456,
814 };
815
363c35fc 816 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST
817 &cfg);
818 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
819 fe->ops.tuner_ops.set_config(fe, &ctl);
820 }
96318d0c
IL
821 break;
822 case CX23885_BOARD_TBS_6920:
09ea33e5 823 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL
824
825 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL
826 &tbs_cx24116_config,
827 &i2c_bus->i2c_adap);
96318d0c 828 if (fe0->dvb.frontend != NULL)
09ea33e5 829 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 830
579943f5
IL
831 break;
832 case CX23885_BOARD_TEVII_S470:
833 i2c_bus = &dev->i2c_bus[1];
834
09ea33e5
IL
835 fe0->dvb.frontend = dvb_attach(ds3000_attach,
836 &tevii_ds3000_config,
837 &i2c_bus->i2c_adap);
579943f5 838 if (fe0->dvb.frontend != NULL)
09ea33e5 839 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
579943f5 840
4c56b04a 841 break;
c9b8b04b
IL
842 case CX23885_BOARD_DVBWORLD_2005:
843 i2c_bus = &dev->i2c_bus[1];
844
845 fe0->dvb.frontend = dvb_attach(cx24116_attach,
846 &dvbworld_cx24116_config,
847 &i2c_bus->i2c_adap);
848 break;
5a23b076
IL
849 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
850 i2c_bus = &dev->i2c_bus[0];
851 switch (port->nr) {
852 /* port B */
853 case 1:
854 fe0->dvb.frontend = dvb_attach(stv0900_attach,
855 &netup_stv0900_config,
856 &i2c_bus->i2c_adap, 0);
857 if (fe0->dvb.frontend != NULL) {
858 if (dvb_attach(stv6110_attach,
859 fe0->dvb.frontend,
860 &netup_stv6110_tunerconfig_a,
861 &i2c_bus->i2c_adap)) {
862 if (!dvb_attach(lnbh24_attach,
863 fe0->dvb.frontend,
864 &i2c_bus->i2c_adap,
9329fb5b
AO
865 LNBH24_PCL | LNBH24_TTX,
866 LNBH24_TEN, 0x09))
5a23b076
IL
867 printk(KERN_ERR
868 "No LNBH24 found!\n");
869
870 }
871 }
872 break;
873 /* port C */
874 case 2:
875 fe0->dvb.frontend = dvb_attach(stv0900_attach,
876 &netup_stv0900_config,
877 &i2c_bus->i2c_adap, 1);
878 if (fe0->dvb.frontend != NULL) {
879 if (dvb_attach(stv6110_attach,
880 fe0->dvb.frontend,
881 &netup_stv6110_tunerconfig_b,
882 &i2c_bus->i2c_adap)) {
883 if (!dvb_attach(lnbh24_attach,
884 fe0->dvb.frontend,
885 &i2c_bus->i2c_adap,
9329fb5b
AO
886 LNBH24_PCL | LNBH24_TTX,
887 LNBH24_TEN, 0x0a))
5a23b076
IL
888 printk(KERN_ERR
889 "No LNBH24 found!\n");
890
891 }
892 }
893 break;
894 }
895 break;
493b7127
DW
896 case CX23885_BOARD_MYGICA_X8506:
897 i2c_bus = &dev->i2c_bus[0];
898 i2c_bus2 = &dev->i2c_bus[1];
899 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
900 &mygica_x8506_lgs8gl5_config,
901 &i2c_bus->i2c_adap);
902 if (fe0->dvb.frontend != NULL) {
903 dvb_attach(xc5000_attach,
904 fe0->dvb.frontend,
905 &i2c_bus2->i2c_adap,
906 &mygica_x8506_xc5000_config);
907 }
908 break;
2365b2d3
DW
909 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
910 i2c_bus = &dev->i2c_bus[0];
911 i2c_bus2 = &dev->i2c_bus[1];
912 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
913 &magicpro_prohdtve2_lgs8g75_config,
914 &i2c_bus->i2c_adap);
915 if (fe0->dvb.frontend != NULL) {
916 dvb_attach(xc5000_attach,
917 fe0->dvb.frontend,
918 &i2c_bus2->i2c_adap,
919 &magicpro_prohdtve2_xc5000_config);
920 }
921 break;
13697380 922 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 923 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST
924 i2c_bus = &dev->i2c_bus[0];
925 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
926 &hcw_s5h1411_config,
927 &i2c_bus->i2c_adap);
928 if (fe0->dvb.frontend != NULL)
929 dvb_attach(tda18271_attach, fe0->dvb.frontend,
930 0x60, &dev->i2c_bus[0].i2c_adap,
931 &hauppauge_tda18271_config);
932 break;
ea5697fe
DW
933 case CX23885_BOARD_MYGICA_X8558PRO:
934 switch (port->nr) {
935 /* port B */
936 case 1:
937 i2c_bus = &dev->i2c_bus[0];
938 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
939 &mygica_x8558pro_atbm8830_cfg1,
940 &i2c_bus->i2c_adap);
941 if (fe0->dvb.frontend != NULL) {
942 dvb_attach(max2165_attach,
943 fe0->dvb.frontend,
944 &i2c_bus->i2c_adap,
945 &mygic_x8558pro_max2165_cfg1);
946 }
947 break;
948 /* port C */
949 case 2:
950 i2c_bus = &dev->i2c_bus[1];
951 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
952 &mygica_x8558pro_atbm8830_cfg2,
953 &i2c_bus->i2c_adap);
954 if (fe0->dvb.frontend != NULL) {
955 dvb_attach(max2165_attach,
956 fe0->dvb.frontend,
957 &i2c_bus->i2c_adap,
958 &mygic_x8558pro_max2165_cfg2);
959 }
960 break;
961 }
962 break;
13697380 963
d19770e5 964 default:
9c8ced51
ST
965 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
966 " isn't supported yet\n",
d19770e5
ST
967 dev->name);
968 break;
969 }
363c35fc 970 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST
971 printk(KERN_ERR "%s: frontend initialization failed\n",
972 dev->name);
d19770e5
ST
973 return -1;
974 }
d7cba043 975 /* define general-purpose callback pointer */
363c35fc 976 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST
977
978 /* Put the analog decoder in standby to keep it quiet */
622b828a 979 call_all(dev, core, s_power, 0);
d19770e5 980
363c35fc
ST
981 if (fe0->dvb.frontend->ops.analog_ops.standby)
982 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 983
d19770e5 984 /* register everything */
5a23b076 985 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
5bdd3962
MK
986 &dev->pci->dev, adapter_nr, 0,
987 cx23885_dvb_fe_ioctl_override);
363c35fc 988
5a23b076
IL
989 /* init CI & MAC */
990 switch (dev->board) {
991 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
992 static struct netup_card_info cinfo;
993
994 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
995 memcpy(port->frontends.adapter.proposed_mac,
996 cinfo.port[port->nr - 1].mac, 6);
997 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
998 "%02X:%02X:%02X:%02X:%02X:%02X\n",
999 port->nr,
1000 port->frontends.adapter.proposed_mac[0],
1001 port->frontends.adapter.proposed_mac[1],
1002 port->frontends.adapter.proposed_mac[2],
1003 port->frontends.adapter.proposed_mac[3],
1004 port->frontends.adapter.proposed_mac[4],
1005 port->frontends.adapter.proposed_mac[5]);
1006
1007 netup_ci_init(port);
1008 break;
1009 }
1010 }
1011
1012 return ret;
d19770e5
ST
1013}
1014
1015int cx23885_dvb_register(struct cx23885_tsport *port)
1016{
363c35fc
ST
1017
1018 struct videobuf_dvb_frontend *fe0;
d19770e5 1019 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST
1020 int err, i;
1021
1022 /* Here we need to allocate the correct number of frontends,
af901ca1 1023 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST
1024 * no cx23885 boards support this - yet. But, if we don't modify this
1025 * code then the second frontend would never be allocated (later)
1026 * and fail with error before the attach in dvb_register().
1027 * Without these changes we risk an OOPS later. The changes here
1028 * are for safety, and should provide a good foundation for the
1029 * future addition of any multi-frontend cx23885 based boards.
1030 */
1031 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1032 port->num_frontends);
d19770e5 1033
eb0c58bb 1034 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1035 if (videobuf_dvb_alloc_frontend(
9c8ced51 1036 &port->frontends, i) == NULL) {
eb0c58bb
ST
1037 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1038 return -ENOMEM;
1039 }
1040
1041 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1042 if (!fe0)
1043 err = -EINVAL;
363c35fc 1044
eb0c58bb 1045 dprintk(1, "%s\n", __func__);
9c8ced51 1046 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST
1047 dev->board,
1048 dev->name,
1049 dev->pci_bus,
1050 dev->pci_slot);
d19770e5 1051
eb0c58bb 1052 err = -ENODEV;
d19770e5 1053
eb0c58bb
ST
1054 /* dvb stuff */
1055 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST
1056 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1057 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1058 &dev->pci->dev, &port->slock,
44a6481d
MK
1059 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
1060 sizeof(struct cx23885_buffer), port);
eb0c58bb 1061 }
d19770e5
ST
1062 err = dvb_register(port);
1063 if (err != 0)
9c8ced51
ST
1064 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1065 __func__, err);
d19770e5 1066
d19770e5
ST
1067 return err;
1068}
1069
1070int cx23885_dvb_unregister(struct cx23885_tsport *port)
1071{
363c35fc
ST
1072 struct videobuf_dvb_frontend *fe0;
1073
eb0c58bb
ST
1074 /* FIXME: in an error condition where the we have
1075 * an expected number of frontends (attach problem)
1076 * then this might not clean up correctly, if 1
1077 * is invalid.
1078 * This comment only applies to future boards IF they
1079 * implement MFE support.
1080 */
92abe9ee 1081 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 1082 if (fe0->dvb.frontend)
363c35fc 1083 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1084
afd96668
HV
1085 switch (port->dev->board) {
1086 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1087 netup_ci_exit(port);
1088 break;
1089 }
5a23b076 1090
d19770e5
ST
1091 return 0;
1092}
44a6481d 1093
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