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V4L/DVB (13335): stv0900: fix diseqc support for NetUP card
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
ST		 44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076 47#include "stv0900.h"
f867c3f4 48#include "stv0900_reg.h"
5a23b076
IL		 49#include "stv6110.h"
50#include "lnbh24.h"
96318d0c 51#include "cx24116.h"
5a23b076 52#include "cimax2.h"
493b7127 53#include "lgs8gxx.h"
5a23b076
IL		 54#include "netup-eeprom.h"
55#include "netup-init.h"
a5dbf457 56#include "lgdt3305.h"
d19770e5 57
4513fc69 58static unsigned int debug;
d19770e5 59
4513fc69
ST		 60#define dprintk(level, fmt, arg...)\
61 do { if (debug >= level)\
62 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
63 } while (0)
d19770e5
ST		 64
65/* ------------------------------------------------------------------ */
66
3ba71d21
MK		 67static unsigned int alt_tuner;
68module_param(alt_tuner, int, 0644);
69MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
70
78e92006
JG		 71DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
72
3ba71d21
MK		 73/* ------------------------------------------------------------------ */
74
d19770e5
ST		 75static int dvb_buf_setup(struct videobuf_queue *q,
76 unsigned int *count, unsigned int *size)
77{
78 struct cx23885_tsport *port = q->priv_data;
79
80 port->ts_packet_size = 188 * 4;
81 port->ts_packet_count = 32;
82
83 *size = port->ts_packet_size * port->ts_packet_count;
84 *count = 32;
85 return 0;
86}
87
44a6481d
MK		 88static int dvb_buf_prepare(struct videobuf_queue *q,
89 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 90{
91 struct cx23885_tsport *port = q->priv_data;
9c8ced51 92 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 93}
94
95static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
96{
97 struct cx23885_tsport *port = q->priv_data;
9c8ced51 98 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 99}
100
44a6481d
MK		 101static void dvb_buf_release(struct videobuf_queue *q,
102 struct videobuf_buffer *vb)
d19770e5 103{
9c8ced51 104 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 105}
106
107static struct videobuf_queue_ops dvb_qops = {
108 .buf_setup = dvb_buf_setup,
109 .buf_prepare = dvb_buf_prepare,
110 .buf_queue = dvb_buf_queue,
111 .buf_release = dvb_buf_release,
112};
113
86184e06 114static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 115 .demod_address = 0x32 >> 1,
116 .output_mode = S5H1409_SERIAL_OUTPUT,
117 .gpio = S5H1409_GPIO_ON,
2b03238a 118 .qam_if = 44000,
fc959bef 119 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 120 .status_mode = S5H1409_DEMODLOCKING,
121 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 122};
123
b3ea0166
ST		 124static struct tda10048_config hauppauge_hvr1200_config = {
125 .demod_address = 0x10 >> 1,
126 .output_mode = TDA10048_SERIAL_OUTPUT,
127 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 128 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 129 .dtv6_if_freq_khz = TDA10048_IF_3300,
130 .dtv7_if_freq_khz = TDA10048_IF_3800,
131 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 132 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 133};
134
6b926eca
MK		 135static struct tda10048_config hauppauge_hvr1210_config = {
136 .demod_address = 0x10 >> 1,
137 .output_mode = TDA10048_SERIAL_OUTPUT,
138 .fwbulkwritelen = TDA10048_BULKWRITE_200,
139 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 140 .dtv6_if_freq_khz = TDA10048_IF_3300,
141 .dtv7_if_freq_khz = TDA10048_IF_3500,
142 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 143 .clk_freq_khz = TDA10048_CLK_16000,
144};
145
3ba71d21
MK		 146static struct s5h1409_config hauppauge_ezqam_config = {
147 .demod_address = 0x32 >> 1,
148 .output_mode = S5H1409_SERIAL_OUTPUT,
149 .gpio = S5H1409_GPIO_OFF,
150 .qam_if = 4000,
151 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 152 .status_mode = S5H1409_DEMODLOCKING,
153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 154};
155
fc959bef 156static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 157 .demod_address = 0x32 >> 1,
158 .output_mode = S5H1409_SERIAL_OUTPUT,
159 .gpio = S5H1409_GPIO_OFF,
2b03238a 160 .qam_if = 44000,
fe475163 161 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 162 .status_mode = S5H1409_DEMODLOCKING,
163 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 164};
165
07b4a835
MK		 166static struct s5h1409_config hauppauge_hvr1500_config = {
167 .demod_address = 0x32 >> 1,
168 .output_mode = S5H1409_SERIAL_OUTPUT,
169 .gpio = S5H1409_GPIO_OFF,
170 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 171 .status_mode = S5H1409_DEMODLOCKING,
172 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 173};
174
86184e06 175static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 176 0x61
177};
178
9bc37caa
MK		 179static struct lgdt330x_config fusionhdtv_5_express = {
180 .demod_address = 0x0e,
181 .demod_chip = LGDT3303,
182 .serial_mpeg = 0x40,
183};
184
d1987d55
ST		 185static struct s5h1409_config hauppauge_hvr1500q_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_ON,
189 .qam_if = 44000,
190 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 193};
194
335377b7
MK		 195static struct s5h1409_config dvico_s5h1409_config = {
196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_ON,
199 .qam_if = 44000,
200 .inversion = S5H1409_INVERSION_OFF,
201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
203};
204
52b50450
MK		 205static struct s5h1411_config dvico_s5h1411_config = {
206 .output_mode = S5H1411_SERIAL_OUTPUT,
207 .gpio = S5H1411_GPIO_ON,
208 .qam_if = S5H1411_IF_44000,
209 .vsb_if = S5H1411_IF_44000,
210 .inversion = S5H1411_INVERSION_OFF,
211 .status_mode = S5H1411_DEMODLOCKING,
212 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
213};
214
19bc5796
MK		 215static struct s5h1411_config hcw_s5h1411_config = {
216 .output_mode = S5H1411_SERIAL_OUTPUT,
217 .gpio = S5H1411_GPIO_OFF,
218 .vsb_if = S5H1411_IF_44000,
219 .qam_if = S5H1411_IF_4000,
220 .inversion = S5H1411_INVERSION_ON,
221 .status_mode = S5H1411_DEMODLOCKING,
222 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
223};
224
d1987d55 225static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 226 .i2c_address = 0x61,
227 .if_khz = 5380,
d1987d55
ST		 228};
229
335377b7
MK		 230static struct xc5000_config dvico_xc5000_tunerconfig = {
231 .i2c_address = 0x64,
232 .if_khz = 5380,
335377b7
MK		 233};
234
4041f1a5
MK		 235static struct tda829x_config tda829x_no_probe = {
236 .probe_tuner = TDA829X_DONT_PROBE,
237};
238
f21e0d7f 239static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 240 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
241 .if_lvl = 6, .rfagc_top = 0x37 },
242 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
243 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 244};
245
b34cdc36
MK		 246static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
247 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
248 .if_lvl = 1, .rfagc_top = 0x37, },
249 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
250 .if_lvl = 1, .rfagc_top = 0x37, },
251 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
252 .if_lvl = 1, .rfagc_top = 0x37, },
253};
254
f21e0d7f
MK		 255static struct tda18271_config hauppauge_tda18271_config = {
256 .std_map = &hauppauge_tda18271_std_map,
257 .gate = TDA18271_GATE_ANALOG,
04a68baa 258 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 259};
260
b3ea0166 261static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 262 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 263 .gate = TDA18271_GATE_ANALOG,
04a68baa 264 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 265};
266
6b926eca
MK		 267static struct tda18271_config hauppauge_hvr1210_tuner_config = {
268 .gate = TDA18271_GATE_DIGITAL,
04a68baa 269 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 270};
271
247bc540 272static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 273 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
274 .if_lvl = 1, .rfagc_top = 0x58 },
275 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
276 .if_lvl = 1, .rfagc_top = 0x58 },
277};
278
247bc540
MK		 279static struct tda18271_config hauppauge_hvr127x_config = {
280 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 281 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 282};
283
247bc540 284static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 285 .i2c_addr = 0x0e,
286 .mpeg_mode = LGDT3305_MPEG_SERIAL,
287 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
288 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
289 .deny_i2c_rptr = 1,
290 .spectral_inversion = 1,
291 .qam_if_khz = 4000,
292 .vsb_if_khz = 3250,
293};
294
b1721d0d 295static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 296 BAND_VHF | BAND_UHF, /* band_caps */
297
298 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
299 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
300 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
301 * P_agc_nb_est=2, P_agc_write=0
302 */
303 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
304 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
305
306 712, /* inv_gain */
307 21, /* time_stabiliz */
308
309 0, /* alpha_level */
310 118, /* thlock */
311
312 0, /* wbd_inv */
313 2867, /* wbd_ref */
314 0, /* wbd_sel */
315 2, /* wbd_alpha */
316
317 0, /* agc1_max */
318 0, /* agc1_min */
319 39718, /* agc2_max */
320 9930, /* agc2_min */
321 0, /* agc1_pt1 */
322 0, /* agc1_pt2 */
323 0, /* agc1_pt3 */
324 0, /* agc1_slope1 */
325 0, /* agc1_slope2 */
326 0, /* agc2_pt1 */
327 128, /* agc2_pt2 */
328 29, /* agc2_slope1 */
329 29, /* agc2_slope2 */
330
331 17, /* alpha_mant */
332 27, /* alpha_exp */
333 23, /* beta_mant */
334 51, /* beta_exp */
335
336 1, /* perform_agc_softsplit */
337};
338
339/* PLL Configuration for COFDM BW_MHz = 8.000000
340 * With external clock = 30.000000 */
b1721d0d 341static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 342 60000, /* internal */
343 30000, /* sampling */
344 1, /* pll_cfg: prediv */
345 8, /* pll_cfg: ratio */
346 3, /* pll_cfg: range */
347 1, /* pll_cfg: reset */
348 0, /* pll_cfg: bypass */
349 0, /* misc: refdiv */
350 0, /* misc: bypclk_div */
351 1, /* misc: IO_CLK_en_core */
352 1, /* misc: ADClkSrc */
353 0, /* misc: modulo */
354 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
355 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
356 20452225, /* timf */
357 30000000 /* xtal_hz */
358};
359
360static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
361 .output_mpeg2_in_188_bytes = 1,
362 .hostbus_diversity = 1,
363 .tuner_is_baseband = 0,
364 .update_lna = NULL,
365
366 .agc_config_count = 1,
367 .agc = &xc3028_agc_config,
368 .bw = &xc3028_bw_config,
369
370 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
371 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
372 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
373
374 .pwm_freq_div = 0,
375 .agc_control = NULL,
376 .spur_protect = 0,
377
378 .output_mode = OUTMODE_MPEG2_SERIAL,
379};
380
aef2d186
ST		 381static struct zl10353_config dvico_fusionhdtv_xc3028 = {
382 .demod_address = 0x0f,
383 .if2 = 45600,
384 .no_tuner = 1,
d4dc673d 385 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 386};
387
f867c3f4
IL		 388static struct stv0900_reg stv0900_ts_regs[] = {
389 { R0900_TSGENERAL, 0x00 },
390 { R0900_P1_TSSPEED, 0x40 },
391 { R0900_P2_TSSPEED, 0x40 },
392 { R0900_P1_TSCFGM, 0xc0 },
393 { R0900_P2_TSCFGM, 0xc0 },
394 { R0900_P1_TSCFGH, 0xe0 },
395 { R0900_P2_TSCFGH, 0xe0 },
396 { R0900_P1_TSCFGL, 0x20 },
397 { R0900_P2_TSCFGL, 0x20 },
398 { 0xffff, 0xff }, /* terminate */
399};
400
5a23b076
IL		 401static struct stv0900_config netup_stv0900_config = {
402 .demod_address = 0x68,
644c7ef0 403 .xtal = 8000000,
5a23b076
IL		 404 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
405 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 406 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 407 .tun1_maddress = 0,/* 0x60 */
408 .tun2_maddress = 3,/* 0x63 */
409 .tun1_adc = 1,/* 1 Vpp */
410 .tun2_adc = 1,/* 1 Vpp */
411};
412
413static struct stv6110_config netup_stv6110_tunerconfig_a = {
414 .i2c_address = 0x60,
644c7ef0
AO		 415 .mclk = 16000000,
416 .clk_div = 1,
873688cd 417 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 418};
419
420static struct stv6110_config netup_stv6110_tunerconfig_b = {
421 .i2c_address = 0x63,
644c7ef0
AO		 422 .mclk = 16000000,
423 .clk_div = 1,
873688cd 424 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 425};
426
96318d0c
IL		 427static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
428{
429 struct cx23885_tsport *port = fe->dvb->priv;
430 struct cx23885_dev *dev = port->dev;
431
432 if (voltage == SEC_VOLTAGE_18)
433 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
434 else if (voltage == SEC_VOLTAGE_13)
435 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
436 else
437 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
438 return 0;
439}
440
441static struct cx24116_config tbs_cx24116_config = {
442 .demod_address = 0x05,
443};
444
579943f5
IL		 445static struct cx24116_config tevii_cx24116_config = {
446 .demod_address = 0x55,
447};
448
c9b8b04b
IL		 449static struct cx24116_config dvbworld_cx24116_config = {
450 .demod_address = 0x05,
451};
452
493b7127
DW		 453static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
454 .prod = LGS8GXX_PROD_LGS8GL5,
455 .demod_address = 0x19,
456 .serial_ts = 0,
457 .ts_clk_pol = 1,
458 .ts_clk_gated = 1,
459 .if_clk_freq = 30400, /* 30.4 MHz */
460 .if_freq = 5380, /* 5.38 MHz */
461 .if_neg_center = 1,
462 .ext_adc = 0,
463 .adc_signed = 0,
464 .if_neg_edge = 0,
465};
466
467static struct xc5000_config mygica_x8506_xc5000_config = {
468 .i2c_address = 0x61,
469 .if_khz = 5380,
470};
471
f35b9e80
MK		 472static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
473 struct dvb_frontend_parameters *param)
474{
475 struct cx23885_tsport *port = fe->dvb->priv;
476 struct cx23885_dev *dev = port->dev;
477
478 switch (dev->board) {
479 case CX23885_BOARD_HAUPPAUGE_HVR1275:
480 switch (param->u.vsb.modulation) {
481 case VSB_8:
482 cx23885_gpio_clear(dev, GPIO_5);
483 break;
484 case QAM_64:
485 case QAM_256:
486 default:
487 cx23885_gpio_set(dev, GPIO_5);
488 break;
489 }
490 break;
6f0d8c02
DW		 491 case CX23885_BOARD_MYGICA_X8506:
492 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
493 /* Select Digital TV */
494 cx23885_gpio_set(dev, GPIO_0);
495 break;
f35b9e80 496 }
5bdd3962 497 return 0;
f35b9e80
MK		 498}
499
5bdd3962
MK		 500static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
501 unsigned int cmd, void *parg,
502 unsigned int stage)
503{
504 int err = 0;
505
506 switch (stage) {
507 case DVB_FE_IOCTL_PRE:
508
509 switch (cmd) {
510 case FE_SET_FRONTEND:
511 err = cx23885_dvb_set_frontend(fe,
512 (struct dvb_frontend_parameters *) parg);
513 break;
514 }
515 break;
516
517 case DVB_FE_IOCTL_POST:
518 /* no post-ioctl handling required */
519 break;
520 }
521 return err;
522};
523
524
2365b2d3
DW		 525static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
526 .prod = LGS8GXX_PROD_LGS8G75,
527 .demod_address = 0x19,
528 .serial_ts = 0,
529 .ts_clk_pol = 1,
530 .ts_clk_gated = 1,
531 .if_clk_freq = 30400, /* 30.4 MHz */
532 .if_freq = 6500, /* 6.50 MHz */
533 .if_neg_center = 1,
534 .ext_adc = 0,
535 .adc_signed = 1,
536 .adc_vpp = 2, /* 1.6 Vpp */
537 .if_neg_edge = 1,
538};
539
540static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
541 .i2c_address = 0x61,
542 .if_khz = 6500,
543};
544
d19770e5
ST		 545static int dvb_register(struct cx23885_tsport *port)
546{
547 struct cx23885_dev *dev = port->dev;
493b7127 548 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
363c35fc 549 struct videobuf_dvb_frontend *fe0;
5a23b076 550 int ret;
363c35fc 551
f972e0bd 552 /* Get the first frontend */
92abe9ee 553 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 554 if (!fe0)
555 return -EINVAL;
d19770e5
ST		 556
557 /* init struct videobuf_dvb */
363c35fc 558 fe0->dvb.name = dev->name;
d19770e5
ST		 559
560 /* init frontend */
561 switch (dev->board) {
a77743bc 562 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 563 i2c_bus = &dev->i2c_bus[0];
363c35fc 564 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 565 &hauppauge_generic_config,
f139fa71 566 &i2c_bus->i2c_adap);
363c35fc
ST		 567 if (fe0->dvb.frontend != NULL) {
568 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 569 &i2c_bus->i2c_adap,
86184e06 570 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 571 }
572 break;
a5dbf457 573 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 574 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 575 i2c_bus = &dev->i2c_bus[0];
576 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 577 &hauppauge_lgdt3305_config,
a5dbf457
MK		 578 &i2c_bus->i2c_adap);
579 if (fe0->dvb.frontend != NULL) {
580 dvb_attach(tda18271_attach, fe0->dvb.frontend,
581 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 582 &hauppauge_hvr127x_config);
a5dbf457
MK		 583 }
584 break;
19bc5796
MK		 585 case CX23885_BOARD_HAUPPAUGE_HVR1255:
586 i2c_bus = &dev->i2c_bus[0];
587 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
588 &hcw_s5h1411_config,
589 &i2c_bus->i2c_adap);
590 if (fe0->dvb.frontend != NULL) {
591 dvb_attach(tda18271_attach, fe0->dvb.frontend,
592 0x60, &dev->i2c_bus[1].i2c_adap,
593 &hauppauge_tda18271_config);
594 }
595 break;
3ba71d21
MK		 596 case CX23885_BOARD_HAUPPAUGE_HVR1800:
597 i2c_bus = &dev->i2c_bus[0];
92abe9ee 598 switch (alt_tuner) {
3ba71d21 599 case 1:
363c35fc 600 fe0->dvb.frontend =
3ba71d21
MK		 601 dvb_attach(s5h1409_attach,
602 &hauppauge_ezqam_config,
603 &i2c_bus->i2c_adap);
363c35fc
ST		 604 if (fe0->dvb.frontend != NULL) {
605 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 606 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 607 &tda829x_no_probe);
363c35fc 608 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 609 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 610 &hauppauge_tda18271_config);
3ba71d21
MK		 611 }
612 break;
613 case 0:
614 default:
363c35fc 615 fe0->dvb.frontend =
3ba71d21
MK		 616 dvb_attach(s5h1409_attach,
617 &hauppauge_generic_config,
618 &i2c_bus->i2c_adap);
363c35fc
ST		 619 if (fe0->dvb.frontend != NULL)
620 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 621 &i2c_bus->i2c_adap,
622 &hauppauge_generic_tunerconfig, 0);
623 break;
624 }
625 break;
fc959bef 626 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 627 i2c_bus = &dev->i2c_bus[0];
363c35fc 628 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 629 &hauppauge_hvr1800lp_config,
f139fa71 630 &i2c_bus->i2c_adap);
363c35fc
ST		 631 if (fe0->dvb.frontend != NULL) {
632 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 633 &i2c_bus->i2c_adap,
fc959bef
ST		 634 &hauppauge_generic_tunerconfig, 0);
635 }
636 break;
9bc37caa 637 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 638 i2c_bus = &dev->i2c_bus[0];
363c35fc 639 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 640 &fusionhdtv_5_express,
f139fa71 641 &i2c_bus->i2c_adap);
363c35fc
ST		 642 if (fe0->dvb.frontend != NULL) {
643 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 644 &i2c_bus->i2c_adap, 0x61,
645 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 646 }
647 break;
d1987d55
ST		 648 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
649 i2c_bus = &dev->i2c_bus[1];
363c35fc 650 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 651 &hauppauge_hvr1500q_config,
652 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 653 if (fe0->dvb.frontend != NULL)
654 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 655 &i2c_bus->i2c_adap,
656 &hauppauge_hvr1500q_tunerconfig);
d1987d55 657 break;
07b4a835
MK		 658 case CX23885_BOARD_HAUPPAUGE_HVR1500:
659 i2c_bus = &dev->i2c_bus[1];
363c35fc 660 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 661 &hauppauge_hvr1500_config,
662 &dev->i2c_bus[0].i2c_adap);
363c35fc 663 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 664 struct dvb_frontend *fe;
665 struct xc2028_config cfg = {
666 .i2c_adap = &i2c_bus->i2c_adap,
667 .i2c_addr = 0x61,
07b4a835
MK		 668 };
669 static struct xc2028_ctrl ctl = {
ef80bfeb 670 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 671 .max_len = 64,
52c3d29c 672 .demod = XC3028_FE_OREN538,
07b4a835
MK		 673 };
674
675 fe = dvb_attach(xc2028_attach,
363c35fc 676 fe0->dvb.frontend, &cfg);
07b4a835
MK		 677 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
678 fe->ops.tuner_ops.set_config(fe, &ctl);
679 }
680 break;
b3ea0166 681 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 682 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 683 i2c_bus = &dev->i2c_bus[0];
363c35fc 684 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 685 &hauppauge_hvr1200_config,
686 &i2c_bus->i2c_adap);
363c35fc
ST		 687 if (fe0->dvb.frontend != NULL) {
688 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 689 &dev->i2c_bus[1].i2c_adap, 0x42,
690 &tda829x_no_probe);
363c35fc 691 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 692 0x60, &dev->i2c_bus[1].i2c_adap,
693 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 694 }
695 break;
696 case CX23885_BOARD_HAUPPAUGE_HVR1210:
697 i2c_bus = &dev->i2c_bus[0];
698 fe0->dvb.frontend = dvb_attach(tda10048_attach,
699 &hauppauge_hvr1210_config,
700 &i2c_bus->i2c_adap);
701 if (fe0->dvb.frontend != NULL) {
702 dvb_attach(tda18271_attach, fe0->dvb.frontend,
703 0x60, &dev->i2c_bus[1].i2c_adap,
704 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 705 }
706 break;
66762373
ST		 707 case CX23885_BOARD_HAUPPAUGE_HVR1400:
708 i2c_bus = &dev->i2c_bus[0];
363c35fc 709 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 710 &i2c_bus->i2c_adap,
711 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 712 if (fe0->dvb.frontend != NULL) {
66762373
ST		 713 struct dvb_frontend *fe;
714 struct xc2028_config cfg = {
715 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
716 .i2c_addr = 0x64,
66762373
ST		 717 };
718 static struct xc2028_ctrl ctl = {
ef80bfeb 719 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST		 720 .max_len = 64,
721 .demod = 5000,
9c8ced51
ST		 722 /* This is true for all demods with
723 v36 firmware? */
0975fc68 724 .type = XC2028_D2633,
66762373
ST		 725 };
726
727 fe = dvb_attach(xc2028_attach,
363c35fc 728 fe0->dvb.frontend, &cfg);
66762373
ST		 729 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
730 fe->ops.tuner_ops.set_config(fe, &ctl);
731 }
732 break;
335377b7
MK		 733 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
734 i2c_bus = &dev->i2c_bus[port->nr - 1];
735
363c35fc 736 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 737 &dvico_s5h1409_config,
738 &i2c_bus->i2c_adap);
363c35fc
ST		 739 if (fe0->dvb.frontend == NULL)
740 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 741 &dvico_s5h1411_config,
742 &i2c_bus->i2c_adap);
363c35fc
ST		 743 if (fe0->dvb.frontend != NULL)
744 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 745 &i2c_bus->i2c_adap,
746 &dvico_xc5000_tunerconfig);
335377b7 747 break;
aef2d186
ST		 748 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
749 i2c_bus = &dev->i2c_bus[port->nr - 1];
750
363c35fc 751 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 752 &dvico_fusionhdtv_xc3028,
753 &i2c_bus->i2c_adap);
363c35fc 754 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 755 struct dvb_frontend *fe;
756 struct xc2028_config cfg = {
757 .i2c_adap = &i2c_bus->i2c_adap,
758 .i2c_addr = 0x61,
aef2d186
ST		 759 };
760 static struct xc2028_ctrl ctl = {
ef80bfeb 761 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 762 .max_len = 64,
763 .demod = XC3028_FE_ZARLINK456,
764 };
765
363c35fc 766 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 767 &cfg);
768 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
769 fe->ops.tuner_ops.set_config(fe, &ctl);
770 }
771 break;
772 }
4c56b04a 773 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 774 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 775 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 776 i2c_bus = &dev->i2c_bus[0];
777
363c35fc 778 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 779 &dvico_fusionhdtv_xc3028,
780 &i2c_bus->i2c_adap);
363c35fc 781 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 782 struct dvb_frontend *fe;
783 struct xc2028_config cfg = {
784 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
785 .i2c_addr = 0x61,
4c56b04a
ST		 786 };
787 static struct xc2028_ctrl ctl = {
ef80bfeb 788 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 789 .max_len = 64,
790 .demod = XC3028_FE_ZARLINK456,
791 };
792
363c35fc 793 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 794 &cfg);
795 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
796 fe->ops.tuner_ops.set_config(fe, &ctl);
797 }
96318d0c
IL		 798 break;
799 case CX23885_BOARD_TBS_6920:
800 i2c_bus = &dev->i2c_bus[0];
801
802 fe0->dvb.frontend = dvb_attach(cx24116_attach,
803 &tbs_cx24116_config,
804 &i2c_bus->i2c_adap);
805 if (fe0->dvb.frontend != NULL)
806 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
807
579943f5
IL		 808 break;
809 case CX23885_BOARD_TEVII_S470:
810 i2c_bus = &dev->i2c_bus[1];
811
812 fe0->dvb.frontend = dvb_attach(cx24116_attach,
813 &tevii_cx24116_config,
814 &i2c_bus->i2c_adap);
815 if (fe0->dvb.frontend != NULL)
816 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
817
4c56b04a 818 break;
c9b8b04b
IL		 819 case CX23885_BOARD_DVBWORLD_2005:
820 i2c_bus = &dev->i2c_bus[1];
821
822 fe0->dvb.frontend = dvb_attach(cx24116_attach,
823 &dvbworld_cx24116_config,
824 &i2c_bus->i2c_adap);
825 break;
5a23b076
IL		 826 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
827 i2c_bus = &dev->i2c_bus[0];
828 switch (port->nr) {
829 /* port B */
830 case 1:
831 fe0->dvb.frontend = dvb_attach(stv0900_attach,
832 &netup_stv0900_config,
833 &i2c_bus->i2c_adap, 0);
834 if (fe0->dvb.frontend != NULL) {
835 if (dvb_attach(stv6110_attach,
836 fe0->dvb.frontend,
837 &netup_stv6110_tunerconfig_a,
838 &i2c_bus->i2c_adap)) {
839 if (!dvb_attach(lnbh24_attach,
840 fe0->dvb.frontend,
841 &i2c_bus->i2c_adap,
9329fb5b
AO		 842 LNBH24_PCL | LNBH24_TTX,
843 LNBH24_TEN, 0x09))
5a23b076
IL		 844 printk(KERN_ERR
845 "No LNBH24 found!\n");
846
847 }
848 }
849 break;
850 /* port C */
851 case 2:
852 fe0->dvb.frontend = dvb_attach(stv0900_attach,
853 &netup_stv0900_config,
854 &i2c_bus->i2c_adap, 1);
855 if (fe0->dvb.frontend != NULL) {
856 if (dvb_attach(stv6110_attach,
857 fe0->dvb.frontend,
858 &netup_stv6110_tunerconfig_b,
859 &i2c_bus->i2c_adap)) {
860 if (!dvb_attach(lnbh24_attach,
861 fe0->dvb.frontend,
862 &i2c_bus->i2c_adap,
9329fb5b
AO		 863 LNBH24_PCL | LNBH24_TTX,
864 LNBH24_TEN, 0x0a))
5a23b076
IL		 865 printk(KERN_ERR
866 "No LNBH24 found!\n");
867
868 }
869 }
870 break;
871 }
872 break;
493b7127
DW		 873 case CX23885_BOARD_MYGICA_X8506:
874 i2c_bus = &dev->i2c_bus[0];
875 i2c_bus2 = &dev->i2c_bus[1];
876 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
877 &mygica_x8506_lgs8gl5_config,
878 &i2c_bus->i2c_adap);
879 if (fe0->dvb.frontend != NULL) {
880 dvb_attach(xc5000_attach,
881 fe0->dvb.frontend,
882 &i2c_bus2->i2c_adap,
883 &mygica_x8506_xc5000_config);
884 }
885 break;
2365b2d3
DW		 886 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
887 i2c_bus = &dev->i2c_bus[0];
888 i2c_bus2 = &dev->i2c_bus[1];
889 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
890 &magicpro_prohdtve2_lgs8g75_config,
891 &i2c_bus->i2c_adap);
892 if (fe0->dvb.frontend != NULL) {
893 dvb_attach(xc5000_attach,
894 fe0->dvb.frontend,
895 &i2c_bus2->i2c_adap,
896 &magicpro_prohdtve2_xc5000_config);
897 }
898 break;
13697380
ST		 899 case CX23885_BOARD_HAUPPAUGE_HVR1850:
900 i2c_bus = &dev->i2c_bus[0];
901 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
902 &hcw_s5h1411_config,
903 &i2c_bus->i2c_adap);
904 if (fe0->dvb.frontend != NULL)
905 dvb_attach(tda18271_attach, fe0->dvb.frontend,
906 0x60, &dev->i2c_bus[0].i2c_adap,
907 &hauppauge_tda18271_config);
908 break;
909
d19770e5 910 default:
9c8ced51
ST		 911 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
912 " isn't supported yet\n",
d19770e5
ST		 913 dev->name);
914 break;
915 }
363c35fc 916 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST		 917 printk(KERN_ERR "%s: frontend initialization failed\n",
918 dev->name);
d19770e5
ST		 919 return -1;
920 }
d7cba043 921 /* define general-purpose callback pointer */
363c35fc 922 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST		 923
924 /* Put the analog decoder in standby to keep it quiet */
622b828a 925 call_all(dev, core, s_power, 0);
d19770e5 926
363c35fc
ST		 927 if (fe0->dvb.frontend->ops.analog_ops.standby)
928 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 929
d19770e5 930 /* register everything */
5a23b076 931 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
5bdd3962
MK		 932 &dev->pci->dev, adapter_nr, 0,
933 cx23885_dvb_fe_ioctl_override);
363c35fc 934
5a23b076
IL		 935 /* init CI & MAC */
936 switch (dev->board) {
937 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
938 static struct netup_card_info cinfo;
939
940 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
941 memcpy(port->frontends.adapter.proposed_mac,
942 cinfo.port[port->nr - 1].mac, 6);
943 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
944 "%02X:%02X:%02X:%02X:%02X:%02X\n",
945 port->nr,
946 port->frontends.adapter.proposed_mac[0],
947 port->frontends.adapter.proposed_mac[1],
948 port->frontends.adapter.proposed_mac[2],
949 port->frontends.adapter.proposed_mac[3],
950 port->frontends.adapter.proposed_mac[4],
951 port->frontends.adapter.proposed_mac[5]);
952
953 netup_ci_init(port);
954 break;
955 }
956 }
957
958 return ret;
d19770e5
ST		 959}
960
961int cx23885_dvb_register(struct cx23885_tsport *port)
962{
363c35fc
ST		 963
964 struct videobuf_dvb_frontend *fe0;
d19770e5 965 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 966 int err, i;
967
968 /* Here we need to allocate the correct number of frontends,
969 * as reflected in the cards struct. The reality is that currrently
970 * no cx23885 boards support this - yet. But, if we don't modify this
971 * code then the second frontend would never be allocated (later)
972 * and fail with error before the attach in dvb_register().
973 * Without these changes we risk an OOPS later. The changes here
974 * are for safety, and should provide a good foundation for the
975 * future addition of any multi-frontend cx23885 based boards.
976 */
977 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
978 port->num_frontends);
d19770e5 979
eb0c58bb 980 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 981 if (videobuf_dvb_alloc_frontend(
9c8ced51 982 &port->frontends, i) == NULL) {
eb0c58bb
ST		 983 printk(KERN_ERR "%s() failed to alloc\n", __func__);
984 return -ENOMEM;
985 }
986
987 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
988 if (!fe0)
989 err = -EINVAL;
363c35fc 990
eb0c58bb 991 dprintk(1, "%s\n", __func__);
9c8ced51 992 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 993 dev->board,
994 dev->name,
995 dev->pci_bus,
996 dev->pci_slot);
d19770e5 997
eb0c58bb 998 err = -ENODEV;
d19770e5 999
eb0c58bb
ST		 1000 /* dvb stuff */
1001 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 1002 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1003 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1004 &dev->pci->dev, &port->slock,
44a6481d
MK		 1005 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
1006 sizeof(struct cx23885_buffer), port);
eb0c58bb 1007 }
d19770e5
ST		 1008 err = dvb_register(port);
1009 if (err != 0)
9c8ced51
ST		 1010 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1011 __func__, err);
d19770e5 1012
d19770e5
ST		 1013 return err;
1014}
1015
1016int cx23885_dvb_unregister(struct cx23885_tsport *port)
1017{
363c35fc
ST		 1018 struct videobuf_dvb_frontend *fe0;
1019
eb0c58bb
ST		 1020 /* FIXME: in an error condition where the we have
1021 * an expected number of frontends (attach problem)
1022 * then this might not clean up correctly, if 1
1023 * is invalid.
1024 * This comment only applies to future boards IF they
1025 * implement MFE support.
1026 */
92abe9ee 1027 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 1028 if (fe0->dvb.frontend)
363c35fc 1029 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1030
afd96668
HV		 1031 switch (port->dev->board) {
1032 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1033 netup_ci_exit(port);
1034 break;
1035 }
5a23b076 1036
d19770e5
ST		 1037 return 0;
1038}
44a6481d 1039
Linux kernel - Deliverables
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