projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
V4L/DVB (12115): tda10048: add missing entry to pll_tab for 3.8 MHz IF
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
ST		 44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076 47#include "stv0900.h"
f867c3f4 48#include "stv0900_reg.h"
5a23b076
IL		 49#include "stv6110.h"
50#include "lnbh24.h"
96318d0c 51#include "cx24116.h"
5a23b076 52#include "cimax2.h"
493b7127 53#include "lgs8gxx.h"
5a23b076
IL		 54#include "netup-eeprom.h"
55#include "netup-init.h"
a5dbf457 56#include "lgdt3305.h"
d19770e5 57
4513fc69 58static unsigned int debug;
d19770e5 59
4513fc69
ST		 60#define dprintk(level, fmt, arg...)\
61 do { if (debug >= level)\
62 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
63 } while (0)
d19770e5
ST		 64
65/* ------------------------------------------------------------------ */
66
3ba71d21
MK		 67static unsigned int alt_tuner;
68module_param(alt_tuner, int, 0644);
69MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
70
78e92006
JG		 71DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
72
3ba71d21
MK		 73/* ------------------------------------------------------------------ */
74
d19770e5
ST		 75static int dvb_buf_setup(struct videobuf_queue *q,
76 unsigned int *count, unsigned int *size)
77{
78 struct cx23885_tsport *port = q->priv_data;
79
80 port->ts_packet_size = 188 * 4;
81 port->ts_packet_count = 32;
82
83 *size = port->ts_packet_size * port->ts_packet_count;
84 *count = 32;
85 return 0;
86}
87
44a6481d
MK		 88static int dvb_buf_prepare(struct videobuf_queue *q,
89 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 90{
91 struct cx23885_tsport *port = q->priv_data;
9c8ced51 92 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 93}
94
95static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
96{
97 struct cx23885_tsport *port = q->priv_data;
9c8ced51 98 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 99}
100
44a6481d
MK		 101static void dvb_buf_release(struct videobuf_queue *q,
102 struct videobuf_buffer *vb)
d19770e5 103{
9c8ced51 104 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 105}
106
107static struct videobuf_queue_ops dvb_qops = {
108 .buf_setup = dvb_buf_setup,
109 .buf_prepare = dvb_buf_prepare,
110 .buf_queue = dvb_buf_queue,
111 .buf_release = dvb_buf_release,
112};
113
86184e06 114static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 115 .demod_address = 0x32 >> 1,
116 .output_mode = S5H1409_SERIAL_OUTPUT,
117 .gpio = S5H1409_GPIO_ON,
2b03238a 118 .qam_if = 44000,
fc959bef 119 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 120 .status_mode = S5H1409_DEMODLOCKING,
121 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 122};
123
b3ea0166
ST		 124static struct tda10048_config hauppauge_hvr1200_config = {
125 .demod_address = 0x10 >> 1,
126 .output_mode = TDA10048_SERIAL_OUTPUT,
127 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 128 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 129 .dtv6_if_freq_khz = TDA10048_IF_3300,
130 .dtv7_if_freq_khz = TDA10048_IF_3800,
131 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 132 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 133};
134
6b926eca
MK		 135static struct tda10048_config hauppauge_hvr1210_config = {
136 .demod_address = 0x10 >> 1,
137 .output_mode = TDA10048_SERIAL_OUTPUT,
138 .fwbulkwritelen = TDA10048_BULKWRITE_200,
139 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 140 .dtv6_if_freq_khz = TDA10048_IF_3300,
141 .dtv7_if_freq_khz = TDA10048_IF_3500,
142 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 143 .clk_freq_khz = TDA10048_CLK_16000,
144};
145
3ba71d21
MK		 146static struct s5h1409_config hauppauge_ezqam_config = {
147 .demod_address = 0x32 >> 1,
148 .output_mode = S5H1409_SERIAL_OUTPUT,
149 .gpio = S5H1409_GPIO_OFF,
150 .qam_if = 4000,
151 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 152 .status_mode = S5H1409_DEMODLOCKING,
153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 154};
155
fc959bef 156static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 157 .demod_address = 0x32 >> 1,
158 .output_mode = S5H1409_SERIAL_OUTPUT,
159 .gpio = S5H1409_GPIO_OFF,
2b03238a 160 .qam_if = 44000,
fe475163 161 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 162 .status_mode = S5H1409_DEMODLOCKING,
163 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 164};
165
07b4a835
MK		 166static struct s5h1409_config hauppauge_hvr1500_config = {
167 .demod_address = 0x32 >> 1,
168 .output_mode = S5H1409_SERIAL_OUTPUT,
169 .gpio = S5H1409_GPIO_OFF,
170 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 171 .status_mode = S5H1409_DEMODLOCKING,
172 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 173};
174
86184e06 175static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 176 0x61
177};
178
9bc37caa
MK		 179static struct lgdt330x_config fusionhdtv_5_express = {
180 .demod_address = 0x0e,
181 .demod_chip = LGDT3303,
182 .serial_mpeg = 0x40,
183};
184
d1987d55
ST		 185static struct s5h1409_config hauppauge_hvr1500q_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_ON,
189 .qam_if = 44000,
190 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 193};
194
335377b7
MK		 195static struct s5h1409_config dvico_s5h1409_config = {
196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_ON,
199 .qam_if = 44000,
200 .inversion = S5H1409_INVERSION_OFF,
201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
203};
204
52b50450
MK		 205static struct s5h1411_config dvico_s5h1411_config = {
206 .output_mode = S5H1411_SERIAL_OUTPUT,
207 .gpio = S5H1411_GPIO_ON,
208 .qam_if = S5H1411_IF_44000,
209 .vsb_if = S5H1411_IF_44000,
210 .inversion = S5H1411_INVERSION_OFF,
211 .status_mode = S5H1411_DEMODLOCKING,
212 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
213};
214
19bc5796
MK		 215static struct s5h1411_config hcw_s5h1411_config = {
216 .output_mode = S5H1411_SERIAL_OUTPUT,
217 .gpio = S5H1411_GPIO_OFF,
218 .vsb_if = S5H1411_IF_44000,
219 .qam_if = S5H1411_IF_4000,
220 .inversion = S5H1411_INVERSION_ON,
221 .status_mode = S5H1411_DEMODLOCKING,
222 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
223};
224
d1987d55 225static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 226 .i2c_address = 0x61,
227 .if_khz = 5380,
d1987d55
ST		 228};
229
335377b7
MK		 230static struct xc5000_config dvico_xc5000_tunerconfig = {
231 .i2c_address = 0x64,
232 .if_khz = 5380,
335377b7
MK		 233};
234
4041f1a5
MK		 235static struct tda829x_config tda829x_no_probe = {
236 .probe_tuner = TDA829X_DONT_PROBE,
237};
238
f21e0d7f 239static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 240 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
241 .if_lvl = 6, .rfagc_top = 0x37 },
242 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
243 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 244};
245
246static struct tda18271_config hauppauge_tda18271_config = {
247 .std_map = &hauppauge_tda18271_std_map,
248 .gate = TDA18271_GATE_ANALOG,
249};
250
b3ea0166
ST		 251static struct tda18271_config hauppauge_hvr1200_tuner_config = {
252 .gate = TDA18271_GATE_ANALOG,
253};
254
6b926eca
MK		 255static struct tda18271_config hauppauge_hvr1210_tuner_config = {
256 .gate = TDA18271_GATE_DIGITAL,
257};
258
247bc540 259static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 260 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
261 .if_lvl = 1, .rfagc_top = 0x58 },
262 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
263 .if_lvl = 1, .rfagc_top = 0x58 },
264};
265
247bc540
MK		 266static struct tda18271_config hauppauge_hvr127x_config = {
267 .std_map = &hauppauge_hvr127x_std_map,
a5dbf457
MK		 268};
269
247bc540 270static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 271 .i2c_addr = 0x0e,
272 .mpeg_mode = LGDT3305_MPEG_SERIAL,
273 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
274 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
275 .deny_i2c_rptr = 1,
276 .spectral_inversion = 1,
277 .qam_if_khz = 4000,
278 .vsb_if_khz = 3250,
279};
280
b1721d0d 281static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 282 BAND_VHF | BAND_UHF, /* band_caps */
283
284 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
285 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
286 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
287 * P_agc_nb_est=2, P_agc_write=0
288 */
289 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
290 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
291
292 712, /* inv_gain */
293 21, /* time_stabiliz */
294
295 0, /* alpha_level */
296 118, /* thlock */
297
298 0, /* wbd_inv */
299 2867, /* wbd_ref */
300 0, /* wbd_sel */
301 2, /* wbd_alpha */
302
303 0, /* agc1_max */
304 0, /* agc1_min */
305 39718, /* agc2_max */
306 9930, /* agc2_min */
307 0, /* agc1_pt1 */
308 0, /* agc1_pt2 */
309 0, /* agc1_pt3 */
310 0, /* agc1_slope1 */
311 0, /* agc1_slope2 */
312 0, /* agc2_pt1 */
313 128, /* agc2_pt2 */
314 29, /* agc2_slope1 */
315 29, /* agc2_slope2 */
316
317 17, /* alpha_mant */
318 27, /* alpha_exp */
319 23, /* beta_mant */
320 51, /* beta_exp */
321
322 1, /* perform_agc_softsplit */
323};
324
325/* PLL Configuration for COFDM BW_MHz = 8.000000
326 * With external clock = 30.000000 */
b1721d0d 327static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 328 60000, /* internal */
329 30000, /* sampling */
330 1, /* pll_cfg: prediv */
331 8, /* pll_cfg: ratio */
332 3, /* pll_cfg: range */
333 1, /* pll_cfg: reset */
334 0, /* pll_cfg: bypass */
335 0, /* misc: refdiv */
336 0, /* misc: bypclk_div */
337 1, /* misc: IO_CLK_en_core */
338 1, /* misc: ADClkSrc */
339 0, /* misc: modulo */
340 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
341 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
342 20452225, /* timf */
343 30000000 /* xtal_hz */
344};
345
346static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
347 .output_mpeg2_in_188_bytes = 1,
348 .hostbus_diversity = 1,
349 .tuner_is_baseband = 0,
350 .update_lna = NULL,
351
352 .agc_config_count = 1,
353 .agc = &xc3028_agc_config,
354 .bw = &xc3028_bw_config,
355
356 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
357 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
358 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
359
360 .pwm_freq_div = 0,
361 .agc_control = NULL,
362 .spur_protect = 0,
363
364 .output_mode = OUTMODE_MPEG2_SERIAL,
365};
366
aef2d186
ST		 367static struct zl10353_config dvico_fusionhdtv_xc3028 = {
368 .demod_address = 0x0f,
369 .if2 = 45600,
370 .no_tuner = 1,
d4dc673d 371 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 372};
373
f867c3f4
IL		 374static struct stv0900_reg stv0900_ts_regs[] = {
375 { R0900_TSGENERAL, 0x00 },
376 { R0900_P1_TSSPEED, 0x40 },
377 { R0900_P2_TSSPEED, 0x40 },
378 { R0900_P1_TSCFGM, 0xc0 },
379 { R0900_P2_TSCFGM, 0xc0 },
380 { R0900_P1_TSCFGH, 0xe0 },
381 { R0900_P2_TSCFGH, 0xe0 },
382 { R0900_P1_TSCFGL, 0x20 },
383 { R0900_P2_TSCFGL, 0x20 },
384 { 0xffff, 0xff }, /* terminate */
385};
386
5a23b076
IL		 387static struct stv0900_config netup_stv0900_config = {
388 .demod_address = 0x68,
389 .xtal = 27000000,
390 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
391 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 392 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 393 .tun1_maddress = 0,/* 0x60 */
394 .tun2_maddress = 3,/* 0x63 */
395 .tun1_adc = 1,/* 1 Vpp */
396 .tun2_adc = 1,/* 1 Vpp */
397};
398
399static struct stv6110_config netup_stv6110_tunerconfig_a = {
400 .i2c_address = 0x60,
401 .mclk = 27000000,
402 .iq_wiring = 0,
403};
404
405static struct stv6110_config netup_stv6110_tunerconfig_b = {
406 .i2c_address = 0x63,
407 .mclk = 27000000,
408 .iq_wiring = 1,
409};
410
96318d0c
IL		 411static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
412{
413 struct cx23885_tsport *port = fe->dvb->priv;
414 struct cx23885_dev *dev = port->dev;
415
416 if (voltage == SEC_VOLTAGE_18)
417 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
418 else if (voltage == SEC_VOLTAGE_13)
419 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
420 else
421 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
422 return 0;
423}
424
425static struct cx24116_config tbs_cx24116_config = {
426 .demod_address = 0x05,
427};
428
579943f5
IL		 429static struct cx24116_config tevii_cx24116_config = {
430 .demod_address = 0x55,
431};
432
c9b8b04b
IL		 433static struct cx24116_config dvbworld_cx24116_config = {
434 .demod_address = 0x05,
435};
436
493b7127
DW		 437static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
438 .prod = LGS8GXX_PROD_LGS8GL5,
439 .demod_address = 0x19,
440 .serial_ts = 0,
441 .ts_clk_pol = 1,
442 .ts_clk_gated = 1,
443 .if_clk_freq = 30400, /* 30.4 MHz */
444 .if_freq = 5380, /* 5.38 MHz */
445 .if_neg_center = 1,
446 .ext_adc = 0,
447 .adc_signed = 0,
448 .if_neg_edge = 0,
449};
450
451static struct xc5000_config mygica_x8506_xc5000_config = {
452 .i2c_address = 0x61,
453 .if_khz = 5380,
454};
455
d19770e5
ST		 456static int dvb_register(struct cx23885_tsport *port)
457{
458 struct cx23885_dev *dev = port->dev;
493b7127 459 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
363c35fc 460 struct videobuf_dvb_frontend *fe0;
5a23b076 461 int ret;
363c35fc 462
f972e0bd 463 /* Get the first frontend */
92abe9ee 464 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 465 if (!fe0)
466 return -EINVAL;
d19770e5
ST		 467
468 /* init struct videobuf_dvb */
363c35fc 469 fe0->dvb.name = dev->name;
d19770e5
ST		 470
471 /* init frontend */
472 switch (dev->board) {
a77743bc 473 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 474 i2c_bus = &dev->i2c_bus[0];
363c35fc 475 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 476 &hauppauge_generic_config,
f139fa71 477 &i2c_bus->i2c_adap);
363c35fc
ST		 478 if (fe0->dvb.frontend != NULL) {
479 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 480 &i2c_bus->i2c_adap,
86184e06 481 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 482 }
483 break;
a5dbf457 484 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 485 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 486 i2c_bus = &dev->i2c_bus[0];
487 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 488 &hauppauge_lgdt3305_config,
a5dbf457
MK		 489 &i2c_bus->i2c_adap);
490 if (fe0->dvb.frontend != NULL) {
491 dvb_attach(tda18271_attach, fe0->dvb.frontend,
492 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 493 &hauppauge_hvr127x_config);
a5dbf457
MK		 494 }
495 break;
19bc5796
MK		 496 case CX23885_BOARD_HAUPPAUGE_HVR1255:
497 i2c_bus = &dev->i2c_bus[0];
498 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
499 &hcw_s5h1411_config,
500 &i2c_bus->i2c_adap);
501 if (fe0->dvb.frontend != NULL) {
502 dvb_attach(tda18271_attach, fe0->dvb.frontend,
503 0x60, &dev->i2c_bus[1].i2c_adap,
504 &hauppauge_tda18271_config);
505 }
506 break;
3ba71d21
MK		 507 case CX23885_BOARD_HAUPPAUGE_HVR1800:
508 i2c_bus = &dev->i2c_bus[0];
92abe9ee 509 switch (alt_tuner) {
3ba71d21 510 case 1:
363c35fc 511 fe0->dvb.frontend =
3ba71d21
MK		 512 dvb_attach(s5h1409_attach,
513 &hauppauge_ezqam_config,
514 &i2c_bus->i2c_adap);
363c35fc
ST		 515 if (fe0->dvb.frontend != NULL) {
516 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 517 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 518 &tda829x_no_probe);
363c35fc 519 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 520 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 521 &hauppauge_tda18271_config);
3ba71d21
MK		 522 }
523 break;
524 case 0:
525 default:
363c35fc 526 fe0->dvb.frontend =
3ba71d21
MK		 527 dvb_attach(s5h1409_attach,
528 &hauppauge_generic_config,
529 &i2c_bus->i2c_adap);
363c35fc
ST		 530 if (fe0->dvb.frontend != NULL)
531 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 532 &i2c_bus->i2c_adap,
533 &hauppauge_generic_tunerconfig, 0);
534 break;
535 }
536 break;
fc959bef 537 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 538 i2c_bus = &dev->i2c_bus[0];
363c35fc 539 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 540 &hauppauge_hvr1800lp_config,
f139fa71 541 &i2c_bus->i2c_adap);
363c35fc
ST		 542 if (fe0->dvb.frontend != NULL) {
543 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 544 &i2c_bus->i2c_adap,
fc959bef
ST		 545 &hauppauge_generic_tunerconfig, 0);
546 }
547 break;
9bc37caa 548 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 549 i2c_bus = &dev->i2c_bus[0];
363c35fc 550 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 551 &fusionhdtv_5_express,
f139fa71 552 &i2c_bus->i2c_adap);
363c35fc
ST		 553 if (fe0->dvb.frontend != NULL) {
554 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 555 &i2c_bus->i2c_adap, 0x61,
556 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 557 }
558 break;
d1987d55
ST		 559 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
560 i2c_bus = &dev->i2c_bus[1];
363c35fc 561 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 562 &hauppauge_hvr1500q_config,
563 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 564 if (fe0->dvb.frontend != NULL)
565 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 566 &i2c_bus->i2c_adap,
567 &hauppauge_hvr1500q_tunerconfig);
d1987d55 568 break;
07b4a835
MK		 569 case CX23885_BOARD_HAUPPAUGE_HVR1500:
570 i2c_bus = &dev->i2c_bus[1];
363c35fc 571 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 572 &hauppauge_hvr1500_config,
573 &dev->i2c_bus[0].i2c_adap);
363c35fc 574 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 575 struct dvb_frontend *fe;
576 struct xc2028_config cfg = {
577 .i2c_adap = &i2c_bus->i2c_adap,
578 .i2c_addr = 0x61,
07b4a835
MK		 579 };
580 static struct xc2028_ctrl ctl = {
ef80bfeb 581 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 582 .max_len = 64,
52c3d29c 583 .demod = XC3028_FE_OREN538,
07b4a835
MK		 584 };
585
586 fe = dvb_attach(xc2028_attach,
363c35fc 587 fe0->dvb.frontend, &cfg);
07b4a835
MK		 588 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
589 fe->ops.tuner_ops.set_config(fe, &ctl);
590 }
591 break;
b3ea0166 592 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 593 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 594 i2c_bus = &dev->i2c_bus[0];
363c35fc 595 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 596 &hauppauge_hvr1200_config,
597 &i2c_bus->i2c_adap);
363c35fc
ST		 598 if (fe0->dvb.frontend != NULL) {
599 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 600 &dev->i2c_bus[1].i2c_adap, 0x42,
601 &tda829x_no_probe);
363c35fc 602 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 603 0x60, &dev->i2c_bus[1].i2c_adap,
604 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 605 }
606 break;
607 case CX23885_BOARD_HAUPPAUGE_HVR1210:
608 i2c_bus = &dev->i2c_bus[0];
609 fe0->dvb.frontend = dvb_attach(tda10048_attach,
610 &hauppauge_hvr1210_config,
611 &i2c_bus->i2c_adap);
612 if (fe0->dvb.frontend != NULL) {
613 dvb_attach(tda18271_attach, fe0->dvb.frontend,
614 0x60, &dev->i2c_bus[1].i2c_adap,
615 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 616 }
617 break;
66762373
ST		 618 case CX23885_BOARD_HAUPPAUGE_HVR1400:
619 i2c_bus = &dev->i2c_bus[0];
363c35fc 620 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 621 &i2c_bus->i2c_adap,
622 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 623 if (fe0->dvb.frontend != NULL) {
66762373
ST		 624 struct dvb_frontend *fe;
625 struct xc2028_config cfg = {
626 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
627 .i2c_addr = 0x64,
66762373
ST		 628 };
629 static struct xc2028_ctrl ctl = {
ef80bfeb 630 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST		 631 .max_len = 64,
632 .demod = 5000,
9c8ced51
ST		 633 /* This is true for all demods with
634 v36 firmware? */
0975fc68 635 .type = XC2028_D2633,
66762373
ST		 636 };
637
638 fe = dvb_attach(xc2028_attach,
363c35fc 639 fe0->dvb.frontend, &cfg);
66762373
ST		 640 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
641 fe->ops.tuner_ops.set_config(fe, &ctl);
642 }
643 break;
335377b7
MK		 644 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
645 i2c_bus = &dev->i2c_bus[port->nr - 1];
646
363c35fc 647 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 648 &dvico_s5h1409_config,
649 &i2c_bus->i2c_adap);
363c35fc
ST		 650 if (fe0->dvb.frontend == NULL)
651 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 652 &dvico_s5h1411_config,
653 &i2c_bus->i2c_adap);
363c35fc
ST		 654 if (fe0->dvb.frontend != NULL)
655 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 656 &i2c_bus->i2c_adap,
657 &dvico_xc5000_tunerconfig);
335377b7 658 break;
aef2d186
ST		 659 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
660 i2c_bus = &dev->i2c_bus[port->nr - 1];
661
363c35fc 662 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 663 &dvico_fusionhdtv_xc3028,
664 &i2c_bus->i2c_adap);
363c35fc 665 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 666 struct dvb_frontend *fe;
667 struct xc2028_config cfg = {
668 .i2c_adap = &i2c_bus->i2c_adap,
669 .i2c_addr = 0x61,
aef2d186
ST		 670 };
671 static struct xc2028_ctrl ctl = {
ef80bfeb 672 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 673 .max_len = 64,
674 .demod = XC3028_FE_ZARLINK456,
675 };
676
363c35fc 677 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 678 &cfg);
679 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
680 fe->ops.tuner_ops.set_config(fe, &ctl);
681 }
682 break;
683 }
4c56b04a 684 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 685 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
4c56b04a
ST		 686 i2c_bus = &dev->i2c_bus[0];
687
363c35fc 688 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 689 &dvico_fusionhdtv_xc3028,
690 &i2c_bus->i2c_adap);
363c35fc 691 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 692 struct dvb_frontend *fe;
693 struct xc2028_config cfg = {
694 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
695 .i2c_addr = 0x61,
4c56b04a
ST		 696 };
697 static struct xc2028_ctrl ctl = {
ef80bfeb 698 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 699 .max_len = 64,
700 .demod = XC3028_FE_ZARLINK456,
701 };
702
363c35fc 703 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 704 &cfg);
705 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
706 fe->ops.tuner_ops.set_config(fe, &ctl);
707 }
96318d0c
IL		 708 break;
709 case CX23885_BOARD_TBS_6920:
710 i2c_bus = &dev->i2c_bus[0];
711
712 fe0->dvb.frontend = dvb_attach(cx24116_attach,
713 &tbs_cx24116_config,
714 &i2c_bus->i2c_adap);
715 if (fe0->dvb.frontend != NULL)
716 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
717
579943f5
IL		 718 break;
719 case CX23885_BOARD_TEVII_S470:
720 i2c_bus = &dev->i2c_bus[1];
721
722 fe0->dvb.frontend = dvb_attach(cx24116_attach,
723 &tevii_cx24116_config,
724 &i2c_bus->i2c_adap);
725 if (fe0->dvb.frontend != NULL)
726 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
727
4c56b04a 728 break;
c9b8b04b
IL		 729 case CX23885_BOARD_DVBWORLD_2005:
730 i2c_bus = &dev->i2c_bus[1];
731
732 fe0->dvb.frontend = dvb_attach(cx24116_attach,
733 &dvbworld_cx24116_config,
734 &i2c_bus->i2c_adap);
735 break;
5a23b076
IL		 736 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
737 i2c_bus = &dev->i2c_bus[0];
738 switch (port->nr) {
739 /* port B */
740 case 1:
741 fe0->dvb.frontend = dvb_attach(stv0900_attach,
742 &netup_stv0900_config,
743 &i2c_bus->i2c_adap, 0);
744 if (fe0->dvb.frontend != NULL) {
745 if (dvb_attach(stv6110_attach,
746 fe0->dvb.frontend,
747 &netup_stv6110_tunerconfig_a,
748 &i2c_bus->i2c_adap)) {
749 if (!dvb_attach(lnbh24_attach,
750 fe0->dvb.frontend,
751 &i2c_bus->i2c_adap,
0cde9b25
IL		 752 LNBH24_PCL,
753 LNBH24_TTX, 0x09))
5a23b076
IL		 754 printk(KERN_ERR
755 "No LNBH24 found!\n");
756
757 }
758 }
759 break;
760 /* port C */
761 case 2:
762 fe0->dvb.frontend = dvb_attach(stv0900_attach,
763 &netup_stv0900_config,
764 &i2c_bus->i2c_adap, 1);
765 if (fe0->dvb.frontend != NULL) {
766 if (dvb_attach(stv6110_attach,
767 fe0->dvb.frontend,
768 &netup_stv6110_tunerconfig_b,
769 &i2c_bus->i2c_adap)) {
770 if (!dvb_attach(lnbh24_attach,
771 fe0->dvb.frontend,
772 &i2c_bus->i2c_adap,
0cde9b25
IL		 773 LNBH24_PCL,
774 LNBH24_TTX, 0x0a))
5a23b076
IL		 775 printk(KERN_ERR
776 "No LNBH24 found!\n");
777
778 }
779 }
780 break;
781 }
782 break;
493b7127
DW		 783 case CX23885_BOARD_MYGICA_X8506:
784 i2c_bus = &dev->i2c_bus[0];
785 i2c_bus2 = &dev->i2c_bus[1];
786 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
787 &mygica_x8506_lgs8gl5_config,
788 &i2c_bus->i2c_adap);
789 if (fe0->dvb.frontend != NULL) {
790 dvb_attach(xc5000_attach,
791 fe0->dvb.frontend,
792 &i2c_bus2->i2c_adap,
793 &mygica_x8506_xc5000_config);
794 }
795 break;
d19770e5 796 default:
9c8ced51
ST		 797 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
798 " isn't supported yet\n",
d19770e5
ST		 799 dev->name);
800 break;
801 }
363c35fc 802 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST		 803 printk(KERN_ERR "%s: frontend initialization failed\n",
804 dev->name);
d19770e5
ST		 805 return -1;
806 }
d7cba043 807 /* define general-purpose callback pointer */
363c35fc 808 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST		 809
810 /* Put the analog decoder in standby to keep it quiet */
7c9fc9d5 811 call_all(dev, tuner, s_standby);
d19770e5 812
363c35fc
ST		 813 if (fe0->dvb.frontend->ops.analog_ops.standby)
814 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 815
d19770e5 816 /* register everything */
5a23b076 817 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
59b1842d 818 &dev->pci->dev, adapter_nr, 0);
363c35fc 819
5a23b076
IL		 820 /* init CI & MAC */
821 switch (dev->board) {
822 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
823 static struct netup_card_info cinfo;
824
825 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
826 memcpy(port->frontends.adapter.proposed_mac,
827 cinfo.port[port->nr - 1].mac, 6);
828 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
829 "%02X:%02X:%02X:%02X:%02X:%02X\n",
830 port->nr,
831 port->frontends.adapter.proposed_mac[0],
832 port->frontends.adapter.proposed_mac[1],
833 port->frontends.adapter.proposed_mac[2],
834 port->frontends.adapter.proposed_mac[3],
835 port->frontends.adapter.proposed_mac[4],
836 port->frontends.adapter.proposed_mac[5]);
837
838 netup_ci_init(port);
839 break;
840 }
841 }
842
843 return ret;
d19770e5
ST		 844}
845
846int cx23885_dvb_register(struct cx23885_tsport *port)
847{
363c35fc
ST		 848
849 struct videobuf_dvb_frontend *fe0;
d19770e5 850 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 851 int err, i;
852
853 /* Here we need to allocate the correct number of frontends,
854 * as reflected in the cards struct. The reality is that currrently
855 * no cx23885 boards support this - yet. But, if we don't modify this
856 * code then the second frontend would never be allocated (later)
857 * and fail with error before the attach in dvb_register().
858 * Without these changes we risk an OOPS later. The changes here
859 * are for safety, and should provide a good foundation for the
860 * future addition of any multi-frontend cx23885 based boards.
861 */
862 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
863 port->num_frontends);
d19770e5 864
eb0c58bb 865 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 866 if (videobuf_dvb_alloc_frontend(
9c8ced51 867 &port->frontends, i) == NULL) {
eb0c58bb
ST		 868 printk(KERN_ERR "%s() failed to alloc\n", __func__);
869 return -ENOMEM;
870 }
871
872 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
873 if (!fe0)
874 err = -EINVAL;
363c35fc 875
eb0c58bb 876 dprintk(1, "%s\n", __func__);
9c8ced51 877 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 878 dev->board,
879 dev->name,
880 dev->pci_bus,
881 dev->pci_slot);
d19770e5 882
eb0c58bb 883 err = -ENODEV;
d19770e5 884
eb0c58bb
ST		 885 /* dvb stuff */
886 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 887 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
888 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
889 &dev->pci->dev, &port->slock,
44a6481d
MK		 890 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
891 sizeof(struct cx23885_buffer), port);
eb0c58bb 892 }
d19770e5
ST		 893 err = dvb_register(port);
894 if (err != 0)
9c8ced51
ST		 895 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
896 __func__, err);
d19770e5 897
d19770e5
ST		 898 return err;
899}
900
901int cx23885_dvb_unregister(struct cx23885_tsport *port)
902{
363c35fc
ST		 903 struct videobuf_dvb_frontend *fe0;
904
eb0c58bb
ST		 905 /* FIXME: in an error condition where the we have
906 * an expected number of frontends (attach problem)
907 * then this might not clean up correctly, if 1
908 * is invalid.
909 * This comment only applies to future boards IF they
910 * implement MFE support.
911 */
92abe9ee 912 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 913 if (fe0->dvb.frontend)
363c35fc 914 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 915
afd96668
HV		 916 switch (port->dev->board) {
917 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
918 netup_ci_exit(port);
919 break;
920 }
5a23b076 921
d19770e5
ST		 922 return 0;
923}
44a6481d 924
Linux kernel - Deliverables
This page took 0.330042 seconds and 5 git commands to generate.