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V4L/DVB (13341): stv0900: big rework to support cut 3.0.
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
ST		 44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076 47#include "stv0900.h"
f867c3f4 48#include "stv0900_reg.h"
5a23b076
IL		 49#include "stv6110.h"
50#include "lnbh24.h"
96318d0c 51#include "cx24116.h"
5a23b076 52#include "cimax2.h"
493b7127 53#include "lgs8gxx.h"
5a23b076
IL		 54#include "netup-eeprom.h"
55#include "netup-init.h"
a5dbf457 56#include "lgdt3305.h"
d19770e5 57
4513fc69 58static unsigned int debug;
d19770e5 59
4513fc69
ST		 60#define dprintk(level, fmt, arg...)\
61 do { if (debug >= level)\
62 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
63 } while (0)
d19770e5
ST		 64
65/* ------------------------------------------------------------------ */
66
3ba71d21
MK		 67static unsigned int alt_tuner;
68module_param(alt_tuner, int, 0644);
69MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
70
78e92006
JG		 71DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
72
3ba71d21
MK		 73/* ------------------------------------------------------------------ */
74
d19770e5
ST		 75static int dvb_buf_setup(struct videobuf_queue *q,
76 unsigned int *count, unsigned int *size)
77{
78 struct cx23885_tsport *port = q->priv_data;
79
80 port->ts_packet_size = 188 * 4;
81 port->ts_packet_count = 32;
82
83 *size = port->ts_packet_size * port->ts_packet_count;
84 *count = 32;
85 return 0;
86}
87
44a6481d
MK		 88static int dvb_buf_prepare(struct videobuf_queue *q,
89 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 90{
91 struct cx23885_tsport *port = q->priv_data;
9c8ced51 92 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 93}
94
95static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
96{
97 struct cx23885_tsport *port = q->priv_data;
9c8ced51 98 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 99}
100
44a6481d
MK		 101static void dvb_buf_release(struct videobuf_queue *q,
102 struct videobuf_buffer *vb)
d19770e5 103{
9c8ced51 104 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 105}
106
107static struct videobuf_queue_ops dvb_qops = {
108 .buf_setup = dvb_buf_setup,
109 .buf_prepare = dvb_buf_prepare,
110 .buf_queue = dvb_buf_queue,
111 .buf_release = dvb_buf_release,
112};
113
86184e06 114static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 115 .demod_address = 0x32 >> 1,
116 .output_mode = S5H1409_SERIAL_OUTPUT,
117 .gpio = S5H1409_GPIO_ON,
2b03238a 118 .qam_if = 44000,
fc959bef 119 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 120 .status_mode = S5H1409_DEMODLOCKING,
121 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 122};
123
b3ea0166
ST		 124static struct tda10048_config hauppauge_hvr1200_config = {
125 .demod_address = 0x10 >> 1,
126 .output_mode = TDA10048_SERIAL_OUTPUT,
127 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 128 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 129 .dtv6_if_freq_khz = TDA10048_IF_3300,
130 .dtv7_if_freq_khz = TDA10048_IF_3800,
131 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 132 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 133};
134
6b926eca
MK		 135static struct tda10048_config hauppauge_hvr1210_config = {
136 .demod_address = 0x10 >> 1,
137 .output_mode = TDA10048_SERIAL_OUTPUT,
138 .fwbulkwritelen = TDA10048_BULKWRITE_200,
139 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 140 .dtv6_if_freq_khz = TDA10048_IF_3300,
141 .dtv7_if_freq_khz = TDA10048_IF_3500,
142 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 143 .clk_freq_khz = TDA10048_CLK_16000,
144};
145
3ba71d21
MK		 146static struct s5h1409_config hauppauge_ezqam_config = {
147 .demod_address = 0x32 >> 1,
148 .output_mode = S5H1409_SERIAL_OUTPUT,
149 .gpio = S5H1409_GPIO_OFF,
150 .qam_if = 4000,
151 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 152 .status_mode = S5H1409_DEMODLOCKING,
153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 154};
155
fc959bef 156static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 157 .demod_address = 0x32 >> 1,
158 .output_mode = S5H1409_SERIAL_OUTPUT,
159 .gpio = S5H1409_GPIO_OFF,
2b03238a 160 .qam_if = 44000,
fe475163 161 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 162 .status_mode = S5H1409_DEMODLOCKING,
163 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 164};
165
07b4a835
MK		 166static struct s5h1409_config hauppauge_hvr1500_config = {
167 .demod_address = 0x32 >> 1,
168 .output_mode = S5H1409_SERIAL_OUTPUT,
169 .gpio = S5H1409_GPIO_OFF,
170 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 171 .status_mode = S5H1409_DEMODLOCKING,
172 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 173};
174
86184e06 175static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 176 0x61
177};
178
9bc37caa
MK		 179static struct lgdt330x_config fusionhdtv_5_express = {
180 .demod_address = 0x0e,
181 .demod_chip = LGDT3303,
182 .serial_mpeg = 0x40,
183};
184
d1987d55
ST		 185static struct s5h1409_config hauppauge_hvr1500q_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_ON,
189 .qam_if = 44000,
190 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 193};
194
335377b7
MK		 195static struct s5h1409_config dvico_s5h1409_config = {
196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_ON,
199 .qam_if = 44000,
200 .inversion = S5H1409_INVERSION_OFF,
201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
203};
204
52b50450
MK		 205static struct s5h1411_config dvico_s5h1411_config = {
206 .output_mode = S5H1411_SERIAL_OUTPUT,
207 .gpio = S5H1411_GPIO_ON,
208 .qam_if = S5H1411_IF_44000,
209 .vsb_if = S5H1411_IF_44000,
210 .inversion = S5H1411_INVERSION_OFF,
211 .status_mode = S5H1411_DEMODLOCKING,
212 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
213};
214
19bc5796
MK		 215static struct s5h1411_config hcw_s5h1411_config = {
216 .output_mode = S5H1411_SERIAL_OUTPUT,
217 .gpio = S5H1411_GPIO_OFF,
218 .vsb_if = S5H1411_IF_44000,
219 .qam_if = S5H1411_IF_4000,
220 .inversion = S5H1411_INVERSION_ON,
221 .status_mode = S5H1411_DEMODLOCKING,
222 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
223};
224
d1987d55 225static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 226 .i2c_address = 0x61,
227 .if_khz = 5380,
d1987d55
ST		 228};
229
335377b7
MK		 230static struct xc5000_config dvico_xc5000_tunerconfig = {
231 .i2c_address = 0x64,
232 .if_khz = 5380,
335377b7
MK		 233};
234
4041f1a5
MK		 235static struct tda829x_config tda829x_no_probe = {
236 .probe_tuner = TDA829X_DONT_PROBE,
237};
238
f21e0d7f 239static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 240 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
241 .if_lvl = 6, .rfagc_top = 0x37 },
242 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
243 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 244};
245
b34cdc36
MK		 246static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
247 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
248 .if_lvl = 1, .rfagc_top = 0x37, },
249 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
250 .if_lvl = 1, .rfagc_top = 0x37, },
251 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
252 .if_lvl = 1, .rfagc_top = 0x37, },
253};
254
f21e0d7f
MK		 255static struct tda18271_config hauppauge_tda18271_config = {
256 .std_map = &hauppauge_tda18271_std_map,
257 .gate = TDA18271_GATE_ANALOG,
04a68baa 258 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 259};
260
b3ea0166 261static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 262 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 263 .gate = TDA18271_GATE_ANALOG,
04a68baa 264 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 265};
266
6b926eca
MK		 267static struct tda18271_config hauppauge_hvr1210_tuner_config = {
268 .gate = TDA18271_GATE_DIGITAL,
04a68baa 269 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 270};
271
247bc540 272static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 273 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
274 .if_lvl = 1, .rfagc_top = 0x58 },
275 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
276 .if_lvl = 1, .rfagc_top = 0x58 },
277};
278
247bc540
MK		 279static struct tda18271_config hauppauge_hvr127x_config = {
280 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 281 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 282};
283
247bc540 284static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 285 .i2c_addr = 0x0e,
286 .mpeg_mode = LGDT3305_MPEG_SERIAL,
287 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
288 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
289 .deny_i2c_rptr = 1,
290 .spectral_inversion = 1,
291 .qam_if_khz = 4000,
292 .vsb_if_khz = 3250,
293};
294
b1721d0d 295static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 296 BAND_VHF | BAND_UHF, /* band_caps */
297
298 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
299 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
300 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
301 * P_agc_nb_est=2, P_agc_write=0
302 */
303 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
304 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
305
306 712, /* inv_gain */
307 21, /* time_stabiliz */
308
309 0, /* alpha_level */
310 118, /* thlock */
311
312 0, /* wbd_inv */
313 2867, /* wbd_ref */
314 0, /* wbd_sel */
315 2, /* wbd_alpha */
316
317 0, /* agc1_max */
318 0, /* agc1_min */
319 39718, /* agc2_max */
320 9930, /* agc2_min */
321 0, /* agc1_pt1 */
322 0, /* agc1_pt2 */
323 0, /* agc1_pt3 */
324 0, /* agc1_slope1 */
325 0, /* agc1_slope2 */
326 0, /* agc2_pt1 */
327 128, /* agc2_pt2 */
328 29, /* agc2_slope1 */
329 29, /* agc2_slope2 */
330
331 17, /* alpha_mant */
332 27, /* alpha_exp */
333 23, /* beta_mant */
334 51, /* beta_exp */
335
336 1, /* perform_agc_softsplit */
337};
338
339/* PLL Configuration for COFDM BW_MHz = 8.000000
340 * With external clock = 30.000000 */
b1721d0d 341static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 342 60000, /* internal */
343 30000, /* sampling */
344 1, /* pll_cfg: prediv */
345 8, /* pll_cfg: ratio */
346 3, /* pll_cfg: range */
347 1, /* pll_cfg: reset */
348 0, /* pll_cfg: bypass */
349 0, /* misc: refdiv */
350 0, /* misc: bypclk_div */
351 1, /* misc: IO_CLK_en_core */
352 1, /* misc: ADClkSrc */
353 0, /* misc: modulo */
354 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
355 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
356 20452225, /* timf */
357 30000000 /* xtal_hz */
358};
359
360static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
361 .output_mpeg2_in_188_bytes = 1,
362 .hostbus_diversity = 1,
363 .tuner_is_baseband = 0,
364 .update_lna = NULL,
365
366 .agc_config_count = 1,
367 .agc = &xc3028_agc_config,
368 .bw = &xc3028_bw_config,
369
370 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
371 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
372 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
373
374 .pwm_freq_div = 0,
375 .agc_control = NULL,
376 .spur_protect = 0,
377
378 .output_mode = OUTMODE_MPEG2_SERIAL,
379};
380
aef2d186
ST		 381static struct zl10353_config dvico_fusionhdtv_xc3028 = {
382 .demod_address = 0x0f,
383 .if2 = 45600,
384 .no_tuner = 1,
d4dc673d 385 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 386};
387
f867c3f4
IL		 388static struct stv0900_reg stv0900_ts_regs[] = {
389 { R0900_TSGENERAL, 0x00 },
390 { R0900_P1_TSSPEED, 0x40 },
391 { R0900_P2_TSSPEED, 0x40 },
392 { R0900_P1_TSCFGM, 0xc0 },
393 { R0900_P2_TSCFGM, 0xc0 },
394 { R0900_P1_TSCFGH, 0xe0 },
395 { R0900_P2_TSCFGH, 0xe0 },
396 { R0900_P1_TSCFGL, 0x20 },
397 { R0900_P2_TSCFGL, 0x20 },
398 { 0xffff, 0xff }, /* terminate */
399};
400
5a23b076
IL		 401static struct stv0900_config netup_stv0900_config = {
402 .demod_address = 0x68,
29372a8d 403 .demod_mode = 1, /* dual */
644c7ef0 404 .xtal = 8000000,
5a23b076
IL		 405 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
406 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 407 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 408 .tun1_maddress = 0,/* 0x60 */
409 .tun2_maddress = 3,/* 0x63 */
410 .tun1_adc = 1,/* 1 Vpp */
411 .tun2_adc = 1,/* 1 Vpp */
412};
413
414static struct stv6110_config netup_stv6110_tunerconfig_a = {
415 .i2c_address = 0x60,
644c7ef0
AO		 416 .mclk = 16000000,
417 .clk_div = 1,
873688cd 418 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 419};
420
421static struct stv6110_config netup_stv6110_tunerconfig_b = {
422 .i2c_address = 0x63,
644c7ef0
AO		 423 .mclk = 16000000,
424 .clk_div = 1,
873688cd 425 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 426};
427
96318d0c
IL		 428static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
429{
430 struct cx23885_tsport *port = fe->dvb->priv;
431 struct cx23885_dev *dev = port->dev;
432
433 if (voltage == SEC_VOLTAGE_18)
434 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
435 else if (voltage == SEC_VOLTAGE_13)
436 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
437 else
438 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
439 return 0;
440}
441
442static struct cx24116_config tbs_cx24116_config = {
443 .demod_address = 0x05,
444};
445
579943f5
IL		 446static struct cx24116_config tevii_cx24116_config = {
447 .demod_address = 0x55,
448};
449
c9b8b04b
IL		 450static struct cx24116_config dvbworld_cx24116_config = {
451 .demod_address = 0x05,
452};
453
493b7127
DW		 454static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
455 .prod = LGS8GXX_PROD_LGS8GL5,
456 .demod_address = 0x19,
457 .serial_ts = 0,
458 .ts_clk_pol = 1,
459 .ts_clk_gated = 1,
460 .if_clk_freq = 30400, /* 30.4 MHz */
461 .if_freq = 5380, /* 5.38 MHz */
462 .if_neg_center = 1,
463 .ext_adc = 0,
464 .adc_signed = 0,
465 .if_neg_edge = 0,
466};
467
468static struct xc5000_config mygica_x8506_xc5000_config = {
469 .i2c_address = 0x61,
470 .if_khz = 5380,
471};
472
f35b9e80
MK		 473static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
474 struct dvb_frontend_parameters *param)
475{
476 struct cx23885_tsport *port = fe->dvb->priv;
477 struct cx23885_dev *dev = port->dev;
478
479 switch (dev->board) {
480 case CX23885_BOARD_HAUPPAUGE_HVR1275:
481 switch (param->u.vsb.modulation) {
482 case VSB_8:
483 cx23885_gpio_clear(dev, GPIO_5);
484 break;
485 case QAM_64:
486 case QAM_256:
487 default:
488 cx23885_gpio_set(dev, GPIO_5);
489 break;
490 }
491 break;
6f0d8c02
DW		 492 case CX23885_BOARD_MYGICA_X8506:
493 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
494 /* Select Digital TV */
495 cx23885_gpio_set(dev, GPIO_0);
496 break;
f35b9e80 497 }
5bdd3962 498 return 0;
f35b9e80
MK		 499}
500
5bdd3962
MK		 501static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
502 unsigned int cmd, void *parg,
503 unsigned int stage)
504{
505 int err = 0;
506
507 switch (stage) {
508 case DVB_FE_IOCTL_PRE:
509
510 switch (cmd) {
511 case FE_SET_FRONTEND:
512 err = cx23885_dvb_set_frontend(fe,
513 (struct dvb_frontend_parameters *) parg);
514 break;
515 }
516 break;
517
518 case DVB_FE_IOCTL_POST:
519 /* no post-ioctl handling required */
520 break;
521 }
522 return err;
523};
524
525
2365b2d3
DW		 526static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
527 .prod = LGS8GXX_PROD_LGS8G75,
528 .demod_address = 0x19,
529 .serial_ts = 0,
530 .ts_clk_pol = 1,
531 .ts_clk_gated = 1,
532 .if_clk_freq = 30400, /* 30.4 MHz */
533 .if_freq = 6500, /* 6.50 MHz */
534 .if_neg_center = 1,
535 .ext_adc = 0,
536 .adc_signed = 1,
537 .adc_vpp = 2, /* 1.6 Vpp */
538 .if_neg_edge = 1,
539};
540
541static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
542 .i2c_address = 0x61,
543 .if_khz = 6500,
544};
545
d19770e5
ST		 546static int dvb_register(struct cx23885_tsport *port)
547{
548 struct cx23885_dev *dev = port->dev;
493b7127 549 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
363c35fc 550 struct videobuf_dvb_frontend *fe0;
5a23b076 551 int ret;
363c35fc 552
f972e0bd 553 /* Get the first frontend */
92abe9ee 554 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 555 if (!fe0)
556 return -EINVAL;
d19770e5
ST		 557
558 /* init struct videobuf_dvb */
363c35fc 559 fe0->dvb.name = dev->name;
d19770e5
ST		 560
561 /* init frontend */
562 switch (dev->board) {
a77743bc 563 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 564 i2c_bus = &dev->i2c_bus[0];
363c35fc 565 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 566 &hauppauge_generic_config,
f139fa71 567 &i2c_bus->i2c_adap);
363c35fc
ST		 568 if (fe0->dvb.frontend != NULL) {
569 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 570 &i2c_bus->i2c_adap,
86184e06 571 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 572 }
573 break;
a5dbf457 574 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 575 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 576 i2c_bus = &dev->i2c_bus[0];
577 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 578 &hauppauge_lgdt3305_config,
a5dbf457
MK		 579 &i2c_bus->i2c_adap);
580 if (fe0->dvb.frontend != NULL) {
581 dvb_attach(tda18271_attach, fe0->dvb.frontend,
582 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 583 &hauppauge_hvr127x_config);
a5dbf457
MK		 584 }
585 break;
19bc5796
MK		 586 case CX23885_BOARD_HAUPPAUGE_HVR1255:
587 i2c_bus = &dev->i2c_bus[0];
588 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
589 &hcw_s5h1411_config,
590 &i2c_bus->i2c_adap);
591 if (fe0->dvb.frontend != NULL) {
592 dvb_attach(tda18271_attach, fe0->dvb.frontend,
593 0x60, &dev->i2c_bus[1].i2c_adap,
594 &hauppauge_tda18271_config);
595 }
596 break;
3ba71d21
MK		 597 case CX23885_BOARD_HAUPPAUGE_HVR1800:
598 i2c_bus = &dev->i2c_bus[0];
92abe9ee 599 switch (alt_tuner) {
3ba71d21 600 case 1:
363c35fc 601 fe0->dvb.frontend =
3ba71d21
MK		 602 dvb_attach(s5h1409_attach,
603 &hauppauge_ezqam_config,
604 &i2c_bus->i2c_adap);
363c35fc
ST		 605 if (fe0->dvb.frontend != NULL) {
606 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 607 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 608 &tda829x_no_probe);
363c35fc 609 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 610 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 611 &hauppauge_tda18271_config);
3ba71d21
MK		 612 }
613 break;
614 case 0:
615 default:
363c35fc 616 fe0->dvb.frontend =
3ba71d21
MK		 617 dvb_attach(s5h1409_attach,
618 &hauppauge_generic_config,
619 &i2c_bus->i2c_adap);
363c35fc
ST		 620 if (fe0->dvb.frontend != NULL)
621 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 622 &i2c_bus->i2c_adap,
623 &hauppauge_generic_tunerconfig, 0);
624 break;
625 }
626 break;
fc959bef 627 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 628 i2c_bus = &dev->i2c_bus[0];
363c35fc 629 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 630 &hauppauge_hvr1800lp_config,
f139fa71 631 &i2c_bus->i2c_adap);
363c35fc
ST		 632 if (fe0->dvb.frontend != NULL) {
633 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 634 &i2c_bus->i2c_adap,
fc959bef
ST		 635 &hauppauge_generic_tunerconfig, 0);
636 }
637 break;
9bc37caa 638 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 639 i2c_bus = &dev->i2c_bus[0];
363c35fc 640 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 641 &fusionhdtv_5_express,
f139fa71 642 &i2c_bus->i2c_adap);
363c35fc
ST		 643 if (fe0->dvb.frontend != NULL) {
644 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 645 &i2c_bus->i2c_adap, 0x61,
646 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 647 }
648 break;
d1987d55
ST		 649 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
650 i2c_bus = &dev->i2c_bus[1];
363c35fc 651 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 652 &hauppauge_hvr1500q_config,
653 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 654 if (fe0->dvb.frontend != NULL)
655 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 656 &i2c_bus->i2c_adap,
657 &hauppauge_hvr1500q_tunerconfig);
d1987d55 658 break;
07b4a835
MK		 659 case CX23885_BOARD_HAUPPAUGE_HVR1500:
660 i2c_bus = &dev->i2c_bus[1];
363c35fc 661 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 662 &hauppauge_hvr1500_config,
663 &dev->i2c_bus[0].i2c_adap);
363c35fc 664 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 665 struct dvb_frontend *fe;
666 struct xc2028_config cfg = {
667 .i2c_adap = &i2c_bus->i2c_adap,
668 .i2c_addr = 0x61,
07b4a835
MK		 669 };
670 static struct xc2028_ctrl ctl = {
ef80bfeb 671 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 672 .max_len = 64,
52c3d29c 673 .demod = XC3028_FE_OREN538,
07b4a835
MK		 674 };
675
676 fe = dvb_attach(xc2028_attach,
363c35fc 677 fe0->dvb.frontend, &cfg);
07b4a835
MK		 678 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
679 fe->ops.tuner_ops.set_config(fe, &ctl);
680 }
681 break;
b3ea0166 682 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 683 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 684 i2c_bus = &dev->i2c_bus[0];
363c35fc 685 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 686 &hauppauge_hvr1200_config,
687 &i2c_bus->i2c_adap);
363c35fc
ST		 688 if (fe0->dvb.frontend != NULL) {
689 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 690 &dev->i2c_bus[1].i2c_adap, 0x42,
691 &tda829x_no_probe);
363c35fc 692 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 693 0x60, &dev->i2c_bus[1].i2c_adap,
694 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 695 }
696 break;
697 case CX23885_BOARD_HAUPPAUGE_HVR1210:
698 i2c_bus = &dev->i2c_bus[0];
699 fe0->dvb.frontend = dvb_attach(tda10048_attach,
700 &hauppauge_hvr1210_config,
701 &i2c_bus->i2c_adap);
702 if (fe0->dvb.frontend != NULL) {
703 dvb_attach(tda18271_attach, fe0->dvb.frontend,
704 0x60, &dev->i2c_bus[1].i2c_adap,
705 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 706 }
707 break;
66762373
ST		 708 case CX23885_BOARD_HAUPPAUGE_HVR1400:
709 i2c_bus = &dev->i2c_bus[0];
363c35fc 710 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 711 &i2c_bus->i2c_adap,
712 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 713 if (fe0->dvb.frontend != NULL) {
66762373
ST		 714 struct dvb_frontend *fe;
715 struct xc2028_config cfg = {
716 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
717 .i2c_addr = 0x64,
66762373
ST		 718 };
719 static struct xc2028_ctrl ctl = {
ef80bfeb 720 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST		 721 .max_len = 64,
722 .demod = 5000,
9c8ced51
ST		 723 /* This is true for all demods with
724 v36 firmware? */
0975fc68 725 .type = XC2028_D2633,
66762373
ST		 726 };
727
728 fe = dvb_attach(xc2028_attach,
363c35fc 729 fe0->dvb.frontend, &cfg);
66762373
ST		 730 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
731 fe->ops.tuner_ops.set_config(fe, &ctl);
732 }
733 break;
335377b7
MK		 734 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
735 i2c_bus = &dev->i2c_bus[port->nr - 1];
736
363c35fc 737 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 738 &dvico_s5h1409_config,
739 &i2c_bus->i2c_adap);
363c35fc
ST		 740 if (fe0->dvb.frontend == NULL)
741 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 742 &dvico_s5h1411_config,
743 &i2c_bus->i2c_adap);
363c35fc
ST		 744 if (fe0->dvb.frontend != NULL)
745 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 746 &i2c_bus->i2c_adap,
747 &dvico_xc5000_tunerconfig);
335377b7 748 break;
aef2d186
ST		 749 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
750 i2c_bus = &dev->i2c_bus[port->nr - 1];
751
363c35fc 752 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 753 &dvico_fusionhdtv_xc3028,
754 &i2c_bus->i2c_adap);
363c35fc 755 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 756 struct dvb_frontend *fe;
757 struct xc2028_config cfg = {
758 .i2c_adap = &i2c_bus->i2c_adap,
759 .i2c_addr = 0x61,
aef2d186
ST		 760 };
761 static struct xc2028_ctrl ctl = {
ef80bfeb 762 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 763 .max_len = 64,
764 .demod = XC3028_FE_ZARLINK456,
765 };
766
363c35fc 767 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 768 &cfg);
769 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
770 fe->ops.tuner_ops.set_config(fe, &ctl);
771 }
772 break;
773 }
4c56b04a 774 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 775 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 776 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 777 i2c_bus = &dev->i2c_bus[0];
778
363c35fc 779 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 780 &dvico_fusionhdtv_xc3028,
781 &i2c_bus->i2c_adap);
363c35fc 782 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 783 struct dvb_frontend *fe;
784 struct xc2028_config cfg = {
785 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
786 .i2c_addr = 0x61,
4c56b04a
ST		 787 };
788 static struct xc2028_ctrl ctl = {
ef80bfeb 789 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 790 .max_len = 64,
791 .demod = XC3028_FE_ZARLINK456,
792 };
793
363c35fc 794 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 795 &cfg);
796 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
797 fe->ops.tuner_ops.set_config(fe, &ctl);
798 }
96318d0c
IL		 799 break;
800 case CX23885_BOARD_TBS_6920:
801 i2c_bus = &dev->i2c_bus[0];
802
803 fe0->dvb.frontend = dvb_attach(cx24116_attach,
804 &tbs_cx24116_config,
805 &i2c_bus->i2c_adap);
806 if (fe0->dvb.frontend != NULL)
807 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
808
579943f5
IL		 809 break;
810 case CX23885_BOARD_TEVII_S470:
811 i2c_bus = &dev->i2c_bus[1];
812
813 fe0->dvb.frontend = dvb_attach(cx24116_attach,
814 &tevii_cx24116_config,
815 &i2c_bus->i2c_adap);
816 if (fe0->dvb.frontend != NULL)
817 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
818
4c56b04a 819 break;
c9b8b04b
IL		 820 case CX23885_BOARD_DVBWORLD_2005:
821 i2c_bus = &dev->i2c_bus[1];
822
823 fe0->dvb.frontend = dvb_attach(cx24116_attach,
824 &dvbworld_cx24116_config,
825 &i2c_bus->i2c_adap);
826 break;
5a23b076
IL		 827 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
828 i2c_bus = &dev->i2c_bus[0];
829 switch (port->nr) {
830 /* port B */
831 case 1:
832 fe0->dvb.frontend = dvb_attach(stv0900_attach,
833 &netup_stv0900_config,
834 &i2c_bus->i2c_adap, 0);
835 if (fe0->dvb.frontend != NULL) {
836 if (dvb_attach(stv6110_attach,
837 fe0->dvb.frontend,
838 &netup_stv6110_tunerconfig_a,
839 &i2c_bus->i2c_adap)) {
840 if (!dvb_attach(lnbh24_attach,
841 fe0->dvb.frontend,
842 &i2c_bus->i2c_adap,
9329fb5b
AO		 843 LNBH24_PCL | LNBH24_TTX,
844 LNBH24_TEN, 0x09))
5a23b076
IL		 845 printk(KERN_ERR
846 "No LNBH24 found!\n");
847
848 }
849 }
850 break;
851 /* port C */
852 case 2:
853 fe0->dvb.frontend = dvb_attach(stv0900_attach,
854 &netup_stv0900_config,
855 &i2c_bus->i2c_adap, 1);
856 if (fe0->dvb.frontend != NULL) {
857 if (dvb_attach(stv6110_attach,
858 fe0->dvb.frontend,
859 &netup_stv6110_tunerconfig_b,
860 &i2c_bus->i2c_adap)) {
861 if (!dvb_attach(lnbh24_attach,
862 fe0->dvb.frontend,
863 &i2c_bus->i2c_adap,
9329fb5b
AO		 864 LNBH24_PCL | LNBH24_TTX,
865 LNBH24_TEN, 0x0a))
5a23b076
IL		 866 printk(KERN_ERR
867 "No LNBH24 found!\n");
868
869 }
870 }
871 break;
872 }
873 break;
493b7127
DW		 874 case CX23885_BOARD_MYGICA_X8506:
875 i2c_bus = &dev->i2c_bus[0];
876 i2c_bus2 = &dev->i2c_bus[1];
877 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
878 &mygica_x8506_lgs8gl5_config,
879 &i2c_bus->i2c_adap);
880 if (fe0->dvb.frontend != NULL) {
881 dvb_attach(xc5000_attach,
882 fe0->dvb.frontend,
883 &i2c_bus2->i2c_adap,
884 &mygica_x8506_xc5000_config);
885 }
886 break;
2365b2d3
DW		 887 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
888 i2c_bus = &dev->i2c_bus[0];
889 i2c_bus2 = &dev->i2c_bus[1];
890 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
891 &magicpro_prohdtve2_lgs8g75_config,
892 &i2c_bus->i2c_adap);
893 if (fe0->dvb.frontend != NULL) {
894 dvb_attach(xc5000_attach,
895 fe0->dvb.frontend,
896 &i2c_bus2->i2c_adap,
897 &magicpro_prohdtve2_xc5000_config);
898 }
899 break;
13697380
ST		 900 case CX23885_BOARD_HAUPPAUGE_HVR1850:
901 i2c_bus = &dev->i2c_bus[0];
902 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
903 &hcw_s5h1411_config,
904 &i2c_bus->i2c_adap);
905 if (fe0->dvb.frontend != NULL)
906 dvb_attach(tda18271_attach, fe0->dvb.frontend,
907 0x60, &dev->i2c_bus[0].i2c_adap,
908 &hauppauge_tda18271_config);
909 break;
910
d19770e5 911 default:
9c8ced51
ST		 912 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
913 " isn't supported yet\n",
d19770e5
ST		 914 dev->name);
915 break;
916 }
363c35fc 917 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST		 918 printk(KERN_ERR "%s: frontend initialization failed\n",
919 dev->name);
d19770e5
ST		 920 return -1;
921 }
d7cba043 922 /* define general-purpose callback pointer */
363c35fc 923 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST		 924
925 /* Put the analog decoder in standby to keep it quiet */
622b828a 926 call_all(dev, core, s_power, 0);
d19770e5 927
363c35fc
ST		 928 if (fe0->dvb.frontend->ops.analog_ops.standby)
929 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 930
d19770e5 931 /* register everything */
5a23b076 932 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
5bdd3962
MK		 933 &dev->pci->dev, adapter_nr, 0,
934 cx23885_dvb_fe_ioctl_override);
363c35fc 935
5a23b076
IL		 936 /* init CI & MAC */
937 switch (dev->board) {
938 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
939 static struct netup_card_info cinfo;
940
941 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
942 memcpy(port->frontends.adapter.proposed_mac,
943 cinfo.port[port->nr - 1].mac, 6);
944 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
945 "%02X:%02X:%02X:%02X:%02X:%02X\n",
946 port->nr,
947 port->frontends.adapter.proposed_mac[0],
948 port->frontends.adapter.proposed_mac[1],
949 port->frontends.adapter.proposed_mac[2],
950 port->frontends.adapter.proposed_mac[3],
951 port->frontends.adapter.proposed_mac[4],
952 port->frontends.adapter.proposed_mac[5]);
953
954 netup_ci_init(port);
955 break;
956 }
957 }
958
959 return ret;
d19770e5
ST		 960}
961
962int cx23885_dvb_register(struct cx23885_tsport *port)
963{
363c35fc
ST		 964
965 struct videobuf_dvb_frontend *fe0;
d19770e5 966 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 967 int err, i;
968
969 /* Here we need to allocate the correct number of frontends,
970 * as reflected in the cards struct. The reality is that currrently
971 * no cx23885 boards support this - yet. But, if we don't modify this
972 * code then the second frontend would never be allocated (later)
973 * and fail with error before the attach in dvb_register().
974 * Without these changes we risk an OOPS later. The changes here
975 * are for safety, and should provide a good foundation for the
976 * future addition of any multi-frontend cx23885 based boards.
977 */
978 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
979 port->num_frontends);
d19770e5 980
eb0c58bb 981 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 982 if (videobuf_dvb_alloc_frontend(
9c8ced51 983 &port->frontends, i) == NULL) {
eb0c58bb
ST		 984 printk(KERN_ERR "%s() failed to alloc\n", __func__);
985 return -ENOMEM;
986 }
987
988 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
989 if (!fe0)
990 err = -EINVAL;
363c35fc 991
eb0c58bb 992 dprintk(1, "%s\n", __func__);
9c8ced51 993 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 994 dev->board,
995 dev->name,
996 dev->pci_bus,
997 dev->pci_slot);
d19770e5 998
eb0c58bb 999 err = -ENODEV;
d19770e5 1000
eb0c58bb
ST		 1001 /* dvb stuff */
1002 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 1003 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1004 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1005 &dev->pci->dev, &port->slock,
44a6481d
MK		 1006 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
1007 sizeof(struct cx23885_buffer), port);
eb0c58bb 1008 }
d19770e5
ST		 1009 err = dvb_register(port);
1010 if (err != 0)
9c8ced51
ST		 1011 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1012 __func__, err);
d19770e5 1013
d19770e5
ST		 1014 return err;
1015}
1016
1017int cx23885_dvb_unregister(struct cx23885_tsport *port)
1018{
363c35fc
ST		 1019 struct videobuf_dvb_frontend *fe0;
1020
eb0c58bb
ST		 1021 /* FIXME: in an error condition where the we have
1022 * an expected number of frontends (attach problem)
1023 * then this might not clean up correctly, if 1
1024 * is invalid.
1025 * This comment only applies to future boards IF they
1026 * implement MFE support.
1027 */
92abe9ee 1028 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 1029 if (fe0->dvb.frontend)
363c35fc 1030 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1031
afd96668
HV		 1032 switch (port->dev->board) {
1033 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1034 netup_ci_exit(port);
1035 break;
1036 }
5a23b076 1037
d19770e5
ST		 1038 return 0;
1039}
44a6481d 1040
Linux kernel - Deliverables
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