[media] cx25840: Add a flag to enable the CX23888 DIF to be enabled or not
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST
1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST
31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
ST
46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
5a23b076
IL
51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
5a23b076 54#include "cimax2.h"
493b7127 55#include "lgs8gxx.h"
5a23b076
IL
56#include "netup-eeprom.h"
57#include "netup-init.h"
a5dbf457 58#include "lgdt3305.h"
ea5697fe 59#include "atbm8830.h"
09ea33e5
IL
60#include "ds3000.h"
61#include "cx23885-f300.h"
78db8547
IL
62#include "altera-ci.h"
63#include "stv0367.h"
d19770e5 64
4513fc69 65static unsigned int debug;
d19770e5 66
4513fc69
ST
67#define dprintk(level, fmt, arg...)\
68 do { if (debug >= level)\
69 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
70 } while (0)
d19770e5
ST
71
72/* ------------------------------------------------------------------ */
73
3ba71d21
MK
74static unsigned int alt_tuner;
75module_param(alt_tuner, int, 0644);
76MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
77
78e92006
JG
78DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
79
3ba71d21
MK
80/* ------------------------------------------------------------------ */
81
d19770e5
ST
82static int dvb_buf_setup(struct videobuf_queue *q,
83 unsigned int *count, unsigned int *size)
84{
85 struct cx23885_tsport *port = q->priv_data;
86
87 port->ts_packet_size = 188 * 4;
88 port->ts_packet_count = 32;
89
90 *size = port->ts_packet_size * port->ts_packet_count;
91 *count = 32;
92 return 0;
93}
94
44a6481d
MK
95static int dvb_buf_prepare(struct videobuf_queue *q,
96 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST
97{
98 struct cx23885_tsport *port = q->priv_data;
9c8ced51 99 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST
100}
101
102static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
103{
104 struct cx23885_tsport *port = q->priv_data;
9c8ced51 105 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST
106}
107
44a6481d
MK
108static void dvb_buf_release(struct videobuf_queue *q,
109 struct videobuf_buffer *vb)
d19770e5 110{
9c8ced51 111 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST
112}
113
a7d44baa
MCC
114static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
115
78db8547
IL
116static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
117{
118 struct videobuf_dvb_frontends *f;
119 struct videobuf_dvb_frontend *fe;
120
121 f = &port->frontends;
122
123 if (f->gate <= 1) /* undefined or fe0 */
124 fe = videobuf_dvb_get_frontend(f, 1);
125 else
126 fe = videobuf_dvb_get_frontend(f, f->gate);
127
128 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
129 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
a7d44baa
MCC
130
131 /*
132 * FIXME: Improve this path to avoid calling the
133 * cx23885_dvb_set_frontend() every time it passes here.
134 */
135 cx23885_dvb_set_frontend(fe->dvb.frontend);
78db8547
IL
136}
137
d19770e5
ST
138static struct videobuf_queue_ops dvb_qops = {
139 .buf_setup = dvb_buf_setup,
140 .buf_prepare = dvb_buf_prepare,
141 .buf_queue = dvb_buf_queue,
142 .buf_release = dvb_buf_release,
143};
144
86184e06 145static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST
146 .demod_address = 0x32 >> 1,
147 .output_mode = S5H1409_SERIAL_OUTPUT,
148 .gpio = S5H1409_GPIO_ON,
2b03238a 149 .qam_if = 44000,
fc959bef 150 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST
151 .status_mode = S5H1409_DEMODLOCKING,
152 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST
153};
154
b3ea0166
ST
155static struct tda10048_config hauppauge_hvr1200_config = {
156 .demod_address = 0x10 >> 1,
157 .output_mode = TDA10048_SERIAL_OUTPUT,
158 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 159 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST
160 .dtv6_if_freq_khz = TDA10048_IF_3300,
161 .dtv7_if_freq_khz = TDA10048_IF_3800,
162 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 163 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST
164};
165
6b926eca
MK
166static struct tda10048_config hauppauge_hvr1210_config = {
167 .demod_address = 0x10 >> 1,
168 .output_mode = TDA10048_SERIAL_OUTPUT,
169 .fwbulkwritelen = TDA10048_BULKWRITE_200,
170 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK
171 .dtv6_if_freq_khz = TDA10048_IF_3300,
172 .dtv7_if_freq_khz = TDA10048_IF_3500,
173 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK
174 .clk_freq_khz = TDA10048_CLK_16000,
175};
176
3ba71d21
MK
177static struct s5h1409_config hauppauge_ezqam_config = {
178 .demod_address = 0x32 >> 1,
179 .output_mode = S5H1409_SERIAL_OUTPUT,
180 .gpio = S5H1409_GPIO_OFF,
181 .qam_if = 4000,
182 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST
183 .status_mode = S5H1409_DEMODLOCKING,
184 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK
185};
186
fc959bef 187static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST
188 .demod_address = 0x32 >> 1,
189 .output_mode = S5H1409_SERIAL_OUTPUT,
190 .gpio = S5H1409_GPIO_OFF,
2b03238a 191 .qam_if = 44000,
fe475163 192 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST
193 .status_mode = S5H1409_DEMODLOCKING,
194 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST
195};
196
07b4a835
MK
197static struct s5h1409_config hauppauge_hvr1500_config = {
198 .demod_address = 0x32 >> 1,
199 .output_mode = S5H1409_SERIAL_OUTPUT,
200 .gpio = S5H1409_GPIO_OFF,
201 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST
202 .status_mode = S5H1409_DEMODLOCKING,
203 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK
204};
205
86184e06 206static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST
207 0x61
208};
209
9bc37caa
MK
210static struct lgdt330x_config fusionhdtv_5_express = {
211 .demod_address = 0x0e,
212 .demod_chip = LGDT3303,
213 .serial_mpeg = 0x40,
214};
215
d1987d55
ST
216static struct s5h1409_config hauppauge_hvr1500q_config = {
217 .demod_address = 0x32 >> 1,
218 .output_mode = S5H1409_SERIAL_OUTPUT,
219 .gpio = S5H1409_GPIO_ON,
220 .qam_if = 44000,
221 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST
222 .status_mode = S5H1409_DEMODLOCKING,
223 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST
224};
225
335377b7
MK
226static struct s5h1409_config dvico_s5h1409_config = {
227 .demod_address = 0x32 >> 1,
228 .output_mode = S5H1409_SERIAL_OUTPUT,
229 .gpio = S5H1409_GPIO_ON,
230 .qam_if = 44000,
231 .inversion = S5H1409_INVERSION_OFF,
232 .status_mode = S5H1409_DEMODLOCKING,
233 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
234};
235
52b50450
MK
236static struct s5h1411_config dvico_s5h1411_config = {
237 .output_mode = S5H1411_SERIAL_OUTPUT,
238 .gpio = S5H1411_GPIO_ON,
239 .qam_if = S5H1411_IF_44000,
240 .vsb_if = S5H1411_IF_44000,
241 .inversion = S5H1411_INVERSION_OFF,
242 .status_mode = S5H1411_DEMODLOCKING,
243 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
244};
245
19bc5796
MK
246static struct s5h1411_config hcw_s5h1411_config = {
247 .output_mode = S5H1411_SERIAL_OUTPUT,
248 .gpio = S5H1411_GPIO_OFF,
249 .vsb_if = S5H1411_IF_44000,
250 .qam_if = S5H1411_IF_4000,
251 .inversion = S5H1411_INVERSION_ON,
252 .status_mode = S5H1411_DEMODLOCKING,
253 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
254};
255
d1987d55 256static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST
257 .i2c_address = 0x61,
258 .if_khz = 5380,
d1987d55
ST
259};
260
335377b7
MK
261static struct xc5000_config dvico_xc5000_tunerconfig = {
262 .i2c_address = 0x64,
263 .if_khz = 5380,
335377b7
MK
264};
265
4041f1a5
MK
266static struct tda829x_config tda829x_no_probe = {
267 .probe_tuner = TDA829X_DONT_PROBE,
268};
269
f21e0d7f 270static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK
271 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
272 .if_lvl = 6, .rfagc_top = 0x37 },
273 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
274 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK
275};
276
b34cdc36
MK
277static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
278 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
279 .if_lvl = 1, .rfagc_top = 0x37, },
280 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
281 .if_lvl = 1, .rfagc_top = 0x37, },
282 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
283 .if_lvl = 1, .rfagc_top = 0x37, },
284};
285
f21e0d7f
MK
286static struct tda18271_config hauppauge_tda18271_config = {
287 .std_map = &hauppauge_tda18271_std_map,
288 .gate = TDA18271_GATE_ANALOG,
04a68baa 289 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK
290};
291
b3ea0166 292static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 293 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 294 .gate = TDA18271_GATE_ANALOG,
04a68baa 295 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST
296};
297
6b926eca
MK
298static struct tda18271_config hauppauge_hvr1210_tuner_config = {
299 .gate = TDA18271_GATE_DIGITAL,
04a68baa 300 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK
301};
302
247bc540 303static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK
304 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
305 .if_lvl = 1, .rfagc_top = 0x58 },
306 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
307 .if_lvl = 1, .rfagc_top = 0x58 },
308};
309
247bc540
MK
310static struct tda18271_config hauppauge_hvr127x_config = {
311 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 312 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK
313};
314
247bc540 315static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK
316 .i2c_addr = 0x0e,
317 .mpeg_mode = LGDT3305_MPEG_SERIAL,
318 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
319 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
320 .deny_i2c_rptr = 1,
321 .spectral_inversion = 1,
322 .qam_if_khz = 4000,
323 .vsb_if_khz = 3250,
324};
325
b1721d0d 326static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST
327 BAND_VHF | BAND_UHF, /* band_caps */
328
329 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
330 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
331 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
332 * P_agc_nb_est=2, P_agc_write=0
333 */
334 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
335 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
336
337 712, /* inv_gain */
338 21, /* time_stabiliz */
339
340 0, /* alpha_level */
341 118, /* thlock */
342
343 0, /* wbd_inv */
344 2867, /* wbd_ref */
345 0, /* wbd_sel */
346 2, /* wbd_alpha */
347
348 0, /* agc1_max */
349 0, /* agc1_min */
350 39718, /* agc2_max */
351 9930, /* agc2_min */
352 0, /* agc1_pt1 */
353 0, /* agc1_pt2 */
354 0, /* agc1_pt3 */
355 0, /* agc1_slope1 */
356 0, /* agc1_slope2 */
357 0, /* agc2_pt1 */
358 128, /* agc2_pt2 */
359 29, /* agc2_slope1 */
360 29, /* agc2_slope2 */
361
362 17, /* alpha_mant */
363 27, /* alpha_exp */
364 23, /* beta_mant */
365 51, /* beta_exp */
366
367 1, /* perform_agc_softsplit */
368};
369
370/* PLL Configuration for COFDM BW_MHz = 8.000000
371 * With external clock = 30.000000 */
b1721d0d 372static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST
373 60000, /* internal */
374 30000, /* sampling */
375 1, /* pll_cfg: prediv */
376 8, /* pll_cfg: ratio */
377 3, /* pll_cfg: range */
378 1, /* pll_cfg: reset */
379 0, /* pll_cfg: bypass */
380 0, /* misc: refdiv */
381 0, /* misc: bypclk_div */
382 1, /* misc: IO_CLK_en_core */
383 1, /* misc: ADClkSrc */
384 0, /* misc: modulo */
385 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
386 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
387 20452225, /* timf */
388 30000000 /* xtal_hz */
389};
390
391static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
392 .output_mpeg2_in_188_bytes = 1,
393 .hostbus_diversity = 1,
394 .tuner_is_baseband = 0,
395 .update_lna = NULL,
396
397 .agc_config_count = 1,
398 .agc = &xc3028_agc_config,
399 .bw = &xc3028_bw_config,
400
401 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
402 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
403 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
404
405 .pwm_freq_div = 0,
406 .agc_control = NULL,
407 .spur_protect = 0,
408
409 .output_mode = OUTMODE_MPEG2_SERIAL,
410};
411
aef2d186
ST
412static struct zl10353_config dvico_fusionhdtv_xc3028 = {
413 .demod_address = 0x0f,
414 .if2 = 45600,
415 .no_tuner = 1,
d4dc673d 416 .disable_i2c_gate_ctrl = 1,
aef2d186
ST
417};
418
f867c3f4
IL
419static struct stv0900_reg stv0900_ts_regs[] = {
420 { R0900_TSGENERAL, 0x00 },
421 { R0900_P1_TSSPEED, 0x40 },
422 { R0900_P2_TSSPEED, 0x40 },
423 { R0900_P1_TSCFGM, 0xc0 },
424 { R0900_P2_TSCFGM, 0xc0 },
425 { R0900_P1_TSCFGH, 0xe0 },
426 { R0900_P2_TSCFGH, 0xe0 },
427 { R0900_P1_TSCFGL, 0x20 },
428 { R0900_P2_TSCFGL, 0x20 },
429 { 0xffff, 0xff }, /* terminate */
430};
431
5a23b076
IL
432static struct stv0900_config netup_stv0900_config = {
433 .demod_address = 0x68,
29372a8d 434 .demod_mode = 1, /* dual */
644c7ef0 435 .xtal = 8000000,
5a23b076
IL
436 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
437 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 438 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL
439 .tun1_maddress = 0,/* 0x60 */
440 .tun2_maddress = 3,/* 0x63 */
441 .tun1_adc = 1,/* 1 Vpp */
442 .tun2_adc = 1,/* 1 Vpp */
443};
444
445static struct stv6110_config netup_stv6110_tunerconfig_a = {
446 .i2c_address = 0x60,
644c7ef0
AO
447 .mclk = 16000000,
448 .clk_div = 1,
873688cd 449 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL
450};
451
452static struct stv6110_config netup_stv6110_tunerconfig_b = {
453 .i2c_address = 0x63,
644c7ef0
AO
454 .mclk = 16000000,
455 .clk_div = 1,
873688cd 456 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL
457};
458
96318d0c 459static struct cx24116_config tbs_cx24116_config = {
09ea33e5 460 .demod_address = 0x55,
96318d0c
IL
461};
462
09ea33e5
IL
463static struct ds3000_config tevii_ds3000_config = {
464 .demod_address = 0x68,
579943f5
IL
465};
466
c9b8b04b
IL
467static struct cx24116_config dvbworld_cx24116_config = {
468 .demod_address = 0x05,
469};
470
493b7127
DW
471static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
472 .prod = LGS8GXX_PROD_LGS8GL5,
473 .demod_address = 0x19,
474 .serial_ts = 0,
475 .ts_clk_pol = 1,
476 .ts_clk_gated = 1,
477 .if_clk_freq = 30400, /* 30.4 MHz */
478 .if_freq = 5380, /* 5.38 MHz */
479 .if_neg_center = 1,
480 .ext_adc = 0,
481 .adc_signed = 0,
482 .if_neg_edge = 0,
483};
484
485static struct xc5000_config mygica_x8506_xc5000_config = {
486 .i2c_address = 0x61,
487 .if_khz = 5380,
488};
489
a7d44baa 490static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 491{
a7d44baa 492 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK
493 struct cx23885_tsport *port = fe->dvb->priv;
494 struct cx23885_dev *dev = port->dev;
495
496 switch (dev->board) {
497 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 498 switch (p->modulation) {
f35b9e80
MK
499 case VSB_8:
500 cx23885_gpio_clear(dev, GPIO_5);
501 break;
502 case QAM_64:
503 case QAM_256:
504 default:
505 cx23885_gpio_set(dev, GPIO_5);
506 break;
507 }
508 break;
6f0d8c02
DW
509 case CX23885_BOARD_MYGICA_X8506:
510 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
511 /* Select Digital TV */
512 cx23885_gpio_set(dev, GPIO_0);
513 break;
f35b9e80 514 }
5bdd3962 515 return 0;
f35b9e80
MK
516}
517
2365b2d3
DW
518static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
519 .prod = LGS8GXX_PROD_LGS8G75,
520 .demod_address = 0x19,
521 .serial_ts = 0,
522 .ts_clk_pol = 1,
523 .ts_clk_gated = 1,
524 .if_clk_freq = 30400, /* 30.4 MHz */
525 .if_freq = 6500, /* 6.50 MHz */
526 .if_neg_center = 1,
527 .ext_adc = 0,
528 .adc_signed = 1,
529 .adc_vpp = 2, /* 1.6 Vpp */
530 .if_neg_edge = 1,
531};
532
533static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
534 .i2c_address = 0x61,
535 .if_khz = 6500,
536};
537
ea5697fe
DW
538static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
539 .prod = ATBM8830_PROD_8830,
540 .demod_address = 0x44,
541 .serial_ts = 0,
542 .ts_sampling_edge = 1,
543 .ts_clk_gated = 0,
544 .osc_clk_freq = 30400, /* in kHz */
545 .if_freq = 0, /* zero IF */
546 .zif_swap_iq = 1,
c245c75c
DW
547 .agc_min = 0x2E,
548 .agc_max = 0xFF,
549 .agc_hold_loop = 0,
ea5697fe
DW
550};
551
552static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
553 .i2c_address = 0x60,
554 .osc_clk = 20
555};
556
557static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
558 .prod = ATBM8830_PROD_8830,
559 .demod_address = 0x44,
560 .serial_ts = 1,
561 .ts_sampling_edge = 1,
562 .ts_clk_gated = 0,
563 .osc_clk_freq = 30400, /* in kHz */
564 .if_freq = 0, /* zero IF */
565 .zif_swap_iq = 1,
c245c75c
DW
566 .agc_min = 0x2E,
567 .agc_max = 0xFF,
568 .agc_hold_loop = 0,
ea5697fe
DW
569};
570
571static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
572 .i2c_address = 0x60,
573 .osc_clk = 20
574};
78db8547
IL
575static struct stv0367_config netup_stv0367_config[] = {
576 {
577 .demod_address = 0x1c,
578 .xtal = 27000000,
579 .if_khz = 4500,
580 .if_iq_mode = 0,
581 .ts_mode = 1,
582 .clk_pol = 0,
583 }, {
584 .demod_address = 0x1d,
585 .xtal = 27000000,
586 .if_khz = 4500,
587 .if_iq_mode = 0,
588 .ts_mode = 1,
589 .clk_pol = 0,
590 },
591};
592
593static struct xc5000_config netup_xc5000_config[] = {
594 {
595 .i2c_address = 0x61,
596 .if_khz = 4500,
597 }, {
598 .i2c_address = 0x64,
599 .if_khz = 4500,
600 },
601};
602
603int netup_altera_fpga_rw(void *device, int flag, int data, int read)
604{
605 struct cx23885_dev *dev = (struct cx23885_dev *)device;
606 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 607 uint32_t mem = 0;
78db8547 608
d164460f 609 mem = cx_read(MC417_RWD);
78db8547
IL
610 if (read)
611 cx_set(MC417_OEN, ALT_DATA);
612 else {
613 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL
614 mem &= ~ALT_DATA;
615 mem |= (data & ALT_DATA);
78db8547
IL
616 }
617
618 if (flag)
d164460f 619 mem |= ALT_AD_RG;
78db8547 620 else
d164460f 621 mem &= ~ALT_AD_RG;
78db8547 622
d164460f 623 mem &= ~ALT_CS;
78db8547 624 if (read)
d164460f 625 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 626 else
d164460f
AO
627 mem = (mem & ~ALT_WR) | ALT_RD;
628
629 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL
630
631 for (;;) {
632 mem = cx_read(MC417_RWD);
633 if ((mem & ALT_RDY) == 0)
634 break;
635 if (time_after(jiffies, timeout))
636 break;
637 udelay(1);
638 }
639
640 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
641 if (read)
642 return mem & ALT_DATA;
643
644 return 0;
645};
ea5697fe 646
d19770e5
ST
647static int dvb_register(struct cx23885_tsport *port)
648{
649 struct cx23885_dev *dev = port->dev;
493b7127 650 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL
651 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
652 int mfe_shared = 0; /* bus not shared by default */
5a23b076 653 int ret;
363c35fc 654
f972e0bd 655 /* Get the first frontend */
92abe9ee 656 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST
657 if (!fe0)
658 return -EINVAL;
d19770e5
ST
659
660 /* init struct videobuf_dvb */
363c35fc 661 fe0->dvb.name = dev->name;
d19770e5 662
78db8547
IL
663 /* multi-frontend gate control is undefined or defaults to fe0 */
664 port->frontends.gate = 0;
665
666 /* Sets the gate control callback to be used by i2c command calls */
667 port->gate_ctrl = cx23885_dvb_gate_ctrl;
668
d19770e5
ST
669 /* init frontend */
670 switch (dev->board) {
a77743bc 671 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 672 i2c_bus = &dev->i2c_bus[0];
363c35fc 673 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 674 &hauppauge_generic_config,
f139fa71 675 &i2c_bus->i2c_adap);
363c35fc
ST
676 if (fe0->dvb.frontend != NULL) {
677 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 678 &i2c_bus->i2c_adap,
86184e06 679 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST
680 }
681 break;
a5dbf457 682 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 683 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK
684 i2c_bus = &dev->i2c_bus[0];
685 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 686 &hauppauge_lgdt3305_config,
a5dbf457
MK
687 &i2c_bus->i2c_adap);
688 if (fe0->dvb.frontend != NULL) {
689 dvb_attach(tda18271_attach, fe0->dvb.frontend,
690 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 691 &hauppauge_hvr127x_config);
a5dbf457
MK
692 }
693 break;
19bc5796
MK
694 case CX23885_BOARD_HAUPPAUGE_HVR1255:
695 i2c_bus = &dev->i2c_bus[0];
696 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
697 &hcw_s5h1411_config,
698 &i2c_bus->i2c_adap);
699 if (fe0->dvb.frontend != NULL) {
700 dvb_attach(tda18271_attach, fe0->dvb.frontend,
701 0x60, &dev->i2c_bus[1].i2c_adap,
702 &hauppauge_tda18271_config);
703 }
704 break;
3ba71d21
MK
705 case CX23885_BOARD_HAUPPAUGE_HVR1800:
706 i2c_bus = &dev->i2c_bus[0];
92abe9ee 707 switch (alt_tuner) {
3ba71d21 708 case 1:
363c35fc 709 fe0->dvb.frontend =
3ba71d21
MK
710 dvb_attach(s5h1409_attach,
711 &hauppauge_ezqam_config,
712 &i2c_bus->i2c_adap);
363c35fc
ST
713 if (fe0->dvb.frontend != NULL) {
714 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 715 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 716 &tda829x_no_probe);
363c35fc 717 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 718 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 719 &hauppauge_tda18271_config);
3ba71d21
MK
720 }
721 break;
722 case 0:
723 default:
363c35fc 724 fe0->dvb.frontend =
3ba71d21
MK
725 dvb_attach(s5h1409_attach,
726 &hauppauge_generic_config,
727 &i2c_bus->i2c_adap);
363c35fc
ST
728 if (fe0->dvb.frontend != NULL)
729 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK
730 &i2c_bus->i2c_adap,
731 &hauppauge_generic_tunerconfig, 0);
732 break;
733 }
734 break;
fc959bef 735 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 736 i2c_bus = &dev->i2c_bus[0];
363c35fc 737 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 738 &hauppauge_hvr1800lp_config,
f139fa71 739 &i2c_bus->i2c_adap);
363c35fc
ST
740 if (fe0->dvb.frontend != NULL) {
741 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 742 &i2c_bus->i2c_adap,
fc959bef
ST
743 &hauppauge_generic_tunerconfig, 0);
744 }
745 break;
9bc37caa 746 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 747 i2c_bus = &dev->i2c_bus[0];
363c35fc 748 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 749 &fusionhdtv_5_express,
f139fa71 750 &i2c_bus->i2c_adap);
363c35fc
ST
751 if (fe0->dvb.frontend != NULL) {
752 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK
753 &i2c_bus->i2c_adap, 0x61,
754 TUNER_LG_TDVS_H06XF);
9bc37caa
MK
755 }
756 break;
d1987d55
ST
757 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
758 i2c_bus = &dev->i2c_bus[1];
363c35fc 759 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST
760 &hauppauge_hvr1500q_config,
761 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST
762 if (fe0->dvb.frontend != NULL)
763 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
764 &i2c_bus->i2c_adap,
765 &hauppauge_hvr1500q_tunerconfig);
d1987d55 766 break;
07b4a835
MK
767 case CX23885_BOARD_HAUPPAUGE_HVR1500:
768 i2c_bus = &dev->i2c_bus[1];
363c35fc 769 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK
770 &hauppauge_hvr1500_config,
771 &dev->i2c_bus[0].i2c_adap);
363c35fc 772 if (fe0->dvb.frontend != NULL) {
07b4a835
MK
773 struct dvb_frontend *fe;
774 struct xc2028_config cfg = {
775 .i2c_adap = &i2c_bus->i2c_adap,
776 .i2c_addr = 0x61,
07b4a835
MK
777 };
778 static struct xc2028_ctrl ctl = {
ef80bfeb 779 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 780 .max_len = 64,
52c3d29c 781 .demod = XC3028_FE_OREN538,
07b4a835
MK
782 };
783
784 fe = dvb_attach(xc2028_attach,
363c35fc 785 fe0->dvb.frontend, &cfg);
07b4a835
MK
786 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
787 fe->ops.tuner_ops.set_config(fe, &ctl);
788 }
789 break;
b3ea0166 790 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 791 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 792 i2c_bus = &dev->i2c_bus[0];
363c35fc 793 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST
794 &hauppauge_hvr1200_config,
795 &i2c_bus->i2c_adap);
363c35fc
ST
796 if (fe0->dvb.frontend != NULL) {
797 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST
798 &dev->i2c_bus[1].i2c_adap, 0x42,
799 &tda829x_no_probe);
363c35fc 800 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST
801 0x60, &dev->i2c_bus[1].i2c_adap,
802 &hauppauge_hvr1200_tuner_config);
6b926eca
MK
803 }
804 break;
805 case CX23885_BOARD_HAUPPAUGE_HVR1210:
806 i2c_bus = &dev->i2c_bus[0];
807 fe0->dvb.frontend = dvb_attach(tda10048_attach,
808 &hauppauge_hvr1210_config,
809 &i2c_bus->i2c_adap);
810 if (fe0->dvb.frontend != NULL) {
811 dvb_attach(tda18271_attach, fe0->dvb.frontend,
812 0x60, &dev->i2c_bus[1].i2c_adap,
813 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST
814 }
815 break;
66762373
ST
816 case CX23885_BOARD_HAUPPAUGE_HVR1400:
817 i2c_bus = &dev->i2c_bus[0];
363c35fc 818 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST
819 &i2c_bus->i2c_adap,
820 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 821 if (fe0->dvb.frontend != NULL) {
66762373
ST
822 struct dvb_frontend *fe;
823 struct xc2028_config cfg = {
824 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
825 .i2c_addr = 0x64,
66762373
ST
826 };
827 static struct xc2028_ctrl ctl = {
ef80bfeb 828 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 829 .max_len = 64,
9bed77ee 830 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST
831 /* This is true for all demods with
832 v36 firmware? */
0975fc68 833 .type = XC2028_D2633,
66762373
ST
834 };
835
836 fe = dvb_attach(xc2028_attach,
363c35fc 837 fe0->dvb.frontend, &cfg);
66762373
ST
838 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
839 fe->ops.tuner_ops.set_config(fe, &ctl);
840 }
841 break;
335377b7
MK
842 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
843 i2c_bus = &dev->i2c_bus[port->nr - 1];
844
363c35fc 845 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK
846 &dvico_s5h1409_config,
847 &i2c_bus->i2c_adap);
363c35fc
ST
848 if (fe0->dvb.frontend == NULL)
849 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK
850 &dvico_s5h1411_config,
851 &i2c_bus->i2c_adap);
363c35fc
ST
852 if (fe0->dvb.frontend != NULL)
853 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
854 &i2c_bus->i2c_adap,
855 &dvico_xc5000_tunerconfig);
335377b7 856 break;
aef2d186
ST
857 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
858 i2c_bus = &dev->i2c_bus[port->nr - 1];
859
363c35fc 860 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST
861 &dvico_fusionhdtv_xc3028,
862 &i2c_bus->i2c_adap);
363c35fc 863 if (fe0->dvb.frontend != NULL) {
aef2d186
ST
864 struct dvb_frontend *fe;
865 struct xc2028_config cfg = {
866 .i2c_adap = &i2c_bus->i2c_adap,
867 .i2c_addr = 0x61,
aef2d186
ST
868 };
869 static struct xc2028_ctrl ctl = {
ef80bfeb 870 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST
871 .max_len = 64,
872 .demod = XC3028_FE_ZARLINK456,
873 };
874
363c35fc 875 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST
876 &cfg);
877 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
878 fe->ops.tuner_ops.set_config(fe, &ctl);
879 }
880 break;
881 }
4c56b04a 882 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 883 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 884 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST
885 i2c_bus = &dev->i2c_bus[0];
886
363c35fc 887 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST
888 &dvico_fusionhdtv_xc3028,
889 &i2c_bus->i2c_adap);
363c35fc 890 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST
891 struct dvb_frontend *fe;
892 struct xc2028_config cfg = {
893 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
894 .i2c_addr = 0x61,
4c56b04a
ST
895 };
896 static struct xc2028_ctrl ctl = {
ef80bfeb 897 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST
898 .max_len = 64,
899 .demod = XC3028_FE_ZARLINK456,
900 };
901
363c35fc 902 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST
903 &cfg);
904 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
905 fe->ops.tuner_ops.set_config(fe, &ctl);
906 }
96318d0c 907 break;
0cf8af57 908 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
909 i2c_bus = &dev->i2c_bus[0];
910
911 fe0->dvb.frontend = dvb_attach(zl10353_attach,
912 &dvico_fusionhdtv_xc3028,
913 &i2c_bus->i2c_adap);
914 if (fe0->dvb.frontend != NULL) {
915 struct dvb_frontend *fe;
916 struct xc4000_config cfg = {
917 .i2c_address = 0x61,
918 .default_pm = 0,
919 .dvb_amplitude = 134,
920 .set_smoothedcvbs = 1,
921 .if_khz = 4560
922 };
923
924 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
925 &dev->i2c_bus[1].i2c_adap, &cfg);
926 }
927 break;
96318d0c 928 case CX23885_BOARD_TBS_6920:
09ea33e5 929 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL
930
931 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL
932 &tbs_cx24116_config,
933 &i2c_bus->i2c_adap);
96318d0c 934 if (fe0->dvb.frontend != NULL)
09ea33e5 935 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 936
579943f5
IL
937 break;
938 case CX23885_BOARD_TEVII_S470:
939 i2c_bus = &dev->i2c_bus[1];
940
09ea33e5
IL
941 fe0->dvb.frontend = dvb_attach(ds3000_attach,
942 &tevii_ds3000_config,
943 &i2c_bus->i2c_adap);
579943f5 944 if (fe0->dvb.frontend != NULL)
09ea33e5 945 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
579943f5 946
4c56b04a 947 break;
c9b8b04b
IL
948 case CX23885_BOARD_DVBWORLD_2005:
949 i2c_bus = &dev->i2c_bus[1];
950
951 fe0->dvb.frontend = dvb_attach(cx24116_attach,
952 &dvbworld_cx24116_config,
953 &i2c_bus->i2c_adap);
954 break;
5a23b076
IL
955 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
956 i2c_bus = &dev->i2c_bus[0];
957 switch (port->nr) {
958 /* port B */
959 case 1:
960 fe0->dvb.frontend = dvb_attach(stv0900_attach,
961 &netup_stv0900_config,
962 &i2c_bus->i2c_adap, 0);
963 if (fe0->dvb.frontend != NULL) {
964 if (dvb_attach(stv6110_attach,
965 fe0->dvb.frontend,
966 &netup_stv6110_tunerconfig_a,
967 &i2c_bus->i2c_adap)) {
968 if (!dvb_attach(lnbh24_attach,
969 fe0->dvb.frontend,
970 &i2c_bus->i2c_adap,
9329fb5b
AO
971 LNBH24_PCL | LNBH24_TTX,
972 LNBH24_TEN, 0x09))
5a23b076
IL
973 printk(KERN_ERR
974 "No LNBH24 found!\n");
975
976 }
977 }
978 break;
979 /* port C */
980 case 2:
981 fe0->dvb.frontend = dvb_attach(stv0900_attach,
982 &netup_stv0900_config,
983 &i2c_bus->i2c_adap, 1);
984 if (fe0->dvb.frontend != NULL) {
985 if (dvb_attach(stv6110_attach,
986 fe0->dvb.frontend,
987 &netup_stv6110_tunerconfig_b,
988 &i2c_bus->i2c_adap)) {
989 if (!dvb_attach(lnbh24_attach,
990 fe0->dvb.frontend,
991 &i2c_bus->i2c_adap,
9329fb5b
AO
992 LNBH24_PCL | LNBH24_TTX,
993 LNBH24_TEN, 0x0a))
5a23b076
IL
994 printk(KERN_ERR
995 "No LNBH24 found!\n");
996
997 }
998 }
999 break;
1000 }
1001 break;
493b7127
DW
1002 case CX23885_BOARD_MYGICA_X8506:
1003 i2c_bus = &dev->i2c_bus[0];
1004 i2c_bus2 = &dev->i2c_bus[1];
1005 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1006 &mygica_x8506_lgs8gl5_config,
1007 &i2c_bus->i2c_adap);
1008 if (fe0->dvb.frontend != NULL) {
1009 dvb_attach(xc5000_attach,
1010 fe0->dvb.frontend,
1011 &i2c_bus2->i2c_adap,
1012 &mygica_x8506_xc5000_config);
1013 }
1014 break;
2365b2d3
DW
1015 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1016 i2c_bus = &dev->i2c_bus[0];
1017 i2c_bus2 = &dev->i2c_bus[1];
1018 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1019 &magicpro_prohdtve2_lgs8g75_config,
1020 &i2c_bus->i2c_adap);
1021 if (fe0->dvb.frontend != NULL) {
1022 dvb_attach(xc5000_attach,
1023 fe0->dvb.frontend,
1024 &i2c_bus2->i2c_adap,
1025 &magicpro_prohdtve2_xc5000_config);
1026 }
1027 break;
13697380 1028 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1029 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST
1030 i2c_bus = &dev->i2c_bus[0];
1031 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1032 &hcw_s5h1411_config,
1033 &i2c_bus->i2c_adap);
1034 if (fe0->dvb.frontend != NULL)
1035 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1036 0x60, &dev->i2c_bus[0].i2c_adap,
1037 &hauppauge_tda18271_config);
1038 break;
ea5697fe
DW
1039 case CX23885_BOARD_MYGICA_X8558PRO:
1040 switch (port->nr) {
1041 /* port B */
1042 case 1:
1043 i2c_bus = &dev->i2c_bus[0];
1044 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1045 &mygica_x8558pro_atbm8830_cfg1,
1046 &i2c_bus->i2c_adap);
1047 if (fe0->dvb.frontend != NULL) {
1048 dvb_attach(max2165_attach,
1049 fe0->dvb.frontend,
1050 &i2c_bus->i2c_adap,
1051 &mygic_x8558pro_max2165_cfg1);
1052 }
1053 break;
1054 /* port C */
1055 case 2:
1056 i2c_bus = &dev->i2c_bus[1];
1057 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1058 &mygica_x8558pro_atbm8830_cfg2,
1059 &i2c_bus->i2c_adap);
1060 if (fe0->dvb.frontend != NULL) {
1061 dvb_attach(max2165_attach,
1062 fe0->dvb.frontend,
1063 &i2c_bus->i2c_adap,
1064 &mygic_x8558pro_max2165_cfg2);
1065 }
1066 break;
1067 }
1068 break;
78db8547
IL
1069 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1070 i2c_bus = &dev->i2c_bus[0];
1071 mfe_shared = 1;/* MFE */
1072 port->frontends.gate = 0;/* not clear for me yet */
1073 /* ports B, C */
1074 /* MFE frontend 1 DVB-T */
1075 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1076 &netup_stv0367_config[port->nr - 1],
1077 &i2c_bus->i2c_adap);
4174ebf5 1078 if (fe0->dvb.frontend != NULL) {
78db8547
IL
1079 if (NULL == dvb_attach(xc5000_attach,
1080 fe0->dvb.frontend,
1081 &i2c_bus->i2c_adap,
1082 &netup_xc5000_config[port->nr - 1]))
1083 goto frontend_detach;
4174ebf5
AO
1084 /* load xc5000 firmware */
1085 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1086 }
78db8547
IL
1087 /* MFE frontend 2 */
1088 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1089 if (fe1 == NULL)
1090 goto frontend_detach;
1091 /* DVB-C init */
1092 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1093 &netup_stv0367_config[port->nr - 1],
1094 &i2c_bus->i2c_adap);
1095 if (fe1->dvb.frontend != NULL) {
1096 fe1->dvb.frontend->id = 1;
1097 if (NULL == dvb_attach(xc5000_attach,
1098 fe1->dvb.frontend,
1099 &i2c_bus->i2c_adap,
1100 &netup_xc5000_config[port->nr - 1]))
1101 goto frontend_detach;
1102 }
1103 break;
d19770e5 1104 default:
9c8ced51
ST
1105 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1106 " isn't supported yet\n",
d19770e5
ST
1107 dev->name);
1108 break;
1109 }
78db8547
IL
1110
1111 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1112 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL
1113 dev->name);
1114 goto frontend_detach;
d19770e5 1115 }
78db8547 1116
d7cba043 1117 /* define general-purpose callback pointer */
363c35fc 1118 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL
1119 if (fe1)
1120 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1121#if 0
1122 /* Ensure all frontends negotiate bus access */
1123 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1124 if (fe1)
1125 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1126#endif
d19770e5
ST
1127
1128 /* Put the analog decoder in standby to keep it quiet */
622b828a 1129 call_all(dev, core, s_power, 0);
d19770e5 1130
363c35fc
ST
1131 if (fe0->dvb.frontend->ops.analog_ops.standby)
1132 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1133
d19770e5 1134 /* register everything */
5a23b076 1135 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
78db8547 1136 &dev->pci->dev, adapter_nr, mfe_shared,
a7d44baa 1137 NULL);
bee30192 1138 if (ret)
78db8547 1139 goto frontend_detach;
363c35fc 1140
5a23b076
IL
1141 /* init CI & MAC */
1142 switch (dev->board) {
1143 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1144 static struct netup_card_info cinfo;
1145
1146 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1147 memcpy(port->frontends.adapter.proposed_mac,
1148 cinfo.port[port->nr - 1].mac, 6);
be395157 1149 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1150 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL
1151
1152 netup_ci_init(port);
1153 break;
1154 }
78db8547
IL
1155 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1156 struct altera_ci_config netup_ci_cfg = {
1157 .dev = dev,/* magic number to identify*/
1158 .adapter = &port->frontends.adapter,/* for CI */
1159 .demux = &fe0->dvb.demux,/* for hw pid filter */
1160 .fpga_rw = netup_altera_fpga_rw,
1161 };
1162
1163 altera_ci_init(&netup_ci_cfg, port->nr);
1164 break;
1165 }
16bfdaa4
PG
1166 case CX23885_BOARD_TEVII_S470: {
1167 u8 eeprom[256]; /* 24C02 i2c eeprom */
1168
1169 if (port->nr != 1)
1170 break;
1171
1172 /* Read entire EEPROM */
1173 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1174 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1175 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG
1176 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1177 break;
1178 }
5a23b076
IL
1179 }
1180
1181 return ret;
78db8547
IL
1182
1183frontend_detach:
1184 port->gate_ctrl = NULL;
1185 videobuf_dvb_dealloc_frontends(&port->frontends);
1186 return -EINVAL;
d19770e5
ST
1187}
1188
1189int cx23885_dvb_register(struct cx23885_tsport *port)
1190{
363c35fc
ST
1191
1192 struct videobuf_dvb_frontend *fe0;
d19770e5 1193 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST
1194 int err, i;
1195
1196 /* Here we need to allocate the correct number of frontends,
af901ca1 1197 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST
1198 * no cx23885 boards support this - yet. But, if we don't modify this
1199 * code then the second frontend would never be allocated (later)
1200 * and fail with error before the attach in dvb_register().
1201 * Without these changes we risk an OOPS later. The changes here
1202 * are for safety, and should provide a good foundation for the
1203 * future addition of any multi-frontend cx23885 based boards.
1204 */
1205 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1206 port->num_frontends);
d19770e5 1207
eb0c58bb 1208 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1209 if (videobuf_dvb_alloc_frontend(
9c8ced51 1210 &port->frontends, i) == NULL) {
eb0c58bb
ST
1211 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1212 return -ENOMEM;
1213 }
1214
1215 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1216 if (!fe0)
1217 err = -EINVAL;
363c35fc 1218
eb0c58bb 1219 dprintk(1, "%s\n", __func__);
9c8ced51 1220 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST
1221 dev->board,
1222 dev->name,
1223 dev->pci_bus,
1224 dev->pci_slot);
d19770e5 1225
eb0c58bb 1226 err = -ENODEV;
d19770e5 1227
eb0c58bb
ST
1228 /* dvb stuff */
1229 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST
1230 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1231 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1232 &dev->pci->dev, &port->slock,
44a6481d 1233 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1234 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1235 }
d19770e5
ST
1236 err = dvb_register(port);
1237 if (err != 0)
9c8ced51
ST
1238 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1239 __func__, err);
d19770e5 1240
d19770e5
ST
1241 return err;
1242}
1243
1244int cx23885_dvb_unregister(struct cx23885_tsport *port)
1245{
363c35fc
ST
1246 struct videobuf_dvb_frontend *fe0;
1247
eb0c58bb
ST
1248 /* FIXME: in an error condition where the we have
1249 * an expected number of frontends (attach problem)
1250 * then this might not clean up correctly, if 1
1251 * is invalid.
1252 * This comment only applies to future boards IF they
1253 * implement MFE support.
1254 */
92abe9ee 1255 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1256 if (fe0 && fe0->dvb.frontend)
363c35fc 1257 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1258
afd96668
HV
1259 switch (port->dev->board) {
1260 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1261 netup_ci_exit(port);
1262 break;
78db8547
IL
1263 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1264 altera_ci_release(port->dev, port->nr);
1265 break;
afd96668 1266 }
5a23b076 1267
78db8547
IL
1268 port->gate_ctrl = NULL;
1269
d19770e5
ST
1270 return 0;
1271}
44a6481d 1272
This page took 0.614571 seconds and 5 git commands to generate.