Commit | Line | Data |
---|---|---|
d19770e5 ST |
1 | /* |
2 | * Driver for the Conexant CX23885 PCIe bridge | |
3 | * | |
6d897616 | 4 | * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> |
d19770e5 ST |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/fs.h> | |
26 | #include <linux/kthread.h> | |
27 | #include <linux/file.h> | |
28 | #include <linux/suspend.h> | |
29 | ||
30 | #include "cx23885.h" | |
d19770e5 ST |
31 | #include <media/v4l2-common.h> |
32 | ||
5a23b076 | 33 | #include "dvb_ca_en50221.h" |
d19770e5 | 34 | #include "s5h1409.h" |
52b50450 | 35 | #include "s5h1411.h" |
d19770e5 | 36 | #include "mt2131.h" |
3ba71d21 | 37 | #include "tda8290.h" |
4041f1a5 | 38 | #include "tda18271.h" |
9bc37caa | 39 | #include "lgdt330x.h" |
0cf8af57 | 40 | #include "xc4000.h" |
d1987d55 | 41 | #include "xc5000.h" |
ea5697fe | 42 | #include "max2165.h" |
b3ea0166 | 43 | #include "tda10048.h" |
07b4a835 | 44 | #include "tuner-xc2028.h" |
827855d3 | 45 | #include "tuner-simple.h" |
66762373 ST |
46 | #include "dib7000p.h" |
47 | #include "dibx000_common.h" | |
aef2d186 | 48 | #include "zl10353.h" |
5a23b076 | 49 | #include "stv0900.h" |
f867c3f4 | 50 | #include "stv0900_reg.h" |
5a23b076 IL |
51 | #include "stv6110.h" |
52 | #include "lnbh24.h" | |
96318d0c | 53 | #include "cx24116.h" |
5a23b076 | 54 | #include "cimax2.h" |
493b7127 | 55 | #include "lgs8gxx.h" |
5a23b076 IL |
56 | #include "netup-eeprom.h" |
57 | #include "netup-init.h" | |
a5dbf457 | 58 | #include "lgdt3305.h" |
ea5697fe | 59 | #include "atbm8830.h" |
09ea33e5 IL |
60 | #include "ds3000.h" |
61 | #include "cx23885-f300.h" | |
78db8547 IL |
62 | #include "altera-ci.h" |
63 | #include "stv0367.h" | |
d19770e5 | 64 | |
4513fc69 | 65 | static unsigned int debug; |
d19770e5 | 66 | |
4513fc69 ST |
67 | #define dprintk(level, fmt, arg...)\ |
68 | do { if (debug >= level)\ | |
69 | printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ | |
70 | } while (0) | |
d19770e5 ST |
71 | |
72 | /* ------------------------------------------------------------------ */ | |
73 | ||
3ba71d21 MK |
74 | static unsigned int alt_tuner; |
75 | module_param(alt_tuner, int, 0644); | |
76 | MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration"); | |
77 | ||
78e92006 JG |
78 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
79 | ||
3ba71d21 MK |
80 | /* ------------------------------------------------------------------ */ |
81 | ||
d19770e5 ST |
82 | static int dvb_buf_setup(struct videobuf_queue *q, |
83 | unsigned int *count, unsigned int *size) | |
84 | { | |
85 | struct cx23885_tsport *port = q->priv_data; | |
86 | ||
87 | port->ts_packet_size = 188 * 4; | |
88 | port->ts_packet_count = 32; | |
89 | ||
90 | *size = port->ts_packet_size * port->ts_packet_count; | |
91 | *count = 32; | |
92 | return 0; | |
93 | } | |
94 | ||
44a6481d MK |
95 | static int dvb_buf_prepare(struct videobuf_queue *q, |
96 | struct videobuf_buffer *vb, enum v4l2_field field) | |
d19770e5 ST |
97 | { |
98 | struct cx23885_tsport *port = q->priv_data; | |
9c8ced51 | 99 | return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field); |
d19770e5 ST |
100 | } |
101 | ||
102 | static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
103 | { | |
104 | struct cx23885_tsport *port = q->priv_data; | |
9c8ced51 | 105 | cx23885_buf_queue(port, (struct cx23885_buffer *)vb); |
d19770e5 ST |
106 | } |
107 | ||
44a6481d MK |
108 | static void dvb_buf_release(struct videobuf_queue *q, |
109 | struct videobuf_buffer *vb) | |
d19770e5 | 110 | { |
9c8ced51 | 111 | cx23885_free_buffer(q, (struct cx23885_buffer *)vb); |
d19770e5 ST |
112 | } |
113 | ||
78db8547 IL |
114 | static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open) |
115 | { | |
116 | struct videobuf_dvb_frontends *f; | |
117 | struct videobuf_dvb_frontend *fe; | |
118 | ||
119 | f = &port->frontends; | |
120 | ||
121 | if (f->gate <= 1) /* undefined or fe0 */ | |
122 | fe = videobuf_dvb_get_frontend(f, 1); | |
123 | else | |
124 | fe = videobuf_dvb_get_frontend(f, f->gate); | |
125 | ||
126 | if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl) | |
127 | fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open); | |
128 | } | |
129 | ||
d19770e5 ST |
130 | static struct videobuf_queue_ops dvb_qops = { |
131 | .buf_setup = dvb_buf_setup, | |
132 | .buf_prepare = dvb_buf_prepare, | |
133 | .buf_queue = dvb_buf_queue, | |
134 | .buf_release = dvb_buf_release, | |
135 | }; | |
136 | ||
86184e06 | 137 | static struct s5h1409_config hauppauge_generic_config = { |
fc959bef ST |
138 | .demod_address = 0x32 >> 1, |
139 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
140 | .gpio = S5H1409_GPIO_ON, | |
2b03238a | 141 | .qam_if = 44000, |
fc959bef | 142 | .inversion = S5H1409_INVERSION_OFF, |
dfc1c08a ST |
143 | .status_mode = S5H1409_DEMODLOCKING, |
144 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
fc959bef ST |
145 | }; |
146 | ||
b3ea0166 ST |
147 | static struct tda10048_config hauppauge_hvr1200_config = { |
148 | .demod_address = 0x10 >> 1, | |
149 | .output_mode = TDA10048_SERIAL_OUTPUT, | |
150 | .fwbulkwritelen = TDA10048_BULKWRITE_200, | |
484d9e05 | 151 | .inversion = TDA10048_INVERSION_ON, |
8816bef5 ST |
152 | .dtv6_if_freq_khz = TDA10048_IF_3300, |
153 | .dtv7_if_freq_khz = TDA10048_IF_3800, | |
154 | .dtv8_if_freq_khz = TDA10048_IF_4300, | |
484d9e05 | 155 | .clk_freq_khz = TDA10048_CLK_16000, |
b3ea0166 ST |
156 | }; |
157 | ||
6b926eca MK |
158 | static struct tda10048_config hauppauge_hvr1210_config = { |
159 | .demod_address = 0x10 >> 1, | |
160 | .output_mode = TDA10048_SERIAL_OUTPUT, | |
161 | .fwbulkwritelen = TDA10048_BULKWRITE_200, | |
162 | .inversion = TDA10048_INVERSION_ON, | |
c27586e4 MK |
163 | .dtv6_if_freq_khz = TDA10048_IF_3300, |
164 | .dtv7_if_freq_khz = TDA10048_IF_3500, | |
165 | .dtv8_if_freq_khz = TDA10048_IF_4000, | |
6b926eca MK |
166 | .clk_freq_khz = TDA10048_CLK_16000, |
167 | }; | |
168 | ||
3ba71d21 MK |
169 | static struct s5h1409_config hauppauge_ezqam_config = { |
170 | .demod_address = 0x32 >> 1, | |
171 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
172 | .gpio = S5H1409_GPIO_OFF, | |
173 | .qam_if = 4000, | |
174 | .inversion = S5H1409_INVERSION_ON, | |
dfc1c08a ST |
175 | .status_mode = S5H1409_DEMODLOCKING, |
176 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
3ba71d21 MK |
177 | }; |
178 | ||
fc959bef | 179 | static struct s5h1409_config hauppauge_hvr1800lp_config = { |
d19770e5 ST |
180 | .demod_address = 0x32 >> 1, |
181 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
182 | .gpio = S5H1409_GPIO_OFF, | |
2b03238a | 183 | .qam_if = 44000, |
fe475163 | 184 | .inversion = S5H1409_INVERSION_OFF, |
dfc1c08a ST |
185 | .status_mode = S5H1409_DEMODLOCKING, |
186 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
d19770e5 ST |
187 | }; |
188 | ||
07b4a835 MK |
189 | static struct s5h1409_config hauppauge_hvr1500_config = { |
190 | .demod_address = 0x32 >> 1, | |
191 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
192 | .gpio = S5H1409_GPIO_OFF, | |
193 | .inversion = S5H1409_INVERSION_OFF, | |
dfc1c08a ST |
194 | .status_mode = S5H1409_DEMODLOCKING, |
195 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
07b4a835 MK |
196 | }; |
197 | ||
86184e06 | 198 | static struct mt2131_config hauppauge_generic_tunerconfig = { |
a77743bc ST |
199 | 0x61 |
200 | }; | |
201 | ||
9bc37caa MK |
202 | static struct lgdt330x_config fusionhdtv_5_express = { |
203 | .demod_address = 0x0e, | |
204 | .demod_chip = LGDT3303, | |
205 | .serial_mpeg = 0x40, | |
206 | }; | |
207 | ||
d1987d55 ST |
208 | static struct s5h1409_config hauppauge_hvr1500q_config = { |
209 | .demod_address = 0x32 >> 1, | |
210 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
211 | .gpio = S5H1409_GPIO_ON, | |
212 | .qam_if = 44000, | |
213 | .inversion = S5H1409_INVERSION_OFF, | |
dfc1c08a ST |
214 | .status_mode = S5H1409_DEMODLOCKING, |
215 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
d1987d55 ST |
216 | }; |
217 | ||
335377b7 MK |
218 | static struct s5h1409_config dvico_s5h1409_config = { |
219 | .demod_address = 0x32 >> 1, | |
220 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
221 | .gpio = S5H1409_GPIO_ON, | |
222 | .qam_if = 44000, | |
223 | .inversion = S5H1409_INVERSION_OFF, | |
224 | .status_mode = S5H1409_DEMODLOCKING, | |
225 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
226 | }; | |
227 | ||
52b50450 MK |
228 | static struct s5h1411_config dvico_s5h1411_config = { |
229 | .output_mode = S5H1411_SERIAL_OUTPUT, | |
230 | .gpio = S5H1411_GPIO_ON, | |
231 | .qam_if = S5H1411_IF_44000, | |
232 | .vsb_if = S5H1411_IF_44000, | |
233 | .inversion = S5H1411_INVERSION_OFF, | |
234 | .status_mode = S5H1411_DEMODLOCKING, | |
235 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
236 | }; | |
237 | ||
19bc5796 MK |
238 | static struct s5h1411_config hcw_s5h1411_config = { |
239 | .output_mode = S5H1411_SERIAL_OUTPUT, | |
240 | .gpio = S5H1411_GPIO_OFF, | |
241 | .vsb_if = S5H1411_IF_44000, | |
242 | .qam_if = S5H1411_IF_4000, | |
243 | .inversion = S5H1411_INVERSION_ON, | |
244 | .status_mode = S5H1411_DEMODLOCKING, | |
245 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
246 | }; | |
247 | ||
d1987d55 | 248 | static struct xc5000_config hauppauge_hvr1500q_tunerconfig = { |
e12671cf ST |
249 | .i2c_address = 0x61, |
250 | .if_khz = 5380, | |
d1987d55 ST |
251 | }; |
252 | ||
335377b7 MK |
253 | static struct xc5000_config dvico_xc5000_tunerconfig = { |
254 | .i2c_address = 0x64, | |
255 | .if_khz = 5380, | |
335377b7 MK |
256 | }; |
257 | ||
4041f1a5 MK |
258 | static struct tda829x_config tda829x_no_probe = { |
259 | .probe_tuner = TDA829X_DONT_PROBE, | |
260 | }; | |
261 | ||
f21e0d7f | 262 | static struct tda18271_std_map hauppauge_tda18271_std_map = { |
c0dc0c11 MK |
263 | .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, |
264 | .if_lvl = 6, .rfagc_top = 0x37 }, | |
265 | .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, | |
266 | .if_lvl = 6, .rfagc_top = 0x37 }, | |
f21e0d7f MK |
267 | }; |
268 | ||
b34cdc36 MK |
269 | static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = { |
270 | .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4, | |
271 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
272 | .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5, | |
273 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
274 | .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6, | |
275 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
276 | }; | |
277 | ||
f21e0d7f MK |
278 | static struct tda18271_config hauppauge_tda18271_config = { |
279 | .std_map = &hauppauge_tda18271_std_map, | |
280 | .gate = TDA18271_GATE_ANALOG, | |
04a68baa | 281 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
f21e0d7f MK |
282 | }; |
283 | ||
b3ea0166 | 284 | static struct tda18271_config hauppauge_hvr1200_tuner_config = { |
b34cdc36 | 285 | .std_map = &hauppauge_hvr1200_tda18271_std_map, |
b3ea0166 | 286 | .gate = TDA18271_GATE_ANALOG, |
04a68baa | 287 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
b3ea0166 ST |
288 | }; |
289 | ||
6b926eca MK |
290 | static struct tda18271_config hauppauge_hvr1210_tuner_config = { |
291 | .gate = TDA18271_GATE_DIGITAL, | |
04a68baa | 292 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
6b926eca MK |
293 | }; |
294 | ||
247bc540 | 295 | static struct tda18271_std_map hauppauge_hvr127x_std_map = { |
a5dbf457 MK |
296 | .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4, |
297 | .if_lvl = 1, .rfagc_top = 0x58 }, | |
298 | .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5, | |
299 | .if_lvl = 1, .rfagc_top = 0x58 }, | |
300 | }; | |
301 | ||
247bc540 MK |
302 | static struct tda18271_config hauppauge_hvr127x_config = { |
303 | .std_map = &hauppauge_hvr127x_std_map, | |
04a68baa | 304 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
a5dbf457 MK |
305 | }; |
306 | ||
247bc540 | 307 | static struct lgdt3305_config hauppauge_lgdt3305_config = { |
a5dbf457 MK |
308 | .i2c_addr = 0x0e, |
309 | .mpeg_mode = LGDT3305_MPEG_SERIAL, | |
310 | .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, | |
311 | .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, | |
312 | .deny_i2c_rptr = 1, | |
313 | .spectral_inversion = 1, | |
314 | .qam_if_khz = 4000, | |
315 | .vsb_if_khz = 3250, | |
316 | }; | |
317 | ||
b1721d0d | 318 | static struct dibx000_agc_config xc3028_agc_config = { |
66762373 ST |
319 | BAND_VHF | BAND_UHF, /* band_caps */ |
320 | ||
321 | /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, | |
322 | * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, | |
323 | * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, | |
324 | * P_agc_nb_est=2, P_agc_write=0 | |
325 | */ | |
326 | (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | | |
327 | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */ | |
328 | ||
329 | 712, /* inv_gain */ | |
330 | 21, /* time_stabiliz */ | |
331 | ||
332 | 0, /* alpha_level */ | |
333 | 118, /* thlock */ | |
334 | ||
335 | 0, /* wbd_inv */ | |
336 | 2867, /* wbd_ref */ | |
337 | 0, /* wbd_sel */ | |
338 | 2, /* wbd_alpha */ | |
339 | ||
340 | 0, /* agc1_max */ | |
341 | 0, /* agc1_min */ | |
342 | 39718, /* agc2_max */ | |
343 | 9930, /* agc2_min */ | |
344 | 0, /* agc1_pt1 */ | |
345 | 0, /* agc1_pt2 */ | |
346 | 0, /* agc1_pt3 */ | |
347 | 0, /* agc1_slope1 */ | |
348 | 0, /* agc1_slope2 */ | |
349 | 0, /* agc2_pt1 */ | |
350 | 128, /* agc2_pt2 */ | |
351 | 29, /* agc2_slope1 */ | |
352 | 29, /* agc2_slope2 */ | |
353 | ||
354 | 17, /* alpha_mant */ | |
355 | 27, /* alpha_exp */ | |
356 | 23, /* beta_mant */ | |
357 | 51, /* beta_exp */ | |
358 | ||
359 | 1, /* perform_agc_softsplit */ | |
360 | }; | |
361 | ||
362 | /* PLL Configuration for COFDM BW_MHz = 8.000000 | |
363 | * With external clock = 30.000000 */ | |
b1721d0d | 364 | static struct dibx000_bandwidth_config xc3028_bw_config = { |
66762373 ST |
365 | 60000, /* internal */ |
366 | 30000, /* sampling */ | |
367 | 1, /* pll_cfg: prediv */ | |
368 | 8, /* pll_cfg: ratio */ | |
369 | 3, /* pll_cfg: range */ | |
370 | 1, /* pll_cfg: reset */ | |
371 | 0, /* pll_cfg: bypass */ | |
372 | 0, /* misc: refdiv */ | |
373 | 0, /* misc: bypclk_div */ | |
374 | 1, /* misc: IO_CLK_en_core */ | |
375 | 1, /* misc: ADClkSrc */ | |
376 | 0, /* misc: modulo */ | |
377 | (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */ | |
378 | (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */ | |
379 | 20452225, /* timf */ | |
380 | 30000000 /* xtal_hz */ | |
381 | }; | |
382 | ||
383 | static struct dib7000p_config hauppauge_hvr1400_dib7000_config = { | |
384 | .output_mpeg2_in_188_bytes = 1, | |
385 | .hostbus_diversity = 1, | |
386 | .tuner_is_baseband = 0, | |
387 | .update_lna = NULL, | |
388 | ||
389 | .agc_config_count = 1, | |
390 | .agc = &xc3028_agc_config, | |
391 | .bw = &xc3028_bw_config, | |
392 | ||
393 | .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS, | |
394 | .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES, | |
395 | .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS, | |
396 | ||
397 | .pwm_freq_div = 0, | |
398 | .agc_control = NULL, | |
399 | .spur_protect = 0, | |
400 | ||
401 | .output_mode = OUTMODE_MPEG2_SERIAL, | |
402 | }; | |
403 | ||
aef2d186 ST |
404 | static struct zl10353_config dvico_fusionhdtv_xc3028 = { |
405 | .demod_address = 0x0f, | |
406 | .if2 = 45600, | |
407 | .no_tuner = 1, | |
d4dc673d | 408 | .disable_i2c_gate_ctrl = 1, |
aef2d186 ST |
409 | }; |
410 | ||
f867c3f4 IL |
411 | static struct stv0900_reg stv0900_ts_regs[] = { |
412 | { R0900_TSGENERAL, 0x00 }, | |
413 | { R0900_P1_TSSPEED, 0x40 }, | |
414 | { R0900_P2_TSSPEED, 0x40 }, | |
415 | { R0900_P1_TSCFGM, 0xc0 }, | |
416 | { R0900_P2_TSCFGM, 0xc0 }, | |
417 | { R0900_P1_TSCFGH, 0xe0 }, | |
418 | { R0900_P2_TSCFGH, 0xe0 }, | |
419 | { R0900_P1_TSCFGL, 0x20 }, | |
420 | { R0900_P2_TSCFGL, 0x20 }, | |
421 | { 0xffff, 0xff }, /* terminate */ | |
422 | }; | |
423 | ||
5a23b076 IL |
424 | static struct stv0900_config netup_stv0900_config = { |
425 | .demod_address = 0x68, | |
29372a8d | 426 | .demod_mode = 1, /* dual */ |
644c7ef0 | 427 | .xtal = 8000000, |
5a23b076 IL |
428 | .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */ |
429 | .diseqc_mode = 2,/* 2/3 PWM */ | |
f867c3f4 | 430 | .ts_config_regs = stv0900_ts_regs, |
5a23b076 IL |
431 | .tun1_maddress = 0,/* 0x60 */ |
432 | .tun2_maddress = 3,/* 0x63 */ | |
433 | .tun1_adc = 1,/* 1 Vpp */ | |
434 | .tun2_adc = 1,/* 1 Vpp */ | |
435 | }; | |
436 | ||
437 | static struct stv6110_config netup_stv6110_tunerconfig_a = { | |
438 | .i2c_address = 0x60, | |
644c7ef0 AO |
439 | .mclk = 16000000, |
440 | .clk_div = 1, | |
873688cd | 441 | .gain = 8, /* +16 dB - maximum gain */ |
5a23b076 IL |
442 | }; |
443 | ||
444 | static struct stv6110_config netup_stv6110_tunerconfig_b = { | |
445 | .i2c_address = 0x63, | |
644c7ef0 AO |
446 | .mclk = 16000000, |
447 | .clk_div = 1, | |
873688cd | 448 | .gain = 8, /* +16 dB - maximum gain */ |
5a23b076 IL |
449 | }; |
450 | ||
96318d0c | 451 | static struct cx24116_config tbs_cx24116_config = { |
09ea33e5 | 452 | .demod_address = 0x55, |
96318d0c IL |
453 | }; |
454 | ||
09ea33e5 IL |
455 | static struct ds3000_config tevii_ds3000_config = { |
456 | .demod_address = 0x68, | |
579943f5 IL |
457 | }; |
458 | ||
c9b8b04b IL |
459 | static struct cx24116_config dvbworld_cx24116_config = { |
460 | .demod_address = 0x05, | |
461 | }; | |
462 | ||
493b7127 DW |
463 | static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = { |
464 | .prod = LGS8GXX_PROD_LGS8GL5, | |
465 | .demod_address = 0x19, | |
466 | .serial_ts = 0, | |
467 | .ts_clk_pol = 1, | |
468 | .ts_clk_gated = 1, | |
469 | .if_clk_freq = 30400, /* 30.4 MHz */ | |
470 | .if_freq = 5380, /* 5.38 MHz */ | |
471 | .if_neg_center = 1, | |
472 | .ext_adc = 0, | |
473 | .adc_signed = 0, | |
474 | .if_neg_edge = 0, | |
475 | }; | |
476 | ||
477 | static struct xc5000_config mygica_x8506_xc5000_config = { | |
478 | .i2c_address = 0x61, | |
479 | .if_khz = 5380, | |
480 | }; | |
481 | ||
f35b9e80 MK |
482 | static int cx23885_dvb_set_frontend(struct dvb_frontend *fe, |
483 | struct dvb_frontend_parameters *param) | |
484 | { | |
485 | struct cx23885_tsport *port = fe->dvb->priv; | |
486 | struct cx23885_dev *dev = port->dev; | |
487 | ||
488 | switch (dev->board) { | |
489 | case CX23885_BOARD_HAUPPAUGE_HVR1275: | |
490 | switch (param->u.vsb.modulation) { | |
491 | case VSB_8: | |
492 | cx23885_gpio_clear(dev, GPIO_5); | |
493 | break; | |
494 | case QAM_64: | |
495 | case QAM_256: | |
496 | default: | |
497 | cx23885_gpio_set(dev, GPIO_5); | |
498 | break; | |
499 | } | |
500 | break; | |
6f0d8c02 DW |
501 | case CX23885_BOARD_MYGICA_X8506: |
502 | case CX23885_BOARD_MAGICPRO_PROHDTVE2: | |
503 | /* Select Digital TV */ | |
504 | cx23885_gpio_set(dev, GPIO_0); | |
505 | break; | |
f35b9e80 | 506 | } |
5bdd3962 | 507 | return 0; |
f35b9e80 MK |
508 | } |
509 | ||
5bdd3962 MK |
510 | static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe, |
511 | unsigned int cmd, void *parg, | |
512 | unsigned int stage) | |
513 | { | |
514 | int err = 0; | |
515 | ||
516 | switch (stage) { | |
517 | case DVB_FE_IOCTL_PRE: | |
518 | ||
519 | switch (cmd) { | |
520 | case FE_SET_FRONTEND: | |
521 | err = cx23885_dvb_set_frontend(fe, | |
522 | (struct dvb_frontend_parameters *) parg); | |
523 | break; | |
524 | } | |
525 | break; | |
526 | ||
527 | case DVB_FE_IOCTL_POST: | |
528 | /* no post-ioctl handling required */ | |
529 | break; | |
530 | } | |
531 | return err; | |
532 | }; | |
533 | ||
534 | ||
2365b2d3 DW |
535 | static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = { |
536 | .prod = LGS8GXX_PROD_LGS8G75, | |
537 | .demod_address = 0x19, | |
538 | .serial_ts = 0, | |
539 | .ts_clk_pol = 1, | |
540 | .ts_clk_gated = 1, | |
541 | .if_clk_freq = 30400, /* 30.4 MHz */ | |
542 | .if_freq = 6500, /* 6.50 MHz */ | |
543 | .if_neg_center = 1, | |
544 | .ext_adc = 0, | |
545 | .adc_signed = 1, | |
546 | .adc_vpp = 2, /* 1.6 Vpp */ | |
547 | .if_neg_edge = 1, | |
548 | }; | |
549 | ||
550 | static struct xc5000_config magicpro_prohdtve2_xc5000_config = { | |
551 | .i2c_address = 0x61, | |
552 | .if_khz = 6500, | |
553 | }; | |
554 | ||
ea5697fe DW |
555 | static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = { |
556 | .prod = ATBM8830_PROD_8830, | |
557 | .demod_address = 0x44, | |
558 | .serial_ts = 0, | |
559 | .ts_sampling_edge = 1, | |
560 | .ts_clk_gated = 0, | |
561 | .osc_clk_freq = 30400, /* in kHz */ | |
562 | .if_freq = 0, /* zero IF */ | |
563 | .zif_swap_iq = 1, | |
c245c75c DW |
564 | .agc_min = 0x2E, |
565 | .agc_max = 0xFF, | |
566 | .agc_hold_loop = 0, | |
ea5697fe DW |
567 | }; |
568 | ||
569 | static struct max2165_config mygic_x8558pro_max2165_cfg1 = { | |
570 | .i2c_address = 0x60, | |
571 | .osc_clk = 20 | |
572 | }; | |
573 | ||
574 | static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = { | |
575 | .prod = ATBM8830_PROD_8830, | |
576 | .demod_address = 0x44, | |
577 | .serial_ts = 1, | |
578 | .ts_sampling_edge = 1, | |
579 | .ts_clk_gated = 0, | |
580 | .osc_clk_freq = 30400, /* in kHz */ | |
581 | .if_freq = 0, /* zero IF */ | |
582 | .zif_swap_iq = 1, | |
c245c75c DW |
583 | .agc_min = 0x2E, |
584 | .agc_max = 0xFF, | |
585 | .agc_hold_loop = 0, | |
ea5697fe DW |
586 | }; |
587 | ||
588 | static struct max2165_config mygic_x8558pro_max2165_cfg2 = { | |
589 | .i2c_address = 0x60, | |
590 | .osc_clk = 20 | |
591 | }; | |
78db8547 IL |
592 | static struct stv0367_config netup_stv0367_config[] = { |
593 | { | |
594 | .demod_address = 0x1c, | |
595 | .xtal = 27000000, | |
596 | .if_khz = 4500, | |
597 | .if_iq_mode = 0, | |
598 | .ts_mode = 1, | |
599 | .clk_pol = 0, | |
600 | }, { | |
601 | .demod_address = 0x1d, | |
602 | .xtal = 27000000, | |
603 | .if_khz = 4500, | |
604 | .if_iq_mode = 0, | |
605 | .ts_mode = 1, | |
606 | .clk_pol = 0, | |
607 | }, | |
608 | }; | |
609 | ||
610 | static struct xc5000_config netup_xc5000_config[] = { | |
611 | { | |
612 | .i2c_address = 0x61, | |
613 | .if_khz = 4500, | |
614 | }, { | |
615 | .i2c_address = 0x64, | |
616 | .if_khz = 4500, | |
617 | }, | |
618 | }; | |
619 | ||
620 | int netup_altera_fpga_rw(void *device, int flag, int data, int read) | |
621 | { | |
622 | struct cx23885_dev *dev = (struct cx23885_dev *)device; | |
623 | unsigned long timeout = jiffies + msecs_to_jiffies(1); | |
d164460f | 624 | uint32_t mem = 0; |
78db8547 | 625 | |
d164460f | 626 | mem = cx_read(MC417_RWD); |
78db8547 IL |
627 | if (read) |
628 | cx_set(MC417_OEN, ALT_DATA); | |
629 | else { | |
630 | cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */ | |
78db8547 IL |
631 | mem &= ~ALT_DATA; |
632 | mem |= (data & ALT_DATA); | |
78db8547 IL |
633 | } |
634 | ||
635 | if (flag) | |
d164460f | 636 | mem |= ALT_AD_RG; |
78db8547 | 637 | else |
d164460f | 638 | mem &= ~ALT_AD_RG; |
78db8547 | 639 | |
d164460f | 640 | mem &= ~ALT_CS; |
78db8547 | 641 | if (read) |
d164460f | 642 | mem = (mem & ~ALT_RD) | ALT_WR; |
78db8547 | 643 | else |
d164460f AO |
644 | mem = (mem & ~ALT_WR) | ALT_RD; |
645 | ||
646 | cx_write(MC417_RWD, mem); /* start RW cycle */ | |
78db8547 IL |
647 | |
648 | for (;;) { | |
649 | mem = cx_read(MC417_RWD); | |
650 | if ((mem & ALT_RDY) == 0) | |
651 | break; | |
652 | if (time_after(jiffies, timeout)) | |
653 | break; | |
654 | udelay(1); | |
655 | } | |
656 | ||
657 | cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS); | |
658 | if (read) | |
659 | return mem & ALT_DATA; | |
660 | ||
661 | return 0; | |
662 | }; | |
ea5697fe | 663 | |
d19770e5 ST |
664 | static int dvb_register(struct cx23885_tsport *port) |
665 | { | |
666 | struct cx23885_dev *dev = port->dev; | |
493b7127 | 667 | struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL; |
78db8547 IL |
668 | struct videobuf_dvb_frontend *fe0, *fe1 = NULL; |
669 | int mfe_shared = 0; /* bus not shared by default */ | |
5a23b076 | 670 | int ret; |
363c35fc | 671 | |
f972e0bd | 672 | /* Get the first frontend */ |
92abe9ee | 673 | fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); |
363c35fc ST |
674 | if (!fe0) |
675 | return -EINVAL; | |
d19770e5 ST |
676 | |
677 | /* init struct videobuf_dvb */ | |
363c35fc | 678 | fe0->dvb.name = dev->name; |
d19770e5 | 679 | |
78db8547 IL |
680 | /* multi-frontend gate control is undefined or defaults to fe0 */ |
681 | port->frontends.gate = 0; | |
682 | ||
683 | /* Sets the gate control callback to be used by i2c command calls */ | |
684 | port->gate_ctrl = cx23885_dvb_gate_ctrl; | |
685 | ||
d19770e5 ST |
686 | /* init frontend */ |
687 | switch (dev->board) { | |
a77743bc | 688 | case CX23885_BOARD_HAUPPAUGE_HVR1250: |
f139fa71 | 689 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 690 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
86184e06 | 691 | &hauppauge_generic_config, |
f139fa71 | 692 | &i2c_bus->i2c_adap); |
363c35fc ST |
693 | if (fe0->dvb.frontend != NULL) { |
694 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
f139fa71 | 695 | &i2c_bus->i2c_adap, |
86184e06 | 696 | &hauppauge_generic_tunerconfig, 0); |
d19770e5 ST |
697 | } |
698 | break; | |
a5dbf457 | 699 | case CX23885_BOARD_HAUPPAUGE_HVR1270: |
d099becb | 700 | case CX23885_BOARD_HAUPPAUGE_HVR1275: |
a5dbf457 MK |
701 | i2c_bus = &dev->i2c_bus[0]; |
702 | fe0->dvb.frontend = dvb_attach(lgdt3305_attach, | |
247bc540 | 703 | &hauppauge_lgdt3305_config, |
a5dbf457 MK |
704 | &i2c_bus->i2c_adap); |
705 | if (fe0->dvb.frontend != NULL) { | |
706 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
707 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
247bc540 | 708 | &hauppauge_hvr127x_config); |
a5dbf457 MK |
709 | } |
710 | break; | |
19bc5796 MK |
711 | case CX23885_BOARD_HAUPPAUGE_HVR1255: |
712 | i2c_bus = &dev->i2c_bus[0]; | |
713 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
714 | &hcw_s5h1411_config, | |
715 | &i2c_bus->i2c_adap); | |
716 | if (fe0->dvb.frontend != NULL) { | |
717 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
718 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
719 | &hauppauge_tda18271_config); | |
720 | } | |
721 | break; | |
3ba71d21 MK |
722 | case CX23885_BOARD_HAUPPAUGE_HVR1800: |
723 | i2c_bus = &dev->i2c_bus[0]; | |
92abe9ee | 724 | switch (alt_tuner) { |
3ba71d21 | 725 | case 1: |
363c35fc | 726 | fe0->dvb.frontend = |
3ba71d21 MK |
727 | dvb_attach(s5h1409_attach, |
728 | &hauppauge_ezqam_config, | |
729 | &i2c_bus->i2c_adap); | |
363c35fc ST |
730 | if (fe0->dvb.frontend != NULL) { |
731 | dvb_attach(tda829x_attach, fe0->dvb.frontend, | |
3ba71d21 | 732 | &dev->i2c_bus[1].i2c_adap, 0x42, |
4041f1a5 | 733 | &tda829x_no_probe); |
363c35fc | 734 | dvb_attach(tda18271_attach, fe0->dvb.frontend, |
4041f1a5 | 735 | 0x60, &dev->i2c_bus[1].i2c_adap, |
f21e0d7f | 736 | &hauppauge_tda18271_config); |
3ba71d21 MK |
737 | } |
738 | break; | |
739 | case 0: | |
740 | default: | |
363c35fc | 741 | fe0->dvb.frontend = |
3ba71d21 MK |
742 | dvb_attach(s5h1409_attach, |
743 | &hauppauge_generic_config, | |
744 | &i2c_bus->i2c_adap); | |
363c35fc ST |
745 | if (fe0->dvb.frontend != NULL) |
746 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
3ba71d21 MK |
747 | &i2c_bus->i2c_adap, |
748 | &hauppauge_generic_tunerconfig, 0); | |
749 | break; | |
750 | } | |
751 | break; | |
fc959bef | 752 | case CX23885_BOARD_HAUPPAUGE_HVR1800lp: |
f139fa71 | 753 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 754 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
fc959bef | 755 | &hauppauge_hvr1800lp_config, |
f139fa71 | 756 | &i2c_bus->i2c_adap); |
363c35fc ST |
757 | if (fe0->dvb.frontend != NULL) { |
758 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
f139fa71 | 759 | &i2c_bus->i2c_adap, |
fc959bef ST |
760 | &hauppauge_generic_tunerconfig, 0); |
761 | } | |
762 | break; | |
9bc37caa | 763 | case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: |
f139fa71 | 764 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 765 | fe0->dvb.frontend = dvb_attach(lgdt330x_attach, |
9bc37caa | 766 | &fusionhdtv_5_express, |
f139fa71 | 767 | &i2c_bus->i2c_adap); |
363c35fc ST |
768 | if (fe0->dvb.frontend != NULL) { |
769 | dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
827855d3 MK |
770 | &i2c_bus->i2c_adap, 0x61, |
771 | TUNER_LG_TDVS_H06XF); | |
9bc37caa MK |
772 | } |
773 | break; | |
d1987d55 ST |
774 | case CX23885_BOARD_HAUPPAUGE_HVR1500Q: |
775 | i2c_bus = &dev->i2c_bus[1]; | |
363c35fc | 776 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
d1987d55 ST |
777 | &hauppauge_hvr1500q_config, |
778 | &dev->i2c_bus[0].i2c_adap); | |
363c35fc ST |
779 | if (fe0->dvb.frontend != NULL) |
780 | dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
30650961 MK |
781 | &i2c_bus->i2c_adap, |
782 | &hauppauge_hvr1500q_tunerconfig); | |
d1987d55 | 783 | break; |
07b4a835 MK |
784 | case CX23885_BOARD_HAUPPAUGE_HVR1500: |
785 | i2c_bus = &dev->i2c_bus[1]; | |
363c35fc | 786 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
07b4a835 MK |
787 | &hauppauge_hvr1500_config, |
788 | &dev->i2c_bus[0].i2c_adap); | |
363c35fc | 789 | if (fe0->dvb.frontend != NULL) { |
07b4a835 MK |
790 | struct dvb_frontend *fe; |
791 | struct xc2028_config cfg = { | |
792 | .i2c_adap = &i2c_bus->i2c_adap, | |
793 | .i2c_addr = 0x61, | |
07b4a835 MK |
794 | }; |
795 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 796 | .fname = XC2028_DEFAULT_FIRMWARE, |
07b4a835 | 797 | .max_len = 64, |
52c3d29c | 798 | .demod = XC3028_FE_OREN538, |
07b4a835 MK |
799 | }; |
800 | ||
801 | fe = dvb_attach(xc2028_attach, | |
363c35fc | 802 | fe0->dvb.frontend, &cfg); |
07b4a835 MK |
803 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) |
804 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
805 | } | |
806 | break; | |
b3ea0166 | 807 | case CX23885_BOARD_HAUPPAUGE_HVR1200: |
a780a31c | 808 | case CX23885_BOARD_HAUPPAUGE_HVR1700: |
b3ea0166 | 809 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 810 | fe0->dvb.frontend = dvb_attach(tda10048_attach, |
b3ea0166 ST |
811 | &hauppauge_hvr1200_config, |
812 | &i2c_bus->i2c_adap); | |
363c35fc ST |
813 | if (fe0->dvb.frontend != NULL) { |
814 | dvb_attach(tda829x_attach, fe0->dvb.frontend, | |
b3ea0166 ST |
815 | &dev->i2c_bus[1].i2c_adap, 0x42, |
816 | &tda829x_no_probe); | |
363c35fc | 817 | dvb_attach(tda18271_attach, fe0->dvb.frontend, |
b3ea0166 ST |
818 | 0x60, &dev->i2c_bus[1].i2c_adap, |
819 | &hauppauge_hvr1200_tuner_config); | |
6b926eca MK |
820 | } |
821 | break; | |
822 | case CX23885_BOARD_HAUPPAUGE_HVR1210: | |
823 | i2c_bus = &dev->i2c_bus[0]; | |
824 | fe0->dvb.frontend = dvb_attach(tda10048_attach, | |
825 | &hauppauge_hvr1210_config, | |
826 | &i2c_bus->i2c_adap); | |
827 | if (fe0->dvb.frontend != NULL) { | |
828 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
829 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
830 | &hauppauge_hvr1210_tuner_config); | |
b3ea0166 ST |
831 | } |
832 | break; | |
66762373 ST |
833 | case CX23885_BOARD_HAUPPAUGE_HVR1400: |
834 | i2c_bus = &dev->i2c_bus[0]; | |
363c35fc | 835 | fe0->dvb.frontend = dvb_attach(dib7000p_attach, |
66762373 ST |
836 | &i2c_bus->i2c_adap, |
837 | 0x12, &hauppauge_hvr1400_dib7000_config); | |
363c35fc | 838 | if (fe0->dvb.frontend != NULL) { |
66762373 ST |
839 | struct dvb_frontend *fe; |
840 | struct xc2028_config cfg = { | |
841 | .i2c_adap = &dev->i2c_bus[1].i2c_adap, | |
842 | .i2c_addr = 0x64, | |
66762373 ST |
843 | }; |
844 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 845 | .fname = XC3028L_DEFAULT_FIRMWARE, |
66762373 | 846 | .max_len = 64, |
9bed77ee | 847 | .demod = XC3028_FE_DIBCOM52, |
9c8ced51 ST |
848 | /* This is true for all demods with |
849 | v36 firmware? */ | |
0975fc68 | 850 | .type = XC2028_D2633, |
66762373 ST |
851 | }; |
852 | ||
853 | fe = dvb_attach(xc2028_attach, | |
363c35fc | 854 | fe0->dvb.frontend, &cfg); |
66762373 ST |
855 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) |
856 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
857 | } | |
858 | break; | |
335377b7 MK |
859 | case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: |
860 | i2c_bus = &dev->i2c_bus[port->nr - 1]; | |
861 | ||
363c35fc | 862 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
335377b7 MK |
863 | &dvico_s5h1409_config, |
864 | &i2c_bus->i2c_adap); | |
363c35fc ST |
865 | if (fe0->dvb.frontend == NULL) |
866 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
52b50450 MK |
867 | &dvico_s5h1411_config, |
868 | &i2c_bus->i2c_adap); | |
363c35fc ST |
869 | if (fe0->dvb.frontend != NULL) |
870 | dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
30650961 MK |
871 | &i2c_bus->i2c_adap, |
872 | &dvico_xc5000_tunerconfig); | |
335377b7 | 873 | break; |
aef2d186 ST |
874 | case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: { |
875 | i2c_bus = &dev->i2c_bus[port->nr - 1]; | |
876 | ||
363c35fc | 877 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
aef2d186 ST |
878 | &dvico_fusionhdtv_xc3028, |
879 | &i2c_bus->i2c_adap); | |
363c35fc | 880 | if (fe0->dvb.frontend != NULL) { |
aef2d186 ST |
881 | struct dvb_frontend *fe; |
882 | struct xc2028_config cfg = { | |
883 | .i2c_adap = &i2c_bus->i2c_adap, | |
884 | .i2c_addr = 0x61, | |
aef2d186 ST |
885 | }; |
886 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 887 | .fname = XC2028_DEFAULT_FIRMWARE, |
aef2d186 ST |
888 | .max_len = 64, |
889 | .demod = XC3028_FE_ZARLINK456, | |
890 | }; | |
891 | ||
363c35fc | 892 | fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, |
aef2d186 ST |
893 | &cfg); |
894 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) | |
895 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
896 | } | |
897 | break; | |
898 | } | |
4c56b04a | 899 | case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: |
9bb1b7e8 | 900 | case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: |
34e383dd | 901 | case CX23885_BOARD_COMPRO_VIDEOMATE_E800: |
4c56b04a ST |
902 | i2c_bus = &dev->i2c_bus[0]; |
903 | ||
363c35fc | 904 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
4c56b04a ST |
905 | &dvico_fusionhdtv_xc3028, |
906 | &i2c_bus->i2c_adap); | |
363c35fc | 907 | if (fe0->dvb.frontend != NULL) { |
4c56b04a ST |
908 | struct dvb_frontend *fe; |
909 | struct xc2028_config cfg = { | |
910 | .i2c_adap = &dev->i2c_bus[1].i2c_adap, | |
911 | .i2c_addr = 0x61, | |
4c56b04a ST |
912 | }; |
913 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 914 | .fname = XC2028_DEFAULT_FIRMWARE, |
4c56b04a ST |
915 | .max_len = 64, |
916 | .demod = XC3028_FE_ZARLINK456, | |
917 | }; | |
918 | ||
363c35fc | 919 | fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, |
4c56b04a ST |
920 | &cfg); |
921 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) | |
922 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
923 | } | |
96318d0c | 924 | break; |
0cf8af57 | 925 | case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: |
926 | i2c_bus = &dev->i2c_bus[0]; | |
927 | ||
928 | fe0->dvb.frontend = dvb_attach(zl10353_attach, | |
929 | &dvico_fusionhdtv_xc3028, | |
930 | &i2c_bus->i2c_adap); | |
931 | if (fe0->dvb.frontend != NULL) { | |
932 | struct dvb_frontend *fe; | |
933 | struct xc4000_config cfg = { | |
934 | .i2c_address = 0x61, | |
935 | .default_pm = 0, | |
936 | .dvb_amplitude = 134, | |
937 | .set_smoothedcvbs = 1, | |
938 | .if_khz = 4560 | |
939 | }; | |
940 | ||
941 | fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, | |
942 | &dev->i2c_bus[1].i2c_adap, &cfg); | |
943 | } | |
944 | break; | |
96318d0c | 945 | case CX23885_BOARD_TBS_6920: |
09ea33e5 | 946 | i2c_bus = &dev->i2c_bus[1]; |
96318d0c IL |
947 | |
948 | fe0->dvb.frontend = dvb_attach(cx24116_attach, | |
09ea33e5 IL |
949 | &tbs_cx24116_config, |
950 | &i2c_bus->i2c_adap); | |
96318d0c | 951 | if (fe0->dvb.frontend != NULL) |
09ea33e5 | 952 | fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; |
96318d0c | 953 | |
579943f5 IL |
954 | break; |
955 | case CX23885_BOARD_TEVII_S470: | |
956 | i2c_bus = &dev->i2c_bus[1]; | |
957 | ||
09ea33e5 IL |
958 | fe0->dvb.frontend = dvb_attach(ds3000_attach, |
959 | &tevii_ds3000_config, | |
960 | &i2c_bus->i2c_adap); | |
579943f5 | 961 | if (fe0->dvb.frontend != NULL) |
09ea33e5 | 962 | fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; |
579943f5 | 963 | |
4c56b04a | 964 | break; |
c9b8b04b IL |
965 | case CX23885_BOARD_DVBWORLD_2005: |
966 | i2c_bus = &dev->i2c_bus[1]; | |
967 | ||
968 | fe0->dvb.frontend = dvb_attach(cx24116_attach, | |
969 | &dvbworld_cx24116_config, | |
970 | &i2c_bus->i2c_adap); | |
971 | break; | |
5a23b076 IL |
972 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: |
973 | i2c_bus = &dev->i2c_bus[0]; | |
974 | switch (port->nr) { | |
975 | /* port B */ | |
976 | case 1: | |
977 | fe0->dvb.frontend = dvb_attach(stv0900_attach, | |
978 | &netup_stv0900_config, | |
979 | &i2c_bus->i2c_adap, 0); | |
980 | if (fe0->dvb.frontend != NULL) { | |
981 | if (dvb_attach(stv6110_attach, | |
982 | fe0->dvb.frontend, | |
983 | &netup_stv6110_tunerconfig_a, | |
984 | &i2c_bus->i2c_adap)) { | |
985 | if (!dvb_attach(lnbh24_attach, | |
986 | fe0->dvb.frontend, | |
987 | &i2c_bus->i2c_adap, | |
9329fb5b AO |
988 | LNBH24_PCL | LNBH24_TTX, |
989 | LNBH24_TEN, 0x09)) | |
5a23b076 IL |
990 | printk(KERN_ERR |
991 | "No LNBH24 found!\n"); | |
992 | ||
993 | } | |
994 | } | |
995 | break; | |
996 | /* port C */ | |
997 | case 2: | |
998 | fe0->dvb.frontend = dvb_attach(stv0900_attach, | |
999 | &netup_stv0900_config, | |
1000 | &i2c_bus->i2c_adap, 1); | |
1001 | if (fe0->dvb.frontend != NULL) { | |
1002 | if (dvb_attach(stv6110_attach, | |
1003 | fe0->dvb.frontend, | |
1004 | &netup_stv6110_tunerconfig_b, | |
1005 | &i2c_bus->i2c_adap)) { | |
1006 | if (!dvb_attach(lnbh24_attach, | |
1007 | fe0->dvb.frontend, | |
1008 | &i2c_bus->i2c_adap, | |
9329fb5b AO |
1009 | LNBH24_PCL | LNBH24_TTX, |
1010 | LNBH24_TEN, 0x0a)) | |
5a23b076 IL |
1011 | printk(KERN_ERR |
1012 | "No LNBH24 found!\n"); | |
1013 | ||
1014 | } | |
1015 | } | |
1016 | break; | |
1017 | } | |
1018 | break; | |
493b7127 DW |
1019 | case CX23885_BOARD_MYGICA_X8506: |
1020 | i2c_bus = &dev->i2c_bus[0]; | |
1021 | i2c_bus2 = &dev->i2c_bus[1]; | |
1022 | fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, | |
1023 | &mygica_x8506_lgs8gl5_config, | |
1024 | &i2c_bus->i2c_adap); | |
1025 | if (fe0->dvb.frontend != NULL) { | |
1026 | dvb_attach(xc5000_attach, | |
1027 | fe0->dvb.frontend, | |
1028 | &i2c_bus2->i2c_adap, | |
1029 | &mygica_x8506_xc5000_config); | |
1030 | } | |
1031 | break; | |
2365b2d3 DW |
1032 | case CX23885_BOARD_MAGICPRO_PROHDTVE2: |
1033 | i2c_bus = &dev->i2c_bus[0]; | |
1034 | i2c_bus2 = &dev->i2c_bus[1]; | |
1035 | fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, | |
1036 | &magicpro_prohdtve2_lgs8g75_config, | |
1037 | &i2c_bus->i2c_adap); | |
1038 | if (fe0->dvb.frontend != NULL) { | |
1039 | dvb_attach(xc5000_attach, | |
1040 | fe0->dvb.frontend, | |
1041 | &i2c_bus2->i2c_adap, | |
1042 | &magicpro_prohdtve2_xc5000_config); | |
1043 | } | |
1044 | break; | |
13697380 | 1045 | case CX23885_BOARD_HAUPPAUGE_HVR1850: |
aee0b24c | 1046 | case CX23885_BOARD_HAUPPAUGE_HVR1290: |
13697380 ST |
1047 | i2c_bus = &dev->i2c_bus[0]; |
1048 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
1049 | &hcw_s5h1411_config, | |
1050 | &i2c_bus->i2c_adap); | |
1051 | if (fe0->dvb.frontend != NULL) | |
1052 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
1053 | 0x60, &dev->i2c_bus[0].i2c_adap, | |
1054 | &hauppauge_tda18271_config); | |
1055 | break; | |
ea5697fe DW |
1056 | case CX23885_BOARD_MYGICA_X8558PRO: |
1057 | switch (port->nr) { | |
1058 | /* port B */ | |
1059 | case 1: | |
1060 | i2c_bus = &dev->i2c_bus[0]; | |
1061 | fe0->dvb.frontend = dvb_attach(atbm8830_attach, | |
1062 | &mygica_x8558pro_atbm8830_cfg1, | |
1063 | &i2c_bus->i2c_adap); | |
1064 | if (fe0->dvb.frontend != NULL) { | |
1065 | dvb_attach(max2165_attach, | |
1066 | fe0->dvb.frontend, | |
1067 | &i2c_bus->i2c_adap, | |
1068 | &mygic_x8558pro_max2165_cfg1); | |
1069 | } | |
1070 | break; | |
1071 | /* port C */ | |
1072 | case 2: | |
1073 | i2c_bus = &dev->i2c_bus[1]; | |
1074 | fe0->dvb.frontend = dvb_attach(atbm8830_attach, | |
1075 | &mygica_x8558pro_atbm8830_cfg2, | |
1076 | &i2c_bus->i2c_adap); | |
1077 | if (fe0->dvb.frontend != NULL) { | |
1078 | dvb_attach(max2165_attach, | |
1079 | fe0->dvb.frontend, | |
1080 | &i2c_bus->i2c_adap, | |
1081 | &mygic_x8558pro_max2165_cfg2); | |
1082 | } | |
1083 | break; | |
1084 | } | |
1085 | break; | |
78db8547 IL |
1086 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: |
1087 | i2c_bus = &dev->i2c_bus[0]; | |
1088 | mfe_shared = 1;/* MFE */ | |
1089 | port->frontends.gate = 0;/* not clear for me yet */ | |
1090 | /* ports B, C */ | |
1091 | /* MFE frontend 1 DVB-T */ | |
1092 | fe0->dvb.frontend = dvb_attach(stv0367ter_attach, | |
1093 | &netup_stv0367_config[port->nr - 1], | |
1094 | &i2c_bus->i2c_adap); | |
4174ebf5 | 1095 | if (fe0->dvb.frontend != NULL) { |
78db8547 IL |
1096 | if (NULL == dvb_attach(xc5000_attach, |
1097 | fe0->dvb.frontend, | |
1098 | &i2c_bus->i2c_adap, | |
1099 | &netup_xc5000_config[port->nr - 1])) | |
1100 | goto frontend_detach; | |
4174ebf5 AO |
1101 | /* load xc5000 firmware */ |
1102 | fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend); | |
1103 | } | |
78db8547 IL |
1104 | /* MFE frontend 2 */ |
1105 | fe1 = videobuf_dvb_get_frontend(&port->frontends, 2); | |
1106 | if (fe1 == NULL) | |
1107 | goto frontend_detach; | |
1108 | /* DVB-C init */ | |
1109 | fe1->dvb.frontend = dvb_attach(stv0367cab_attach, | |
1110 | &netup_stv0367_config[port->nr - 1], | |
1111 | &i2c_bus->i2c_adap); | |
1112 | if (fe1->dvb.frontend != NULL) { | |
1113 | fe1->dvb.frontend->id = 1; | |
1114 | if (NULL == dvb_attach(xc5000_attach, | |
1115 | fe1->dvb.frontend, | |
1116 | &i2c_bus->i2c_adap, | |
1117 | &netup_xc5000_config[port->nr - 1])) | |
1118 | goto frontend_detach; | |
1119 | } | |
1120 | break; | |
d19770e5 | 1121 | default: |
9c8ced51 ST |
1122 | printk(KERN_INFO "%s: The frontend of your DVB/ATSC card " |
1123 | " isn't supported yet\n", | |
d19770e5 ST |
1124 | dev->name); |
1125 | break; | |
1126 | } | |
78db8547 IL |
1127 | |
1128 | if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) { | |
9c8ced51 | 1129 | printk(KERN_ERR "%s: frontend initialization failed\n", |
78db8547 IL |
1130 | dev->name); |
1131 | goto frontend_detach; | |
d19770e5 | 1132 | } |
78db8547 | 1133 | |
d7cba043 | 1134 | /* define general-purpose callback pointer */ |
363c35fc | 1135 | fe0->dvb.frontend->callback = cx23885_tuner_callback; |
78db8547 IL |
1136 | if (fe1) |
1137 | fe1->dvb.frontend->callback = cx23885_tuner_callback; | |
1138 | #if 0 | |
1139 | /* Ensure all frontends negotiate bus access */ | |
1140 | fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; | |
1141 | if (fe1) | |
1142 | fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; | |
1143 | #endif | |
d19770e5 ST |
1144 | |
1145 | /* Put the analog decoder in standby to keep it quiet */ | |
622b828a | 1146 | call_all(dev, core, s_power, 0); |
d19770e5 | 1147 | |
363c35fc ST |
1148 | if (fe0->dvb.frontend->ops.analog_ops.standby) |
1149 | fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend); | |
3ba71d21 | 1150 | |
d19770e5 | 1151 | /* register everything */ |
5a23b076 | 1152 | ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port, |
78db8547 | 1153 | &dev->pci->dev, adapter_nr, mfe_shared, |
5bdd3962 | 1154 | cx23885_dvb_fe_ioctl_override); |
bee30192 | 1155 | if (ret) |
78db8547 | 1156 | goto frontend_detach; |
363c35fc | 1157 | |
5a23b076 IL |
1158 | /* init CI & MAC */ |
1159 | switch (dev->board) { | |
1160 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: { | |
1161 | static struct netup_card_info cinfo; | |
1162 | ||
1163 | netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); | |
1164 | memcpy(port->frontends.adapter.proposed_mac, | |
1165 | cinfo.port[port->nr - 1].mac, 6); | |
be395157 | 1166 | printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n", |
1167 | port->nr, port->frontends.adapter.proposed_mac); | |
5a23b076 IL |
1168 | |
1169 | netup_ci_init(port); | |
1170 | break; | |
1171 | } | |
78db8547 IL |
1172 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { |
1173 | struct altera_ci_config netup_ci_cfg = { | |
1174 | .dev = dev,/* magic number to identify*/ | |
1175 | .adapter = &port->frontends.adapter,/* for CI */ | |
1176 | .demux = &fe0->dvb.demux,/* for hw pid filter */ | |
1177 | .fpga_rw = netup_altera_fpga_rw, | |
1178 | }; | |
1179 | ||
1180 | altera_ci_init(&netup_ci_cfg, port->nr); | |
1181 | break; | |
1182 | } | |
16bfdaa4 PG |
1183 | case CX23885_BOARD_TEVII_S470: { |
1184 | u8 eeprom[256]; /* 24C02 i2c eeprom */ | |
1185 | ||
1186 | if (port->nr != 1) | |
1187 | break; | |
1188 | ||
1189 | /* Read entire EEPROM */ | |
1190 | dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; | |
1191 | tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); | |
5cac1f66 | 1192 | printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0); |
16bfdaa4 PG |
1193 | memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6); |
1194 | break; | |
1195 | } | |
5a23b076 IL |
1196 | } |
1197 | ||
1198 | return ret; | |
78db8547 IL |
1199 | |
1200 | frontend_detach: | |
1201 | port->gate_ctrl = NULL; | |
1202 | videobuf_dvb_dealloc_frontends(&port->frontends); | |
1203 | return -EINVAL; | |
d19770e5 ST |
1204 | } |
1205 | ||
1206 | int cx23885_dvb_register(struct cx23885_tsport *port) | |
1207 | { | |
363c35fc ST |
1208 | |
1209 | struct videobuf_dvb_frontend *fe0; | |
d19770e5 | 1210 | struct cx23885_dev *dev = port->dev; |
eb0c58bb ST |
1211 | int err, i; |
1212 | ||
1213 | /* Here we need to allocate the correct number of frontends, | |
af901ca1 | 1214 | * as reflected in the cards struct. The reality is that currently |
eb0c58bb ST |
1215 | * no cx23885 boards support this - yet. But, if we don't modify this |
1216 | * code then the second frontend would never be allocated (later) | |
1217 | * and fail with error before the attach in dvb_register(). | |
1218 | * Without these changes we risk an OOPS later. The changes here | |
1219 | * are for safety, and should provide a good foundation for the | |
1220 | * future addition of any multi-frontend cx23885 based boards. | |
1221 | */ | |
1222 | printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, | |
1223 | port->num_frontends); | |
d19770e5 | 1224 | |
eb0c58bb | 1225 | for (i = 1; i <= port->num_frontends; i++) { |
96b7a1a8 | 1226 | if (videobuf_dvb_alloc_frontend( |
9c8ced51 | 1227 | &port->frontends, i) == NULL) { |
eb0c58bb ST |
1228 | printk(KERN_ERR "%s() failed to alloc\n", __func__); |
1229 | return -ENOMEM; | |
1230 | } | |
1231 | ||
1232 | fe0 = videobuf_dvb_get_frontend(&port->frontends, i); | |
1233 | if (!fe0) | |
1234 | err = -EINVAL; | |
363c35fc | 1235 | |
eb0c58bb | 1236 | dprintk(1, "%s\n", __func__); |
9c8ced51 | 1237 | dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n", |
eb0c58bb ST |
1238 | dev->board, |
1239 | dev->name, | |
1240 | dev->pci_bus, | |
1241 | dev->pci_slot); | |
d19770e5 | 1242 | |
eb0c58bb | 1243 | err = -ENODEV; |
d19770e5 | 1244 | |
eb0c58bb ST |
1245 | /* dvb stuff */ |
1246 | /* We have to init the queue for each frontend on a port. */ | |
9c8ced51 ST |
1247 | printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name); |
1248 | videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops, | |
1249 | &dev->pci->dev, &port->slock, | |
44a6481d | 1250 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP, |
08bff03e | 1251 | sizeof(struct cx23885_buffer), port, NULL); |
eb0c58bb | 1252 | } |
d19770e5 ST |
1253 | err = dvb_register(port); |
1254 | if (err != 0) | |
9c8ced51 ST |
1255 | printk(KERN_ERR "%s() dvb_register failed err = %d\n", |
1256 | __func__, err); | |
d19770e5 | 1257 | |
d19770e5 ST |
1258 | return err; |
1259 | } | |
1260 | ||
1261 | int cx23885_dvb_unregister(struct cx23885_tsport *port) | |
1262 | { | |
363c35fc ST |
1263 | struct videobuf_dvb_frontend *fe0; |
1264 | ||
eb0c58bb ST |
1265 | /* FIXME: in an error condition where the we have |
1266 | * an expected number of frontends (attach problem) | |
1267 | * then this might not clean up correctly, if 1 | |
1268 | * is invalid. | |
1269 | * This comment only applies to future boards IF they | |
1270 | * implement MFE support. | |
1271 | */ | |
92abe9ee | 1272 | fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); |
e66131ce | 1273 | if (fe0 && fe0->dvb.frontend) |
363c35fc | 1274 | videobuf_dvb_unregister_bus(&port->frontends); |
d19770e5 | 1275 | |
afd96668 HV |
1276 | switch (port->dev->board) { |
1277 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: | |
1278 | netup_ci_exit(port); | |
1279 | break; | |
78db8547 IL |
1280 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: |
1281 | altera_ci_release(port->dev, port->nr); | |
1282 | break; | |
afd96668 | 1283 | } |
5a23b076 | 1284 | |
78db8547 IL |
1285 | port->gate_ctrl = NULL; |
1286 | ||
d19770e5 ST |
1287 | return 0; |
1288 | } | |
44a6481d | 1289 |