V4L/DVB (11769): cx23885: add ATSC/QAM tuning support for Hauppauge WinTV-HVR1275
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
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1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
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5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
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31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
ST
44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076
IL
47#include "stv0900.h"
48#include "stv6110.h"
49#include "lnbh24.h"
96318d0c 50#include "cx24116.h"
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IL
51#include "cimax2.h"
52#include "netup-eeprom.h"
53#include "netup-init.h"
a5dbf457 54#include "lgdt3305.h"
d19770e5 55
4513fc69 56static unsigned int debug;
d19770e5 57
4513fc69
ST
58#define dprintk(level, fmt, arg...)\
59 do { if (debug >= level)\
60 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
61 } while (0)
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62
63/* ------------------------------------------------------------------ */
64
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65static unsigned int alt_tuner;
66module_param(alt_tuner, int, 0644);
67MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
68
78e92006
JG
69DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
70
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71/* ------------------------------------------------------------------ */
72
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73static int dvb_buf_setup(struct videobuf_queue *q,
74 unsigned int *count, unsigned int *size)
75{
76 struct cx23885_tsport *port = q->priv_data;
77
78 port->ts_packet_size = 188 * 4;
79 port->ts_packet_count = 32;
80
81 *size = port->ts_packet_size * port->ts_packet_count;
82 *count = 32;
83 return 0;
84}
85
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MK
86static int dvb_buf_prepare(struct videobuf_queue *q,
87 struct videobuf_buffer *vb, enum v4l2_field field)
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88{
89 struct cx23885_tsport *port = q->priv_data;
9c8ced51 90 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
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91}
92
93static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
94{
95 struct cx23885_tsport *port = q->priv_data;
9c8ced51 96 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
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97}
98
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99static void dvb_buf_release(struct videobuf_queue *q,
100 struct videobuf_buffer *vb)
d19770e5 101{
9c8ced51 102 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
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103}
104
105static struct videobuf_queue_ops dvb_qops = {
106 .buf_setup = dvb_buf_setup,
107 .buf_prepare = dvb_buf_prepare,
108 .buf_queue = dvb_buf_queue,
109 .buf_release = dvb_buf_release,
110};
111
86184e06 112static struct s5h1409_config hauppauge_generic_config = {
fc959bef
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113 .demod_address = 0x32 >> 1,
114 .output_mode = S5H1409_SERIAL_OUTPUT,
115 .gpio = S5H1409_GPIO_ON,
2b03238a 116 .qam_if = 44000,
fc959bef 117 .inversion = S5H1409_INVERSION_OFF,
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118 .status_mode = S5H1409_DEMODLOCKING,
119 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
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120};
121
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122static struct tda10048_config hauppauge_hvr1200_config = {
123 .demod_address = 0x10 >> 1,
124 .output_mode = TDA10048_SERIAL_OUTPUT,
125 .fwbulkwritelen = TDA10048_BULKWRITE_200,
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126 .inversion = TDA10048_INVERSION_ON,
127 .if_freq_khz = TDA10048_IF_4300,
128 .clk_freq_khz = TDA10048_CLK_16000,
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129};
130
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131static struct s5h1409_config hauppauge_ezqam_config = {
132 .demod_address = 0x32 >> 1,
133 .output_mode = S5H1409_SERIAL_OUTPUT,
134 .gpio = S5H1409_GPIO_OFF,
135 .qam_if = 4000,
136 .inversion = S5H1409_INVERSION_ON,
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137 .status_mode = S5H1409_DEMODLOCKING,
138 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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139};
140
fc959bef 141static struct s5h1409_config hauppauge_hvr1800lp_config = {
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142 .demod_address = 0x32 >> 1,
143 .output_mode = S5H1409_SERIAL_OUTPUT,
144 .gpio = S5H1409_GPIO_OFF,
2b03238a 145 .qam_if = 44000,
fe475163 146 .inversion = S5H1409_INVERSION_OFF,
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147 .status_mode = S5H1409_DEMODLOCKING,
148 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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149};
150
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151static struct s5h1409_config hauppauge_hvr1500_config = {
152 .demod_address = 0x32 >> 1,
153 .output_mode = S5H1409_SERIAL_OUTPUT,
154 .gpio = S5H1409_GPIO_OFF,
155 .inversion = S5H1409_INVERSION_OFF,
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156 .status_mode = S5H1409_DEMODLOCKING,
157 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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158};
159
86184e06 160static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
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161 0x61
162};
163
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164static struct lgdt330x_config fusionhdtv_5_express = {
165 .demod_address = 0x0e,
166 .demod_chip = LGDT3303,
167 .serial_mpeg = 0x40,
168};
169
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170static struct s5h1409_config hauppauge_hvr1500q_config = {
171 .demod_address = 0x32 >> 1,
172 .output_mode = S5H1409_SERIAL_OUTPUT,
173 .gpio = S5H1409_GPIO_ON,
174 .qam_if = 44000,
175 .inversion = S5H1409_INVERSION_OFF,
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176 .status_mode = S5H1409_DEMODLOCKING,
177 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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178};
179
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180static struct s5h1409_config dvico_s5h1409_config = {
181 .demod_address = 0x32 >> 1,
182 .output_mode = S5H1409_SERIAL_OUTPUT,
183 .gpio = S5H1409_GPIO_ON,
184 .qam_if = 44000,
185 .inversion = S5H1409_INVERSION_OFF,
186 .status_mode = S5H1409_DEMODLOCKING,
187 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
188};
189
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190static struct s5h1411_config dvico_s5h1411_config = {
191 .output_mode = S5H1411_SERIAL_OUTPUT,
192 .gpio = S5H1411_GPIO_ON,
193 .qam_if = S5H1411_IF_44000,
194 .vsb_if = S5H1411_IF_44000,
195 .inversion = S5H1411_INVERSION_OFF,
196 .status_mode = S5H1411_DEMODLOCKING,
197 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
198};
199
d1987d55 200static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
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201 .i2c_address = 0x61,
202 .if_khz = 5380,
d1987d55
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203};
204
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205static struct xc5000_config dvico_xc5000_tunerconfig = {
206 .i2c_address = 0x64,
207 .if_khz = 5380,
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208};
209
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210static struct tda829x_config tda829x_no_probe = {
211 .probe_tuner = TDA829X_DONT_PROBE,
212};
213
f21e0d7f 214static struct tda18271_std_map hauppauge_tda18271_std_map = {
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215 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
216 .if_lvl = 6, .rfagc_top = 0x37 },
217 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
218 .if_lvl = 6, .rfagc_top = 0x37 },
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219};
220
221static struct tda18271_config hauppauge_tda18271_config = {
222 .std_map = &hauppauge_tda18271_std_map,
223 .gate = TDA18271_GATE_ANALOG,
224};
225
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226static struct tda18271_config hauppauge_hvr1200_tuner_config = {
227 .gate = TDA18271_GATE_ANALOG,
228};
229
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230static struct tda18271_std_map hcw_lgdt3305_tda18271_std_map = {
231 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
232 .if_lvl = 1, .rfagc_top = 0x58 },
233 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
234 .if_lvl = 1, .rfagc_top = 0x58 },
235};
236
237static struct tda18271_config hcw_lgdt3305_tda18271_config = {
238 .std_map = &hcw_lgdt3305_tda18271_std_map,
239};
240
241static struct lgdt3305_config hcw_lgdt3305_config = {
242 .i2c_addr = 0x0e,
243 .mpeg_mode = LGDT3305_MPEG_SERIAL,
244 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
245 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
246 .deny_i2c_rptr = 1,
247 .spectral_inversion = 1,
248 .qam_if_khz = 4000,
249 .vsb_if_khz = 3250,
250};
251
b1721d0d 252static struct dibx000_agc_config xc3028_agc_config = {
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ST
253 BAND_VHF | BAND_UHF, /* band_caps */
254
255 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
256 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
257 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
258 * P_agc_nb_est=2, P_agc_write=0
259 */
260 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
261 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
262
263 712, /* inv_gain */
264 21, /* time_stabiliz */
265
266 0, /* alpha_level */
267 118, /* thlock */
268
269 0, /* wbd_inv */
270 2867, /* wbd_ref */
271 0, /* wbd_sel */
272 2, /* wbd_alpha */
273
274 0, /* agc1_max */
275 0, /* agc1_min */
276 39718, /* agc2_max */
277 9930, /* agc2_min */
278 0, /* agc1_pt1 */
279 0, /* agc1_pt2 */
280 0, /* agc1_pt3 */
281 0, /* agc1_slope1 */
282 0, /* agc1_slope2 */
283 0, /* agc2_pt1 */
284 128, /* agc2_pt2 */
285 29, /* agc2_slope1 */
286 29, /* agc2_slope2 */
287
288 17, /* alpha_mant */
289 27, /* alpha_exp */
290 23, /* beta_mant */
291 51, /* beta_exp */
292
293 1, /* perform_agc_softsplit */
294};
295
296/* PLL Configuration for COFDM BW_MHz = 8.000000
297 * With external clock = 30.000000 */
b1721d0d 298static struct dibx000_bandwidth_config xc3028_bw_config = {
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ST
299 60000, /* internal */
300 30000, /* sampling */
301 1, /* pll_cfg: prediv */
302 8, /* pll_cfg: ratio */
303 3, /* pll_cfg: range */
304 1, /* pll_cfg: reset */
305 0, /* pll_cfg: bypass */
306 0, /* misc: refdiv */
307 0, /* misc: bypclk_div */
308 1, /* misc: IO_CLK_en_core */
309 1, /* misc: ADClkSrc */
310 0, /* misc: modulo */
311 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
312 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
313 20452225, /* timf */
314 30000000 /* xtal_hz */
315};
316
317static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
318 .output_mpeg2_in_188_bytes = 1,
319 .hostbus_diversity = 1,
320 .tuner_is_baseband = 0,
321 .update_lna = NULL,
322
323 .agc_config_count = 1,
324 .agc = &xc3028_agc_config,
325 .bw = &xc3028_bw_config,
326
327 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
328 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
329 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
330
331 .pwm_freq_div = 0,
332 .agc_control = NULL,
333 .spur_protect = 0,
334
335 .output_mode = OUTMODE_MPEG2_SERIAL,
336};
337
aef2d186
ST
338static struct zl10353_config dvico_fusionhdtv_xc3028 = {
339 .demod_address = 0x0f,
340 .if2 = 45600,
341 .no_tuner = 1,
d4dc673d 342 .disable_i2c_gate_ctrl = 1,
aef2d186
ST
343};
344
5a23b076
IL
345static struct stv0900_config netup_stv0900_config = {
346 .demod_address = 0x68,
347 .xtal = 27000000,
348 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
349 .diseqc_mode = 2,/* 2/3 PWM */
350 .path1_mode = 2,/*Serial continues clock */
351 .path2_mode = 2,/*Serial continues clock */
352 .tun1_maddress = 0,/* 0x60 */
353 .tun2_maddress = 3,/* 0x63 */
354 .tun1_adc = 1,/* 1 Vpp */
355 .tun2_adc = 1,/* 1 Vpp */
356};
357
358static struct stv6110_config netup_stv6110_tunerconfig_a = {
359 .i2c_address = 0x60,
360 .mclk = 27000000,
361 .iq_wiring = 0,
362};
363
364static struct stv6110_config netup_stv6110_tunerconfig_b = {
365 .i2c_address = 0x63,
366 .mclk = 27000000,
367 .iq_wiring = 1,
368};
369
96318d0c
IL
370static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
371{
372 struct cx23885_tsport *port = fe->dvb->priv;
373 struct cx23885_dev *dev = port->dev;
374
375 if (voltage == SEC_VOLTAGE_18)
376 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
377 else if (voltage == SEC_VOLTAGE_13)
378 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
379 else
380 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
381 return 0;
382}
383
384static struct cx24116_config tbs_cx24116_config = {
385 .demod_address = 0x05,
386};
387
579943f5
IL
388static struct cx24116_config tevii_cx24116_config = {
389 .demod_address = 0x55,
390};
391
c9b8b04b
IL
392static struct cx24116_config dvbworld_cx24116_config = {
393 .demod_address = 0x05,
394};
395
d19770e5
ST
396static int dvb_register(struct cx23885_tsport *port)
397{
398 struct cx23885_dev *dev = port->dev;
f139fa71 399 struct cx23885_i2c *i2c_bus = NULL;
363c35fc 400 struct videobuf_dvb_frontend *fe0;
5a23b076 401 int ret;
363c35fc 402
f972e0bd 403 /* Get the first frontend */
92abe9ee 404 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST
405 if (!fe0)
406 return -EINVAL;
d19770e5
ST
407
408 /* init struct videobuf_dvb */
363c35fc 409 fe0->dvb.name = dev->name;
d19770e5
ST
410
411 /* init frontend */
412 switch (dev->board) {
a77743bc 413 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 414 i2c_bus = &dev->i2c_bus[0];
363c35fc 415 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 416 &hauppauge_generic_config,
f139fa71 417 &i2c_bus->i2c_adap);
363c35fc
ST
418 if (fe0->dvb.frontend != NULL) {
419 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 420 &i2c_bus->i2c_adap,
86184e06 421 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST
422 }
423 break;
a5dbf457 424 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 425 case CX23885_BOARD_HAUPPAUGE_HVR1275:
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MK
426 i2c_bus = &dev->i2c_bus[0];
427 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
428 &hcw_lgdt3305_config,
429 &i2c_bus->i2c_adap);
430 if (fe0->dvb.frontend != NULL) {
431 dvb_attach(tda18271_attach, fe0->dvb.frontend,
432 0x60, &dev->i2c_bus[1].i2c_adap,
433 &hcw_lgdt3305_tda18271_config);
434 }
435 break;
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MK
436 case CX23885_BOARD_HAUPPAUGE_HVR1800:
437 i2c_bus = &dev->i2c_bus[0];
92abe9ee 438 switch (alt_tuner) {
3ba71d21 439 case 1:
363c35fc 440 fe0->dvb.frontend =
3ba71d21
MK
441 dvb_attach(s5h1409_attach,
442 &hauppauge_ezqam_config,
443 &i2c_bus->i2c_adap);
363c35fc
ST
444 if (fe0->dvb.frontend != NULL) {
445 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 446 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 447 &tda829x_no_probe);
363c35fc 448 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 449 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 450 &hauppauge_tda18271_config);
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MK
451 }
452 break;
453 case 0:
454 default:
363c35fc 455 fe0->dvb.frontend =
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MK
456 dvb_attach(s5h1409_attach,
457 &hauppauge_generic_config,
458 &i2c_bus->i2c_adap);
363c35fc
ST
459 if (fe0->dvb.frontend != NULL)
460 dvb_attach(mt2131_attach, fe0->dvb.frontend,
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MK
461 &i2c_bus->i2c_adap,
462 &hauppauge_generic_tunerconfig, 0);
463 break;
464 }
465 break;
fc959bef 466 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 467 i2c_bus = &dev->i2c_bus[0];
363c35fc 468 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 469 &hauppauge_hvr1800lp_config,
f139fa71 470 &i2c_bus->i2c_adap);
363c35fc
ST
471 if (fe0->dvb.frontend != NULL) {
472 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 473 &i2c_bus->i2c_adap,
fc959bef
ST
474 &hauppauge_generic_tunerconfig, 0);
475 }
476 break;
9bc37caa 477 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 478 i2c_bus = &dev->i2c_bus[0];
363c35fc 479 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 480 &fusionhdtv_5_express,
f139fa71 481 &i2c_bus->i2c_adap);
363c35fc
ST
482 if (fe0->dvb.frontend != NULL) {
483 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
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MK
484 &i2c_bus->i2c_adap, 0x61,
485 TUNER_LG_TDVS_H06XF);
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MK
486 }
487 break;
d1987d55
ST
488 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
489 i2c_bus = &dev->i2c_bus[1];
363c35fc 490 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST
491 &hauppauge_hvr1500q_config,
492 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST
493 if (fe0->dvb.frontend != NULL)
494 dvb_attach(xc5000_attach, fe0->dvb.frontend,
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MK
495 &i2c_bus->i2c_adap,
496 &hauppauge_hvr1500q_tunerconfig);
d1987d55 497 break;
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MK
498 case CX23885_BOARD_HAUPPAUGE_HVR1500:
499 i2c_bus = &dev->i2c_bus[1];
363c35fc 500 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK
501 &hauppauge_hvr1500_config,
502 &dev->i2c_bus[0].i2c_adap);
363c35fc 503 if (fe0->dvb.frontend != NULL) {
07b4a835
MK
504 struct dvb_frontend *fe;
505 struct xc2028_config cfg = {
506 .i2c_adap = &i2c_bus->i2c_adap,
507 .i2c_addr = 0x61,
07b4a835
MK
508 };
509 static struct xc2028_ctrl ctl = {
ef80bfeb 510 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 511 .max_len = 64,
52c3d29c 512 .demod = XC3028_FE_OREN538,
07b4a835
MK
513 };
514
515 fe = dvb_attach(xc2028_attach,
363c35fc 516 fe0->dvb.frontend, &cfg);
07b4a835
MK
517 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
518 fe->ops.tuner_ops.set_config(fe, &ctl);
519 }
520 break;
b3ea0166 521 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 522 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 523 i2c_bus = &dev->i2c_bus[0];
363c35fc 524 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST
525 &hauppauge_hvr1200_config,
526 &i2c_bus->i2c_adap);
363c35fc
ST
527 if (fe0->dvb.frontend != NULL) {
528 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST
529 &dev->i2c_bus[1].i2c_adap, 0x42,
530 &tda829x_no_probe);
363c35fc 531 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST
532 0x60, &dev->i2c_bus[1].i2c_adap,
533 &hauppauge_hvr1200_tuner_config);
534 }
535 break;
66762373
ST
536 case CX23885_BOARD_HAUPPAUGE_HVR1400:
537 i2c_bus = &dev->i2c_bus[0];
363c35fc 538 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST
539 &i2c_bus->i2c_adap,
540 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 541 if (fe0->dvb.frontend != NULL) {
66762373
ST
542 struct dvb_frontend *fe;
543 struct xc2028_config cfg = {
544 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
545 .i2c_addr = 0x64,
66762373
ST
546 };
547 static struct xc2028_ctrl ctl = {
ef80bfeb 548 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST
549 .max_len = 64,
550 .demod = 5000,
9c8ced51
ST
551 /* This is true for all demods with
552 v36 firmware? */
0975fc68 553 .type = XC2028_D2633,
66762373
ST
554 };
555
556 fe = dvb_attach(xc2028_attach,
363c35fc 557 fe0->dvb.frontend, &cfg);
66762373
ST
558 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
559 fe->ops.tuner_ops.set_config(fe, &ctl);
560 }
561 break;
335377b7
MK
562 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
563 i2c_bus = &dev->i2c_bus[port->nr - 1];
564
363c35fc 565 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK
566 &dvico_s5h1409_config,
567 &i2c_bus->i2c_adap);
363c35fc
ST
568 if (fe0->dvb.frontend == NULL)
569 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK
570 &dvico_s5h1411_config,
571 &i2c_bus->i2c_adap);
363c35fc
ST
572 if (fe0->dvb.frontend != NULL)
573 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
574 &i2c_bus->i2c_adap,
575 &dvico_xc5000_tunerconfig);
335377b7 576 break;
aef2d186
ST
577 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
578 i2c_bus = &dev->i2c_bus[port->nr - 1];
579
363c35fc 580 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST
581 &dvico_fusionhdtv_xc3028,
582 &i2c_bus->i2c_adap);
363c35fc 583 if (fe0->dvb.frontend != NULL) {
aef2d186
ST
584 struct dvb_frontend *fe;
585 struct xc2028_config cfg = {
586 .i2c_adap = &i2c_bus->i2c_adap,
587 .i2c_addr = 0x61,
aef2d186
ST
588 };
589 static struct xc2028_ctrl ctl = {
ef80bfeb 590 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST
591 .max_len = 64,
592 .demod = XC3028_FE_ZARLINK456,
593 };
594
363c35fc 595 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST
596 &cfg);
597 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
598 fe->ops.tuner_ops.set_config(fe, &ctl);
599 }
600 break;
601 }
4c56b04a 602 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 603 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
4c56b04a
ST
604 i2c_bus = &dev->i2c_bus[0];
605
363c35fc 606 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST
607 &dvico_fusionhdtv_xc3028,
608 &i2c_bus->i2c_adap);
363c35fc 609 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST
610 struct dvb_frontend *fe;
611 struct xc2028_config cfg = {
612 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
613 .i2c_addr = 0x61,
4c56b04a
ST
614 };
615 static struct xc2028_ctrl ctl = {
ef80bfeb 616 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST
617 .max_len = 64,
618 .demod = XC3028_FE_ZARLINK456,
619 };
620
363c35fc 621 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST
622 &cfg);
623 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
624 fe->ops.tuner_ops.set_config(fe, &ctl);
625 }
96318d0c
IL
626 break;
627 case CX23885_BOARD_TBS_6920:
628 i2c_bus = &dev->i2c_bus[0];
629
630 fe0->dvb.frontend = dvb_attach(cx24116_attach,
631 &tbs_cx24116_config,
632 &i2c_bus->i2c_adap);
633 if (fe0->dvb.frontend != NULL)
634 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
635
579943f5
IL
636 break;
637 case CX23885_BOARD_TEVII_S470:
638 i2c_bus = &dev->i2c_bus[1];
639
640 fe0->dvb.frontend = dvb_attach(cx24116_attach,
641 &tevii_cx24116_config,
642 &i2c_bus->i2c_adap);
643 if (fe0->dvb.frontend != NULL)
644 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
645
4c56b04a 646 break;
c9b8b04b
IL
647 case CX23885_BOARD_DVBWORLD_2005:
648 i2c_bus = &dev->i2c_bus[1];
649
650 fe0->dvb.frontend = dvb_attach(cx24116_attach,
651 &dvbworld_cx24116_config,
652 &i2c_bus->i2c_adap);
653 break;
5a23b076
IL
654 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
655 i2c_bus = &dev->i2c_bus[0];
656 switch (port->nr) {
657 /* port B */
658 case 1:
659 fe0->dvb.frontend = dvb_attach(stv0900_attach,
660 &netup_stv0900_config,
661 &i2c_bus->i2c_adap, 0);
662 if (fe0->dvb.frontend != NULL) {
663 if (dvb_attach(stv6110_attach,
664 fe0->dvb.frontend,
665 &netup_stv6110_tunerconfig_a,
666 &i2c_bus->i2c_adap)) {
667 if (!dvb_attach(lnbh24_attach,
668 fe0->dvb.frontend,
669 &i2c_bus->i2c_adap,
670 LNBH24_PCL, 0, 0x09))
671 printk(KERN_ERR
672 "No LNBH24 found!\n");
673
674 }
675 }
676 break;
677 /* port C */
678 case 2:
679 fe0->dvb.frontend = dvb_attach(stv0900_attach,
680 &netup_stv0900_config,
681 &i2c_bus->i2c_adap, 1);
682 if (fe0->dvb.frontend != NULL) {
683 if (dvb_attach(stv6110_attach,
684 fe0->dvb.frontend,
685 &netup_stv6110_tunerconfig_b,
686 &i2c_bus->i2c_adap)) {
687 if (!dvb_attach(lnbh24_attach,
688 fe0->dvb.frontend,
689 &i2c_bus->i2c_adap,
690 LNBH24_PCL, 0, 0x0a))
691 printk(KERN_ERR
692 "No LNBH24 found!\n");
693
694 }
695 }
696 break;
697 }
698 break;
d19770e5 699 default:
9c8ced51
ST
700 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
701 " isn't supported yet\n",
d19770e5
ST
702 dev->name);
703 break;
704 }
363c35fc 705 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST
706 printk(KERN_ERR "%s: frontend initialization failed\n",
707 dev->name);
d19770e5
ST
708 return -1;
709 }
d7cba043 710 /* define general-purpose callback pointer */
363c35fc 711 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST
712
713 /* Put the analog decoder in standby to keep it quiet */
7c9fc9d5 714 call_all(dev, tuner, s_standby);
d19770e5 715
363c35fc
ST
716 if (fe0->dvb.frontend->ops.analog_ops.standby)
717 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 718
d19770e5 719 /* register everything */
5a23b076 720 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
59b1842d 721 &dev->pci->dev, adapter_nr, 0);
363c35fc 722
5a23b076
IL
723 /* init CI & MAC */
724 switch (dev->board) {
725 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
726 static struct netup_card_info cinfo;
727
728 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
729 memcpy(port->frontends.adapter.proposed_mac,
730 cinfo.port[port->nr - 1].mac, 6);
731 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
732 "%02X:%02X:%02X:%02X:%02X:%02X\n",
733 port->nr,
734 port->frontends.adapter.proposed_mac[0],
735 port->frontends.adapter.proposed_mac[1],
736 port->frontends.adapter.proposed_mac[2],
737 port->frontends.adapter.proposed_mac[3],
738 port->frontends.adapter.proposed_mac[4],
739 port->frontends.adapter.proposed_mac[5]);
740
741 netup_ci_init(port);
742 break;
743 }
744 }
745
746 return ret;
d19770e5
ST
747}
748
749int cx23885_dvb_register(struct cx23885_tsport *port)
750{
363c35fc
ST
751
752 struct videobuf_dvb_frontend *fe0;
d19770e5 753 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST
754 int err, i;
755
756 /* Here we need to allocate the correct number of frontends,
757 * as reflected in the cards struct. The reality is that currrently
758 * no cx23885 boards support this - yet. But, if we don't modify this
759 * code then the second frontend would never be allocated (later)
760 * and fail with error before the attach in dvb_register().
761 * Without these changes we risk an OOPS later. The changes here
762 * are for safety, and should provide a good foundation for the
763 * future addition of any multi-frontend cx23885 based boards.
764 */
765 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
766 port->num_frontends);
d19770e5 767
eb0c58bb 768 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 769 if (videobuf_dvb_alloc_frontend(
9c8ced51 770 &port->frontends, i) == NULL) {
eb0c58bb
ST
771 printk(KERN_ERR "%s() failed to alloc\n", __func__);
772 return -ENOMEM;
773 }
774
775 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
776 if (!fe0)
777 err = -EINVAL;
363c35fc 778
eb0c58bb 779 dprintk(1, "%s\n", __func__);
9c8ced51 780 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST
781 dev->board,
782 dev->name,
783 dev->pci_bus,
784 dev->pci_slot);
d19770e5 785
eb0c58bb 786 err = -ENODEV;
d19770e5 787
eb0c58bb
ST
788 /* dvb stuff */
789 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST
790 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
791 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
792 &dev->pci->dev, &port->slock,
44a6481d
MK
793 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
794 sizeof(struct cx23885_buffer), port);
eb0c58bb 795 }
d19770e5
ST
796 err = dvb_register(port);
797 if (err != 0)
9c8ced51
ST
798 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
799 __func__, err);
d19770e5 800
d19770e5
ST
801 return err;
802}
803
804int cx23885_dvb_unregister(struct cx23885_tsport *port)
805{
363c35fc
ST
806 struct videobuf_dvb_frontend *fe0;
807
eb0c58bb
ST
808 /* FIXME: in an error condition where the we have
809 * an expected number of frontends (attach problem)
810 * then this might not clean up correctly, if 1
811 * is invalid.
812 * This comment only applies to future boards IF they
813 * implement MFE support.
814 */
92abe9ee 815 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 816 if (fe0->dvb.frontend)
363c35fc 817 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 818
afd96668
HV
819 switch (port->dev->board) {
820 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
821 netup_ci_exit(port);
822 break;
823 }
5a23b076 824
d19770e5
ST
825 return 0;
826}
44a6481d 827
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