V4L/DVB (12310): stv6110 tuner: remove unused iq_wiring configuration parameter.
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
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1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
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5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
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31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
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44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076 47#include "stv0900.h"
f867c3f4 48#include "stv0900_reg.h"
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IL
49#include "stv6110.h"
50#include "lnbh24.h"
96318d0c 51#include "cx24116.h"
5a23b076 52#include "cimax2.h"
493b7127 53#include "lgs8gxx.h"
5a23b076
IL
54#include "netup-eeprom.h"
55#include "netup-init.h"
a5dbf457 56#include "lgdt3305.h"
d19770e5 57
4513fc69 58static unsigned int debug;
d19770e5 59
4513fc69
ST
60#define dprintk(level, fmt, arg...)\
61 do { if (debug >= level)\
62 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
63 } while (0)
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64
65/* ------------------------------------------------------------------ */
66
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67static unsigned int alt_tuner;
68module_param(alt_tuner, int, 0644);
69MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
70
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JG
71DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
72
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73/* ------------------------------------------------------------------ */
74
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75static int dvb_buf_setup(struct videobuf_queue *q,
76 unsigned int *count, unsigned int *size)
77{
78 struct cx23885_tsport *port = q->priv_data;
79
80 port->ts_packet_size = 188 * 4;
81 port->ts_packet_count = 32;
82
83 *size = port->ts_packet_size * port->ts_packet_count;
84 *count = 32;
85 return 0;
86}
87
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88static int dvb_buf_prepare(struct videobuf_queue *q,
89 struct videobuf_buffer *vb, enum v4l2_field field)
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90{
91 struct cx23885_tsport *port = q->priv_data;
9c8ced51 92 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
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93}
94
95static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
96{
97 struct cx23885_tsport *port = q->priv_data;
9c8ced51 98 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
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99}
100
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101static void dvb_buf_release(struct videobuf_queue *q,
102 struct videobuf_buffer *vb)
d19770e5 103{
9c8ced51 104 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
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105}
106
107static struct videobuf_queue_ops dvb_qops = {
108 .buf_setup = dvb_buf_setup,
109 .buf_prepare = dvb_buf_prepare,
110 .buf_queue = dvb_buf_queue,
111 .buf_release = dvb_buf_release,
112};
113
86184e06 114static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST
115 .demod_address = 0x32 >> 1,
116 .output_mode = S5H1409_SERIAL_OUTPUT,
117 .gpio = S5H1409_GPIO_ON,
2b03238a 118 .qam_if = 44000,
fc959bef 119 .inversion = S5H1409_INVERSION_OFF,
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120 .status_mode = S5H1409_DEMODLOCKING,
121 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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122};
123
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124static struct tda10048_config hauppauge_hvr1200_config = {
125 .demod_address = 0x10 >> 1,
126 .output_mode = TDA10048_SERIAL_OUTPUT,
127 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 128 .inversion = TDA10048_INVERSION_ON,
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129 .dtv6_if_freq_khz = TDA10048_IF_3300,
130 .dtv7_if_freq_khz = TDA10048_IF_3800,
131 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 132 .clk_freq_khz = TDA10048_CLK_16000,
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133};
134
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135static struct tda10048_config hauppauge_hvr1210_config = {
136 .demod_address = 0x10 >> 1,
137 .output_mode = TDA10048_SERIAL_OUTPUT,
138 .fwbulkwritelen = TDA10048_BULKWRITE_200,
139 .inversion = TDA10048_INVERSION_ON,
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140 .dtv6_if_freq_khz = TDA10048_IF_3300,
141 .dtv7_if_freq_khz = TDA10048_IF_3500,
142 .dtv8_if_freq_khz = TDA10048_IF_4000,
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143 .clk_freq_khz = TDA10048_CLK_16000,
144};
145
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146static struct s5h1409_config hauppauge_ezqam_config = {
147 .demod_address = 0x32 >> 1,
148 .output_mode = S5H1409_SERIAL_OUTPUT,
149 .gpio = S5H1409_GPIO_OFF,
150 .qam_if = 4000,
151 .inversion = S5H1409_INVERSION_ON,
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152 .status_mode = S5H1409_DEMODLOCKING,
153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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154};
155
fc959bef 156static struct s5h1409_config hauppauge_hvr1800lp_config = {
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157 .demod_address = 0x32 >> 1,
158 .output_mode = S5H1409_SERIAL_OUTPUT,
159 .gpio = S5H1409_GPIO_OFF,
2b03238a 160 .qam_if = 44000,
fe475163 161 .inversion = S5H1409_INVERSION_OFF,
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162 .status_mode = S5H1409_DEMODLOCKING,
163 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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164};
165
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166static struct s5h1409_config hauppauge_hvr1500_config = {
167 .demod_address = 0x32 >> 1,
168 .output_mode = S5H1409_SERIAL_OUTPUT,
169 .gpio = S5H1409_GPIO_OFF,
170 .inversion = S5H1409_INVERSION_OFF,
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171 .status_mode = S5H1409_DEMODLOCKING,
172 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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173};
174
86184e06 175static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
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176 0x61
177};
178
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179static struct lgdt330x_config fusionhdtv_5_express = {
180 .demod_address = 0x0e,
181 .demod_chip = LGDT3303,
182 .serial_mpeg = 0x40,
183};
184
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185static struct s5h1409_config hauppauge_hvr1500q_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_ON,
189 .qam_if = 44000,
190 .inversion = S5H1409_INVERSION_OFF,
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191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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193};
194
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195static struct s5h1409_config dvico_s5h1409_config = {
196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_ON,
199 .qam_if = 44000,
200 .inversion = S5H1409_INVERSION_OFF,
201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
203};
204
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205static struct s5h1411_config dvico_s5h1411_config = {
206 .output_mode = S5H1411_SERIAL_OUTPUT,
207 .gpio = S5H1411_GPIO_ON,
208 .qam_if = S5H1411_IF_44000,
209 .vsb_if = S5H1411_IF_44000,
210 .inversion = S5H1411_INVERSION_OFF,
211 .status_mode = S5H1411_DEMODLOCKING,
212 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
213};
214
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215static struct s5h1411_config hcw_s5h1411_config = {
216 .output_mode = S5H1411_SERIAL_OUTPUT,
217 .gpio = S5H1411_GPIO_OFF,
218 .vsb_if = S5H1411_IF_44000,
219 .qam_if = S5H1411_IF_4000,
220 .inversion = S5H1411_INVERSION_ON,
221 .status_mode = S5H1411_DEMODLOCKING,
222 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
223};
224
d1987d55 225static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
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226 .i2c_address = 0x61,
227 .if_khz = 5380,
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228};
229
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230static struct xc5000_config dvico_xc5000_tunerconfig = {
231 .i2c_address = 0x64,
232 .if_khz = 5380,
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233};
234
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235static struct tda829x_config tda829x_no_probe = {
236 .probe_tuner = TDA829X_DONT_PROBE,
237};
238
f21e0d7f 239static struct tda18271_std_map hauppauge_tda18271_std_map = {
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240 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
241 .if_lvl = 6, .rfagc_top = 0x37 },
242 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
243 .if_lvl = 6, .rfagc_top = 0x37 },
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244};
245
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246static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
247 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
248 .if_lvl = 1, .rfagc_top = 0x37, },
249 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
250 .if_lvl = 1, .rfagc_top = 0x37, },
251 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
252 .if_lvl = 1, .rfagc_top = 0x37, },
253};
254
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255static struct tda18271_config hauppauge_tda18271_config = {
256 .std_map = &hauppauge_tda18271_std_map,
257 .gate = TDA18271_GATE_ANALOG,
258};
259
b3ea0166 260static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 261 .std_map = &hauppauge_hvr1200_tda18271_std_map,
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262 .gate = TDA18271_GATE_ANALOG,
263};
264
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265static struct tda18271_config hauppauge_hvr1210_tuner_config = {
266 .gate = TDA18271_GATE_DIGITAL,
267};
268
247bc540 269static struct tda18271_std_map hauppauge_hvr127x_std_map = {
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270 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
271 .if_lvl = 1, .rfagc_top = 0x58 },
272 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
273 .if_lvl = 1, .rfagc_top = 0x58 },
274};
275
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MK
276static struct tda18271_config hauppauge_hvr127x_config = {
277 .std_map = &hauppauge_hvr127x_std_map,
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278};
279
247bc540 280static struct lgdt3305_config hauppauge_lgdt3305_config = {
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281 .i2c_addr = 0x0e,
282 .mpeg_mode = LGDT3305_MPEG_SERIAL,
283 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
284 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
285 .deny_i2c_rptr = 1,
286 .spectral_inversion = 1,
287 .qam_if_khz = 4000,
288 .vsb_if_khz = 3250,
289};
290
b1721d0d 291static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST
292 BAND_VHF | BAND_UHF, /* band_caps */
293
294 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
295 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
296 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
297 * P_agc_nb_est=2, P_agc_write=0
298 */
299 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
300 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
301
302 712, /* inv_gain */
303 21, /* time_stabiliz */
304
305 0, /* alpha_level */
306 118, /* thlock */
307
308 0, /* wbd_inv */
309 2867, /* wbd_ref */
310 0, /* wbd_sel */
311 2, /* wbd_alpha */
312
313 0, /* agc1_max */
314 0, /* agc1_min */
315 39718, /* agc2_max */
316 9930, /* agc2_min */
317 0, /* agc1_pt1 */
318 0, /* agc1_pt2 */
319 0, /* agc1_pt3 */
320 0, /* agc1_slope1 */
321 0, /* agc1_slope2 */
322 0, /* agc2_pt1 */
323 128, /* agc2_pt2 */
324 29, /* agc2_slope1 */
325 29, /* agc2_slope2 */
326
327 17, /* alpha_mant */
328 27, /* alpha_exp */
329 23, /* beta_mant */
330 51, /* beta_exp */
331
332 1, /* perform_agc_softsplit */
333};
334
335/* PLL Configuration for COFDM BW_MHz = 8.000000
336 * With external clock = 30.000000 */
b1721d0d 337static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST
338 60000, /* internal */
339 30000, /* sampling */
340 1, /* pll_cfg: prediv */
341 8, /* pll_cfg: ratio */
342 3, /* pll_cfg: range */
343 1, /* pll_cfg: reset */
344 0, /* pll_cfg: bypass */
345 0, /* misc: refdiv */
346 0, /* misc: bypclk_div */
347 1, /* misc: IO_CLK_en_core */
348 1, /* misc: ADClkSrc */
349 0, /* misc: modulo */
350 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
351 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
352 20452225, /* timf */
353 30000000 /* xtal_hz */
354};
355
356static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
357 .output_mpeg2_in_188_bytes = 1,
358 .hostbus_diversity = 1,
359 .tuner_is_baseband = 0,
360 .update_lna = NULL,
361
362 .agc_config_count = 1,
363 .agc = &xc3028_agc_config,
364 .bw = &xc3028_bw_config,
365
366 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
367 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
368 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
369
370 .pwm_freq_div = 0,
371 .agc_control = NULL,
372 .spur_protect = 0,
373
374 .output_mode = OUTMODE_MPEG2_SERIAL,
375};
376
aef2d186
ST
377static struct zl10353_config dvico_fusionhdtv_xc3028 = {
378 .demod_address = 0x0f,
379 .if2 = 45600,
380 .no_tuner = 1,
d4dc673d 381 .disable_i2c_gate_ctrl = 1,
aef2d186
ST
382};
383
f867c3f4
IL
384static struct stv0900_reg stv0900_ts_regs[] = {
385 { R0900_TSGENERAL, 0x00 },
386 { R0900_P1_TSSPEED, 0x40 },
387 { R0900_P2_TSSPEED, 0x40 },
388 { R0900_P1_TSCFGM, 0xc0 },
389 { R0900_P2_TSCFGM, 0xc0 },
390 { R0900_P1_TSCFGH, 0xe0 },
391 { R0900_P2_TSCFGH, 0xe0 },
392 { R0900_P1_TSCFGL, 0x20 },
393 { R0900_P2_TSCFGL, 0x20 },
394 { 0xffff, 0xff }, /* terminate */
395};
396
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IL
397static struct stv0900_config netup_stv0900_config = {
398 .demod_address = 0x68,
399 .xtal = 27000000,
400 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
401 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 402 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL
403 .tun1_maddress = 0,/* 0x60 */
404 .tun2_maddress = 3,/* 0x63 */
405 .tun1_adc = 1,/* 1 Vpp */
406 .tun2_adc = 1,/* 1 Vpp */
407};
408
409static struct stv6110_config netup_stv6110_tunerconfig_a = {
410 .i2c_address = 0x60,
411 .mclk = 27000000,
5a23b076
IL
412};
413
414static struct stv6110_config netup_stv6110_tunerconfig_b = {
415 .i2c_address = 0x63,
416 .mclk = 27000000,
5a23b076
IL
417};
418
96318d0c
IL
419static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
420{
421 struct cx23885_tsport *port = fe->dvb->priv;
422 struct cx23885_dev *dev = port->dev;
423
424 if (voltage == SEC_VOLTAGE_18)
425 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
426 else if (voltage == SEC_VOLTAGE_13)
427 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
428 else
429 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
430 return 0;
431}
432
433static struct cx24116_config tbs_cx24116_config = {
434 .demod_address = 0x05,
435};
436
579943f5
IL
437static struct cx24116_config tevii_cx24116_config = {
438 .demod_address = 0x55,
439};
440
c9b8b04b
IL
441static struct cx24116_config dvbworld_cx24116_config = {
442 .demod_address = 0x05,
443};
444
493b7127
DW
445static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
446 .prod = LGS8GXX_PROD_LGS8GL5,
447 .demod_address = 0x19,
448 .serial_ts = 0,
449 .ts_clk_pol = 1,
450 .ts_clk_gated = 1,
451 .if_clk_freq = 30400, /* 30.4 MHz */
452 .if_freq = 5380, /* 5.38 MHz */
453 .if_neg_center = 1,
454 .ext_adc = 0,
455 .adc_signed = 0,
456 .if_neg_edge = 0,
457};
458
459static struct xc5000_config mygica_x8506_xc5000_config = {
460 .i2c_address = 0x61,
461 .if_khz = 5380,
462};
463
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MK
464static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
465 struct dvb_frontend_parameters *param)
466{
467 struct cx23885_tsport *port = fe->dvb->priv;
468 struct cx23885_dev *dev = port->dev;
469
470 switch (dev->board) {
471 case CX23885_BOARD_HAUPPAUGE_HVR1275:
472 switch (param->u.vsb.modulation) {
473 case VSB_8:
474 cx23885_gpio_clear(dev, GPIO_5);
475 break;
476 case QAM_64:
477 case QAM_256:
478 default:
479 cx23885_gpio_set(dev, GPIO_5);
480 break;
481 }
482 break;
483 }
484 return (port->set_frontend_save) ?
485 port->set_frontend_save(fe, param) : -ENODEV;
486}
487
2365b2d3
DW
488static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
489 .prod = LGS8GXX_PROD_LGS8G75,
490 .demod_address = 0x19,
491 .serial_ts = 0,
492 .ts_clk_pol = 1,
493 .ts_clk_gated = 1,
494 .if_clk_freq = 30400, /* 30.4 MHz */
495 .if_freq = 6500, /* 6.50 MHz */
496 .if_neg_center = 1,
497 .ext_adc = 0,
498 .adc_signed = 1,
499 .adc_vpp = 2, /* 1.6 Vpp */
500 .if_neg_edge = 1,
501};
502
503static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
504 .i2c_address = 0x61,
505 .if_khz = 6500,
506};
507
d19770e5
ST
508static int dvb_register(struct cx23885_tsport *port)
509{
510 struct cx23885_dev *dev = port->dev;
493b7127 511 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
363c35fc 512 struct videobuf_dvb_frontend *fe0;
5a23b076 513 int ret;
363c35fc 514
f972e0bd 515 /* Get the first frontend */
92abe9ee 516 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST
517 if (!fe0)
518 return -EINVAL;
d19770e5
ST
519
520 /* init struct videobuf_dvb */
363c35fc 521 fe0->dvb.name = dev->name;
d19770e5
ST
522
523 /* init frontend */
524 switch (dev->board) {
a77743bc 525 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 526 i2c_bus = &dev->i2c_bus[0];
363c35fc 527 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 528 &hauppauge_generic_config,
f139fa71 529 &i2c_bus->i2c_adap);
363c35fc
ST
530 if (fe0->dvb.frontend != NULL) {
531 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 532 &i2c_bus->i2c_adap,
86184e06 533 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST
534 }
535 break;
a5dbf457 536 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 537 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK
538 i2c_bus = &dev->i2c_bus[0];
539 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 540 &hauppauge_lgdt3305_config,
a5dbf457
MK
541 &i2c_bus->i2c_adap);
542 if (fe0->dvb.frontend != NULL) {
543 dvb_attach(tda18271_attach, fe0->dvb.frontend,
544 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 545 &hauppauge_hvr127x_config);
a5dbf457 546 }
f35b9e80 547
b179bc45 548 /* FIXME: temporary hack */
f35b9e80
MK
549 /* define bridge override to set_frontend */
550 port->set_frontend_save = fe0->dvb.frontend->ops.set_frontend;
551 fe0->dvb.frontend->ops.set_frontend = cx23885_dvb_set_frontend;
552
a5dbf457 553 break;
19bc5796
MK
554 case CX23885_BOARD_HAUPPAUGE_HVR1255:
555 i2c_bus = &dev->i2c_bus[0];
556 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
557 &hcw_s5h1411_config,
558 &i2c_bus->i2c_adap);
559 if (fe0->dvb.frontend != NULL) {
560 dvb_attach(tda18271_attach, fe0->dvb.frontend,
561 0x60, &dev->i2c_bus[1].i2c_adap,
562 &hauppauge_tda18271_config);
563 }
564 break;
3ba71d21
MK
565 case CX23885_BOARD_HAUPPAUGE_HVR1800:
566 i2c_bus = &dev->i2c_bus[0];
92abe9ee 567 switch (alt_tuner) {
3ba71d21 568 case 1:
363c35fc 569 fe0->dvb.frontend =
3ba71d21
MK
570 dvb_attach(s5h1409_attach,
571 &hauppauge_ezqam_config,
572 &i2c_bus->i2c_adap);
363c35fc
ST
573 if (fe0->dvb.frontend != NULL) {
574 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 575 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 576 &tda829x_no_probe);
363c35fc 577 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 578 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 579 &hauppauge_tda18271_config);
3ba71d21
MK
580 }
581 break;
582 case 0:
583 default:
363c35fc 584 fe0->dvb.frontend =
3ba71d21
MK
585 dvb_attach(s5h1409_attach,
586 &hauppauge_generic_config,
587 &i2c_bus->i2c_adap);
363c35fc
ST
588 if (fe0->dvb.frontend != NULL)
589 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK
590 &i2c_bus->i2c_adap,
591 &hauppauge_generic_tunerconfig, 0);
592 break;
593 }
594 break;
fc959bef 595 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 596 i2c_bus = &dev->i2c_bus[0];
363c35fc 597 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 598 &hauppauge_hvr1800lp_config,
f139fa71 599 &i2c_bus->i2c_adap);
363c35fc
ST
600 if (fe0->dvb.frontend != NULL) {
601 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 602 &i2c_bus->i2c_adap,
fc959bef
ST
603 &hauppauge_generic_tunerconfig, 0);
604 }
605 break;
9bc37caa 606 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 607 i2c_bus = &dev->i2c_bus[0];
363c35fc 608 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 609 &fusionhdtv_5_express,
f139fa71 610 &i2c_bus->i2c_adap);
363c35fc
ST
611 if (fe0->dvb.frontend != NULL) {
612 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK
613 &i2c_bus->i2c_adap, 0x61,
614 TUNER_LG_TDVS_H06XF);
9bc37caa
MK
615 }
616 break;
d1987d55
ST
617 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
618 i2c_bus = &dev->i2c_bus[1];
363c35fc 619 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST
620 &hauppauge_hvr1500q_config,
621 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST
622 if (fe0->dvb.frontend != NULL)
623 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
624 &i2c_bus->i2c_adap,
625 &hauppauge_hvr1500q_tunerconfig);
d1987d55 626 break;
07b4a835
MK
627 case CX23885_BOARD_HAUPPAUGE_HVR1500:
628 i2c_bus = &dev->i2c_bus[1];
363c35fc 629 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK
630 &hauppauge_hvr1500_config,
631 &dev->i2c_bus[0].i2c_adap);
363c35fc 632 if (fe0->dvb.frontend != NULL) {
07b4a835
MK
633 struct dvb_frontend *fe;
634 struct xc2028_config cfg = {
635 .i2c_adap = &i2c_bus->i2c_adap,
636 .i2c_addr = 0x61,
07b4a835
MK
637 };
638 static struct xc2028_ctrl ctl = {
ef80bfeb 639 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 640 .max_len = 64,
52c3d29c 641 .demod = XC3028_FE_OREN538,
07b4a835
MK
642 };
643
644 fe = dvb_attach(xc2028_attach,
363c35fc 645 fe0->dvb.frontend, &cfg);
07b4a835
MK
646 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
647 fe->ops.tuner_ops.set_config(fe, &ctl);
648 }
649 break;
b3ea0166 650 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 651 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 652 i2c_bus = &dev->i2c_bus[0];
363c35fc 653 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST
654 &hauppauge_hvr1200_config,
655 &i2c_bus->i2c_adap);
363c35fc
ST
656 if (fe0->dvb.frontend != NULL) {
657 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST
658 &dev->i2c_bus[1].i2c_adap, 0x42,
659 &tda829x_no_probe);
363c35fc 660 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST
661 0x60, &dev->i2c_bus[1].i2c_adap,
662 &hauppauge_hvr1200_tuner_config);
6b926eca
MK
663 }
664 break;
665 case CX23885_BOARD_HAUPPAUGE_HVR1210:
666 i2c_bus = &dev->i2c_bus[0];
667 fe0->dvb.frontend = dvb_attach(tda10048_attach,
668 &hauppauge_hvr1210_config,
669 &i2c_bus->i2c_adap);
670 if (fe0->dvb.frontend != NULL) {
671 dvb_attach(tda18271_attach, fe0->dvb.frontend,
672 0x60, &dev->i2c_bus[1].i2c_adap,
673 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST
674 }
675 break;
66762373
ST
676 case CX23885_BOARD_HAUPPAUGE_HVR1400:
677 i2c_bus = &dev->i2c_bus[0];
363c35fc 678 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST
679 &i2c_bus->i2c_adap,
680 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 681 if (fe0->dvb.frontend != NULL) {
66762373
ST
682 struct dvb_frontend *fe;
683 struct xc2028_config cfg = {
684 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
685 .i2c_addr = 0x64,
66762373
ST
686 };
687 static struct xc2028_ctrl ctl = {
ef80bfeb 688 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST
689 .max_len = 64,
690 .demod = 5000,
9c8ced51
ST
691 /* This is true for all demods with
692 v36 firmware? */
0975fc68 693 .type = XC2028_D2633,
66762373
ST
694 };
695
696 fe = dvb_attach(xc2028_attach,
363c35fc 697 fe0->dvb.frontend, &cfg);
66762373
ST
698 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
699 fe->ops.tuner_ops.set_config(fe, &ctl);
700 }
701 break;
335377b7
MK
702 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
703 i2c_bus = &dev->i2c_bus[port->nr - 1];
704
363c35fc 705 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK
706 &dvico_s5h1409_config,
707 &i2c_bus->i2c_adap);
363c35fc
ST
708 if (fe0->dvb.frontend == NULL)
709 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK
710 &dvico_s5h1411_config,
711 &i2c_bus->i2c_adap);
363c35fc
ST
712 if (fe0->dvb.frontend != NULL)
713 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
714 &i2c_bus->i2c_adap,
715 &dvico_xc5000_tunerconfig);
335377b7 716 break;
aef2d186
ST
717 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
718 i2c_bus = &dev->i2c_bus[port->nr - 1];
719
363c35fc 720 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST
721 &dvico_fusionhdtv_xc3028,
722 &i2c_bus->i2c_adap);
363c35fc 723 if (fe0->dvb.frontend != NULL) {
aef2d186
ST
724 struct dvb_frontend *fe;
725 struct xc2028_config cfg = {
726 .i2c_adap = &i2c_bus->i2c_adap,
727 .i2c_addr = 0x61,
aef2d186
ST
728 };
729 static struct xc2028_ctrl ctl = {
ef80bfeb 730 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST
731 .max_len = 64,
732 .demod = XC3028_FE_ZARLINK456,
733 };
734
363c35fc 735 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST
736 &cfg);
737 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
738 fe->ops.tuner_ops.set_config(fe, &ctl);
739 }
740 break;
741 }
4c56b04a 742 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 743 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
4c56b04a
ST
744 i2c_bus = &dev->i2c_bus[0];
745
363c35fc 746 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST
747 &dvico_fusionhdtv_xc3028,
748 &i2c_bus->i2c_adap);
363c35fc 749 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST
750 struct dvb_frontend *fe;
751 struct xc2028_config cfg = {
752 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
753 .i2c_addr = 0x61,
4c56b04a
ST
754 };
755 static struct xc2028_ctrl ctl = {
ef80bfeb 756 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST
757 .max_len = 64,
758 .demod = XC3028_FE_ZARLINK456,
759 };
760
363c35fc 761 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST
762 &cfg);
763 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
764 fe->ops.tuner_ops.set_config(fe, &ctl);
765 }
96318d0c
IL
766 break;
767 case CX23885_BOARD_TBS_6920:
768 i2c_bus = &dev->i2c_bus[0];
769
770 fe0->dvb.frontend = dvb_attach(cx24116_attach,
771 &tbs_cx24116_config,
772 &i2c_bus->i2c_adap);
773 if (fe0->dvb.frontend != NULL)
774 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
775
579943f5
IL
776 break;
777 case CX23885_BOARD_TEVII_S470:
778 i2c_bus = &dev->i2c_bus[1];
779
780 fe0->dvb.frontend = dvb_attach(cx24116_attach,
781 &tevii_cx24116_config,
782 &i2c_bus->i2c_adap);
783 if (fe0->dvb.frontend != NULL)
784 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
785
4c56b04a 786 break;
c9b8b04b
IL
787 case CX23885_BOARD_DVBWORLD_2005:
788 i2c_bus = &dev->i2c_bus[1];
789
790 fe0->dvb.frontend = dvb_attach(cx24116_attach,
791 &dvbworld_cx24116_config,
792 &i2c_bus->i2c_adap);
793 break;
5a23b076
IL
794 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
795 i2c_bus = &dev->i2c_bus[0];
796 switch (port->nr) {
797 /* port B */
798 case 1:
799 fe0->dvb.frontend = dvb_attach(stv0900_attach,
800 &netup_stv0900_config,
801 &i2c_bus->i2c_adap, 0);
802 if (fe0->dvb.frontend != NULL) {
803 if (dvb_attach(stv6110_attach,
804 fe0->dvb.frontend,
805 &netup_stv6110_tunerconfig_a,
806 &i2c_bus->i2c_adap)) {
807 if (!dvb_attach(lnbh24_attach,
808 fe0->dvb.frontend,
809 &i2c_bus->i2c_adap,
0cde9b25
IL
810 LNBH24_PCL,
811 LNBH24_TTX, 0x09))
5a23b076
IL
812 printk(KERN_ERR
813 "No LNBH24 found!\n");
814
815 }
816 }
817 break;
818 /* port C */
819 case 2:
820 fe0->dvb.frontend = dvb_attach(stv0900_attach,
821 &netup_stv0900_config,
822 &i2c_bus->i2c_adap, 1);
823 if (fe0->dvb.frontend != NULL) {
824 if (dvb_attach(stv6110_attach,
825 fe0->dvb.frontend,
826 &netup_stv6110_tunerconfig_b,
827 &i2c_bus->i2c_adap)) {
828 if (!dvb_attach(lnbh24_attach,
829 fe0->dvb.frontend,
830 &i2c_bus->i2c_adap,
0cde9b25
IL
831 LNBH24_PCL,
832 LNBH24_TTX, 0x0a))
5a23b076
IL
833 printk(KERN_ERR
834 "No LNBH24 found!\n");
835
836 }
837 }
838 break;
839 }
840 break;
493b7127
DW
841 case CX23885_BOARD_MYGICA_X8506:
842 i2c_bus = &dev->i2c_bus[0];
843 i2c_bus2 = &dev->i2c_bus[1];
844 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
845 &mygica_x8506_lgs8gl5_config,
846 &i2c_bus->i2c_adap);
847 if (fe0->dvb.frontend != NULL) {
848 dvb_attach(xc5000_attach,
849 fe0->dvb.frontend,
850 &i2c_bus2->i2c_adap,
851 &mygica_x8506_xc5000_config);
852 }
853 break;
2365b2d3
DW
854 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
855 i2c_bus = &dev->i2c_bus[0];
856 i2c_bus2 = &dev->i2c_bus[1];
857 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
858 &magicpro_prohdtve2_lgs8g75_config,
859 &i2c_bus->i2c_adap);
860 if (fe0->dvb.frontend != NULL) {
861 dvb_attach(xc5000_attach,
862 fe0->dvb.frontend,
863 &i2c_bus2->i2c_adap,
864 &magicpro_prohdtve2_xc5000_config);
865 }
866 break;
13697380
ST
867 case CX23885_BOARD_HAUPPAUGE_HVR1850:
868 i2c_bus = &dev->i2c_bus[0];
869 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
870 &hcw_s5h1411_config,
871 &i2c_bus->i2c_adap);
872 if (fe0->dvb.frontend != NULL)
873 dvb_attach(tda18271_attach, fe0->dvb.frontend,
874 0x60, &dev->i2c_bus[0].i2c_adap,
875 &hauppauge_tda18271_config);
876 break;
877
d19770e5 878 default:
9c8ced51
ST
879 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
880 " isn't supported yet\n",
d19770e5
ST
881 dev->name);
882 break;
883 }
363c35fc 884 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST
885 printk(KERN_ERR "%s: frontend initialization failed\n",
886 dev->name);
d19770e5
ST
887 return -1;
888 }
d7cba043 889 /* define general-purpose callback pointer */
363c35fc 890 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST
891
892 /* Put the analog decoder in standby to keep it quiet */
7c9fc9d5 893 call_all(dev, tuner, s_standby);
d19770e5 894
363c35fc
ST
895 if (fe0->dvb.frontend->ops.analog_ops.standby)
896 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 897
d19770e5 898 /* register everything */
5a23b076 899 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
59b1842d 900 &dev->pci->dev, adapter_nr, 0);
363c35fc 901
5a23b076
IL
902 /* init CI & MAC */
903 switch (dev->board) {
904 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
905 static struct netup_card_info cinfo;
906
907 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
908 memcpy(port->frontends.adapter.proposed_mac,
909 cinfo.port[port->nr - 1].mac, 6);
910 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
911 "%02X:%02X:%02X:%02X:%02X:%02X\n",
912 port->nr,
913 port->frontends.adapter.proposed_mac[0],
914 port->frontends.adapter.proposed_mac[1],
915 port->frontends.adapter.proposed_mac[2],
916 port->frontends.adapter.proposed_mac[3],
917 port->frontends.adapter.proposed_mac[4],
918 port->frontends.adapter.proposed_mac[5]);
919
920 netup_ci_init(port);
921 break;
922 }
923 }
924
925 return ret;
d19770e5
ST
926}
927
928int cx23885_dvb_register(struct cx23885_tsport *port)
929{
363c35fc
ST
930
931 struct videobuf_dvb_frontend *fe0;
d19770e5 932 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST
933 int err, i;
934
935 /* Here we need to allocate the correct number of frontends,
936 * as reflected in the cards struct. The reality is that currrently
937 * no cx23885 boards support this - yet. But, if we don't modify this
938 * code then the second frontend would never be allocated (later)
939 * and fail with error before the attach in dvb_register().
940 * Without these changes we risk an OOPS later. The changes here
941 * are for safety, and should provide a good foundation for the
942 * future addition of any multi-frontend cx23885 based boards.
943 */
944 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
945 port->num_frontends);
d19770e5 946
eb0c58bb 947 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 948 if (videobuf_dvb_alloc_frontend(
9c8ced51 949 &port->frontends, i) == NULL) {
eb0c58bb
ST
950 printk(KERN_ERR "%s() failed to alloc\n", __func__);
951 return -ENOMEM;
952 }
953
954 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
955 if (!fe0)
956 err = -EINVAL;
363c35fc 957
eb0c58bb 958 dprintk(1, "%s\n", __func__);
9c8ced51 959 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST
960 dev->board,
961 dev->name,
962 dev->pci_bus,
963 dev->pci_slot);
d19770e5 964
eb0c58bb 965 err = -ENODEV;
d19770e5 966
eb0c58bb
ST
967 /* dvb stuff */
968 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST
969 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
970 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
971 &dev->pci->dev, &port->slock,
44a6481d
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972 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
973 sizeof(struct cx23885_buffer), port);
eb0c58bb 974 }
d19770e5
ST
975 err = dvb_register(port);
976 if (err != 0)
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ST
977 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
978 __func__, err);
d19770e5 979
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ST
980 return err;
981}
982
983int cx23885_dvb_unregister(struct cx23885_tsport *port)
984{
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ST
985 struct videobuf_dvb_frontend *fe0;
986
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ST
987 /* FIXME: in an error condition where the we have
988 * an expected number of frontends (attach problem)
989 * then this might not clean up correctly, if 1
990 * is invalid.
991 * This comment only applies to future boards IF they
992 * implement MFE support.
993 */
92abe9ee 994 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 995 if (fe0->dvb.frontend)
363c35fc 996 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 997
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HV
998 switch (port->dev->board) {
999 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1000 netup_ci_exit(port);
1001 break;
1002 }
5a23b076 1003
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ST
1004 return 0;
1005}
44a6481d 1006
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