Commit | Line | Data |
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d19770e5 ST |
1 | /* |
2 | * Driver for the Conexant CX23885 PCIe bridge | |
3 | * | |
6d897616 | 4 | * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> |
d19770e5 ST |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/pci.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/i2c-algo-bit.h> | |
25 | #include <linux/kdev_t.h> | |
26 | ||
c0714f6c | 27 | #include <media/v4l2-device.h> |
d19770e5 ST |
28 | #include <media/tuner.h> |
29 | #include <media/tveeprom.h> | |
409d84f8 TP |
30 | #include <media/videobuf-dma-sg.h> |
31 | #include <media/videobuf-dvb.h> | |
d19770e5 ST |
32 | |
33 | #include "btcx-risc.h" | |
34 | #include "cx23885-reg.h" | |
b1b81f1d | 35 | #include "media/cx2341x.h" |
d19770e5 ST |
36 | |
37 | #include <linux/version.h> | |
38 | #include <linux/mutex.h> | |
39 | ||
3ff4ad81 | 40 | #define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2) |
d19770e5 ST |
41 | |
42 | #define UNSET (-1U) | |
43 | ||
44 | #define CX23885_MAXBOARDS 8 | |
45 | ||
d19770e5 ST |
46 | /* Max number of inputs by card */ |
47 | #define MAX_CX23885_INPUT 8 | |
7b888014 ST |
48 | #define INPUT(nr) (&cx23885_boards[dev->board].input[nr]) |
49 | #define RESOURCE_OVERLAY 1 | |
50 | #define RESOURCE_VIDEO 2 | |
51 | #define RESOURCE_VBI 4 | |
d19770e5 | 52 | |
d19770e5 ST |
53 | #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */ |
54 | ||
55 | #define CX23885_BOARD_NOAUTO UNSET | |
56 | #define CX23885_BOARD_UNKNOWN 0 | |
57 | #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1 | |
58 | #define CX23885_BOARD_HAUPPAUGE_HVR1800 2 | |
a77743bc | 59 | #define CX23885_BOARD_HAUPPAUGE_HVR1250 3 |
9bc37caa | 60 | #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4 |
d1987d55 | 61 | #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5 |
07b4a835 | 62 | #define CX23885_BOARD_HAUPPAUGE_HVR1500 6 |
b3ea0166 | 63 | #define CX23885_BOARD_HAUPPAUGE_HVR1200 7 |
a780a31c | 64 | #define CX23885_BOARD_HAUPPAUGE_HVR1700 8 |
66762373 | 65 | #define CX23885_BOARD_HAUPPAUGE_HVR1400 9 |
335377b7 | 66 | #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10 |
aef2d186 | 67 | #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11 |
4c56b04a | 68 | #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12 |
9bb1b7e8 | 69 | #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13 |
96318d0c | 70 | #define CX23885_BOARD_TBS_6920 14 |
579943f5 | 71 | #define CX23885_BOARD_TEVII_S470 15 |
c9b8b04b | 72 | #define CX23885_BOARD_DVBWORLD_2005 16 |
5a23b076 | 73 | #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17 |
2074dffa | 74 | #define CX23885_BOARD_HAUPPAUGE_HVR1270 18 |
d099becb | 75 | #define CX23885_BOARD_HAUPPAUGE_HVR1275 19 |
19bc5796 | 76 | #define CX23885_BOARD_HAUPPAUGE_HVR1255 20 |
6b926eca | 77 | #define CX23885_BOARD_HAUPPAUGE_HVR1210 21 |
493b7127 | 78 | #define CX23885_BOARD_MYGICA_X8506 22 |
2365b2d3 | 79 | #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23 |
d19770e5 | 80 | |
6f8bee9b ST |
81 | #define GPIO_0 0x00000001 |
82 | #define GPIO_1 0x00000002 | |
83 | #define GPIO_2 0x00000004 | |
84 | #define GPIO_3 0x00000008 | |
85 | #define GPIO_4 0x00000010 | |
86 | #define GPIO_5 0x00000020 | |
87 | #define GPIO_6 0x00000040 | |
88 | #define GPIO_7 0x00000080 | |
89 | #define GPIO_8 0x00000100 | |
90 | #define GPIO_9 0x00000200 | |
f659c513 ST |
91 | #define GPIO_10 0x00000400 |
92 | #define GPIO_11 0x00000800 | |
93 | #define GPIO_12 0x00001000 | |
94 | #define GPIO_13 0x00002000 | |
95 | #define GPIO_14 0x00004000 | |
96 | #define GPIO_15 0x00008000 | |
6f8bee9b | 97 | |
7b888014 ST |
98 | /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */ |
99 | #define CX23885_NORMS (\ | |
100 | V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \ | |
101 | V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \ | |
102 | V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \ | |
103 | V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK) | |
104 | ||
105 | struct cx23885_fmt { | |
106 | char *name; | |
107 | u32 fourcc; /* v4l2 format id */ | |
108 | int depth; | |
109 | int flags; | |
110 | u32 cxformat; | |
111 | }; | |
112 | ||
113 | struct cx23885_ctrl { | |
114 | struct v4l2_queryctrl v; | |
115 | u32 off; | |
116 | u32 reg; | |
117 | u32 mask; | |
118 | u32 shift; | |
119 | }; | |
120 | ||
121 | struct cx23885_tvnorm { | |
122 | char *name; | |
123 | v4l2_std_id id; | |
124 | u32 cxiformat; | |
125 | u32 cxoformat; | |
126 | }; | |
127 | ||
128 | struct cx23885_fh { | |
129 | struct cx23885_dev *dev; | |
130 | enum v4l2_buf_type type; | |
131 | int radio; | |
132 | u32 resources; | |
133 | ||
134 | /* video overlay */ | |
135 | struct v4l2_window win; | |
136 | struct v4l2_clip *clips; | |
137 | unsigned int nclips; | |
138 | ||
139 | /* video capture */ | |
140 | struct cx23885_fmt *fmt; | |
141 | unsigned int width, height; | |
142 | ||
143 | /* vbi capture */ | |
144 | struct videobuf_queue vidq; | |
145 | struct videobuf_queue vbiq; | |
146 | ||
147 | /* MPEG Encoder specifics ONLY */ | |
148 | struct videobuf_queue mpegq; | |
149 | atomic_t v4l_reading; | |
150 | }; | |
151 | ||
d19770e5 ST |
152 | enum cx23885_itype { |
153 | CX23885_VMUX_COMPOSITE1 = 1, | |
154 | CX23885_VMUX_COMPOSITE2, | |
155 | CX23885_VMUX_COMPOSITE3, | |
156 | CX23885_VMUX_COMPOSITE4, | |
157 | CX23885_VMUX_SVIDEO, | |
158 | CX23885_VMUX_TELEVISION, | |
159 | CX23885_VMUX_CABLE, | |
160 | CX23885_VMUX_DVB, | |
161 | CX23885_VMUX_DEBUG, | |
162 | CX23885_RADIO, | |
163 | }; | |
164 | ||
579f1163 ST |
165 | enum cx23885_src_sel_type { |
166 | CX23885_SRC_SEL_EXT_656_VIDEO = 0, | |
167 | CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO | |
168 | }; | |
169 | ||
d19770e5 ST |
170 | /* buffer for one video frame */ |
171 | struct cx23885_buffer { | |
172 | /* common v4l buffer stuff -- must be first */ | |
173 | struct videobuf_buffer vb; | |
174 | ||
175 | /* cx23885 specific */ | |
176 | unsigned int bpl; | |
177 | struct btcx_riscmem risc; | |
178 | struct cx23885_fmt *fmt; | |
179 | u32 count; | |
180 | }; | |
181 | ||
182 | struct cx23885_input { | |
183 | enum cx23885_itype type; | |
184 | unsigned int vmux; | |
185 | u32 gpio0, gpio1, gpio2, gpio3; | |
186 | }; | |
187 | ||
661c7e44 ST |
188 | typedef enum { |
189 | CX23885_MPEG_UNDEFINED = 0, | |
7b888014 ST |
190 | CX23885_MPEG_DVB, |
191 | CX23885_ANALOG_VIDEO, | |
b1b81f1d | 192 | CX23885_MPEG_ENCODER, |
661c7e44 ST |
193 | } port_t; |
194 | ||
d19770e5 ST |
195 | struct cx23885_board { |
196 | char *name; | |
7b888014 ST |
197 | port_t porta, portb, portc; |
198 | unsigned int tuner_type; | |
199 | unsigned int radio_type; | |
200 | unsigned char tuner_addr; | |
201 | unsigned char radio_addr; | |
c7712613 ST |
202 | |
203 | /* Vendors can and do run the PCIe bridge at different | |
204 | * clock rates, driven physically by crystals on the PCBs. | |
205 | * The core has to accomodate this. This allows the user | |
206 | * to add new boards with new frequencys. The value is | |
207 | * expressed in Hz. | |
208 | * | |
209 | * The core framework will default this value based on | |
210 | * current designs, but it can vary. | |
211 | */ | |
212 | u32 clk_freq; | |
d19770e5 | 213 | struct cx23885_input input[MAX_CX23885_INPUT]; |
5a23b076 | 214 | int cimax; /* for NetUP */ |
d19770e5 ST |
215 | }; |
216 | ||
217 | struct cx23885_subid { | |
218 | u16 subvendor; | |
219 | u16 subdevice; | |
220 | u32 card; | |
221 | }; | |
222 | ||
223 | struct cx23885_i2c { | |
224 | struct cx23885_dev *dev; | |
225 | ||
226 | int nr; | |
227 | ||
228 | /* i2c i/o */ | |
229 | struct i2c_adapter i2c_adap; | |
230 | struct i2c_algo_bit_data i2c_algo; | |
231 | struct i2c_client i2c_client; | |
232 | u32 i2c_rc; | |
233 | ||
234 | /* 885 registers used for raw addess */ | |
235 | u32 i2c_period; | |
236 | u32 reg_ctrl; | |
237 | u32 reg_stat; | |
238 | u32 reg_addr; | |
239 | u32 reg_rdata; | |
240 | u32 reg_wdata; | |
241 | }; | |
242 | ||
243 | struct cx23885_dmaqueue { | |
244 | struct list_head active; | |
245 | struct list_head queued; | |
246 | struct timer_list timeout; | |
247 | struct btcx_riscmem stopper; | |
248 | u32 count; | |
249 | }; | |
250 | ||
251 | struct cx23885_tsport { | |
252 | struct cx23885_dev *dev; | |
253 | ||
254 | int nr; | |
255 | int sram_chno; | |
256 | ||
363c35fc | 257 | struct videobuf_dvb_frontends frontends; |
d19770e5 ST |
258 | |
259 | /* dma queues */ | |
260 | struct cx23885_dmaqueue mpegq; | |
261 | u32 ts_packet_size; | |
262 | u32 ts_packet_count; | |
263 | ||
264 | int width; | |
265 | int height; | |
266 | ||
267 | spinlock_t slock; | |
268 | ||
269 | /* registers */ | |
270 | u32 reg_gpcnt; | |
271 | u32 reg_gpcnt_ctl; | |
272 | u32 reg_dma_ctl; | |
273 | u32 reg_lngth; | |
274 | u32 reg_hw_sop_ctrl; | |
275 | u32 reg_gen_ctrl; | |
276 | u32 reg_bd_pkt_status; | |
277 | u32 reg_sop_status; | |
278 | u32 reg_fifo_ovfl_stat; | |
279 | u32 reg_vld_misc; | |
280 | u32 reg_ts_clk_en; | |
281 | u32 reg_ts_int_msk; | |
a6a3f140 | 282 | u32 reg_ts_int_stat; |
579f1163 | 283 | u32 reg_src_sel; |
d19770e5 ST |
284 | |
285 | /* Default register vals */ | |
286 | int pci_irqmask; | |
287 | u32 dma_ctl_val; | |
288 | u32 ts_int_msk_val; | |
289 | u32 gen_ctrl_val; | |
290 | u32 ts_clk_en_val; | |
579f1163 | 291 | u32 src_sel_val; |
b1b81f1d ST |
292 | u32 vld_misc_val; |
293 | u32 hw_sop_ctrl_val; | |
a739a7e4 ST |
294 | |
295 | /* Allow a single tsport to have multiple frontends */ | |
296 | u32 num_frontends; | |
5a23b076 | 297 | void *port_priv; |
b179bc45 MK |
298 | |
299 | /* FIXME: temporary hack */ | |
f35b9e80 MK |
300 | int (*set_frontend_save) (struct dvb_frontend *, |
301 | struct dvb_frontend_parameters *); | |
d19770e5 ST |
302 | }; |
303 | ||
304 | struct cx23885_dev { | |
305 | struct list_head devlist; | |
306 | atomic_t refcount; | |
c0714f6c | 307 | struct v4l2_device v4l2_dev; |
d19770e5 ST |
308 | |
309 | /* pci stuff */ | |
310 | struct pci_dev *pci; | |
311 | unsigned char pci_rev, pci_lat; | |
312 | int pci_bus, pci_slot; | |
313 | u32 __iomem *lmmio; | |
314 | u8 __iomem *bmmio; | |
d19770e5 | 315 | int pci_irqmask; |
0ac5881a | 316 | int hwrevision; |
d19770e5 | 317 | |
c7712613 ST |
318 | /* This valud is board specific and is used to configure the |
319 | * AV core so we see nice clean and stable video and audio. */ | |
320 | u32 clk_freq; | |
321 | ||
44a6481d | 322 | /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ |
d19770e5 ST |
323 | struct cx23885_i2c i2c_bus[3]; |
324 | ||
325 | int nr; | |
326 | struct mutex lock; | |
327 | ||
328 | /* board details */ | |
329 | unsigned int board; | |
330 | char name[32]; | |
331 | ||
a6a3f140 | 332 | struct cx23885_tsport ts1, ts2; |
d19770e5 ST |
333 | |
334 | /* sram configuration */ | |
335 | struct sram_channel *sram_channels; | |
e133be0f ST |
336 | |
337 | enum { | |
338 | CX23885_BRIDGE_UNDEFINED = 0, | |
339 | CX23885_BRIDGE_885 = 885, | |
340 | CX23885_BRIDGE_887 = 887, | |
341 | } bridge; | |
7b888014 ST |
342 | |
343 | /* Analog video */ | |
344 | u32 resources; | |
345 | unsigned int input; | |
346 | u32 tvaudio; | |
347 | v4l2_std_id tvnorm; | |
348 | unsigned int tuner_type; | |
349 | unsigned char tuner_addr; | |
350 | unsigned int radio_type; | |
351 | unsigned char radio_addr; | |
352 | unsigned int has_radio; | |
0d5a19f1 | 353 | struct v4l2_subdev *sd_cx25840; |
7b888014 ST |
354 | |
355 | /* V4l */ | |
356 | u32 freq; | |
357 | struct video_device *video_dev; | |
358 | struct video_device *vbi_dev; | |
359 | struct video_device *radio_dev; | |
360 | ||
361 | struct cx23885_dmaqueue vidq; | |
362 | struct cx23885_dmaqueue vbiq; | |
363 | spinlock_t slock; | |
b1b81f1d ST |
364 | |
365 | /* MPEG Encoder ONLY settings */ | |
366 | u32 cx23417_mailbox; | |
367 | struct cx2341x_mpeg_params mpeg_params; | |
368 | struct video_device *v4l_device; | |
369 | atomic_t v4l_reader_count; | |
370 | struct cx23885_tvnorm encodernorm; | |
371 | ||
d19770e5 ST |
372 | }; |
373 | ||
c0714f6c HV |
374 | static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev) |
375 | { | |
376 | return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev); | |
377 | } | |
378 | ||
0d5a19f1 HV |
379 | #define call_all(dev, o, f, args...) \ |
380 | v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args) | |
381 | ||
7b888014 ST |
382 | extern struct list_head cx23885_devlist; |
383 | ||
d19770e5 ST |
384 | #define SRAM_CH01 0 /* Video A */ |
385 | #define SRAM_CH02 1 /* VBI A */ | |
386 | #define SRAM_CH03 2 /* Video B */ | |
387 | #define SRAM_CH04 3 /* Transport via B */ | |
388 | #define SRAM_CH05 4 /* VBI B */ | |
389 | #define SRAM_CH06 5 /* Video C */ | |
390 | #define SRAM_CH07 6 /* Transport via C */ | |
391 | #define SRAM_CH08 7 /* Audio Internal A */ | |
392 | #define SRAM_CH09 8 /* Audio Internal B */ | |
393 | #define SRAM_CH10 9 /* Audio External */ | |
394 | #define SRAM_CH11 10 /* COMB_3D_N */ | |
395 | #define SRAM_CH12 11 /* Comb 3D N1 */ | |
396 | #define SRAM_CH13 12 /* Comb 3D N2 */ | |
397 | #define SRAM_CH14 13 /* MOE Vid */ | |
398 | #define SRAM_CH15 14 /* MOE RSLT */ | |
399 | ||
400 | struct sram_channel { | |
401 | char *name; | |
402 | u32 cmds_start; | |
403 | u32 ctrl_start; | |
404 | u32 cdt; | |
1ebcad77 | 405 | u32 fifo_start; |
d19770e5 ST |
406 | u32 fifo_size; |
407 | u32 ptr1_reg; | |
408 | u32 ptr2_reg; | |
409 | u32 cnt1_reg; | |
410 | u32 cnt2_reg; | |
411 | u32 jumponly; | |
412 | }; | |
413 | ||
414 | /* ----------------------------------------------------------- */ | |
415 | ||
416 | #define cx_read(reg) readl(dev->lmmio + ((reg)>>2)) | |
9c8ced51 | 417 | #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) |
d19770e5 | 418 | |
9c8ced51 | 419 | #define cx_andor(reg, mask, value) \ |
d19770e5 ST |
420 | writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ |
421 | ((value) & (mask)), dev->lmmio+((reg)>>2)) | |
422 | ||
9c8ced51 ST |
423 | #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) |
424 | #define cx_clear(reg, bit) cx_andor((reg), (bit), 0) | |
d19770e5 | 425 | |
d19770e5 | 426 | /* ----------------------------------------------------------- */ |
7b888014 ST |
427 | /* cx23885-core.c */ |
428 | ||
429 | extern int cx23885_sram_channel_setup(struct cx23885_dev *dev, | |
430 | struct sram_channel *ch, | |
431 | unsigned int bpl, u32 risc); | |
432 | ||
433 | extern void cx23885_sram_channel_dump(struct cx23885_dev *dev, | |
434 | struct sram_channel *ch); | |
d19770e5 | 435 | |
7b888014 ST |
436 | extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc, |
437 | u32 reg, u32 mask, u32 value); | |
438 | ||
439 | extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, | |
440 | struct scatterlist *sglist, | |
441 | unsigned int top_offset, unsigned int bottom_offset, | |
442 | unsigned int bpl, unsigned int padding, unsigned int lines); | |
443 | ||
444 | void cx23885_cancel_buffers(struct cx23885_tsport *port); | |
445 | ||
446 | extern int cx23885_restart_queue(struct cx23885_tsport *port, | |
447 | struct cx23885_dmaqueue *q); | |
448 | ||
449 | extern void cx23885_wakeup(struct cx23885_tsport *port, | |
450 | struct cx23885_dmaqueue *q, u32 count); | |
451 | ||
6f8bee9b ST |
452 | extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask); |
453 | extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask); | |
454 | extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, | |
455 | int asoutput); | |
456 | ||
7b888014 ST |
457 | |
458 | /* ----------------------------------------------------------- */ | |
459 | /* cx23885-cards.c */ | |
d19770e5 ST |
460 | extern struct cx23885_board cx23885_boards[]; |
461 | extern const unsigned int cx23885_bcount; | |
462 | ||
463 | extern struct cx23885_subid cx23885_subids[]; | |
464 | extern const unsigned int cx23885_idcount; | |
465 | ||
9c8ced51 ST |
466 | extern int cx23885_tuner_callback(void *priv, int component, |
467 | int command, int arg); | |
d19770e5 | 468 | extern void cx23885_card_list(struct cx23885_dev *dev); |
a6a3f140 ST |
469 | extern int cx23885_ir_init(struct cx23885_dev *dev); |
470 | extern void cx23885_gpio_setup(struct cx23885_dev *dev); | |
d19770e5 ST |
471 | extern void cx23885_card_setup(struct cx23885_dev *dev); |
472 | extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev); | |
473 | ||
474 | extern int cx23885_dvb_register(struct cx23885_tsport *port); | |
475 | extern int cx23885_dvb_unregister(struct cx23885_tsport *port); | |
476 | ||
44a6481d MK |
477 | extern int cx23885_buf_prepare(struct videobuf_queue *q, |
478 | struct cx23885_tsport *port, | |
479 | struct cx23885_buffer *buf, | |
480 | enum v4l2_field field); | |
44a6481d MK |
481 | extern void cx23885_buf_queue(struct cx23885_tsport *port, |
482 | struct cx23885_buffer *buf); | |
483 | extern void cx23885_free_buffer(struct videobuf_queue *q, | |
484 | struct cx23885_buffer *buf); | |
d19770e5 ST |
485 | |
486 | /* ----------------------------------------------------------- */ | |
7b888014 ST |
487 | /* cx23885-video.c */ |
488 | /* Video */ | |
489 | extern int cx23885_video_register(struct cx23885_dev *dev); | |
490 | extern void cx23885_video_unregister(struct cx23885_dev *dev); | |
491 | extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status); | |
492 | ||
493 | /* ----------------------------------------------------------- */ | |
494 | /* cx23885-vbi.c */ | |
495 | extern int cx23885_vbi_fmt(struct file *file, void *priv, | |
496 | struct v4l2_format *f); | |
497 | extern void cx23885_vbi_timeout(unsigned long data); | |
498 | extern struct videobuf_queue_ops cx23885_vbi_qops; | |
499 | ||
d19770e5 ST |
500 | /* cx23885-i2c.c */ |
501 | extern int cx23885_i2c_register(struct cx23885_i2c *bus); | |
502 | extern int cx23885_i2c_unregister(struct cx23885_i2c *bus); | |
a589b665 | 503 | extern void cx23885_av_clk(struct cx23885_dev *dev, int enable); |
d19770e5 | 504 | |
b1b81f1d ST |
505 | /* ----------------------------------------------------------- */ |
506 | /* cx23885-417.c */ | |
507 | extern int cx23885_417_register(struct cx23885_dev *dev); | |
508 | extern void cx23885_417_unregister(struct cx23885_dev *dev); | |
509 | extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status); | |
510 | extern void cx23885_417_check_encoder(struct cx23885_dev *dev); | |
511 | extern void cx23885_mc417_init(struct cx23885_dev *dev); | |
512 | extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value); | |
513 | extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value); | |
f659c513 ST |
514 | extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask); |
515 | extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask); | |
516 | extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput); | |
b1b81f1d ST |
517 | |
518 | ||
7b888014 ST |
519 | /* ----------------------------------------------------------- */ |
520 | /* tv norms */ | |
521 | ||
522 | static inline unsigned int norm_maxw(v4l2_std_id norm) | |
523 | { | |
524 | return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768; | |
525 | } | |
526 | ||
527 | static inline unsigned int norm_maxh(v4l2_std_id norm) | |
528 | { | |
529 | return (norm & V4L2_STD_625_50) ? 576 : 480; | |
530 | } | |
531 | ||
532 | static inline unsigned int norm_swidth(v4l2_std_id norm) | |
533 | { | |
534 | return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922; | |
535 | } |