[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885.h

/*
 *  Driver for the Conexant CX23885 PCIe bridge
 *
 *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/kdev_t.h>

#include <media/v4l2-device.h>
#include <media/tuner.h>
#include <media/tveeprom.h>
#include <media/videobuf-dma-sg.h>
#include <media/videobuf-dvb.h>

#include "btcx-risc.h"
#include "cx23885-reg.h"
#include "media/cx2341x.h"

#include <linux/version.h>
#include <linux/mutex.h>

#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)

#define UNSET (-1U)

#define CX23885_MAXBOARDS 8

/* Max number of inputs by card */
#define MAX_CX23885_INPUT 8
#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
#define RESOURCE_OVERLAY       1
#define RESOURCE_VIDEO         2
#define RESOURCE_VBI           4

#define BUFFER_TIMEOUT     (HZ)  /* 0.5 seconds */

#define CX23885_BOARD_NOAUTO               UNSET
#define CX23885_BOARD_UNKNOWN                  0
#define CX23885_BOARD_HAUPPAUGE_HVR1800lp      1
#define CX23885_BOARD_HAUPPAUGE_HVR1800        2
#define CX23885_BOARD_HAUPPAUGE_HVR1250        3
#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP   4
#define CX23885_BOARD_HAUPPAUGE_HVR1500Q       5
#define CX23885_BOARD_HAUPPAUGE_HVR1500        6
#define CX23885_BOARD_HAUPPAUGE_HVR1200        7
#define CX23885_BOARD_HAUPPAUGE_HVR1700        8
#define CX23885_BOARD_HAUPPAUGE_HVR1400        9
#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F   13
#define CX23885_BOARD_TBS_6920                 14
#define CX23885_BOARD_TEVII_S470               15
#define CX23885_BOARD_DVBWORLD_2005            16
#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI      17

#define GPIO_0 0x00000001
#define GPIO_1 0x00000002
#define GPIO_2 0x00000004
#define GPIO_3 0x00000008
#define GPIO_4 0x00000010
#define GPIO_5 0x00000020
#define GPIO_6 0x00000040
#define GPIO_7 0x00000080
#define GPIO_8 0x00000100
#define GPIO_9 0x00000200

/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
#define CX23885_NORMS (\
	V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP |  V4L2_STD_NTSC_443 | \
	V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
	V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_Nc   | \
	V4L2_STD_PAL_60 |  V4L2_STD_SECAM_L   |  V4L2_STD_SECAM_DK)

struct cx23885_fmt {
	char  *name;
	u32   fourcc;          /* v4l2 format id */
	int   depth;
	int   flags;
	u32   cxformat;
};

struct cx23885_ctrl {
	struct v4l2_queryctrl v;
	u32                   off;
	u32                   reg;
	u32                   mask;
	u32                   shift;
};

struct cx23885_tvnorm {
	char		*name;
	v4l2_std_id	id;
	u32		cxiformat;
	u32		cxoformat;
};

struct cx23885_fh {
	struct cx23885_dev         *dev;
	enum v4l2_buf_type         type;
	int                        radio;
	u32                        resources;

	/* video overlay */
	struct v4l2_window         win;
	struct v4l2_clip           *clips;
	unsigned int               nclips;

	/* video capture */
	struct cx23885_fmt         *fmt;
	unsigned int               width, height;

	/* vbi capture */
	struct videobuf_queue      vidq;
	struct videobuf_queue      vbiq;

	/* MPEG Encoder specifics ONLY */
	struct videobuf_queue      mpegq;
	atomic_t                   v4l_reading;
};

enum cx23885_itype {
	CX23885_VMUX_COMPOSITE1 = 1,
	CX23885_VMUX_COMPOSITE2,
	CX23885_VMUX_COMPOSITE3,
	CX23885_VMUX_COMPOSITE4,
	CX23885_VMUX_SVIDEO,
	CX23885_VMUX_TELEVISION,
	CX23885_VMUX_CABLE,
	CX23885_VMUX_DVB,
	CX23885_VMUX_DEBUG,
	CX23885_RADIO,
};

enum cx23885_src_sel_type {
	CX23885_SRC_SEL_EXT_656_VIDEO = 0,
	CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
};

/* buffer for one video frame */
struct cx23885_buffer {
	/* common v4l buffer stuff -- must be first */
	struct videobuf_buffer vb;

	/* cx23885 specific */
	unsigned int           bpl;
	struct btcx_riscmem    risc;
	struct cx23885_fmt     *fmt;
	u32                    count;
};

struct cx23885_input {
	enum cx23885_itype type;
	unsigned int    vmux;
	u32             gpio0, gpio1, gpio2, gpio3;
};

typedef enum {
	CX23885_MPEG_UNDEFINED = 0,
	CX23885_MPEG_DVB,
	CX23885_ANALOG_VIDEO,
	CX23885_MPEG_ENCODER,
} port_t;

struct cx23885_board {
	char                    *name;
	port_t			porta, portb, portc;
	unsigned int		tuner_type;
	unsigned int		radio_type;
	unsigned char		tuner_addr;
	unsigned char		radio_addr;

	/* Vendors can and do run the PCIe bridge at different
	 * clock rates, driven physically by crystals on the PCBs.
	 * The core has to accomodate this. This allows the user
	 * to add new boards with new frequencys. The value is
	 * expressed in Hz.
	 *
	 * The core framework will default this value based on
	 * current designs, but it can vary.
	 */
	u32			clk_freq;
	struct cx23885_input    input[MAX_CX23885_INPUT];
	int			cimax; /* for NetUP */
};

struct cx23885_subid {
	u16     subvendor;
	u16     subdevice;
	u32     card;
};

struct cx23885_i2c {
	struct cx23885_dev *dev;

	int                        nr;

	/* i2c i/o */
	struct i2c_adapter         i2c_adap;
	struct i2c_algo_bit_data   i2c_algo;
	struct i2c_client          i2c_client;
	u32                        i2c_rc;

	/* 885 registers used for raw addess */
	u32                        i2c_period;
	u32                        reg_ctrl;
	u32                        reg_stat;
	u32                        reg_addr;
	u32                        reg_rdata;
	u32                        reg_wdata;
};

struct cx23885_dmaqueue {
	struct list_head       active;
	struct list_head       queued;
	struct timer_list      timeout;
	struct btcx_riscmem    stopper;
	u32                    count;
};

struct cx23885_tsport {
	struct cx23885_dev *dev;

	int                        nr;
	int                        sram_chno;

	struct videobuf_dvb_frontends frontends;

	/* dma queues */
	struct cx23885_dmaqueue    mpegq;
	u32                        ts_packet_size;
	u32                        ts_packet_count;

	int                        width;
	int                        height;

	spinlock_t                 slock;

	/* registers */
	u32                        reg_gpcnt;
	u32                        reg_gpcnt_ctl;
	u32                        reg_dma_ctl;
	u32                        reg_lngth;
	u32                        reg_hw_sop_ctrl;
	u32                        reg_gen_ctrl;
	u32                        reg_bd_pkt_status;
	u32                        reg_sop_status;
	u32                        reg_fifo_ovfl_stat;
	u32                        reg_vld_misc;
	u32                        reg_ts_clk_en;
	u32                        reg_ts_int_msk;
	u32                        reg_ts_int_stat;
	u32                        reg_src_sel;

	/* Default register vals */
	int                        pci_irqmask;
	u32                        dma_ctl_val;
	u32                        ts_int_msk_val;
	u32                        gen_ctrl_val;
	u32                        ts_clk_en_val;
	u32                        src_sel_val;
	u32                        vld_misc_val;
	u32                        hw_sop_ctrl_val;

	/* Allow a single tsport to have multiple frontends */
	u32                        num_frontends;
	void                       *port_priv;
};

struct cx23885_dev {
	struct list_head           devlist;
	atomic_t                   refcount;
	struct v4l2_device 	   v4l2_dev;

	/* pci stuff */
	struct pci_dev             *pci;
	unsigned char              pci_rev, pci_lat;
	int                        pci_bus, pci_slot;
	u32                        __iomem *lmmio;
	u8                         __iomem *bmmio;
	int                        pci_irqmask;
	int                        hwrevision;

	/* This valud is board specific and is used to configure the
	 * AV core so we see nice clean and stable video and audio. */
	u32                        clk_freq;

	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
	struct cx23885_i2c         i2c_bus[3];

	int                        nr;
	struct mutex               lock;

	/* board details */
	unsigned int               board;
	char                       name[32];

	struct cx23885_tsport      ts1, ts2;

	/* sram configuration */
	struct sram_channel        *sram_channels;

	enum {
		CX23885_BRIDGE_UNDEFINED = 0,
		CX23885_BRIDGE_885 = 885,
		CX23885_BRIDGE_887 = 887,
	} bridge;

	/* Analog video */
	u32                        resources;
	unsigned int               input;
	u32                        tvaudio;
	v4l2_std_id                tvnorm;
	unsigned int               tuner_type;
	unsigned char              tuner_addr;
	unsigned int               radio_type;
	unsigned char              radio_addr;
	unsigned int               has_radio;
	struct v4l2_subdev 	   *sd_cx25840;

	/* V4l */
	u32                        freq;
	struct video_device        *video_dev;
	struct video_device        *vbi_dev;
	struct video_device        *radio_dev;

	struct cx23885_dmaqueue    vidq;
	struct cx23885_dmaqueue    vbiq;
	spinlock_t                 slock;

	/* MPEG Encoder ONLY settings */
	u32                        cx23417_mailbox;
	struct cx2341x_mpeg_params mpeg_params;
	struct video_device        *v4l_device;
	atomic_t                   v4l_reader_count;
	struct cx23885_tvnorm      encodernorm;

};

static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
{
	return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
}

#define call_all(dev, o, f, args...) \
	v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)

extern struct list_head cx23885_devlist;

#define SRAM_CH01  0 /* Video A */
#define SRAM_CH02  1 /* VBI A */
#define SRAM_CH03  2 /* Video B */
#define SRAM_CH04  3 /* Transport via B */
#define SRAM_CH05  4 /* VBI B */
#define SRAM_CH06  5 /* Video C */
#define SRAM_CH07  6 /* Transport via C */
#define SRAM_CH08  7 /* Audio Internal A */
#define SRAM_CH09  8 /* Audio Internal B */
#define SRAM_CH10  9 /* Audio External */
#define SRAM_CH11 10 /* COMB_3D_N */
#define SRAM_CH12 11 /* Comb 3D N1 */
#define SRAM_CH13 12 /* Comb 3D N2 */
#define SRAM_CH14 13 /* MOE Vid */
#define SRAM_CH15 14 /* MOE RSLT */

struct sram_channel {
	char *name;
	u32  cmds_start;
	u32  ctrl_start;
	u32  cdt;
	u32  fifo_start;;
	u32  fifo_size;
	u32  ptr1_reg;
	u32  ptr2_reg;
	u32  cnt1_reg;
	u32  cnt2_reg;
	u32  jumponly;
};

/* ----------------------------------------------------------- */

#define cx_read(reg)             readl(dev->lmmio + ((reg)>>2))
#define cx_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))

#define cx_andor(reg, mask, value) \
  writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
  ((value) & (mask)), dev->lmmio+((reg)>>2))

#define cx_set(reg, bit)          cx_andor((reg), (bit), (bit))
#define cx_clear(reg, bit)        cx_andor((reg), (bit), 0)

/* ----------------------------------------------------------- */
/* cx23885-core.c                                              */

extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
	struct sram_channel *ch,
	unsigned int bpl, u32 risc);

extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
	struct sram_channel *ch);

extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
	u32 reg, u32 mask, u32 value);

extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
	struct scatterlist *sglist,
	unsigned int top_offset, unsigned int bottom_offset,
	unsigned int bpl, unsigned int padding, unsigned int lines);

void cx23885_cancel_buffers(struct cx23885_tsport *port);

extern int cx23885_restart_queue(struct cx23885_tsport *port,
				struct cx23885_dmaqueue *q);

extern void cx23885_wakeup(struct cx23885_tsport *port,
			   struct cx23885_dmaqueue *q, u32 count);

extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
	int asoutput);


/* ----------------------------------------------------------- */
/* cx23885-cards.c                                             */
extern struct cx23885_board cx23885_boards[];
extern const unsigned int cx23885_bcount;

extern struct cx23885_subid cx23885_subids[];
extern const unsigned int cx23885_idcount;

extern int cx23885_tuner_callback(void *priv, int component,
	int command, int arg);
extern void cx23885_card_list(struct cx23885_dev *dev);
extern int  cx23885_ir_init(struct cx23885_dev *dev);
extern void cx23885_gpio_setup(struct cx23885_dev *dev);
extern void cx23885_card_setup(struct cx23885_dev *dev);
extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);

extern int cx23885_dvb_register(struct cx23885_tsport *port);
extern int cx23885_dvb_unregister(struct cx23885_tsport *port);

extern int cx23885_buf_prepare(struct videobuf_queue *q,
			       struct cx23885_tsport *port,
			       struct cx23885_buffer *buf,
			       enum v4l2_field field);
extern void cx23885_buf_queue(struct cx23885_tsport *port,
			      struct cx23885_buffer *buf);
extern void cx23885_free_buffer(struct videobuf_queue *q,
				struct cx23885_buffer *buf);

/* ----------------------------------------------------------- */
/* cx23885-video.c                                             */
/* Video */
extern int cx23885_video_register(struct cx23885_dev *dev);
extern void cx23885_video_unregister(struct cx23885_dev *dev);
extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);

/* ----------------------------------------------------------- */
/* cx23885-vbi.c                                               */
extern int cx23885_vbi_fmt(struct file *file, void *priv,
	struct v4l2_format *f);
extern void cx23885_vbi_timeout(unsigned long data);
extern struct videobuf_queue_ops cx23885_vbi_qops;

/* cx23885-i2c.c                                                */
extern int cx23885_i2c_register(struct cx23885_i2c *bus);
extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);

/* ----------------------------------------------------------- */
/* cx23885-417.c                                               */
extern int cx23885_417_register(struct cx23885_dev *dev);
extern void cx23885_417_unregister(struct cx23885_dev *dev);
extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
extern void cx23885_mc417_init(struct cx23885_dev *dev);
extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);


/* ----------------------------------------------------------- */
/* tv norms                                                    */

static inline unsigned int norm_maxw(v4l2_std_id norm)
{
	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
}

static inline unsigned int norm_maxh(v4l2_std_id norm)
{
	return (norm & V4L2_STD_625_50) ? 576 : 480;
}

static inline unsigned int norm_swidth(v4l2_std_id norm)
{
	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
}
Commit	Line	Data
d19770e5 ST	1	/*
	2	* Driver for the Conexant CX23885 PCIe bridge
	3	*
6d897616	4	* Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5 ST	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	*
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	#include <linux/pci.h>
	23	#include <linux/i2c.h>
	24	#include <linux/i2c-algo-bit.h>
	25	#include <linux/kdev_t.h>
	26
c0714f6c	27	#include <media/v4l2-device.h>
d19770e5 ST	28	#include <media/tuner.h>
d19770e5 ST	29	#include <media/tveeprom.h>
409d84f8 TP	30	#include <media/videobuf-dma-sg.h>
409d84f8 TP	31	#include <media/videobuf-dvb.h>
d19770e5 ST	32
	33	#include "btcx-risc.h"
	34	#include "cx23885-reg.h"
b1b81f1d	35	#include "media/cx2341x.h"
d19770e5 ST	36
	37	#include <linux/version.h>
	38	#include <linux/mutex.h>
	39
3ff4ad81	40	#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
d19770e5 ST	41
	42	#define UNSET (-1U)
	43
	44	#define CX23885_MAXBOARDS 8
	45
d19770e5 ST	46	/* Max number of inputs by card */
d19770e5 ST	47	#define MAX_CX23885_INPUT 8
7b888014 ST	48	#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
	49	#define RESOURCE_OVERLAY 1
	50	#define RESOURCE_VIDEO 2
	51	#define RESOURCE_VBI 4
d19770e5	52
d19770e5 ST	53	#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
	54
	55	#define CX23885_BOARD_NOAUTO UNSET
	56	#define CX23885_BOARD_UNKNOWN 0
	57	#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
	58	#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc	59	#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa	60	#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55	61	#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835	62	#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166	63	#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c	64	#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373	65	#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7	66	#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186	67	#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a	68	#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8	69	#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c	70	#define CX23885_BOARD_TBS_6920 14
579943f5	71	#define CX23885_BOARD_TEVII_S470 15
c9b8b04b	72	#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076	73	#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
d19770e5	74
6f8bee9b ST	75	#define GPIO_0 0x00000001
	76	#define GPIO_1 0x00000002
	77	#define GPIO_2 0x00000004
	78	#define GPIO_3 0x00000008
	79	#define GPIO_4 0x00000010
	80	#define GPIO_5 0x00000020
	81	#define GPIO_6 0x00000040
	82	#define GPIO_7 0x00000080
	83	#define GPIO_8 0x00000100
	84	#define GPIO_9 0x00000200
	85
7b888014 ST	86	/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
	87	#define CX23885_NORMS (\
	88	V4L2_STD_NTSC_M \| V4L2_STD_NTSC_M_JP \| V4L2_STD_NTSC_443 \| \
	89	V4L2_STD_PAL_BG \| V4L2_STD_PAL_DK \| V4L2_STD_PAL_I \| \
	90	V4L2_STD_PAL_M \| V4L2_STD_PAL_N \| V4L2_STD_PAL_Nc \| \
	91	V4L2_STD_PAL_60 \| V4L2_STD_SECAM_L \| V4L2_STD_SECAM_DK)
	92
	93	struct cx23885_fmt {
	94	char *name;
	95	u32 fourcc; /* v4l2 format id */
	96	int depth;
	97	int flags;
	98	u32 cxformat;
	99	};
	100
	101	struct cx23885_ctrl {
	102	struct v4l2_queryctrl v;
	103	u32 off;
	104	u32 reg;
	105	u32 mask;
	106	u32 shift;
	107	};
	108
	109	struct cx23885_tvnorm {
	110	char *name;
	111	v4l2_std_id id;
	112	u32 cxiformat;
	113	u32 cxoformat;
	114	};
	115
	116	struct cx23885_fh {
	117	struct cx23885_dev *dev;
	118	enum v4l2_buf_type type;
	119	int radio;
	120	u32 resources;
	121
	122	/* video overlay */
	123	struct v4l2_window win;
	124	struct v4l2_clip *clips;
	125	unsigned int nclips;
	126
	127	/* video capture */
	128	struct cx23885_fmt *fmt;
	129	unsigned int width, height;
	130
	131	/* vbi capture */
	132	struct videobuf_queue vidq;
	133	struct videobuf_queue vbiq;
	134
	135	/* MPEG Encoder specifics ONLY */
	136	struct videobuf_queue mpegq;
	137	atomic_t v4l_reading;
	138	};
	139
d19770e5 ST	140	enum cx23885_itype {
	141	CX23885_VMUX_COMPOSITE1 = 1,
	142	CX23885_VMUX_COMPOSITE2,
	143	CX23885_VMUX_COMPOSITE3,
	144	CX23885_VMUX_COMPOSITE4,
	145	CX23885_VMUX_SVIDEO,
	146	CX23885_VMUX_TELEVISION,
	147	CX23885_VMUX_CABLE,
	148	CX23885_VMUX_DVB,
	149	CX23885_VMUX_DEBUG,
	150	CX23885_RADIO,
	151	};
	152
579f1163 ST	153	enum cx23885_src_sel_type {
	154	CX23885_SRC_SEL_EXT_656_VIDEO = 0,
	155	CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
	156	};
	157
d19770e5 ST	158	/* buffer for one video frame */
	159	struct cx23885_buffer {
	160	/* common v4l buffer stuff -- must be first */
	161	struct videobuf_buffer vb;
	162
	163	/* cx23885 specific */
	164	unsigned int bpl;
	165	struct btcx_riscmem risc;
	166	struct cx23885_fmt *fmt;
	167	u32 count;
	168	};
	169
	170	struct cx23885_input {
	171	enum cx23885_itype type;
	172	unsigned int vmux;
	173	u32 gpio0, gpio1, gpio2, gpio3;
	174	};
	175
661c7e44 ST	176	typedef enum {
661c7e44 ST	177	CX23885_MPEG_UNDEFINED = 0,
7b888014 ST	178	CX23885_MPEG_DVB,
7b888014 ST	179	CX23885_ANALOG_VIDEO,
b1b81f1d	180	CX23885_MPEG_ENCODER,
661c7e44 ST	181	} port_t;
661c7e44 ST	182
d19770e5 ST	183	struct cx23885_board {
d19770e5 ST	184	char *name;
7b888014 ST	185	port_t porta, portb, portc;
	186	unsigned int tuner_type;
	187	unsigned int radio_type;
	188	unsigned char tuner_addr;
	189	unsigned char radio_addr;
c7712613 ST	190
	191	/* Vendors can and do run the PCIe bridge at different
	192	* clock rates, driven physically by crystals on the PCBs.
	193	* The core has to accomodate this. This allows the user
	194	* to add new boards with new frequencys. The value is
	195	* expressed in Hz.
	196	*
	197	* The core framework will default this value based on
	198	* current designs, but it can vary.
	199	*/
	200	u32 clk_freq;
d19770e5	201	struct cx23885_input input[MAX_CX23885_INPUT];
5a23b076	202	int cimax; /* for NetUP */
d19770e5 ST	203	};
	204
	205	struct cx23885_subid {
	206	u16 subvendor;
	207	u16 subdevice;
	208	u32 card;
	209	};
	210
	211	struct cx23885_i2c {
	212	struct cx23885_dev *dev;
	213
	214	int nr;
	215
	216	/* i2c i/o */
	217	struct i2c_adapter i2c_adap;
	218	struct i2c_algo_bit_data i2c_algo;
	219	struct i2c_client i2c_client;
	220	u32 i2c_rc;
	221
	222	/* 885 registers used for raw addess */
	223	u32 i2c_period;
	224	u32 reg_ctrl;
	225	u32 reg_stat;
	226	u32 reg_addr;
	227	u32 reg_rdata;
	228	u32 reg_wdata;
	229	};
	230
	231	struct cx23885_dmaqueue {
	232	struct list_head active;
	233	struct list_head queued;
	234	struct timer_list timeout;
	235	struct btcx_riscmem stopper;
	236	u32 count;
	237	};
	238
	239	struct cx23885_tsport {
	240	struct cx23885_dev *dev;
	241
	242	int nr;
	243	int sram_chno;
	244
363c35fc	245	struct videobuf_dvb_frontends frontends;
d19770e5 ST	246
	247	/* dma queues */
	248	struct cx23885_dmaqueue mpegq;
	249	u32 ts_packet_size;
	250	u32 ts_packet_count;
	251
	252	int width;
	253	int height;
	254
	255	spinlock_t slock;
	256
	257	/* registers */
	258	u32 reg_gpcnt;
	259	u32 reg_gpcnt_ctl;
	260	u32 reg_dma_ctl;
	261	u32 reg_lngth;
	262	u32 reg_hw_sop_ctrl;
	263	u32 reg_gen_ctrl;
	264	u32 reg_bd_pkt_status;
	265	u32 reg_sop_status;
	266	u32 reg_fifo_ovfl_stat;
	267	u32 reg_vld_misc;
	268	u32 reg_ts_clk_en;
	269	u32 reg_ts_int_msk;
a6a3f140	270	u32 reg_ts_int_stat;
579f1163	271	u32 reg_src_sel;
d19770e5 ST	272
	273	/* Default register vals */
	274	int pci_irqmask;
	275	u32 dma_ctl_val;
	276	u32 ts_int_msk_val;
	277	u32 gen_ctrl_val;
	278	u32 ts_clk_en_val;
579f1163	279	u32 src_sel_val;
b1b81f1d ST	280	u32 vld_misc_val;
b1b81f1d ST	281	u32 hw_sop_ctrl_val;
a739a7e4 ST	282
	283	/* Allow a single tsport to have multiple frontends */
	284	u32 num_frontends;
5a23b076	285	void *port_priv;
d19770e5 ST	286	};
	287
	288	struct cx23885_dev {
	289	struct list_head devlist;
	290	atomic_t refcount;
c0714f6c	291	struct v4l2_device v4l2_dev;
d19770e5 ST	292
	293	/* pci stuff */
	294	struct pci_dev *pci;
	295	unsigned char pci_rev, pci_lat;
	296	int pci_bus, pci_slot;
	297	u32 __iomem *lmmio;
	298	u8 __iomem *bmmio;
d19770e5	299	int pci_irqmask;
0ac5881a	300	int hwrevision;
d19770e5	301
c7712613 ST	302	/* This valud is board specific and is used to configure the
	303	* AV core so we see nice clean and stable video and audio. */
	304	u32 clk_freq;
	305
44a6481d	306	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5 ST	307	struct cx23885_i2c i2c_bus[3];
	308
	309	int nr;
	310	struct mutex lock;
	311
	312	/* board details */
	313	unsigned int board;
	314	char name[32];
	315
a6a3f140	316	struct cx23885_tsport ts1, ts2;
d19770e5 ST	317
	318	/* sram configuration */
	319	struct sram_channel *sram_channels;
e133be0f ST	320
	321	enum {
	322	CX23885_BRIDGE_UNDEFINED = 0,
	323	CX23885_BRIDGE_885 = 885,
	324	CX23885_BRIDGE_887 = 887,
	325	} bridge;
7b888014 ST	326
	327	/* Analog video */
	328	u32 resources;
	329	unsigned int input;
	330	u32 tvaudio;
	331	v4l2_std_id tvnorm;
	332	unsigned int tuner_type;
	333	unsigned char tuner_addr;
	334	unsigned int radio_type;
	335	unsigned char radio_addr;
	336	unsigned int has_radio;
0d5a19f1	337	struct v4l2_subdev *sd_cx25840;
7b888014 ST	338
	339	/* V4l */
	340	u32 freq;
	341	struct video_device *video_dev;
	342	struct video_device *vbi_dev;
	343	struct video_device *radio_dev;
	344
	345	struct cx23885_dmaqueue vidq;
	346	struct cx23885_dmaqueue vbiq;
	347	spinlock_t slock;
b1b81f1d ST	348
	349	/* MPEG Encoder ONLY settings */
	350	u32 cx23417_mailbox;
	351	struct cx2341x_mpeg_params mpeg_params;
	352	struct video_device *v4l_device;
	353	atomic_t v4l_reader_count;
	354	struct cx23885_tvnorm encodernorm;
	355
d19770e5 ST	356	};
d19770e5 ST	357
c0714f6c HV	358	static inline struct cx23885_dev to_cx23885(struct v4l2_device v4l2_dev)
	359	{
	360	return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
	361	}
	362
0d5a19f1 HV	363	#define call_all(dev, o, f, args...) \
	364	v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
	365
7b888014 ST	366	extern struct list_head cx23885_devlist;
7b888014 ST	367
d19770e5 ST	368	#define SRAM_CH01 0 /* Video A */
	369	#define SRAM_CH02 1 /* VBI A */
	370	#define SRAM_CH03 2 /* Video B */
	371	#define SRAM_CH04 3 /* Transport via B */
	372	#define SRAM_CH05 4 /* VBI B */
	373	#define SRAM_CH06 5 /* Video C */
	374	#define SRAM_CH07 6 /* Transport via C */
	375	#define SRAM_CH08 7 /* Audio Internal A */
	376	#define SRAM_CH09 8 /* Audio Internal B */
	377	#define SRAM_CH10 9 /* Audio External */
	378	#define SRAM_CH11 10 /* COMB_3D_N */
	379	#define SRAM_CH12 11 /* Comb 3D N1 */
	380	#define SRAM_CH13 12 /* Comb 3D N2 */
	381	#define SRAM_CH14 13 /* MOE Vid */
	382	#define SRAM_CH15 14 /* MOE RSLT */
	383
	384	struct sram_channel {
	385	char *name;
	386	u32 cmds_start;
	387	u32 ctrl_start;
	388	u32 cdt;
	389	u32 fifo_start;;
	390	u32 fifo_size;
	391	u32 ptr1_reg;
	392	u32 ptr2_reg;
	393	u32 cnt1_reg;
	394	u32 cnt2_reg;
	395	u32 jumponly;
	396	};
	397
	398	/* ----------------------------------------------------------- */
	399
	400	#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51	401	#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5	402
9c8ced51	403	#define cx_andor(reg, mask, value) \
d19770e5 ST	404	writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) \|\
	405	((value) & (mask)), dev->lmmio+((reg)>>2))
	406
9c8ced51 ST	407	#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
9c8ced51 ST	408	#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5	409
d19770e5	410	/* ----------------------------------------------------------- */
7b888014 ST	411	/* cx23885-core.c */
	412
	413	extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
	414	struct sram_channel *ch,
	415	unsigned int bpl, u32 risc);
	416
	417	extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
	418	struct sram_channel *ch);
d19770e5	419
7b888014 ST	420	extern int cx23885_risc_stopper(struct pci_dev pci, struct btcx_riscmem risc,
	421	u32 reg, u32 mask, u32 value);
	422
	423	extern int cx23885_risc_buffer(struct pci_dev pci, struct btcx_riscmem risc,
	424	struct scatterlist *sglist,
	425	unsigned int top_offset, unsigned int bottom_offset,
	426	unsigned int bpl, unsigned int padding, unsigned int lines);
	427
	428	void cx23885_cancel_buffers(struct cx23885_tsport *port);
	429
	430	extern int cx23885_restart_queue(struct cx23885_tsport *port,
	431	struct cx23885_dmaqueue *q);
	432
	433	extern void cx23885_wakeup(struct cx23885_tsport *port,
	434	struct cx23885_dmaqueue *q, u32 count);
	435
6f8bee9b ST	436	extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
	437	extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
	438	extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
	439	int asoutput);
	440
7b888014 ST	441
	442	/* ----------------------------------------------------------- */
	443	/* cx23885-cards.c */
d19770e5 ST	444	extern struct cx23885_board cx23885_boards[];
	445	extern const unsigned int cx23885_bcount;
	446
	447	extern struct cx23885_subid cx23885_subids[];
	448	extern const unsigned int cx23885_idcount;
	449
9c8ced51 ST	450	extern int cx23885_tuner_callback(void *priv, int component,
9c8ced51 ST	451	int command, int arg);
d19770e5	452	extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 ST	453	extern int cx23885_ir_init(struct cx23885_dev *dev);
a6a3f140 ST	454	extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5 ST	455	extern void cx23885_card_setup(struct cx23885_dev *dev);
	456	extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
	457
	458	extern int cx23885_dvb_register(struct cx23885_tsport *port);
	459	extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
	460
44a6481d MK	461	extern int cx23885_buf_prepare(struct videobuf_queue *q,
	462	struct cx23885_tsport *port,
	463	struct cx23885_buffer *buf,
	464	enum v4l2_field field);
44a6481d MK	465	extern void cx23885_buf_queue(struct cx23885_tsport *port,
	466	struct cx23885_buffer *buf);
	467	extern void cx23885_free_buffer(struct videobuf_queue *q,
	468	struct cx23885_buffer *buf);
d19770e5 ST	469
d19770e5 ST	470	/* ----------------------------------------------------------- */
7b888014 ST	471	/* cx23885-video.c */
	472	/* Video */
	473	extern int cx23885_video_register(struct cx23885_dev *dev);
	474	extern void cx23885_video_unregister(struct cx23885_dev *dev);
	475	extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
	476
	477	/* ----------------------------------------------------------- */
	478	/* cx23885-vbi.c */
	479	extern int cx23885_vbi_fmt(struct file file, void priv,
	480	struct v4l2_format *f);
	481	extern void cx23885_vbi_timeout(unsigned long data);
	482	extern struct videobuf_queue_ops cx23885_vbi_qops;
	483
d19770e5 ST	484	/* cx23885-i2c.c */
	485	extern int cx23885_i2c_register(struct cx23885_i2c *bus);
	486	extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665	487	extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5	488
b1b81f1d ST	489	/* ----------------------------------------------------------- */
	490	/* cx23885-417.c */
	491	extern int cx23885_417_register(struct cx23885_dev *dev);
	492	extern void cx23885_417_unregister(struct cx23885_dev *dev);
	493	extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
	494	extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
	495	extern void cx23885_mc417_init(struct cx23885_dev *dev);
	496	extern int mc417_memory_read(struct cx23885_dev dev, u32 address, u32 value);
	497	extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
	498
	499
7b888014 ST	500	/* ----------------------------------------------------------- */
	501	/* tv norms */
	502
	503	static inline unsigned int norm_maxw(v4l2_std_id norm)
	504	{
	505	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
	506	}
	507
	508	static inline unsigned int norm_maxh(v4l2_std_id norm)
	509	{
	510	return (norm & V4L2_STD_625_50) ? 576 : 480;
	511	}
	512
	513	static inline unsigned int norm_swidth(v4l2_std_id norm)
	514	{
	515	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
	516	}