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V4L/DVB (6246): GemTek Radio card - Control Word
[deliverable/linux.git] / drivers / media / video / cx88 / cx88-core.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 *
3 * device driver for Conexant 2388x based TV cards
4 * driver core
5 *
6 * (c) 2003 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
7 *
8d87cb9f
MCC		 8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
9 * - Multituner support
10 * - video_ioctl2 conversion
11 * - PAL/M fixes
12 *
1da177e4
LT		 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/list.h>
30#include <linux/module.h>
1da177e4
LT		 31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/kmod.h>
34#include <linux/sound.h>
35#include <linux/interrupt.h>
36#include <linux/pci.h>
37#include <linux/delay.h>
98f30ed0 38#include <linux/videodev2.h>
1e4baed3 39#include <linux/mutex.h>
1da177e4
LT		 40
41#include "cx88.h"
5e453dc7 42#include <media/v4l2-common.h>
1da177e4
LT		 43
44MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
45MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
46MODULE_LICENSE("GPL");
47
48/* ------------------------------------------------------------------ */
49
50static unsigned int core_debug = 0;
51module_param(core_debug,int,0644);
52MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
53
1da177e4
LT		 54static unsigned int nicam = 0;
55module_param(nicam,int,0644);
56MODULE_PARM_DESC(nicam,"tv audio is nicam");
57
58static unsigned int nocomb = 0;
59module_param(nocomb,int,0644);
60MODULE_PARM_DESC(nocomb,"disable comb filter");
61
62#define dprintk(level,fmt, arg...) if (core_debug >= level) \
63 printk(KERN_DEBUG "%s: " fmt, core->name , ## arg)
64
65static unsigned int cx88_devcount;
66static LIST_HEAD(cx88_devlist);
1e4baed3 67static DEFINE_MUTEX(devlist);
1da177e4 68
1da177e4
LT		 69#define NO_SYNC_LINE (-1U)
70
05b27233
TP		 71/* @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be
72 generated _after_ lpi lines are transferred. */
1da177e4
LT		 73static u32* cx88_risc_field(u32 *rp, struct scatterlist *sglist,
74 unsigned int offset, u32 sync_line,
75 unsigned int bpl, unsigned int padding,
05b27233 76 unsigned int lines, unsigned int lpi)
1da177e4
LT		 77{
78 struct scatterlist *sg;
05b27233 79 unsigned int line,todo,sol;
1da177e4
LT		 80
81 /* sync instruction */
82 if (sync_line != NO_SYNC_LINE)
83 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
84
85 /* scan lines */
86 sg = sglist;
87 for (line = 0; line < lines; line++) {
88 while (offset && offset >= sg_dma_len(sg)) {
89 offset -= sg_dma_len(sg);
90 sg++;
91 }
05b27233
TP		 92 if (lpi && line>0 && !(line % lpi))
93 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
94 else
95 sol = RISC_SOL;
1da177e4
LT		 96 if (bpl <= sg_dma_len(sg)-offset) {
97 /* fits into current chunk */
05b27233 98 *(rp++)=cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl);
4ac97914
MCC		 99 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
100 offset+=bpl;
1da177e4 101 } else {
d1009bd7 102 /* scanline needs to be split */
4ac97914 103 todo = bpl;
05b27233 104 *(rp++)=cpu_to_le32(RISC_WRITE|sol|
1da177e4 105 (sg_dma_len(sg)-offset));
4ac97914
MCC		 106 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
107 todo -= (sg_dma_len(sg)-offset);
108 offset = 0;
109 sg++;
110 while (todo > sg_dma_len(sg)) {
f2421ca3 111 *(rp++)=cpu_to_le32(RISC_WRITE|
1da177e4 112 sg_dma_len(sg));
f2421ca3 113 *(rp++)=cpu_to_le32(sg_dma_address(sg));
1da177e4
LT		 114 todo -= sg_dma_len(sg);
115 sg++;
116 }
4ac97914 117 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1da177e4
LT		 118 *(rp++)=cpu_to_le32(sg_dma_address(sg));
119 offset += todo;
120 }
121 offset += padding;
122 }
123
124 return rp;
125}
126
127int cx88_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
128 struct scatterlist *sglist,
129 unsigned int top_offset, unsigned int bottom_offset,
130 unsigned int bpl, unsigned int padding, unsigned int lines)
131{
132 u32 instructions,fields;
133 u32 *rp;
134 int rc;
135
136 fields = 0;
137 if (UNSET != top_offset)
138 fields++;
139 if (UNSET != bottom_offset)
140 fields++;
141
142 /* estimate risc mem: worst case is one write per page border +
bba3ad76
DS		 143 one write per scan line + syncs + jump (all 2 dwords). Padding
144 can cause next bpl to start close to a page border. First DMA
145 region may be smaller than PAGE_SIZE */
146 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
147 instructions += 2;
1da177e4
LT		 148 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
149 return rc;
150
151 /* write risc instructions */
152 rp = risc->cpu;
153 if (UNSET != top_offset)
154 rp = cx88_risc_field(rp, sglist, top_offset, 0,
05b27233 155 bpl, padding, lines, 0);
1da177e4
LT		 156 if (UNSET != bottom_offset)
157 rp = cx88_risc_field(rp, sglist, bottom_offset, 0x200,
05b27233 158 bpl, padding, lines, 0);
1da177e4
LT		 159
160 /* save pointer to jmp instruction address */
161 risc->jmp = rp;
4a287cfe 162 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1da177e4
LT		 163 return 0;
164}
165
166int cx88_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
167 struct scatterlist *sglist, unsigned int bpl,
05b27233 168 unsigned int lines, unsigned int lpi)
1da177e4
LT		 169{
170 u32 instructions;
171 u32 *rp;
172 int rc;
173
174 /* estimate risc mem: worst case is one write per page border +
bba3ad76
DS		 175 one write per scan line + syncs + jump (all 2 dwords). Here
176 there is no padding and no sync. First DMA region may be smaller
177 than PAGE_SIZE */
178 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
179 instructions += 1;
1da177e4
LT		 180 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
181 return rc;
182
183 /* write risc instructions */
184 rp = risc->cpu;
05b27233 185 rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines, lpi);
1da177e4
LT		 186
187 /* save pointer to jmp instruction address */
188 risc->jmp = rp;
4a287cfe 189 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1da177e4
LT		 190 return 0;
191}
192
193int cx88_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
194 u32 reg, u32 mask, u32 value)
195{
196 u32 *rp;
197 int rc;
198
199 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
200 return rc;
201
202 /* write risc instructions */
203 rp = risc->cpu;
204 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2 | RISC_IMM);
205 *(rp++) = cpu_to_le32(reg);
206 *(rp++) = cpu_to_le32(value);
207 *(rp++) = cpu_to_le32(mask);
208 *(rp++) = cpu_to_le32(RISC_JUMP);
209 *(rp++) = cpu_to_le32(risc->dma);
210 return 0;
211}
212
213void
c7b0ac05 214cx88_free_buffer(struct videobuf_queue *q, struct cx88_buffer *buf)
1da177e4 215{
ae24601b 216 BUG_ON(in_interrupt());
1da177e4 217 videobuf_waiton(&buf->vb,0,0);
c7b0ac05 218 videobuf_dma_unmap(q, &buf->vb.dma);
1da177e4 219 videobuf_dma_free(&buf->vb.dma);
c7b0ac05 220 btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
1da177e4
LT		 221 buf->vb.state = STATE_NEEDS_INIT;
222}
223
224/* ------------------------------------------------------------------ */
225/* our SRAM memory layout */
226
227/* we are going to put all thr risc programs into host memory, so we
228 * can use the whole SDRAM for the DMA fifos. To simplify things, we
229 * use a static memory layout. That surely will waste memory in case
230 * we don't use all DMA channels at the same time (which will be the
231 * case most of the time). But that still gives us enougth FIFO space
232 * to be able to deal with insane long pci latencies ...
233 *
234 * FIFO space allocations:
235 * channel 21 (y video) - 10.0k
236 * channel 22 (u video) - 2.0k
237 * channel 23 (v video) - 2.0k
238 * channel 24 (vbi) - 4.0k
b7f355d2 239 * channels 25+26 (audio) - 4.0k
1da177e4 240 * channel 28 (mpeg) - 4.0k
b7f355d2 241 * TOTAL = 29.0k
1da177e4
LT		 242 *
243 * Every channel has 160 bytes control data (64 bytes instruction
244 * queue and 6 CDT entries), which is close to 2k total.
245 *
246 * Address layout:
247 * 0x0000 - 0x03ff CMDs / reserved
248 * 0x0400 - 0x0bff instruction queues + CDs
249 * 0x0c00 - FIFOs
250 */
251
252struct sram_channel cx88_sram_channels[] = {
253 [SRAM_CH21] = {
254 .name = "video y / packed",
255 .cmds_start = 0x180040,
256 .ctrl_start = 0x180400,
4ac97914 257 .cdt = 0x180400 + 64,
1da177e4
LT		 258 .fifo_start = 0x180c00,
259 .fifo_size = 0x002800,
260 .ptr1_reg = MO_DMA21_PTR1,
261 .ptr2_reg = MO_DMA21_PTR2,
262 .cnt1_reg = MO_DMA21_CNT1,
263 .cnt2_reg = MO_DMA21_CNT2,
264 },
265 [SRAM_CH22] = {
266 .name = "video u",
267 .cmds_start = 0x180080,
268 .ctrl_start = 0x1804a0,
4ac97914 269 .cdt = 0x1804a0 + 64,
1da177e4
LT		 270 .fifo_start = 0x183400,
271 .fifo_size = 0x000800,
272 .ptr1_reg = MO_DMA22_PTR1,
273 .ptr2_reg = MO_DMA22_PTR2,
274 .cnt1_reg = MO_DMA22_CNT1,
275 .cnt2_reg = MO_DMA22_CNT2,
276 },
277 [SRAM_CH23] = {
278 .name = "video v",
279 .cmds_start = 0x1800c0,
280 .ctrl_start = 0x180540,
4ac97914 281 .cdt = 0x180540 + 64,
1da177e4
LT		 282 .fifo_start = 0x183c00,
283 .fifo_size = 0x000800,
284 .ptr1_reg = MO_DMA23_PTR1,
285 .ptr2_reg = MO_DMA23_PTR2,
286 .cnt1_reg = MO_DMA23_CNT1,
287 .cnt2_reg = MO_DMA23_CNT2,
288 },
289 [SRAM_CH24] = {
290 .name = "vbi",
291 .cmds_start = 0x180100,
292 .ctrl_start = 0x1805e0,
4ac97914 293 .cdt = 0x1805e0 + 64,
1da177e4
LT		 294 .fifo_start = 0x184400,
295 .fifo_size = 0x001000,
296 .ptr1_reg = MO_DMA24_PTR1,
297 .ptr2_reg = MO_DMA24_PTR2,
298 .cnt1_reg = MO_DMA24_CNT1,
299 .cnt2_reg = MO_DMA24_CNT2,
300 },
301 [SRAM_CH25] = {
302 .name = "audio from",
303 .cmds_start = 0x180140,
304 .ctrl_start = 0x180680,
4ac97914 305 .cdt = 0x180680 + 64,
1da177e4 306 .fifo_start = 0x185400,
b7f355d2 307 .fifo_size = 0x001000,
1da177e4
LT		 308 .ptr1_reg = MO_DMA25_PTR1,
309 .ptr2_reg = MO_DMA25_PTR2,
310 .cnt1_reg = MO_DMA25_CNT1,
311 .cnt2_reg = MO_DMA25_CNT2,
312 },
313 [SRAM_CH26] = {
314 .name = "audio to",
315 .cmds_start = 0x180180,
316 .ctrl_start = 0x180720,
4ac97914 317 .cdt = 0x180680 + 64, /* same as audio IN */
1da177e4 318 .fifo_start = 0x185400, /* same as audio IN */
b7f355d2 319 .fifo_size = 0x001000, /* same as audio IN */
1da177e4
LT		 320 .ptr1_reg = MO_DMA26_PTR1,
321 .ptr2_reg = MO_DMA26_PTR2,
322 .cnt1_reg = MO_DMA26_CNT1,
323 .cnt2_reg = MO_DMA26_CNT2,
324 },
325 [SRAM_CH28] = {
326 .name = "mpeg",
327 .cmds_start = 0x180200,
328 .ctrl_start = 0x1807C0,
329 .cdt = 0x1807C0 + 64,
b7f355d2 330 .fifo_start = 0x186400,
1da177e4
LT		 331 .fifo_size = 0x001000,
332 .ptr1_reg = MO_DMA28_PTR1,
333 .ptr2_reg = MO_DMA28_PTR2,
334 .cnt1_reg = MO_DMA28_CNT1,
335 .cnt2_reg = MO_DMA28_CNT2,
336 },
337};
338
339int cx88_sram_channel_setup(struct cx88_core *core,
340 struct sram_channel *ch,
341 unsigned int bpl, u32 risc)
342{
343 unsigned int i,lines;
344 u32 cdt;
345
346 bpl = (bpl + 7) & ~7; /* alignment */
347 cdt = ch->cdt;
348 lines = ch->fifo_size / bpl;
349 if (lines > 6)
350 lines = 6;
351 BUG_ON(lines < 2);
352
353 /* write CDT */
354 for (i = 0; i < lines; i++)
355 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
356
357 /* write CMDS */
358 cx_write(ch->cmds_start + 0, risc);
359 cx_write(ch->cmds_start + 4, cdt);
360 cx_write(ch->cmds_start + 8, (lines*16) >> 3);
361 cx_write(ch->cmds_start + 12, ch->ctrl_start);
362 cx_write(ch->cmds_start + 16, 64 >> 2);
363 for (i = 20; i < 64; i += 4)
364 cx_write(ch->cmds_start + i, 0);
365
366 /* fill registers */
367 cx_write(ch->ptr1_reg, ch->fifo_start);
368 cx_write(ch->ptr2_reg, cdt);
369 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
370 cx_write(ch->cnt2_reg, (lines*16) >> 3);
371
372 dprintk(2,"sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines);
373 return 0;
374}
375
376/* ------------------------------------------------------------------ */
377/* debug helper code */
378
f9e7a020 379static int cx88_risc_decode(u32 risc)
1da177e4
LT		 380{
381 static char *instr[16] = {
382 [ RISC_SYNC >> 28 ] = "sync",
383 [ RISC_WRITE >> 28 ] = "write",
384 [ RISC_WRITEC >> 28 ] = "writec",
385 [ RISC_READ >> 28 ] = "read",
386 [ RISC_READC >> 28 ] = "readc",
387 [ RISC_JUMP >> 28 ] = "jump",
388 [ RISC_SKIP >> 28 ] = "skip",
389 [ RISC_WRITERM >> 28 ] = "writerm",
390 [ RISC_WRITECM >> 28 ] = "writecm",
391 [ RISC_WRITECR >> 28 ] = "writecr",
392 };
393 static int incr[16] = {
394 [ RISC_WRITE >> 28 ] = 2,
395 [ RISC_JUMP >> 28 ] = 2,
396 [ RISC_WRITERM >> 28 ] = 3,
397 [ RISC_WRITECM >> 28 ] = 3,
398 [ RISC_WRITECR >> 28 ] = 4,
399 };
400 static char *bits[] = {
401 "12", "13", "14", "resync",
402 "cnt0", "cnt1", "18", "19",
403 "20", "21", "22", "23",
404 "irq1", "irq2", "eol", "sol",
405 };
406 int i;
407
408 printk("0x%08x [ %s", risc,
409 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
410 for (i = ARRAY_SIZE(bits)-1; i >= 0; i--)
411 if (risc & (1 << (i + 12)))
412 printk(" %s",bits[i]);
413 printk(" count=%d ]\n", risc & 0xfff);
414 return incr[risc >> 28] ? incr[risc >> 28] : 1;
415}
416
1da177e4
LT		 417
418void cx88_sram_channel_dump(struct cx88_core *core,
419 struct sram_channel *ch)
420{
421 static char *name[] = {
422 "initial risc",
423 "cdt base",
424 "cdt size",
425 "iq base",
426 "iq size",
427 "risc pc",
428 "iq wr ptr",
429 "iq rd ptr",
430 "cdt current",
431 "pci target",
432 "line / byte",
433 };
434 u32 risc;
435 unsigned int i,j,n;
436
437 printk("%s: %s - dma channel status dump\n",
438 core->name,ch->name);
439 for (i = 0; i < ARRAY_SIZE(name); i++)
440 printk("%s: cmds: %-12s: 0x%08x\n",
441 core->name,name[i],
442 cx_read(ch->cmds_start + 4*i));
16cf1d0c 443 for (n = 1, i = 0; i < 4; i++) {
1da177e4
LT		 444 risc = cx_read(ch->cmds_start + 4 * (i+11));
445 printk("%s: risc%d: ", core->name, i);
16cf1d0c
TP		 446 if (--n)
447 printk("0x%08x [ arg #%d ]\n", risc, n);
448 else
449 n = cx88_risc_decode(risc);
1da177e4
LT		 450 }
451 for (i = 0; i < 16; i += n) {
452 risc = cx_read(ch->ctrl_start + 4 * i);
453 printk("%s: iq %x: ", core->name, i);
454 n = cx88_risc_decode(risc);
455 for (j = 1; j < n; j++) {
456 risc = cx_read(ch->ctrl_start + 4 * (i+j));
457 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
458 core->name, i+j, risc, j);
459 }
460 }
461
462 printk("%s: fifo: 0x%08x -> 0x%x\n",
463 core->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
464 printk("%s: ctrl: 0x%08x -> 0x%x\n",
465 core->name, ch->ctrl_start, ch->ctrl_start+6*16);
466 printk("%s: ptr1_reg: 0x%08x\n",
467 core->name,cx_read(ch->ptr1_reg));
468 printk("%s: ptr2_reg: 0x%08x\n",
469 core->name,cx_read(ch->ptr2_reg));
470 printk("%s: cnt1_reg: 0x%08x\n",
471 core->name,cx_read(ch->cnt1_reg));
472 printk("%s: cnt2_reg: 0x%08x\n",
473 core->name,cx_read(ch->cnt2_reg));
474}
475
408b664a 476static char *cx88_pci_irqs[32] = {
1da177e4
LT		 477 "vid", "aud", "ts", "vip", "hst", "5", "6", "tm1",
478 "src_dma", "dst_dma", "risc_rd_err", "risc_wr_err",
479 "brdg_err", "src_dma_err", "dst_dma_err", "ipb_dma_err",
480 "i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1"
481};
1da177e4
LT		 482
483void cx88_print_irqbits(char *name, char *tag, char **strings,
66623a04 484 int len, u32 bits, u32 mask)
1da177e4
LT		 485{
486 unsigned int i;
487
488 printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits);
66623a04 489 for (i = 0; i < len; i++) {
1da177e4
LT		 490 if (!(bits & (1 << i)))
491 continue;
492 if (strings[i])
493 printk(" %s", strings[i]);
494 else
495 printk(" %d", i);
496 if (!(mask & (1 << i)))
497 continue;
498 printk("*");
499 }
500 printk("\n");
501}
502
503/* ------------------------------------------------------------------ */
504
505int cx88_core_irq(struct cx88_core *core, u32 status)
506{
507 int handled = 0;
508
8ddac9ee 509 if (status & PCI_INT_IR_SMPINT) {
1da177e4
LT		 510 cx88_ir_irq(core);
511 handled++;
512 }
513 if (!handled)
514 cx88_print_irqbits(core->name, "irq pci",
66623a04
MCC		 515 cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs),
516 status, core->pci_irqmask);
1da177e4
LT		 517 return handled;
518}
519
520void cx88_wakeup(struct cx88_core *core,
521 struct cx88_dmaqueue *q, u32 count)
522{
523 struct cx88_buffer *buf;
524 int bc;
525
526 for (bc = 0;; bc++) {
527 if (list_empty(&q->active))
528 break;
529 buf = list_entry(q->active.next,
530 struct cx88_buffer, vb.queue);
1da177e4
LT		 531 /* count comes from the hw and is is 16bit wide --
532 * this trick handles wrap-arounds correctly for
533 * up to 32767 buffers in flight... */
534 if ((s16) (count - buf->count) < 0)
535 break;
1da177e4
LT		 536 do_gettimeofday(&buf->vb.ts);
537 dprintk(2,"[%p/%d] wakeup reg=%d buf=%d\n",buf,buf->vb.i,
538 count, buf->count);
539 buf->vb.state = STATE_DONE;
540 list_del(&buf->vb.queue);
541 wake_up(&buf->vb.done);
542 }
543 if (list_empty(&q->active)) {
544 del_timer(&q->timeout);
545 } else {
546 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
547 }
548 if (bc != 1)
549 printk("%s: %d buffers handled (should be 1)\n",__FUNCTION__,bc);
550}
551
552void cx88_shutdown(struct cx88_core *core)
553{
554 /* disable RISC controller + IRQs */
555 cx_write(MO_DEV_CNTRL2, 0);
556
557 /* stop dma transfers */
558 cx_write(MO_VID_DMACNTRL, 0x0);
559 cx_write(MO_AUD_DMACNTRL, 0x0);
560 cx_write(MO_TS_DMACNTRL, 0x0);
561 cx_write(MO_VIP_DMACNTRL, 0x0);
562 cx_write(MO_GPHST_DMACNTRL, 0x0);
563
564 /* stop interrupts */
565 cx_write(MO_PCI_INTMSK, 0x0);
566 cx_write(MO_VID_INTMSK, 0x0);
567 cx_write(MO_AUD_INTMSK, 0x0);
568 cx_write(MO_TS_INTMSK, 0x0);
569 cx_write(MO_VIP_INTMSK, 0x0);
570 cx_write(MO_GPHST_INTMSK, 0x0);
571
572 /* stop capturing */
573 cx_write(VID_CAPTURE_CONTROL, 0);
574}
575
576int cx88_reset(struct cx88_core *core)
577{
578 dprintk(1,"%s\n",__FUNCTION__);
579 cx88_shutdown(core);
580
581 /* clear irq status */
582 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
583 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
584 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
585
586 /* wait a bit */
587 msleep(100);
588
589 /* init sram */
590 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], 720*4, 0);
591 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0);
592 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0);
593 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0);
594 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0);
595 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0);
596 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], 188*4, 0);
597
598 /* misc init ... */
599 cx_write(MO_INPUT_FORMAT, ((1 << 13) | // agc enable
600 (1 << 12) | // agc gain
601 (1 << 11) | // adaptibe agc
602 (0 << 10) | // chroma agc
603 (0 << 9) | // ckillen
604 (7)));
605
606 /* setup image format */
607 cx_andor(MO_COLOR_CTRL, 0x4000, 0x4000);
608
609 /* setup FIFO Threshholds */
610 cx_write(MO_PDMA_STHRSH, 0x0807);
611 cx_write(MO_PDMA_DTHRSH, 0x0807);
612
613 /* fixes flashing of image */
614 cx_write(MO_AGC_SYNC_TIP1, 0x0380000F);
615 cx_write(MO_AGC_BACK_VBI, 0x00E00555);
616
617 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
618 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
619 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
620
621 /* Reset on-board parts */
622 cx_write(MO_SRST_IO, 0);
623 msleep(10);
624 cx_write(MO_SRST_IO, 1);
625
626 return 0;
627}
628
629/* ------------------------------------------------------------------ */
630
63ab1bdc 631static unsigned int inline norm_swidth(v4l2_std_id norm)
1da177e4 632{
63ab1bdc 633 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
1da177e4
LT		 634}
635
63ab1bdc 636static unsigned int inline norm_hdelay(v4l2_std_id norm)
1da177e4 637{
63ab1bdc 638 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 135 : 186;
1da177e4
LT		 639}
640
63ab1bdc 641static unsigned int inline norm_vdelay(v4l2_std_id norm)
1da177e4 642{
63ab1bdc 643 return (norm & V4L2_STD_625_50) ? 0x24 : 0x18;
1da177e4
LT		 644}
645
63ab1bdc 646static unsigned int inline norm_fsc8(v4l2_std_id norm)
1da177e4 647{
63ab1bdc 648 if (norm & V4L2_STD_PAL_M)
315eb962
MCC		 649 return 28604892; // 3.575611 MHz
650
63ab1bdc 651 if (norm & (V4L2_STD_PAL_Nc))
315eb962
MCC		 652 return 28656448; // 3.582056 MHz
653
63ab1bdc 654 if (norm & V4L2_STD_NTSC) // All NTSC/M and variants
315eb962 655 return 28636360; // 3.57954545 MHz +/- 10 Hz
1da177e4 656
315eb962
MCC		 657 /* SECAM have also different sub carrier for chroma,
658 but step_db and step_dr, at cx88_set_tvnorm already handles that.
659
660 The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N
661 */
662
663 return 35468950; // 4.43361875 MHz +/- 5 Hz
1da177e4
LT		 664}
665
63ab1bdc 666static unsigned int inline norm_htotal(v4l2_std_id norm)
1da177e4 667{
59dcd948 668
315eb962 669 unsigned int fsc4=norm_fsc8(norm)/2;
59dcd948 670
315eb962 671 /* returns 4*FSC / vtotal / frames per seconds */
63ab1bdc 672 return (norm & V4L2_STD_625_50) ?
315eb962
MCC		 673 ((fsc4+312)/625+12)/25 :
674 ((fsc4+262)/525*1001+15000)/30000;
1da177e4
LT		 675}
676
63ab1bdc 677static unsigned int inline norm_vbipack(v4l2_std_id norm)
1da177e4 678{
63ab1bdc 679 return (norm & V4L2_STD_625_50) ? 511 : 400;
1da177e4
LT		 680}
681
682int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int height,
683 enum v4l2_field field)
684{
685 unsigned int swidth = norm_swidth(core->tvnorm);
686 unsigned int sheight = norm_maxh(core->tvnorm);
687 u32 value;
688
689 dprintk(1,"set_scale: %dx%d [%s%s,%s]\n", width, height,
690 V4L2_FIELD_HAS_TOP(field) ? "T" : "",
691 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
63ab1bdc 692 v4l2_norm_to_name(core->tvnorm));
1da177e4
LT		 693 if (!V4L2_FIELD_HAS_BOTH(field))
694 height *= 2;
695
696 // recalc H delay and scale registers
697 value = (width * norm_hdelay(core->tvnorm)) / swidth;
698 value &= 0x3fe;
699 cx_write(MO_HDELAY_EVEN, value);
700 cx_write(MO_HDELAY_ODD, value);
315eb962 701 dprintk(1,"set_scale: hdelay 0x%04x (width %d)\n", value,swidth);
1da177e4
LT		 702
703 value = (swidth * 4096 / width) - 4096;
704 cx_write(MO_HSCALE_EVEN, value);
705 cx_write(MO_HSCALE_ODD, value);
706 dprintk(1,"set_scale: hscale 0x%04x\n", value);
707
708 cx_write(MO_HACTIVE_EVEN, width);
709 cx_write(MO_HACTIVE_ODD, width);
710 dprintk(1,"set_scale: hactive 0x%04x\n", width);
711
712 // recalc V scale Register (delay is constant)
713 cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm));
714 cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm));
715 dprintk(1,"set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm));
716
717 value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff;
718 cx_write(MO_VSCALE_EVEN, value);
719 cx_write(MO_VSCALE_ODD, value);
720 dprintk(1,"set_scale: vscale 0x%04x\n", value);
721
722 cx_write(MO_VACTIVE_EVEN, sheight);
723 cx_write(MO_VACTIVE_ODD, sheight);
724 dprintk(1,"set_scale: vactive 0x%04x\n", sheight);
725
726 // setup filters
727 value = 0;
728 value |= (1 << 19); // CFILT (default)
63ab1bdc 729 if (core->tvnorm & V4L2_STD_SECAM) {
1da177e4
LT		 730 value |= (1 << 15);
731 value |= (1 << 16);
732 }
6a59d64c 733 if (INPUT(core->input).type == CX88_VMUX_SVIDEO)
1da177e4
LT		 734 value |= (1 << 13) | (1 << 5);
735 if (V4L2_FIELD_INTERLACED == field)
736 value |= (1 << 3); // VINT (interlaced vertical scaling)
737 if (width < 385)
738 value |= (1 << 0); // 3-tap interpolation
739 if (width < 193)
740 value |= (1 << 1); // 5-tap interpolation
741 if (nocomb)
742 value |= (3 << 5); // disable comb filter
743
744 cx_write(MO_FILTER_EVEN, value);
745 cx_write(MO_FILTER_ODD, value);
746 dprintk(1,"set_scale: filter 0x%04x\n", value);
747
748 return 0;
749}
750
751static const u32 xtal = 28636363;
752
753static int set_pll(struct cx88_core *core, int prescale, u32 ofreq)
754{
755 static u32 pre[] = { 0, 0, 0, 3, 2, 1 };
756 u64 pll;
757 u32 reg;
758 int i;
759
760 if (prescale < 2)
761 prescale = 2;
762 if (prescale > 5)
763 prescale = 5;
764
765 pll = ofreq * 8 * prescale * (u64)(1 << 20);
766 do_div(pll,xtal);
767 reg = (pll & 0x3ffffff) | (pre[prescale] << 26);
768 if (((reg >> 20) & 0x3f) < 14) {
769 printk("%s/0: pll out of range\n",core->name);
770 return -1;
771 }
772
773 dprintk(1,"set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n",
774 reg, cx_read(MO_PLL_REG), ofreq);
775 cx_write(MO_PLL_REG, reg);
776 for (i = 0; i < 100; i++) {
777 reg = cx_read(MO_DEVICE_STATUS);
778 if (reg & (1<<2)) {
779 dprintk(1,"pll locked [pre=%d,ofreq=%d]\n",
780 prescale,ofreq);
781 return 0;
782 }
783 dprintk(1,"pll not locked yet, waiting ...\n");
784 msleep(10);
785 }
786 dprintk(1,"pll NOT locked [pre=%d,ofreq=%d]\n",prescale,ofreq);
787 return -1;
788}
789
6f502b8a
MCC		 790int cx88_start_audio_dma(struct cx88_core *core)
791{
17801f5f
MR		 792 /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */
793 int bpl = cx88_sram_channels[SRAM_CH25].fifo_size/4;
e738e35d
RC		 794
795 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */
796 if (cx_read(MO_AUD_DMACNTRL) & 0x10)
797 return 0;
798
6f502b8a 799 /* setup fifo + format */
17801f5f
MR		 800 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0);
801 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0);
6f502b8a 802
17801f5f
MR		 803 cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */
804 cx_write(MO_AUDR_LNGTH, bpl); /* fifo bpl size */
6f502b8a
MCC		 805
806 /* start dma */
807 cx_write(MO_AUD_DMACNTRL, 0x0003); /* Up and Down fifo enable */
e738e35d 808
6f502b8a
MCC		 809 return 0;
810}
811
812int cx88_stop_audio_dma(struct cx88_core *core)
813{
e738e35d
RC		 814 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */
815 if (cx_read(MO_AUD_DMACNTRL) & 0x10)
816 return 0;
817
6f502b8a
MCC		 818 /* stop dma */
819 cx_write(MO_AUD_DMACNTRL, 0x0000);
820
821 return 0;
822}
823
1da177e4
LT		 824static int set_tvaudio(struct cx88_core *core)
825{
63ab1bdc 826 v4l2_std_id norm = core->tvnorm;
1da177e4 827
6a59d64c 828 if (CX88_VMUX_TELEVISION != INPUT(core->input).type)
1da177e4
LT		 829 return 0;
830
63ab1bdc 831 if (V4L2_STD_PAL_BG & norm) {
b1706b91 832 core->tvaudio = WW_BG;
1da177e4 833
63ab1bdc 834 } else if (V4L2_STD_PAL_DK & norm) {
b1706b91 835 core->tvaudio = WW_DK;
1da177e4 836
63ab1bdc 837 } else if (V4L2_STD_PAL_I & norm) {
b1706b91 838 core->tvaudio = WW_I;
1da177e4 839
63ab1bdc 840 } else if (V4L2_STD_SECAM_L & norm) {
b1706b91 841 core->tvaudio = WW_L;
1da177e4 842
63ab1bdc 843 } else if (V4L2_STD_SECAM_DK & norm) {
b1706b91 844 core->tvaudio = WW_DK;
1da177e4 845
63ab1bdc
MCC		 846 } else if ((V4L2_STD_NTSC_M & norm) ||
847 (V4L2_STD_PAL_M & norm)) {
1da177e4
LT		 848 core->tvaudio = WW_BTSC;
849
63ab1bdc 850 } else if (V4L2_STD_NTSC_M_JP & norm) {
1da177e4
LT		 851 core->tvaudio = WW_EIAJ;
852
853 } else {
854 printk("%s/0: tvaudio support needs work for this tv norm [%s], sorry\n",
63ab1bdc 855 core->name, v4l2_norm_to_name(core->tvnorm));
1da177e4
LT		 856 core->tvaudio = 0;
857 return 0;
858 }
859
860 cx_andor(MO_AFECFG_IO, 0x1f, 0x0);
861 cx88_set_tvaudio(core);
e52e98a7 862 /* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */
1da177e4 863
6f502b8a
MCC		 864/*
865 This should be needed only on cx88-alsa. It seems that some cx88 chips have
866 bugs and does require DMA enabled for it to work.
867 */
868 cx88_start_audio_dma(core);
1da177e4
LT		 869 return 0;
870}
871
6f502b8a
MCC		 872
873
63ab1bdc 874int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm)
1da177e4
LT		 875{
876 u32 fsc8;
877 u32 adc_clock;
878 u32 vdec_clock;
879 u32 step_db,step_dr;
880 u64 tmp64;
881 u32 bdelay,agcdelay,htotal;
8d87cb9f 882 u32 cxiformat, cxoformat;
1da177e4
LT		 883
884 core->tvnorm = norm;
885 fsc8 = norm_fsc8(norm);
886 adc_clock = xtal;
887 vdec_clock = fsc8;
888 step_db = fsc8;
889 step_dr = fsc8;
890
63ab1bdc 891 if (norm & V4L2_STD_NTSC_M_JP) {
8d87cb9f
MCC		 892 cxiformat = VideoFormatNTSCJapan;
893 cxoformat = 0x181f0008;
63ab1bdc 894 } else if (norm & V4L2_STD_NTSC_443) {
1427f6b6
MCC		 895 cxiformat = VideoFormatNTSC443;
896 cxoformat = 0x181f0008;
63ab1bdc 897 } else if (norm & V4L2_STD_PAL_M) {
8d87cb9f
MCC		 898 cxiformat = VideoFormatPALM;
899 cxoformat = 0x1c1f0008;
63ab1bdc 900 } else if (norm & V4L2_STD_PAL_N) {
8d87cb9f
MCC		 901 cxiformat = VideoFormatPALN;
902 cxoformat = 0x1c1f0008;
63ab1bdc 903 } else if (norm & V4L2_STD_PAL_Nc) {
8d87cb9f
MCC		 904 cxiformat = VideoFormatPALNC;
905 cxoformat = 0x1c1f0008;
63ab1bdc 906 } else if (norm & V4L2_STD_PAL_60) {
8d87cb9f
MCC		 907 cxiformat = VideoFormatPAL60;
908 cxoformat = 0x181f0008;
63ab1bdc 909 } else if (norm & V4L2_STD_NTSC) {
8d87cb9f
MCC		 910 cxiformat = VideoFormatNTSC;
911 cxoformat = 0x181f0008;
63ab1bdc 912 } else if (norm & V4L2_STD_SECAM) {
1da177e4
LT		 913 step_db = 4250000 * 8;
914 step_dr = 4406250 * 8;
1427f6b6
MCC		 915
916 cxiformat = VideoFormatSECAM;
917 cxoformat = 0x181f0008;
8d87cb9f
MCC		 918 } else { /* PAL */
919 cxiformat = VideoFormatPAL;
920 cxoformat = 0x181f0008;
1da177e4
LT		 921 }
922
923 dprintk(1,"set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n",
63ab1bdc
MCC		 924 v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock,
925 step_db, step_dr);
1da177e4
LT		 926 set_pll(core,2,vdec_clock);
927
928 dprintk(1,"set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n",
8d87cb9f
MCC		 929 cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f);
930 cx_andor(MO_INPUT_FORMAT, 0xf, cxiformat);
1da177e4 931
1da177e4
LT		 932 // FIXME: as-is from DScaler
933 dprintk(1,"set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n",
8d87cb9f
MCC		 934 cxoformat, cx_read(MO_OUTPUT_FORMAT));
935 cx_write(MO_OUTPUT_FORMAT, cxoformat);
1da177e4
LT		 936
937 // MO_SCONV_REG = adc clock / video dec clock * 2^17
938 tmp64 = adc_clock * (u64)(1 << 17);
939 do_div(tmp64, vdec_clock);
940 dprintk(1,"set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n",
941 (u32)tmp64, cx_read(MO_SCONV_REG));
942 cx_write(MO_SCONV_REG, (u32)tmp64);
943
944 // MO_SUB_STEP = 8 * fsc / video dec clock * 2^22
945 tmp64 = step_db * (u64)(1 << 22);
946 do_div(tmp64, vdec_clock);
947 dprintk(1,"set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n",
948 (u32)tmp64, cx_read(MO_SUB_STEP));
949 cx_write(MO_SUB_STEP, (u32)tmp64);
950
951 // MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22
952 tmp64 = step_dr * (u64)(1 << 22);
953 do_div(tmp64, vdec_clock);
954 dprintk(1,"set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n",
955 (u32)tmp64, cx_read(MO_SUB_STEP_DR));
956 cx_write(MO_SUB_STEP_DR, (u32)tmp64);
957
958 // bdelay + agcdelay
959 bdelay = vdec_clock * 65 / 20000000 + 21;
960 agcdelay = vdec_clock * 68 / 20000000 + 15;
961 dprintk(1,"set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n",
962 (bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST), bdelay, agcdelay);
963 cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay);
964
965 // htotal
966 tmp64 = norm_htotal(norm) * (u64)vdec_clock;
967 do_div(tmp64, fsc8);
ccbf64b1 968 htotal = (u32)tmp64 | (HLNotchFilter4xFsc << 11);
1da177e4
LT		 969 dprintk(1,"set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n",
970 htotal, cx_read(MO_HTOTAL), (u32)tmp64);
971 cx_write(MO_HTOTAL, htotal);
972
3eb73170
TP		 973 // vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes
974 // the effective vbi offset ~244 samples, the same as the Bt8x8
975 cx_write(MO_VBI_PACKET, (10<<11) | norm_vbipack(norm));
1da177e4
LT		 976
977 // this is needed as well to set all tvnorm parameter
978 cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED);
979
980 // audio
981 set_tvaudio(core);
982
983 // tell i2c chips
63ab1bdc 984 cx88_call_i2c_clients(core,VIDIOC_S_STD,&norm);
1da177e4
LT		 985
986 // done
987 return 0;
988}
989
990/* ------------------------------------------------------------------ */
991
1da177e4
LT		 992struct video_device *cx88_vdev_init(struct cx88_core *core,
993 struct pci_dev *pci,
994 struct video_device *template,
995 char *type)
996{
997 struct video_device *vfd;
998
999 vfd = video_device_alloc();
1000 if (NULL == vfd)
1001 return NULL;
1002 *vfd = *template;
1003 vfd->minor = -1;
1004 vfd->dev = &pci->dev;
1005 vfd->release = video_device_release;
1006 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
6a59d64c 1007 core->name, type, core->board.name);
1da177e4
LT		 1008 return vfd;
1009}
1010
1da177e4
LT		 1011struct cx88_core* cx88_core_get(struct pci_dev *pci)
1012{
1013 struct cx88_core *core;
1014 struct list_head *item;
1da177e4 1015
1e4baed3 1016 mutex_lock(&devlist);
1da177e4
LT		 1017 list_for_each(item,&cx88_devlist) {
1018 core = list_entry(item, struct cx88_core, devlist);
1019 if (pci->bus->number != core->pci_bus)
1020 continue;
1021 if (PCI_SLOT(pci->devfn) != core->pci_slot)
1022 continue;
1023
bbc83597
TP		 1024 if (0 != cx88_get_resources(core, pci)) {
1025 mutex_unlock(&devlist);
1026 return NULL;
1027 }
1da177e4 1028 atomic_inc(&core->refcount);
1e4baed3 1029 mutex_unlock(&devlist);
1da177e4
LT		 1030 return core;
1031 }
b45009b0 1032
bbc83597
TP		 1033 core = cx88_core_create(pci, cx88_devcount);
1034 if (NULL != core) {
1035 cx88_devcount++;
1036 list_add_tail(&core->devlist, &cx88_devlist);
1037 }
1da177e4 1038
1e4baed3 1039 mutex_unlock(&devlist);
1da177e4 1040 return core;
1da177e4
LT		 1041}
1042
1043void cx88_core_put(struct cx88_core *core, struct pci_dev *pci)
1044{
1045 release_mem_region(pci_resource_start(pci,0),
1046 pci_resource_len(pci,0));
1047
1048 if (!atomic_dec_and_test(&core->refcount))
1049 return;
1050
1e4baed3 1051 mutex_lock(&devlist);
1da177e4
LT		 1052 cx88_ir_fini(core);
1053 if (0 == core->i2c_rc)
3269711b 1054 i2c_del_adapter(&core->i2c_adap);
1da177e4
LT		 1055 list_del(&core->devlist);
1056 iounmap(core->lmmio);
1057 cx88_devcount--;
1e4baed3 1058 mutex_unlock(&devlist);
1da177e4
LT		 1059 kfree(core);
1060}
1061
1062/* ------------------------------------------------------------------ */
1063
1da177e4
LT		 1064EXPORT_SYMBOL(cx88_print_irqbits);
1065
1066EXPORT_SYMBOL(cx88_core_irq);
1067EXPORT_SYMBOL(cx88_wakeup);
1068EXPORT_SYMBOL(cx88_reset);
1069EXPORT_SYMBOL(cx88_shutdown);
1070
1071EXPORT_SYMBOL(cx88_risc_buffer);
1072EXPORT_SYMBOL(cx88_risc_databuffer);
1073EXPORT_SYMBOL(cx88_risc_stopper);
1074EXPORT_SYMBOL(cx88_free_buffer);
1075
1076EXPORT_SYMBOL(cx88_sram_channels);
1077EXPORT_SYMBOL(cx88_sram_channel_setup);
1078EXPORT_SYMBOL(cx88_sram_channel_dump);
1079
1080EXPORT_SYMBOL(cx88_set_tvnorm);
1081EXPORT_SYMBOL(cx88_set_scale);
1082
1083EXPORT_SYMBOL(cx88_vdev_init);
1084EXPORT_SYMBOL(cx88_core_get);
1085EXPORT_SYMBOL(cx88_core_put);
1086
1087/*
1088 * Local variables:
1089 * c-basic-offset: 8
1090 * End:
e52e98a7 1091 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1da177e4 1092 */
Linux kernel - Deliverables
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