Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[deliverable/linux.git] / drivers / media / video / cx88 / cx88-dvb.c
CommitLineData
1da177e4 1/*
1da177e4
LT
2 *
3 * device driver for Conexant 2388x based TV cards
4 * MPEG Transport Stream (DVB) routines
5 *
fc40b261 6 * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
1da177e4
LT
7 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/device.h>
27#include <linux/fs.h>
28#include <linux/kthread.h>
29#include <linux/file.h>
30#include <linux/suspend.h>
31
1da177e4
LT
32#include "cx88.h"
33#include "dvb-pll.h"
5e453dc7 34#include <media/v4l2-common.h>
41ef7c1e 35
1f10c7af
AQ
36#include "mt352.h"
37#include "mt352_priv.h"
ecf854df 38#include "cx88-vp3054-i2c.h"
1f10c7af
AQ
39#include "zl10353.h"
40#include "cx22702.h"
41#include "or51132.h"
42#include "lgdt330x.h"
60464da8 43#include "s5h1409.h"
c21973e8 44#include "xc4000.h"
60464da8 45#include "xc5000.h"
1f10c7af
AQ
46#include "nxt200x.h"
47#include "cx24123.h"
cd20ca9f 48#include "isl6421.h"
0df31f83 49#include "tuner-simple.h"
827855d3 50#include "tda9887.h"
d893d5dc 51#include "s5h1411.h"
e4aab64c
IL
52#include "stv0299.h"
53#include "z0194a.h"
54#include "stv0288.h"
55#include "stb6000.h"
5bd1b663 56#include "cx24116.h"
b699c271
IL
57#include "stv0900.h"
58#include "stb6100.h"
59#include "stb6100_proc.h"
111ac84a 60#include "mb86a16.h"
0cb73639 61#include "ds3000.h"
1da177e4
LT
62
63MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
64MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
65MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
66MODULE_LICENSE("GPL");
1990d50b 67MODULE_VERSION(CX88_VERSION);
1da177e4 68
ff699e6b 69static unsigned int debug;
1da177e4
LT
70module_param(debug, int, 0644);
71MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
72
44c6e2a7
AWC
73static unsigned int dvb_buf_tscnt = 32;
74module_param(dvb_buf_tscnt, int, 0644);
75MODULE_PARM_DESC(dvb_buf_tscnt, "DVB Buffer TS count [dvb]");
76
78e92006
JG
77DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
78
1da177e4 79#define dprintk(level,fmt, arg...) if (debug >= level) \
6c5be74c 80 printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
1da177e4
LT
81
82/* ------------------------------------------------------------------ */
83
84static int dvb_buf_setup(struct videobuf_queue *q,
85 unsigned int *count, unsigned int *size)
86{
87 struct cx8802_dev *dev = q->priv_data;
88
89 dev->ts_packet_size = 188 * 4;
44c6e2a7 90 dev->ts_packet_count = dvb_buf_tscnt;
1da177e4
LT
91
92 *size = dev->ts_packet_size * dev->ts_packet_count;
44c6e2a7 93 *count = dvb_buf_tscnt;
1da177e4
LT
94 return 0;
95}
96
4a390558
MK
97static int dvb_buf_prepare(struct videobuf_queue *q,
98 struct videobuf_buffer *vb, enum v4l2_field field)
1da177e4
LT
99{
100 struct cx8802_dev *dev = q->priv_data;
c7b0ac05 101 return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
1da177e4
LT
102}
103
104static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
105{
106 struct cx8802_dev *dev = q->priv_data;
107 cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
108}
109
4a390558
MK
110static void dvb_buf_release(struct videobuf_queue *q,
111 struct videobuf_buffer *vb)
1da177e4 112{
c7b0ac05 113 cx88_free_buffer(q, (struct cx88_buffer*)vb);
1da177e4
LT
114}
115
2e4e98e7 116static const struct videobuf_queue_ops dvb_qops = {
1da177e4
LT
117 .buf_setup = dvb_buf_setup,
118 .buf_prepare = dvb_buf_prepare,
119 .buf_queue = dvb_buf_queue,
120 .buf_release = dvb_buf_release,
121};
122
123/* ------------------------------------------------------------------ */
22f3f17d
MK
124
125static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
126{
127 struct cx8802_dev *dev= fe->dvb->priv;
128 struct cx8802_driver *drv = NULL;
129 int ret = 0;
363c35fc
ST
130 int fe_id;
131
132 fe_id = videobuf_dvb_find_frontend(&dev->frontends, fe);
133 if (!fe_id) {
2af03eea 134 printk(KERN_ERR "%s() No frontend found\n", __func__);
363c35fc
ST
135 return -EINVAL;
136 }
137
8a317a87 138 mutex_lock(&dev->core->lock);
22f3f17d
MK
139 drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
140 if (drv) {
363c35fc
ST
141 if (acquire){
142 dev->frontends.active_fe_id = fe_id;
22f3f17d 143 ret = drv->request_acquire(drv);
363c35fc 144 } else {
22f3f17d 145 ret = drv->request_release(drv);
363c35fc
ST
146 dev->frontends.active_fe_id = 0;
147 }
22f3f17d 148 }
1fe70e96 149 mutex_unlock(&dev->core->lock);
22f3f17d
MK
150
151 return ret;
152}
153
e32fadc4
MCC
154static void cx88_dvb_gate_ctrl(struct cx88_core *core, int open)
155{
156 struct videobuf_dvb_frontends *f;
157 struct videobuf_dvb_frontend *fe;
158
159 if (!core->dvbdev)
160 return;
161
162 f = &core->dvbdev->frontends;
163
164 if (!f)
165 return;
166
167 if (f->gate <= 1) /* undefined or fe0 */
168 fe = videobuf_dvb_get_frontend(f, 1);
169 else
170 fe = videobuf_dvb_get_frontend(f, f->gate);
171
172 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
173 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
174}
175
22f3f17d
MK
176/* ------------------------------------------------------------------ */
177
3d7d027a 178static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
1da177e4 179{
2e4e98e7 180 static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
181 static const u8 reset [] = { RESET, 0x80 };
182 static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
183 static const u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
184 static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
185 static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
1da177e4
LT
186
187 mt352_write(fe, clock_config, sizeof(clock_config));
188 udelay(200);
189 mt352_write(fe, reset, sizeof(reset));
190 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
191
192 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
193 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
194 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
195 return 0;
196}
197
43eabb4e
CP
198static int dvico_dual_demod_init(struct dvb_frontend *fe)
199{
2e4e98e7 200 static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
201 static const u8 reset [] = { RESET, 0x80 };
202 static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
203 static const u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
204 static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
205 static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
43eabb4e
CP
206
207 mt352_write(fe, clock_config, sizeof(clock_config));
208 udelay(200);
209 mt352_write(fe, reset, sizeof(reset));
210 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
211
212 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
213 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
214 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
215
216 return 0;
217}
218
1da177e4
LT
219static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
220{
2e4e98e7 221 static const u8 clock_config [] = { 0x89, 0x38, 0x39 };
222 static const u8 reset [] = { 0x50, 0x80 };
223 static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
224 static const u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
f2421ca3 225 0x00, 0xFF, 0x00, 0x40, 0x40 };
2e4e98e7 226 static const u8 dntv_extra[] = { 0xB5, 0x7A };
227 static const u8 capt_range_cfg[] = { 0x75, 0x32 };
1da177e4
LT
228
229 mt352_write(fe, clock_config, sizeof(clock_config));
230 udelay(2000);
231 mt352_write(fe, reset, sizeof(reset));
232 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
233
234 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
235 udelay(2000);
236 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
237 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
238
239 return 0;
240}
241
2e4e98e7 242static const struct mt352_config dvico_fusionhdtv = {
f7b54b10 243 .demod_address = 0x0f,
3d7d027a 244 .demod_init = dvico_fusionhdtv_demod_init,
1da177e4
LT
245};
246
2e4e98e7 247static const struct mt352_config dntv_live_dvbt_config = {
1da177e4
LT
248 .demod_address = 0x0f,
249 .demod_init = dntv_live_dvbt_demod_init,
1da177e4 250};
fc40b261 251
2e4e98e7 252static const struct mt352_config dvico_fusionhdtv_dual = {
f7b54b10 253 .demod_address = 0x0f,
43eabb4e 254 .demod_init = dvico_dual_demod_init,
43eabb4e
CP
255};
256
2e4e98e7 257static const struct zl10353_config cx88_terratec_cinergy_ht_pci_mkii_config = {
70101a27
SW
258 .demod_address = (0x1e >> 1),
259 .no_tuner = 1,
260 .if2 = 45600,
261};
262
111ac84a
SI
263static struct mb86a16_config twinhan_vp1027 = {
264 .demod_address = 0x08,
265};
266
ecf854df 267#if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
3d7d027a
CP
268static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
269{
2e4e98e7 270 static const u8 clock_config [] = { 0x89, 0x38, 0x38 };
271 static const u8 reset [] = { 0x50, 0x80 };
272 static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
273 static const u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
3d7d027a 274 0x00, 0xFF, 0x00, 0x40, 0x40 };
2e4e98e7 275 static const u8 dntv_extra[] = { 0xB5, 0x7A };
276 static const u8 capt_range_cfg[] = { 0x75, 0x32 };
3d7d027a
CP
277
278 mt352_write(fe, clock_config, sizeof(clock_config));
279 udelay(2000);
280 mt352_write(fe, reset, sizeof(reset));
281 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
282
283 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
284 udelay(2000);
285 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
286 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
287
288 return 0;
289}
290
2e4e98e7 291static const struct mt352_config dntv_live_dvbt_pro_config = {
fc40b261
CP
292 .demod_address = 0x0f,
293 .no_tuner = 1,
3d7d027a 294 .demod_init = dntv_live_dvbt_pro_demod_init,
fc40b261
CP
295};
296#endif
1da177e4 297
2e4e98e7 298static const struct zl10353_config dvico_fusionhdtv_hybrid = {
f7b54b10 299 .demod_address = 0x0f,
f54376e2 300 .no_tuner = 1,
780dfef3
CP
301};
302
2e4e98e7 303static const struct zl10353_config dvico_fusionhdtv_xc3028 = {
b3fb91d2
CP
304 .demod_address = 0x0f,
305 .if2 = 45600,
306 .no_tuner = 1,
307};
308
2e4e98e7 309static const struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
b3fb91d2
CP
310 .demod_address = 0x0f,
311 .if2 = 4560,
312 .no_tuner = 1,
313 .demod_init = dvico_fusionhdtv_demod_init,
314};
315
2e4e98e7 316static const struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
f7b54b10 317 .demod_address = 0x0f,
780dfef3 318};
780dfef3 319
2e4e98e7 320static const struct cx22702_config connexant_refboard_config = {
1da177e4 321 .demod_address = 0x43,
38d84c3b 322 .output_mode = CX22702_SERIAL_OUTPUT,
1da177e4
LT
323};
324
2e4e98e7 325static const struct cx22702_config hauppauge_hvr_config = {
aa481a65
ST
326 .demod_address = 0x63,
327 .output_mode = CX22702_SERIAL_OUTPUT,
328};
1da177e4 329
4a390558 330static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
1da177e4
LT
331{
332 struct cx8802_dev *dev= fe->dvb->priv;
333 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
334 return 0;
335}
336
2e4e98e7 337static const struct or51132_config pchdtv_hd3000 = {
f7b54b10
MK
338 .demod_address = 0x15,
339 .set_ts_params = or51132_set_ts_param,
1da177e4 340};
1da177e4 341
6ddcc919 342static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
0ccef6db
MK
343{
344 struct cx8802_dev *dev= fe->dvb->priv;
345 struct cx88_core *core = dev->core;
346
32d83efc 347 dprintk(1, "%s: index = %d\n", __func__, index);
0ccef6db
MK
348 if (index == 0)
349 cx_clear(MO_GP0_IO, 8);
350 else
351 cx_set(MO_GP0_IO, 8);
352 return 0;
353}
354
6ddcc919 355static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
f1798495
MK
356{
357 struct cx8802_dev *dev= fe->dvb->priv;
358 if (is_punctured)
359 dev->ts_gen_cntrl |= 0x04;
360 else
361 dev->ts_gen_cntrl &= ~0x04;
362 return 0;
363}
364
6ddcc919 365static struct lgdt330x_config fusionhdtv_3_gold = {
f7b54b10
MK
366 .demod_address = 0x0e,
367 .demod_chip = LGDT3302,
368 .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
369 .set_ts_params = lgdt330x_set_ts_param,
0d723c09 370};
e52e98a7 371
2e4e98e7 372static const struct lgdt330x_config fusionhdtv_5_gold = {
f7b54b10
MK
373 .demod_address = 0x0e,
374 .demod_chip = LGDT3303,
375 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
376 .set_ts_params = lgdt330x_set_ts_param,
e52e98a7 377};
da215d22 378
2e4e98e7 379static const struct lgdt330x_config pchdtv_hd5500 = {
f7b54b10
MK
380 .demod_address = 0x59,
381 .demod_chip = LGDT3303,
382 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
383 .set_ts_params = lgdt330x_set_ts_param,
da215d22 384};
f1798495 385
4a390558 386static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
fde6d31e
KL
387{
388 struct cx8802_dev *dev= fe->dvb->priv;
389 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
390 return 0;
391}
392
2e4e98e7 393static const struct nxt200x_config ati_hdtvwonder = {
f7b54b10 394 .demod_address = 0x0a,
f7b54b10 395 .set_ts_params = nxt200x_set_ts_param,
fde6d31e 396};
fde6d31e 397
0fa14aa6
ST
398static int cx24123_set_ts_param(struct dvb_frontend* fe,
399 int is_punctured)
400{
401 struct cx8802_dev *dev= fe->dvb->priv;
f7b54b10 402 dev->ts_gen_cntrl = 0x02;
0fa14aa6
ST
403 return 0;
404}
405
f7b54b10
MK
406static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
407 fe_sec_voltage_t voltage)
0e0351e3
VC
408{
409 struct cx8802_dev *dev= fe->dvb->priv;
410 struct cx88_core *core = dev->core;
411
4a390558 412 if (voltage == SEC_VOLTAGE_OFF)
f7b54b10 413 cx_write(MO_GP0_IO, 0x000006fb);
4a390558 414 else
cd20ca9f 415 cx_write(MO_GP0_IO, 0x000006f9);
cd20ca9f
AQ
416
417 if (core->prev_set_voltage)
418 return core->prev_set_voltage(fe, voltage);
419 return 0;
0e0351e3
VC
420}
421
f7b54b10
MK
422static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
423 fe_sec_voltage_t voltage)
c02a34f4
SA
424{
425 struct cx8802_dev *dev= fe->dvb->priv;
426 struct cx88_core *core = dev->core;
427
428 if (voltage == SEC_VOLTAGE_OFF) {
429 dprintk(1,"LNB Voltage OFF\n");
430 cx_write(MO_GP0_IO, 0x0000efff);
431 }
432
433 if (core->prev_set_voltage)
434 return core->prev_set_voltage(fe, voltage);
435 return 0;
436}
437
af832623
IL
438static int tevii_dvbs_set_voltage(struct dvb_frontend *fe,
439 fe_sec_voltage_t voltage)
440{
441 struct cx8802_dev *dev= fe->dvb->priv;
442 struct cx88_core *core = dev->core;
443
ad5f74c0 444 cx_set(MO_GP0_IO, 0x6040);
af832623 445 switch (voltage) {
111ac84a
SI
446 case SEC_VOLTAGE_13:
447 cx_clear(MO_GP0_IO, 0x20);
448 break;
449 case SEC_VOLTAGE_18:
450 cx_set(MO_GP0_IO, 0x20);
451 break;
452 case SEC_VOLTAGE_OFF:
453 cx_clear(MO_GP0_IO, 0x20);
454 break;
455 }
456
457 if (core->prev_set_voltage)
458 return core->prev_set_voltage(fe, voltage);
459 return 0;
460}
461
462static int vp1027_set_voltage(struct dvb_frontend *fe,
463 fe_sec_voltage_t voltage)
464{
465 struct cx8802_dev *dev = fe->dvb->priv;
466 struct cx88_core *core = dev->core;
467
468 switch (voltage) {
469 case SEC_VOLTAGE_13:
470 dprintk(1, "LNB SEC Voltage=13\n");
471 cx_write(MO_GP0_IO, 0x00001220);
472 break;
473 case SEC_VOLTAGE_18:
474 dprintk(1, "LNB SEC Voltage=18\n");
475 cx_write(MO_GP0_IO, 0x00001222);
476 break;
477 case SEC_VOLTAGE_OFF:
478 dprintk(1, "LNB Voltage OFF\n");
479 cx_write(MO_GP0_IO, 0x00001230);
480 break;
af832623
IL
481 }
482
483 if (core->prev_set_voltage)
484 return core->prev_set_voltage(fe, voltage);
485 return 0;
486}
487
2e4e98e7 488static const struct cx24123_config geniatech_dvbs_config = {
f7b54b10
MK
489 .demod_address = 0x55,
490 .set_ts_params = cx24123_set_ts_param,
c02a34f4
SA
491};
492
2e4e98e7 493static const struct cx24123_config hauppauge_novas_config = {
f7b54b10
MK
494 .demod_address = 0x55,
495 .set_ts_params = cx24123_set_ts_param,
0e0351e3
VC
496};
497
2e4e98e7 498static const struct cx24123_config kworld_dvbs_100_config = {
f7b54b10
MK
499 .demod_address = 0x15,
500 .set_ts_params = cx24123_set_ts_param,
ef76856d 501 .lnb_polarity = 1,
0fa14aa6 502};
0fa14aa6 503
2e4e98e7 504static const struct s5h1409_config pinnacle_pctv_hd_800i_config = {
60464da8
ST
505 .demod_address = 0x32 >> 1,
506 .output_mode = S5H1409_PARALLEL_OUTPUT,
507 .gpio = S5H1409_GPIO_ON,
508 .qam_if = 44000,
509 .inversion = S5H1409_INVERSION_OFF,
510 .status_mode = S5H1409_DEMODLOCKING,
4917019d 511 .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK,
60464da8
ST
512};
513
2e4e98e7 514static const struct s5h1409_config dvico_hdtv5_pci_nano_config = {
5c00fac0
ST
515 .demod_address = 0x32 >> 1,
516 .output_mode = S5H1409_SERIAL_OUTPUT,
517 .gpio = S5H1409_GPIO_OFF,
518 .inversion = S5H1409_INVERSION_OFF,
519 .status_mode = S5H1409_DEMODLOCKING,
520 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
521};
522
2e4e98e7 523static const struct s5h1409_config kworld_atsc_120_config = {
99e09eac 524 .demod_address = 0x32 >> 1,
99e09eac
MCC
525 .output_mode = S5H1409_SERIAL_OUTPUT,
526 .gpio = S5H1409_GPIO_OFF,
527 .inversion = S5H1409_INVERSION_OFF,
528 .status_mode = S5H1409_DEMODLOCKING,
529 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
530};
531
2e4e98e7 532static const struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
60464da8
ST
533 .i2c_address = 0x64,
534 .if_khz = 5380,
60464da8
ST
535};
536
2e4e98e7 537static const struct zl10353_config cx88_pinnacle_hybrid_pctv = {
3f6014fc
SV
538 .demod_address = (0x1e >> 1),
539 .no_tuner = 1,
540 .if2 = 45600,
541};
542
2e4e98e7 543static const struct zl10353_config cx88_geniatech_x8000_mt = {
57069349
MCC
544 .demod_address = (0x1e >> 1),
545 .no_tuner = 1,
546 .disable_i2c_gate_ctrl = 1,
9507901e
MCC
547};
548
2e4e98e7 549static const struct s5h1411_config dvico_fusionhdtv7_config = {
d893d5dc
ST
550 .output_mode = S5H1411_SERIAL_OUTPUT,
551 .gpio = S5H1411_GPIO_ON,
552 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
553 .qam_if = S5H1411_IF_44000,
554 .vsb_if = S5H1411_IF_44000,
555 .inversion = S5H1411_INVERSION_OFF,
556 .status_mode = S5H1411_DEMODLOCKING
557};
558
2e4e98e7 559static const struct xc5000_config dvico_fusionhdtv7_tuner_config = {
d893d5dc
ST
560 .i2c_address = 0xc2 >> 1,
561 .if_khz = 5380,
d893d5dc
ST
562};
563
23fb348d
MCC
564static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
565{
566 struct dvb_frontend *fe;
363c35fc 567 struct videobuf_dvb_frontend *fe0 = NULL;
99e09eac 568 struct xc2028_ctrl ctl;
23fb348d
MCC
569 struct xc2028_config cfg = {
570 .i2c_adap = &dev->core->i2c_adap,
571 .i2c_addr = addr,
99e09eac 572 .ctrl = &ctl,
23fb348d
MCC
573 };
574
92abe9ee 575 /* Get the first frontend */
363c35fc
ST
576 fe0 = videobuf_dvb_get_frontend(&dev->frontends, 1);
577 if (!fe0)
578 return -EINVAL;
579
580 if (!fe0->dvb.frontend) {
ddd5441d
MCC
581 printk(KERN_ERR "%s/2: dvb frontend not attached. "
582 "Can't attach xc3028\n",
583 dev->core->name);
584 return -EINVAL;
585 }
586
99e09eac
MCC
587 /*
588 * Some xc3028 devices may be hidden by an I2C gate. This is known
589 * to happen with some s5h1409-based devices.
590 * Now that I2C gate is open, sets up xc3028 configuration
591 */
592 cx88_setup_xc3028(dev->core, &ctl);
593
363c35fc 594 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg);
23fb348d
MCC
595 if (!fe) {
596 printk(KERN_ERR "%s/2: xc3028 attach failed\n",
597 dev->core->name);
363c35fc
ST
598 dvb_frontend_detach(fe0->dvb.frontend);
599 dvb_unregister_frontend(fe0->dvb.frontend);
600 fe0->dvb.frontend = NULL;
23fb348d
MCC
601 return -EINVAL;
602 }
603
604 printk(KERN_INFO "%s/2: xc3028 attached\n",
605 dev->core->name);
606
607 return 0;
608}
9507901e 609
c21973e8 610static int attach_xc4000(struct cx8802_dev *dev, struct xc4000_config *cfg)
611{
612 struct dvb_frontend *fe;
613 struct videobuf_dvb_frontend *fe0 = NULL;
614
615 /* Get the first frontend */
616 fe0 = videobuf_dvb_get_frontend(&dev->frontends, 1);
617 if (!fe0)
618 return -EINVAL;
619
620 if (!fe0->dvb.frontend) {
621 printk(KERN_ERR "%s/2: dvb frontend not attached. "
622 "Can't attach xc4000\n",
623 dev->core->name);
624 return -EINVAL;
625 }
626
627 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, &dev->core->i2c_adap,
628 cfg);
629 if (!fe) {
630 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
631 dev->core->name);
632 dvb_frontend_detach(fe0->dvb.frontend);
633 dvb_unregister_frontend(fe0->dvb.frontend);
634 fe0->dvb.frontend = NULL;
635 return -EINVAL;
636 }
637
638 printk(KERN_INFO "%s/2: xc4000 attached\n", dev->core->name);
639
640 return 0;
641}
642
5bd1b663
ST
643static int cx24116_set_ts_param(struct dvb_frontend *fe,
644 int is_punctured)
645{
646 struct cx8802_dev *dev = fe->dvb->priv;
647 dev->ts_gen_cntrl = 0x2;
648
649 return 0;
650}
651
b699c271
IL
652static int stv0900_set_ts_param(struct dvb_frontend *fe,
653 int is_punctured)
654{
655 struct cx8802_dev *dev = fe->dvb->priv;
656 dev->ts_gen_cntrl = 0;
657
658 return 0;
659}
660
5bd1b663
ST
661static int cx24116_reset_device(struct dvb_frontend *fe)
662{
663 struct cx8802_dev *dev = fe->dvb->priv;
664 struct cx88_core *core = dev->core;
665
666 /* Reset the part */
363c35fc 667 /* Put the cx24116 into reset */
5bd1b663
ST
668 cx_write(MO_SRST_IO, 0);
669 msleep(10);
363c35fc 670 /* Take the cx24116 out of reset */
5bd1b663
ST
671 cx_write(MO_SRST_IO, 1);
672 msleep(10);
673
674 return 0;
675}
676
2e4e98e7 677static const struct cx24116_config hauppauge_hvr4000_config = {
5bd1b663
ST
678 .demod_address = 0x05,
679 .set_ts_params = cx24116_set_ts_param,
680 .reset_device = cx24116_reset_device,
681};
682
2e4e98e7 683static const struct cx24116_config tevii_s460_config = {
af832623
IL
684 .demod_address = 0x55,
685 .set_ts_params = cx24116_set_ts_param,
686 .reset_device = cx24116_reset_device,
687};
688
0cb73639
IL
689static int ds3000_set_ts_param(struct dvb_frontend *fe,
690 int is_punctured)
691{
692 struct cx8802_dev *dev = fe->dvb->priv;
693 dev->ts_gen_cntrl = 4;
694
695 return 0;
696}
697
698static struct ds3000_config tevii_ds3000_config = {
699 .demod_address = 0x68,
700 .set_ts_params = ds3000_set_ts_param,
701};
702
2e4e98e7 703static const struct stv0900_config prof_7301_stv0900_config = {
b699c271
IL
704 .demod_address = 0x6a,
705/* demod_mode = 0,*/
706 .xtal = 27000000,
707 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
708 .diseqc_mode = 2,/* 2/3 PWM */
709 .tun1_maddress = 0,/* 0x60 */
710 .tun1_adc = 0,/* 2 Vpp */
711 .path1_mode = 3,
712 .set_ts_params = stv0900_set_ts_param,
713};
714
2e4e98e7 715static const struct stb6100_config prof_7301_stb6100_config = {
b699c271
IL
716 .tuner_address = 0x60,
717 .refclock = 27000000,
718};
719
2e4e98e7 720static const struct stv0299_config tevii_tuner_sharp_config = {
e4aab64c 721 .demod_address = 0x68,
d4305c68 722 .inittab = sharp_z0194a_inittab,
e4aab64c
IL
723 .mclk = 88000000UL,
724 .invert = 1,
725 .skip_reinit = 0,
726 .lock_output = 1,
727 .volt13_op0_op1 = STV0299_VOLT13_OP1,
728 .min_delay_ms = 100,
d4305c68 729 .set_symbol_rate = sharp_z0194a_set_symbol_rate,
e4aab64c
IL
730 .set_ts_params = cx24116_set_ts_param,
731};
732
2e4e98e7 733static const struct stv0288_config tevii_tuner_earda_config = {
e4aab64c
IL
734 .demod_address = 0x68,
735 .min_delay_ms = 100,
736 .set_ts_params = cx24116_set_ts_param,
737};
738
6e0e12f1 739static int cx8802_alloc_frontends(struct cx8802_dev *dev)
1da177e4 740{
0590d91c 741 struct cx88_core *core = dev->core;
6e0e12f1 742 struct videobuf_dvb_frontend *fe = NULL;
e32fadc4 743 int i;
0590d91c 744
e32fadc4
MCC
745 mutex_init(&dev->frontends.lock);
746 INIT_LIST_HEAD(&dev->frontends.felist);
747
6e0e12f1
AW
748 if (!core->board.num_frontends)
749 return -ENODEV;
750
e32fadc4
MCC
751 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
752 core->board.num_frontends);
753 for (i = 1; i <= core->board.num_frontends; i++) {
6e0e12f1
AW
754 fe = videobuf_dvb_alloc_frontend(&dev->frontends, i);
755 if (!fe) {
e32fadc4
MCC
756 printk(KERN_ERR "%s() failed to alloc\n", __func__);
757 videobuf_dvb_dealloc_frontends(&dev->frontends);
6e0e12f1 758 return -ENOMEM;
e32fadc4
MCC
759 }
760 }
6e0e12f1
AW
761 return 0;
762}
763
4f3ca2f1
DH
764
765
2e4e98e7 766static const u8 samsung_smt_7020_inittab[] = {
4f3ca2f1
DH
767 0x01, 0x15,
768 0x02, 0x00,
769 0x03, 0x00,
770 0x04, 0x7D,
771 0x05, 0x0F,
772 0x06, 0x02,
773 0x07, 0x00,
774 0x08, 0x60,
775
776 0x0A, 0xC2,
777 0x0B, 0x00,
778 0x0C, 0x01,
779 0x0D, 0x81,
780 0x0E, 0x44,
781 0x0F, 0x09,
782 0x10, 0x3C,
783 0x11, 0x84,
784 0x12, 0xDA,
785 0x13, 0x99,
786 0x14, 0x8D,
787 0x15, 0xCE,
788 0x16, 0xE8,
789 0x17, 0x43,
790 0x18, 0x1C,
791 0x19, 0x1B,
792 0x1A, 0x1D,
793
794 0x1C, 0x12,
795 0x1D, 0x00,
796 0x1E, 0x00,
797 0x1F, 0x00,
798 0x20, 0x00,
799 0x21, 0x00,
800 0x22, 0x00,
801 0x23, 0x00,
802
803 0x28, 0x02,
804 0x29, 0x28,
805 0x2A, 0x14,
806 0x2B, 0x0F,
807 0x2C, 0x09,
808 0x2D, 0x05,
809
810 0x31, 0x1F,
811 0x32, 0x19,
812 0x33, 0xFC,
813 0x34, 0x13,
814 0xff, 0xff,
815};
816
817
14d24d14 818static int samsung_smt_7020_tuner_set_params(struct dvb_frontend *fe)
4f3ca2f1 819{
b738ae16 820 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
4f3ca2f1
DH
821 struct cx8802_dev *dev = fe->dvb->priv;
822 u8 buf[4];
823 u32 div;
824 struct i2c_msg msg = {
825 .addr = 0x61,
826 .flags = 0,
827 .buf = buf,
828 .len = sizeof(buf) };
829
b738ae16 830 div = c->frequency / 125;
4f3ca2f1
DH
831
832 buf[0] = (div >> 8) & 0x7f;
833 buf[1] = div & 0xff;
834 buf[2] = 0x84; /* 0xC4 */
835 buf[3] = 0x00;
836
b738ae16 837 if (c->frequency < 1500000)
4f3ca2f1
DH
838 buf[3] |= 0x10;
839
840 if (fe->ops.i2c_gate_ctrl)
841 fe->ops.i2c_gate_ctrl(fe, 1);
842
843 if (i2c_transfer(&dev->core->i2c_adap, &msg, 1) != 1)
844 return -EIO;
845
846 return 0;
847}
848
849static int samsung_smt_7020_set_tone(struct dvb_frontend *fe,
850 fe_sec_tone_mode_t tone)
851{
852 struct cx8802_dev *dev = fe->dvb->priv;
853 struct cx88_core *core = dev->core;
854
855 cx_set(MO_GP0_IO, 0x0800);
856
857 switch (tone) {
858 case SEC_TONE_ON:
859 cx_set(MO_GP0_IO, 0x08);
860 break;
861 case SEC_TONE_OFF:
862 cx_clear(MO_GP0_IO, 0x08);
863 break;
864 default:
865 return -EINVAL;
866 }
867
868 return 0;
869}
870
871static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe,
872 fe_sec_voltage_t voltage)
873{
874 struct cx8802_dev *dev = fe->dvb->priv;
875 struct cx88_core *core = dev->core;
876
877 u8 data;
878 struct i2c_msg msg = {
879 .addr = 8,
880 .flags = 0,
881 .buf = &data,
882 .len = sizeof(data) };
883
884 cx_set(MO_GP0_IO, 0x8000);
885
886 switch (voltage) {
887 case SEC_VOLTAGE_OFF:
888 break;
889 case SEC_VOLTAGE_13:
890 data = ISL6421_EN1 | ISL6421_LLC1;
891 cx_clear(MO_GP0_IO, 0x80);
892 break;
893 case SEC_VOLTAGE_18:
894 data = ISL6421_EN1 | ISL6421_LLC1 | ISL6421_VSEL1;
895 cx_clear(MO_GP0_IO, 0x80);
896 break;
897 default:
898 return -EINVAL;
899 };
900
901 return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
902}
903
904static int samsung_smt_7020_stv0299_set_symbol_rate(struct dvb_frontend *fe,
905 u32 srate, u32 ratio)
906{
907 u8 aclk = 0;
908 u8 bclk = 0;
909
910 if (srate < 1500000) {
911 aclk = 0xb7;
912 bclk = 0x47;
913 } else if (srate < 3000000) {
914 aclk = 0xb7;
915 bclk = 0x4b;
916 } else if (srate < 7000000) {
917 aclk = 0xb7;
918 bclk = 0x4f;
919 } else if (srate < 14000000) {
920 aclk = 0xb7;
921 bclk = 0x53;
922 } else if (srate < 30000000) {
923 aclk = 0xb6;
924 bclk = 0x53;
925 } else if (srate < 45000000) {
926 aclk = 0xb4;
927 bclk = 0x51;
928 }
929
930 stv0299_writereg(fe, 0x13, aclk);
931 stv0299_writereg(fe, 0x14, bclk);
932 stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
933 stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
934 stv0299_writereg(fe, 0x21, ratio & 0xf0);
935
936 return 0;
937}
938
939
2e4e98e7 940static const struct stv0299_config samsung_stv0299_config = {
4f3ca2f1
DH
941 .demod_address = 0x68,
942 .inittab = samsung_smt_7020_inittab,
943 .mclk = 88000000UL,
944 .invert = 0,
945 .skip_reinit = 0,
946 .lock_output = STV0299_LOCKOUTPUT_LK,
947 .volt13_op0_op1 = STV0299_VOLT13_OP1,
948 .min_delay_ms = 100,
949 .set_symbol_rate = samsung_smt_7020_stv0299_set_symbol_rate,
950};
951
6e0e12f1
AW
952static int dvb_register(struct cx8802_dev *dev)
953{
954 struct cx88_core *core = dev->core;
955 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
956 int mfe_shared = 0; /* bus not shared by default */
7b0962d3 957 int res = -EINVAL;
6e0e12f1
AW
958
959 if (0 != core->i2c_rc) {
960 printk(KERN_ERR "%s/2: no i2c-bus available, cannot attach dvb drivers\n", core->name);
961 goto frontend_detach;
962 }
e32fadc4 963
363c35fc
ST
964 /* Get the first frontend */
965 fe0 = videobuf_dvb_get_frontend(&dev->frontends, 1);
966 if (!fe0)
60a5a927 967 goto frontend_detach;
1da177e4 968
8e739090
DB
969 /* multi-frontend gate control is undefined or defaults to fe0 */
970 dev->frontends.gate = 0;
971
e32fadc4
MCC
972 /* Sets the gate control callback to be used by i2c command calls */
973 core->gate_ctrl = cx88_dvb_gate_ctrl;
974
8e739090 975 /* init frontend(s) */
0590d91c 976 switch (core->boardnr) {
1da177e4 977 case CX88_BOARD_HAUPPAUGE_DVB_T1:
363c35fc 978 fe0->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 979 &connexant_refboard_config,
0590d91c 980 &core->i2c_adap);
363c35fc
ST
981 if (fe0->dvb.frontend != NULL) {
982 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
983 0x61, &core->i2c_adap,
984 DVB_PLL_THOMSON_DTT759X))
985 goto frontend_detach;
f54376e2 986 }
1da177e4 987 break;
e057ee11 988 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
1da177e4 989 case CX88_BOARD_CONEXANT_DVB_T1:
f39624fd 990 case CX88_BOARD_KWORLD_DVB_T_CX22702:
2b5200a7 991 case CX88_BOARD_WINFAST_DTV1000:
363c35fc 992 fe0->dvb.frontend = dvb_attach(cx22702_attach,
f7b54b10 993 &connexant_refboard_config,
0590d91c 994 &core->i2c_adap);
363c35fc
ST
995 if (fe0->dvb.frontend != NULL) {
996 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
997 0x60, &core->i2c_adap,
998 DVB_PLL_THOMSON_DTT7579))
999 goto frontend_detach;
f54376e2 1000 }
1da177e4 1001 break;
4bd6e9d9 1002 case CX88_BOARD_WINFAST_DTV2000H:
611900c1
ST
1003 case CX88_BOARD_HAUPPAUGE_HVR1100:
1004 case CX88_BOARD_HAUPPAUGE_HVR1100LP:
a5a2ecfc 1005 case CX88_BOARD_HAUPPAUGE_HVR1300:
363c35fc 1006 fe0->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 1007 &hauppauge_hvr_config,
0590d91c 1008 &core->i2c_adap);
363c35fc
ST
1009 if (fe0->dvb.frontend != NULL) {
1010 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1011 &core->i2c_adap, 0x61,
1012 TUNER_PHILIPS_FMD1216ME_MK3))
1013 goto frontend_detach;
f54376e2 1014 }
611900c1 1015 break;
27b93d8a
MS
1016 case CX88_BOARD_WINFAST_DTV2000H_J:
1017 fe0->dvb.frontend = dvb_attach(cx22702_attach,
1018 &hauppauge_hvr_config,
1019 &core->i2c_adap);
1020 if (fe0->dvb.frontend != NULL) {
1021 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
1022 &core->i2c_adap, 0x61,
1023 TUNER_PHILIPS_FMD1216MEX_MK3))
1024 goto frontend_detach;
1025 }
1026 break;
363c35fc 1027 case CX88_BOARD_HAUPPAUGE_HVR3000:
60a5a927
DB
1028 /* MFE frontend 1 */
1029 mfe_shared = 1;
1030 dev->frontends.gate = 2;
363c35fc
ST
1031 /* DVB-S init */
1032 fe0->dvb.frontend = dvb_attach(cx24123_attach,
60a5a927
DB
1033 &hauppauge_novas_config,
1034 &dev->core->i2c_adap);
363c35fc 1035 if (fe0->dvb.frontend) {
60a5a927
DB
1036 if (!dvb_attach(isl6421_attach,
1037 fe0->dvb.frontend,
1038 &dev->core->i2c_adap,
1039 0x08, ISL6421_DCL, 0x00))
1040 goto frontend_detach;
363c35fc 1041 }
60a5a927 1042 /* MFE frontend 2 */
363c35fc 1043 fe1 = videobuf_dvb_get_frontend(&dev->frontends, 2);
60a5a927
DB
1044 if (!fe1)
1045 goto frontend_detach;
1046 /* DVB-T init */
1047 fe1->dvb.frontend = dvb_attach(cx22702_attach,
1048 &hauppauge_hvr_config,
1049 &dev->core->i2c_adap);
1050 if (fe1->dvb.frontend) {
1051 fe1->dvb.frontend->id = 1;
1052 if (!dvb_attach(simple_tuner_attach,
1053 fe1->dvb.frontend,
1054 &dev->core->i2c_adap,
1055 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
1056 goto frontend_detach;
363c35fc
ST
1057 }
1058 break;
780dfef3 1059 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
363c35fc 1060 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1061 &dvico_fusionhdtv,
0590d91c 1062 &core->i2c_adap);
363c35fc
ST
1063 if (fe0->dvb.frontend != NULL) {
1064 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
1065 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
1066 goto frontend_detach;
780dfef3 1067 break;
f54376e2 1068 }
780dfef3 1069 /* ZL10353 replaces MT352 on later cards */
363c35fc 1070 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1071 &dvico_fusionhdtv_plus_v1_1,
0590d91c 1072 &core->i2c_adap);
363c35fc
ST
1073 if (fe0->dvb.frontend != NULL) {
1074 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
1075 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
1076 goto frontend_detach;
f54376e2 1077 }
c2af3cd6
MK
1078 break;
1079 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
c2af3cd6
MK
1080 /* The tin box says DEE1601, but it seems to be DTT7579
1081 * compatible, with a slightly different MT352 AGC gain. */
363c35fc 1082 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1083 &dvico_fusionhdtv_dual,
0590d91c 1084 &core->i2c_adap);
363c35fc
ST
1085 if (fe0->dvb.frontend != NULL) {
1086 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
1087 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
1088 goto frontend_detach;
c2af3cd6
MK
1089 break;
1090 }
c2af3cd6 1091 /* ZL10353 replaces MT352 on later cards */
363c35fc 1092 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1093 &dvico_fusionhdtv_plus_v1_1,
0590d91c 1094 &core->i2c_adap);
363c35fc
ST
1095 if (fe0->dvb.frontend != NULL) {
1096 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
1097 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
1098 goto frontend_detach;
c2af3cd6 1099 }
1da177e4 1100 break;
780dfef3 1101 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
363c35fc 1102 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1103 &dvico_fusionhdtv,
0590d91c 1104 &core->i2c_adap);
363c35fc
ST
1105 if (fe0->dvb.frontend != NULL) {
1106 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
1107 0x61, NULL, DVB_PLL_LG_Z201))
1108 goto frontend_detach;
f54376e2 1109 }
1da177e4
LT
1110 break;
1111 case CX88_BOARD_KWORLD_DVB_T:
1112 case CX88_BOARD_DNTV_LIVE_DVB_T:
a82decf6 1113 case CX88_BOARD_ADSTECH_DVB_T_PCI:
363c35fc 1114 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1115 &dntv_live_dvbt_config,
0590d91c 1116 &core->i2c_adap);
363c35fc
ST
1117 if (fe0->dvb.frontend != NULL) {
1118 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC
1119 0x61, NULL, DVB_PLL_UNKNOWN_1))
1120 goto frontend_detach;
f54376e2 1121 }
1da177e4 1122 break;
fc40b261 1123 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
ecf854df 1124#if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
f0ad9097 1125 /* MT352 is on a secondary I2C bus made from some GPIO lines */
363c35fc 1126 fe0->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
f0ad9097 1127 &dev->vp3054->adap);
363c35fc
ST
1128 if (fe0->dvb.frontend != NULL) {
1129 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1130 &core->i2c_adap, 0x61,
1131 TUNER_PHILIPS_FMD1216ME_MK3))
1132 goto frontend_detach;
f54376e2 1133 }
fc40b261 1134#else
0590d91c
MCC
1135 printk(KERN_ERR "%s/2: built without vp3054 support\n",
1136 core->name);
fc40b261
CP
1137#endif
1138 break;
780dfef3 1139 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
363c35fc 1140 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1141 &dvico_fusionhdtv_hybrid,
0590d91c 1142 &core->i2c_adap);
363c35fc
ST
1143 if (fe0->dvb.frontend != NULL) {
1144 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1145 &core->i2c_adap, 0x61,
1146 TUNER_THOMSON_FE6600))
1147 goto frontend_detach;
f54376e2 1148 }
780dfef3 1149 break;
b3fb91d2 1150 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
363c35fc 1151 fe0->dvb.frontend = dvb_attach(zl10353_attach,
b3fb91d2 1152 &dvico_fusionhdtv_xc3028,
0590d91c 1153 &core->i2c_adap);
363c35fc
ST
1154 if (fe0->dvb.frontend == NULL)
1155 fe0->dvb.frontend = dvb_attach(mt352_attach,
b3fb91d2 1156 &dvico_fusionhdtv_mt352_xc3028,
0590d91c 1157 &core->i2c_adap);
8765561f
CP
1158 /*
1159 * On this board, the demod provides the I2C bus pullup.
1160 * We must not permit gate_ctrl to be performed, or
1161 * the xc3028 cannot communicate on the bus.
1162 */
363c35fc
ST
1163 if (fe0->dvb.frontend)
1164 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
23fb348d 1165 if (attach_xc3028(0x61, dev) < 0)
becd4305 1166 goto frontend_detach;
b3fb91d2 1167 break;
1da177e4 1168 case CX88_BOARD_PCHDTV_HD3000:
363c35fc 1169 fe0->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
0590d91c 1170 &core->i2c_adap);
363c35fc
ST
1171 if (fe0->dvb.frontend != NULL) {
1172 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1173 &core->i2c_adap, 0x61,
1174 TUNER_THOMSON_DTT761X))
1175 goto frontend_detach;
f54376e2 1176 }
1da177e4 1177 break;
f1798495
MK
1178 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
1179 dev->ts_gen_cntrl = 0x08;
f1798495 1180
0590d91c 1181 /* Do a hardware reset of chip before using it. */
f1798495
MK
1182 cx_clear(MO_GP0_IO, 1);
1183 mdelay(100);
0ccef6db 1184 cx_set(MO_GP0_IO, 1);
f1798495 1185 mdelay(200);
0ccef6db
MK
1186
1187 /* Select RF connector callback */
6ddcc919 1188 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
363c35fc 1189 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1190 &fusionhdtv_3_gold,
0590d91c 1191 &core->i2c_adap);
363c35fc
ST
1192 if (fe0->dvb.frontend != NULL) {
1193 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1194 &core->i2c_adap, 0x61,
1195 TUNER_MICROTUNE_4042FI5))
1196 goto frontend_detach;
f1798495
MK
1197 }
1198 break;
0d723c09
MK
1199 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
1200 dev->ts_gen_cntrl = 0x08;
0d723c09 1201
0590d91c 1202 /* Do a hardware reset of chip before using it. */
0d723c09
MK
1203 cx_clear(MO_GP0_IO, 1);
1204 mdelay(100);
d975872c 1205 cx_set(MO_GP0_IO, 9);
0d723c09 1206 mdelay(200);
363c35fc 1207 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1208 &fusionhdtv_3_gold,
0590d91c 1209 &core->i2c_adap);
363c35fc
ST
1210 if (fe0->dvb.frontend != NULL) {
1211 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1212 &core->i2c_adap, 0x61,
1213 TUNER_THOMSON_DTT761X))
1214 goto frontend_detach;
0d723c09
MK
1215 }
1216 break;
e52e98a7
MCC
1217 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
1218 dev->ts_gen_cntrl = 0x08;
e52e98a7 1219
0590d91c 1220 /* Do a hardware reset of chip before using it. */
e52e98a7
MCC
1221 cx_clear(MO_GP0_IO, 1);
1222 mdelay(100);
1223 cx_set(MO_GP0_IO, 1);
1224 mdelay(200);
363c35fc 1225 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1226 &fusionhdtv_5_gold,
0590d91c 1227 &core->i2c_adap);
363c35fc
ST
1228 if (fe0->dvb.frontend != NULL) {
1229 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1230 &core->i2c_adap, 0x61,
1231 TUNER_LG_TDVS_H06XF))
1232 goto frontend_detach;
363c35fc 1233 if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
0590d91c
MCC
1234 &core->i2c_adap, 0x43))
1235 goto frontend_detach;
e52e98a7
MCC
1236 }
1237 break;
da215d22
RS
1238 case CX88_BOARD_PCHDTV_HD5500:
1239 dev->ts_gen_cntrl = 0x08;
da215d22 1240
0590d91c 1241 /* Do a hardware reset of chip before using it. */
da215d22
RS
1242 cx_clear(MO_GP0_IO, 1);
1243 mdelay(100);
1244 cx_set(MO_GP0_IO, 1);
1245 mdelay(200);
363c35fc 1246 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1247 &pchdtv_hd5500,
0590d91c 1248 &core->i2c_adap);
363c35fc
ST
1249 if (fe0->dvb.frontend != NULL) {
1250 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1251 &core->i2c_adap, 0x61,
1252 TUNER_LG_TDVS_H06XF))
1253 goto frontend_detach;
363c35fc 1254 if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
0590d91c
MCC
1255 &core->i2c_adap, 0x43))
1256 goto frontend_detach;
da215d22
RS
1257 }
1258 break;
fde6d31e 1259 case CX88_BOARD_ATI_HDTVWONDER:
363c35fc 1260 fe0->dvb.frontend = dvb_attach(nxt200x_attach,
f7b54b10 1261 &ati_hdtvwonder,
0590d91c 1262 &core->i2c_adap);
363c35fc
ST
1263 if (fe0->dvb.frontend != NULL) {
1264 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC
1265 &core->i2c_adap, 0x61,
1266 TUNER_PHILIPS_TUV1236D))
1267 goto frontend_detach;
f54376e2 1268 }
0fa14aa6 1269 break;
0fa14aa6
ST
1270 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
1271 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
363c35fc 1272 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1273 &hauppauge_novas_config,
0590d91c 1274 &core->i2c_adap);
363c35fc
ST
1275 if (fe0->dvb.frontend) {
1276 if (!dvb_attach(isl6421_attach, fe0->dvb.frontend,
83fe92e7 1277 &core->i2c_adap, 0x08, ISL6421_DCL, 0x00))
0590d91c 1278 goto frontend_detach;
cd20ca9f 1279 }
0e0351e3
VC
1280 break;
1281 case CX88_BOARD_KWORLD_DVBS_100:
363c35fc 1282 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1283 &kworld_dvbs_100_config,
0590d91c 1284 &core->i2c_adap);
363c35fc
ST
1285 if (fe0->dvb.frontend) {
1286 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1287 fe0->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
cd20ca9f 1288 }
fde6d31e 1289 break;
c02a34f4 1290 case CX88_BOARD_GENIATECH_DVBS:
363c35fc 1291 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1292 &geniatech_dvbs_config,
0590d91c 1293 &core->i2c_adap);
363c35fc
ST
1294 if (fe0->dvb.frontend) {
1295 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1296 fe0->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
c02a34f4
SA
1297 }
1298 break;
60464da8 1299 case CX88_BOARD_PINNACLE_PCTV_HD_800i:
363c35fc 1300 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
60464da8 1301 &pinnacle_pctv_hd_800i_config,
0590d91c 1302 &core->i2c_adap);
363c35fc
ST
1303 if (fe0->dvb.frontend != NULL) {
1304 if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
0590d91c 1305 &core->i2c_adap,
30650961 1306 &pinnacle_pctv_hd_800i_tuner_config))
0590d91c 1307 goto frontend_detach;
60464da8
ST
1308 }
1309 break;
5c00fac0 1310 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
363c35fc 1311 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
5c00fac0 1312 &dvico_hdtv5_pci_nano_config,
0590d91c 1313 &core->i2c_adap);
363c35fc 1314 if (fe0->dvb.frontend != NULL) {
5c00fac0
ST
1315 struct dvb_frontend *fe;
1316 struct xc2028_config cfg = {
0590d91c 1317 .i2c_adap = &core->i2c_adap,
5c00fac0 1318 .i2c_addr = 0x61,
5c00fac0
ST
1319 };
1320 static struct xc2028_ctrl ctl = {
ef80bfeb 1321 .fname = XC2028_DEFAULT_FIRMWARE,
5c00fac0 1322 .max_len = 64,
33e53161 1323 .scode_table = XC3028_FE_OREN538,
5c00fac0
ST
1324 };
1325
1326 fe = dvb_attach(xc2028_attach,
363c35fc 1327 fe0->dvb.frontend, &cfg);
5c00fac0
ST
1328 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1329 fe->ops.tuner_ops.set_config(fe, &ctl);
1330 }
1331 break;
d49f7a24 1332 case CX88_BOARD_PINNACLE_HYBRID_PCTV:
3047a176 1333 case CX88_BOARD_WINFAST_DTV1800H:
363c35fc 1334 fe0->dvb.frontend = dvb_attach(zl10353_attach,
3f6014fc 1335 &cx88_pinnacle_hybrid_pctv,
0590d91c 1336 &core->i2c_adap);
363c35fc
ST
1337 if (fe0->dvb.frontend) {
1338 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
3f6014fc
SV
1339 if (attach_xc3028(0x61, dev) < 0)
1340 goto frontend_detach;
1341 }
9507901e 1342 break;
8eb79c0b 1343 case CX88_BOARD_WINFAST_DTV1800H_XC4000:
f271a3af 1344 case CX88_BOARD_WINFAST_DTV2000H_PLUS:
1345 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1346 &cx88_pinnacle_hybrid_pctv,
1347 &core->i2c_adap);
1348 if (fe0->dvb.frontend) {
1349 struct xc4000_config cfg = {
1350 .i2c_address = 0x61,
1351 .default_pm = 0,
1352 .dvb_amplitude = 134,
1353 .set_smoothedcvbs = 1,
1354 .if_khz = 4560
1355 };
1356 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
1357 if (attach_xc4000(dev, &cfg) < 0)
1358 goto frontend_detach;
1359 }
1360 break;
1361 case CX88_BOARD_GENIATECH_X8000_MT:
99e09eac 1362 dev->ts_gen_cntrl = 0x00;
9507901e 1363
363c35fc 1364 fe0->dvb.frontend = dvb_attach(zl10353_attach,
9507901e 1365 &cx88_geniatech_x8000_mt,
0590d91c 1366 &core->i2c_adap);
23fb348d 1367 if (attach_xc3028(0x61, dev) < 0)
0590d91c 1368 goto frontend_detach;
9507901e 1369 break;
99e09eac 1370 case CX88_BOARD_KWORLD_ATSC_120:
363c35fc 1371 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
99e09eac 1372 &kworld_atsc_120_config,
0590d91c 1373 &core->i2c_adap);
99e09eac 1374 if (attach_xc3028(0x61, dev) < 0)
0590d91c 1375 goto frontend_detach;
99e09eac 1376 break;
d893d5dc 1377 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
363c35fc 1378 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
d893d5dc 1379 &dvico_fusionhdtv7_config,
0590d91c 1380 &core->i2c_adap);
363c35fc
ST
1381 if (fe0->dvb.frontend != NULL) {
1382 if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
0590d91c 1383 &core->i2c_adap,
30650961 1384 &dvico_fusionhdtv7_tuner_config))
0590d91c 1385 goto frontend_detach;
d893d5dc
ST
1386 }
1387 break;
5bd1b663 1388 case CX88_BOARD_HAUPPAUGE_HVR4000:
60a5a927
DB
1389 /* MFE frontend 1 */
1390 mfe_shared = 1;
1391 dev->frontends.gate = 2;
363c35fc
ST
1392 /* DVB-S/S2 Init */
1393 fe0->dvb.frontend = dvb_attach(cx24116_attach,
60a5a927
DB
1394 &hauppauge_hvr4000_config,
1395 &dev->core->i2c_adap);
363c35fc 1396 if (fe0->dvb.frontend) {
60a5a927
DB
1397 if (!dvb_attach(isl6421_attach,
1398 fe0->dvb.frontend,
1399 &dev->core->i2c_adap,
1400 0x08, ISL6421_DCL, 0x00))
1401 goto frontend_detach;
363c35fc 1402 }
60a5a927 1403 /* MFE frontend 2 */
363c35fc 1404 fe1 = videobuf_dvb_get_frontend(&dev->frontends, 2);
60a5a927
DB
1405 if (!fe1)
1406 goto frontend_detach;
1407 /* DVB-T Init */
1408 fe1->dvb.frontend = dvb_attach(cx22702_attach,
1409 &hauppauge_hvr_config,
1410 &dev->core->i2c_adap);
1411 if (fe1->dvb.frontend) {
1412 fe1->dvb.frontend->id = 1;
1413 if (!dvb_attach(simple_tuner_attach,
1414 fe1->dvb.frontend,
1415 &dev->core->i2c_adap,
1416 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
1417 goto frontend_detach;
363c35fc
ST
1418 }
1419 break;
5bd1b663 1420 case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
363c35fc 1421 fe0->dvb.frontend = dvb_attach(cx24116_attach,
60a5a927
DB
1422 &hauppauge_hvr4000_config,
1423 &dev->core->i2c_adap);
363c35fc 1424 if (fe0->dvb.frontend) {
60a5a927
DB
1425 if (!dvb_attach(isl6421_attach,
1426 fe0->dvb.frontend,
1427 &dev->core->i2c_adap,
1428 0x08, ISL6421_DCL, 0x00))
1429 goto frontend_detach;
5bd1b663
ST
1430 }
1431 break;
cd3cde12 1432 case CX88_BOARD_PROF_6200:
4b29631d 1433 case CX88_BOARD_TBS_8910:
e4aab64c 1434 case CX88_BOARD_TEVII_S420:
363c35fc 1435 fe0->dvb.frontend = dvb_attach(stv0299_attach,
e4aab64c
IL
1436 &tevii_tuner_sharp_config,
1437 &core->i2c_adap);
363c35fc
ST
1438 if (fe0->dvb.frontend != NULL) {
1439 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60,
e4aab64c
IL
1440 &core->i2c_adap, DVB_PLL_OPERA1))
1441 goto frontend_detach;
363c35fc
ST
1442 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1443 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
e4aab64c
IL
1444
1445 } else {
363c35fc 1446 fe0->dvb.frontend = dvb_attach(stv0288_attach,
e4aab64c
IL
1447 &tevii_tuner_earda_config,
1448 &core->i2c_adap);
363c35fc
ST
1449 if (fe0->dvb.frontend != NULL) {
1450 if (!dvb_attach(stb6000_attach, fe0->dvb.frontend, 0x61,
e4aab64c
IL
1451 &core->i2c_adap))
1452 goto frontend_detach;
363c35fc
ST
1453 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1454 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
e4aab64c
IL
1455 }
1456 }
1457 break;
af832623 1458 case CX88_BOARD_TEVII_S460:
363c35fc 1459 fe0->dvb.frontend = dvb_attach(cx24116_attach,
af832623
IL
1460 &tevii_s460_config,
1461 &core->i2c_adap);
93f26c14 1462 if (fe0->dvb.frontend != NULL)
363c35fc 1463 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
4cd7fb87 1464 break;
0cb73639
IL
1465 case CX88_BOARD_TEVII_S464:
1466 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1467 &tevii_ds3000_config,
1468 &core->i2c_adap);
1469 if (fe0->dvb.frontend != NULL)
1470 fe0->dvb.frontend->ops.set_voltage =
1471 tevii_dvbs_set_voltage;
1472 break;
4cd7fb87 1473 case CX88_BOARD_OMICOM_SS4_PCI:
ee73042c 1474 case CX88_BOARD_TBS_8920:
57f51dbc 1475 case CX88_BOARD_PROF_7300:
4b29631d 1476 case CX88_BOARD_SATTRADE_ST4200:
363c35fc 1477 fe0->dvb.frontend = dvb_attach(cx24116_attach,
ee73042c
OR
1478 &hauppauge_hvr4000_config,
1479 &core->i2c_adap);
93f26c14 1480 if (fe0->dvb.frontend != NULL)
363c35fc 1481 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
af832623 1482 break;
70101a27
SW
1483 case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII:
1484 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1485 &cx88_terratec_cinergy_ht_pci_mkii_config,
1486 &core->i2c_adap);
1487 if (fe0->dvb.frontend) {
1488 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
1489 if (attach_xc3028(0x61, dev) < 0)
1490 goto frontend_detach;
1491 }
1492 break;
b699c271
IL
1493 case CX88_BOARD_PROF_7301:{
1494 struct dvb_tuner_ops *tuner_ops = NULL;
1495
1496 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1497 &prof_7301_stv0900_config,
1498 &core->i2c_adap, 0);
1499 if (fe0->dvb.frontend != NULL) {
1500 if (!dvb_attach(stb6100_attach, fe0->dvb.frontend,
1501 &prof_7301_stb6100_config,
1502 &core->i2c_adap))
1503 goto frontend_detach;
1504
1505 tuner_ops = &fe0->dvb.frontend->ops.tuner_ops;
1506 tuner_ops->set_frequency = stb6100_set_freq;
1507 tuner_ops->get_frequency = stb6100_get_freq;
1508 tuner_ops->set_bandwidth = stb6100_set_bandw;
1509 tuner_ops->get_bandwidth = stb6100_get_bandw;
1510
1511 core->prev_set_voltage =
1512 fe0->dvb.frontend->ops.set_voltage;
1513 fe0->dvb.frontend->ops.set_voltage =
1514 tevii_dvbs_set_voltage;
1515 }
1516 break;
1517 }
4f3ca2f1
DH
1518 case CX88_BOARD_SAMSUNG_SMT_7020:
1519 dev->ts_gen_cntrl = 0x08;
1520
4f3ca2f1
DH
1521 cx_set(MO_GP0_IO, 0x0101);
1522
1523 cx_clear(MO_GP0_IO, 0x01);
1524 mdelay(100);
1525 cx_set(MO_GP0_IO, 0x01);
1526 mdelay(200);
1527
1528 fe0->dvb.frontend = dvb_attach(stv0299_attach,
1529 &samsung_stv0299_config,
1530 &dev->core->i2c_adap);
1531 if (fe0->dvb.frontend) {
1532 fe0->dvb.frontend->ops.tuner_ops.set_params =
1533 samsung_smt_7020_tuner_set_params;
1534 fe0->dvb.frontend->tuner_priv =
1535 &dev->core->i2c_adap;
1536 fe0->dvb.frontend->ops.set_voltage =
1537 samsung_smt_7020_set_voltage;
1538 fe0->dvb.frontend->ops.set_tone =
1539 samsung_smt_7020_set_tone;
1540 }
1541
1542 break;
111ac84a
SI
1543 case CX88_BOARD_TWINHAN_VP1027_DVBS:
1544 dev->ts_gen_cntrl = 0x00;
1545 fe0->dvb.frontend = dvb_attach(mb86a16_attach,
1546 &twinhan_vp1027,
1547 &core->i2c_adap);
1548 if (fe0->dvb.frontend) {
1549 core->prev_set_voltage =
1550 fe0->dvb.frontend->ops.set_voltage;
1551 fe0->dvb.frontend->ops.set_voltage =
1552 vp1027_set_voltage;
1553 }
1554 break;
4f3ca2f1 1555
1da177e4 1556 default:
5772f813 1557 printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
0590d91c 1558 core->name);
1da177e4
LT
1559 break;
1560 }
363c35fc 1561
2c9bcea1 1562 if ( (NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend) ) {
9507901e
MCC
1563 printk(KERN_ERR
1564 "%s/2: frontend initialization failed\n",
0590d91c 1565 core->name);
60a5a927 1566 goto frontend_detach;
9507901e 1567 }
d7cba043 1568 /* define general-purpose callback pointer */
363c35fc 1569 fe0->dvb.frontend->callback = cx88_tuner_callback;
9507901e 1570
6c5be74c 1571 /* Ensure all frontends negotiate bus access */
363c35fc
ST
1572 fe0->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
1573 if (fe1)
1574 fe1->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
1da177e4 1575
93352f5c 1576 /* Put the analog decoder in standby to keep it quiet */
622b828a 1577 call_all(core, core, s_power, 0);
93352f5c 1578
1da177e4 1579 /* register everything */
7b0962d3
DF
1580 res = videobuf_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
1581 &dev->pci->dev, adapter_nr, mfe_shared, NULL);
1582 if (res)
1583 goto frontend_detach;
1584 return res;
0590d91c
MCC
1585
1586frontend_detach:
e32fadc4 1587 core->gate_ctrl = NULL;
becd4305 1588 videobuf_dvb_dealloc_frontends(&dev->frontends);
7b0962d3 1589 return res;
1da177e4
LT
1590}
1591
1592/* ----------------------------------------------------------- */
1593
6c5be74c
ST
1594/* CX8802 MPEG -> mini driver - We have been given the hardware */
1595static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
1da177e4 1596{
6c5be74c
ST
1597 struct cx88_core *core = drv->core;
1598 int err = 0;
32d83efc 1599 dprintk( 1, "%s\n", __func__);
6c5be74c 1600
6a59d64c 1601 switch (core->boardnr) {
6c5be74c
ST
1602 case CX88_BOARD_HAUPPAUGE_HVR1300:
1603 /* We arrive here with either the cx23416 or the cx22702
1604 * on the bus. Take the bus from the cx23416 and enable the
1605 * cx22702 demod
1606 */
79392737
DB
1607 /* Toggle reset on cx22702 leaving i2c active */
1608 cx_set(MO_GP0_IO, 0x00000080);
1609 udelay(1000);
1610 cx_clear(MO_GP0_IO, 0x00000080);
1611 udelay(50);
1612 cx_set(MO_GP0_IO, 0x00000080);
1613 udelay(1000);
1614 /* enable the cx22702 pins */
6c5be74c
ST
1615 cx_clear(MO_GP0_IO, 0x00000004);
1616 udelay(1000);
1617 break;
363c35fc 1618
92abe9ee 1619 case CX88_BOARD_HAUPPAUGE_HVR3000:
363c35fc 1620 case CX88_BOARD_HAUPPAUGE_HVR4000:
79392737
DB
1621 /* Toggle reset on cx22702 leaving i2c active */
1622 cx_set(MO_GP0_IO, 0x00000080);
1623 udelay(1000);
1624 cx_clear(MO_GP0_IO, 0x00000080);
1625 udelay(50);
1626 cx_set(MO_GP0_IO, 0x00000080);
1627 udelay(1000);
1628 switch (core->dvbdev->frontends.active_fe_id) {
1629 case 1: /* DVB-S/S2 Enabled */
1630 /* tri-state the cx22702 pins */
1631 cx_set(MO_GP0_IO, 0x00000004);
1632 /* Take the cx24116/cx24123 out of reset */
1633 cx_write(MO_SRST_IO, 1);
363c35fc 1634 core->dvbdev->ts_gen_cntrl = 0x02; /* Parallel IO */
79392737
DB
1635 break;
1636 case 2: /* DVB-T Enabled */
363c35fc
ST
1637 /* Put the cx24116/cx24123 into reset */
1638 cx_write(MO_SRST_IO, 0);
79392737 1639 /* enable the cx22702 pins */
363c35fc
ST
1640 cx_clear(MO_GP0_IO, 0x00000004);
1641 core->dvbdev->ts_gen_cntrl = 0x0c; /* Serial IO */
79392737 1642 break;
363c35fc 1643 }
79392737 1644 udelay(1000);
363c35fc
ST
1645 break;
1646
f271a3af 1647 case CX88_BOARD_WINFAST_DTV2000H_PLUS:
1648 /* set RF input to AIR for DVB-T (GPIO 16) */
1649 cx_write(MO_GP2_IO, 0x0101);
1650 break;
1651
6c5be74c
ST
1652 default:
1653 err = -ENODEV;
1654 }
1655 return err;
1656}
1657
1658/* CX8802 MPEG -> mini driver - We no longer have the hardware */
1659static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
1660{
1661 struct cx88_core *core = drv->core;
1662 int err = 0;
32d83efc 1663 dprintk( 1, "%s\n", __func__);
6c5be74c 1664
6a59d64c 1665 switch (core->boardnr) {
6c5be74c
ST
1666 case CX88_BOARD_HAUPPAUGE_HVR1300:
1667 /* Do Nothing, leave the cx22702 on the bus. */
1668 break;
363c35fc
ST
1669 case CX88_BOARD_HAUPPAUGE_HVR3000:
1670 case CX88_BOARD_HAUPPAUGE_HVR4000:
1671 break;
6c5be74c
ST
1672 default:
1673 err = -ENODEV;
1674 }
1675 return err;
1676}
1677
1678static int cx8802_dvb_probe(struct cx8802_driver *drv)
1679{
1680 struct cx88_core *core = drv->core;
1681 struct cx8802_dev *dev = drv->core->dvbdev;
cbd82441 1682 int err;
6e0e12f1
AW
1683 struct videobuf_dvb_frontend *fe;
1684 int i;
1da177e4 1685
32d83efc 1686 dprintk( 1, "%s\n", __func__);
6c5be74c 1687 dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
6a59d64c 1688 core->boardnr,
6c5be74c
ST
1689 core->name,
1690 core->pci_bus,
1691 core->pci_slot);
1da177e4
LT
1692
1693 err = -ENODEV;
6a59d64c 1694 if (!(core->board.mpeg & CX88_MPEG_DVB))
1da177e4
LT
1695 goto fail_core;
1696
ecf854df 1697 /* If vp3054 isn't enabled, a stub will just return 0 */
fc40b261
CP
1698 err = vp3054_i2c_probe(dev);
1699 if (0 != err)
6e0e12f1 1700 goto fail_core;
fc40b261 1701
1da177e4 1702 /* dvb stuff */
5772f813 1703 printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
363c35fc
ST
1704 dev->ts_gen_cntrl = 0x0c;
1705
6e0e12f1
AW
1706 err = cx8802_alloc_frontends(dev);
1707 if (err)
1708 goto fail_core;
1709
cbd82441 1710 err = -ENODEV;
6e0e12f1
AW
1711 for (i = 1; i <= core->board.num_frontends; i++) {
1712 fe = videobuf_dvb_get_frontend(&core->dvbdev->frontends, i);
1713 if (fe == NULL) {
1714 printk(KERN_ERR "%s() failed to get frontend(%d)\n",
cbd82441 1715 __func__, i);
6e0e12f1
AW
1716 goto fail_probe;
1717 }
1718 videobuf_queue_sg_init(&fe->dvb.dvbq, &dvb_qops,
cbd82441
DB
1719 &dev->pci->dev, &dev->slock,
1720 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1721 V4L2_FIELD_TOP,
1722 sizeof(struct cx88_buffer),
08bff03e 1723 dev, NULL);
6e0e12f1
AW
1724 /* init struct videobuf_dvb */
1725 fe->dvb.name = dev->core->name;
363c35fc 1726 }
6e0e12f1 1727
1da177e4 1728 err = dvb_register(dev);
cbd82441
DB
1729 if (err)
1730 /* frontends/adapter de-allocated in dvb_register */
5772f813
TP
1731 printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
1732 core->name, err);
cbd82441
DB
1733 return err;
1734fail_probe:
1735 videobuf_dvb_dealloc_frontends(&core->dvbdev->frontends);
92abe9ee 1736fail_core:
1da177e4
LT
1737 return err;
1738}
1739
6c5be74c 1740static int cx8802_dvb_remove(struct cx8802_driver *drv)
1da177e4 1741{
0fcd488d 1742 struct cx88_core *core = drv->core;
6c5be74c 1743 struct cx8802_dev *dev = drv->core->dvbdev;
611900c1 1744
0fcd488d
DB
1745 dprintk( 1, "%s\n", __func__);
1746
363c35fc 1747 videobuf_dvb_unregister_bus(&dev->frontends);
1da177e4 1748
fc40b261 1749 vp3054_i2c_remove(dev);
fc40b261 1750
e32fadc4
MCC
1751 core->gate_ctrl = NULL;
1752
6c5be74c 1753 return 0;
1da177e4
LT
1754}
1755
6c5be74c
ST
1756static struct cx8802_driver cx8802_dvb_driver = {
1757 .type_id = CX88_MPEG_DVB,
1758 .hw_access = CX8802_DRVCTL_SHARED,
1759 .probe = cx8802_dvb_probe,
1760 .remove = cx8802_dvb_remove,
1761 .advise_acquire = cx8802_dvb_advise_acquire,
1762 .advise_release = cx8802_dvb_advise_release,
1da177e4
LT
1763};
1764
31d0f845 1765static int __init dvb_init(void)
1da177e4 1766{
1990d50b
MCC
1767 printk(KERN_INFO "cx88/2: cx2388x dvb driver version %s loaded\n",
1768 CX88_VERSION);
6c5be74c 1769 return cx8802_register_driver(&cx8802_dvb_driver);
1da177e4
LT
1770}
1771
31d0f845 1772static void __exit dvb_fini(void)
1da177e4 1773{
6c5be74c 1774 cx8802_unregister_driver(&cx8802_dvb_driver);
1da177e4
LT
1775}
1776
1777module_init(dvb_init);
1778module_exit(dvb_fini);
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