Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
b45009b0 | 2 | * $Id: cx88-mpeg.c,v 1.26 2005/06/03 13:31:51 mchehab Exp $ |
1da177e4 LT |
3 | * |
4 | * Support for the mpeg transport stream transfers | |
5 | * PCI function #2 of the cx2388x. | |
6 | * | |
7 | * (c) 2004 Jelle Foks <jelle@foks.8m.com> | |
8 | * (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au> | |
9 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/moduleparam.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/device.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <asm/delay.h> | |
32 | ||
33 | #include "cx88.h" | |
34 | ||
35 | /* ------------------------------------------------------------------ */ | |
36 | ||
37 | MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards"); | |
38 | MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>"); | |
39 | MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>"); | |
40 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); | |
41 | MODULE_LICENSE("GPL"); | |
42 | ||
43 | static unsigned int debug = 0; | |
44 | module_param(debug,int,0644); | |
45 | MODULE_PARM_DESC(debug,"enable debug messages [mpeg]"); | |
46 | ||
47 | #define dprintk(level,fmt, arg...) if (debug >= level) \ | |
48 | printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg) | |
49 | ||
50 | /* ------------------------------------------------------------------ */ | |
51 | ||
52 | static int cx8802_start_dma(struct cx8802_dev *dev, | |
53 | struct cx88_dmaqueue *q, | |
54 | struct cx88_buffer *buf) | |
55 | { | |
56 | struct cx88_core *core = dev->core; | |
57 | ||
b45009b0 | 58 | dprintk(0, "cx8802_start_dma %d\n", buf->vb.width); |
1da177e4 LT |
59 | |
60 | /* setup fifo + format */ | |
61 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], | |
62 | dev->ts_packet_size, buf->risc.dma); | |
63 | ||
64 | /* write TS length to chip */ | |
65 | cx_write(MO_TS_LNGTH, buf->vb.width); | |
66 | ||
67 | #if 1 | |
68 | /* FIXME: this needs a review. | |
69 | * also: move to cx88-blackbird + cx88-dvb source files? */ | |
70 | ||
71 | if (cx88_boards[core->board].dvb) { | |
72 | /* negedge driven & software reset */ | |
73 | cx_write(TS_GEN_CNTRL, 0x40); | |
74 | udelay(100); | |
75 | cx_write(MO_PINMUX_IO, 0x00); | |
76 | cx_write(TS_HW_SOP_CNTRL,47<<16|188<<4|0x00); | |
77 | cx_write(TS_SOP_STAT,0x00); | |
78 | cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl); | |
79 | udelay(100); | |
80 | } | |
81 | ||
82 | if (cx88_boards[core->board].blackbird) { | |
83 | cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */ | |
84 | ||
85 | // cx_write(TS_F2_CMD_STAT_MM, 0x2900106); /* F2_CMD_STAT_MM defaults + master + memory space */ | |
86 | cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */ | |
87 | udelay(100); | |
88 | ||
89 | cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */ | |
90 | //cx_write(TS_HW_SOP_CNTRL, 0x2F0BC0); /* mpeg start byte ts: 0x2F0BC0 ? */ | |
91 | cx_write(TS_VALERR_CNTRL, 0x2000); | |
92 | ||
93 | cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */ | |
94 | udelay(100); | |
95 | } | |
96 | #endif | |
97 | ||
98 | /* reset counter */ | |
99 | cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET); | |
100 | q->count = 1; | |
101 | ||
102 | /* enable irqs */ | |
b45009b0 | 103 | dprintk( 0, "setting the interrupt mask\n" ); |
1da177e4 | 104 | cx_set(MO_PCI_INTMSK, core->pci_irqmask | 0x04); |
b45009b0 MCC |
105 | cx_set(MO_TS_INTMSK, 0x1f0011); |
106 | //cx_write(MO_TS_INTMSK, 0x0f0011); | |
1da177e4 LT |
107 | |
108 | /* start dma */ | |
b45009b0 MCC |
109 | cx_set(MO_DEV_CNTRL2, (1<<5)); |
110 | cx_set(MO_TS_DMACNTRL, 0x11); | |
1da177e4 LT |
111 | return 0; |
112 | } | |
113 | ||
114 | static int cx8802_stop_dma(struct cx8802_dev *dev) | |
115 | { | |
116 | struct cx88_core *core = dev->core; | |
b45009b0 | 117 | dprintk( 0, "cx8802_stop_dma\n" ); |
1da177e4 LT |
118 | |
119 | /* stop dma */ | |
120 | cx_clear(MO_TS_DMACNTRL, 0x11); | |
121 | ||
122 | /* disable irqs */ | |
123 | cx_clear(MO_PCI_INTMSK, 0x000004); | |
124 | cx_clear(MO_TS_INTMSK, 0x1f0011); | |
125 | ||
126 | /* Reset the controller */ | |
127 | cx_write(TS_GEN_CNTRL, 0xcd); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static int cx8802_restart_queue(struct cx8802_dev *dev, | |
132 | struct cx88_dmaqueue *q) | |
133 | { | |
134 | struct cx88_buffer *buf; | |
135 | struct list_head *item; | |
136 | ||
b45009b0 | 137 | dprintk( 0, "cx8802_restart_queue\n" ); |
1da177e4 | 138 | if (list_empty(&q->active)) |
b45009b0 MCC |
139 | { |
140 | dprintk( 0, "cx8802_restart_queue: queue is empty\n" ); | |
1da177e4 | 141 | return 0; |
b45009b0 | 142 | } |
1da177e4 LT |
143 | |
144 | buf = list_entry(q->active.next, struct cx88_buffer, vb.queue); | |
145 | dprintk(2,"restart_queue [%p/%d]: restart dma\n", | |
146 | buf, buf->vb.i); | |
147 | cx8802_start_dma(dev, q, buf); | |
148 | list_for_each(item,&q->active) { | |
149 | buf = list_entry(item, struct cx88_buffer, vb.queue); | |
150 | buf->count = q->count++; | |
151 | } | |
152 | mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); | |
153 | return 0; | |
154 | } | |
155 | ||
156 | /* ------------------------------------------------------------------ */ | |
157 | ||
158 | int cx8802_buf_prepare(struct cx8802_dev *dev, struct cx88_buffer *buf) | |
159 | { | |
160 | int size = dev->ts_packet_size * dev->ts_packet_count; | |
161 | int rc; | |
162 | ||
163 | dprintk(1, "%s: %p\n", __FUNCTION__, buf); | |
164 | if (0 != buf->vb.baddr && buf->vb.bsize < size) | |
165 | return -EINVAL; | |
166 | ||
167 | if (STATE_NEEDS_INIT == buf->vb.state) { | |
168 | buf->vb.width = dev->ts_packet_size; | |
169 | buf->vb.height = dev->ts_packet_count; | |
170 | buf->vb.size = size; | |
171 | buf->vb.field = V4L2_FIELD_TOP; | |
172 | ||
173 | if (0 != (rc = videobuf_iolock(dev->pci,&buf->vb,NULL))) | |
174 | goto fail; | |
175 | cx88_risc_databuffer(dev->pci, &buf->risc, | |
176 | buf->vb.dma.sglist, | |
177 | buf->vb.width, buf->vb.height); | |
178 | } | |
179 | buf->vb.state = STATE_PREPARED; | |
180 | return 0; | |
181 | ||
182 | fail: | |
183 | cx88_free_buffer(dev->pci,buf); | |
184 | return rc; | |
185 | } | |
186 | ||
187 | void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf) | |
188 | { | |
189 | struct cx88_buffer *prev; | |
190 | struct cx88_dmaqueue *q = &dev->mpegq; | |
191 | ||
b45009b0 | 192 | dprintk( 1, "cx8802_buf_queue\n" ); |
1da177e4 LT |
193 | /* add jump to stopper */ |
194 | buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); | |
195 | buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma); | |
196 | ||
197 | if (list_empty(&q->active)) { | |
b45009b0 | 198 | dprintk( 0, "queue is empty - first active\n" ); |
1da177e4 LT |
199 | list_add_tail(&buf->vb.queue,&q->active); |
200 | cx8802_start_dma(dev, q, buf); | |
201 | buf->vb.state = STATE_ACTIVE; | |
202 | buf->count = q->count++; | |
203 | mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); | |
b45009b0 | 204 | dprintk(0,"[%p/%d] %s - first active\n", |
1da177e4 | 205 | buf, buf->vb.i, __FUNCTION__); |
b45009b0 | 206 | //udelay(100); |
1da177e4 LT |
207 | |
208 | } else { | |
b45009b0 | 209 | dprintk( 1, "queue is not empty - append to active\n" ); |
1da177e4 LT |
210 | prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue); |
211 | list_add_tail(&buf->vb.queue,&q->active); | |
212 | buf->vb.state = STATE_ACTIVE; | |
213 | buf->count = q->count++; | |
214 | prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); | |
b45009b0 | 215 | dprintk( 1, "[%p/%d] %s - append to active\n", |
1da177e4 | 216 | buf, buf->vb.i, __FUNCTION__); |
b45009b0 | 217 | //udelay(100); |
1da177e4 LT |
218 | } |
219 | } | |
220 | ||
221 | /* ----------------------------------------------------------- */ | |
222 | ||
223 | static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart) | |
224 | { | |
225 | struct cx88_dmaqueue *q = &dev->mpegq; | |
226 | struct cx88_buffer *buf; | |
227 | unsigned long flags; | |
228 | ||
229 | spin_lock_irqsave(&dev->slock,flags); | |
230 | while (!list_empty(&q->active)) { | |
231 | buf = list_entry(q->active.next, struct cx88_buffer, vb.queue); | |
232 | list_del(&buf->vb.queue); | |
233 | buf->vb.state = STATE_ERROR; | |
234 | wake_up(&buf->vb.done); | |
235 | dprintk(1,"[%p/%d] %s - dma=0x%08lx\n", | |
236 | buf, buf->vb.i, reason, (unsigned long)buf->risc.dma); | |
237 | } | |
238 | if (restart) | |
b45009b0 MCC |
239 | { |
240 | dprintk(0, "restarting queue\n" ); | |
1da177e4 | 241 | cx8802_restart_queue(dev,q); |
b45009b0 | 242 | } |
1da177e4 LT |
243 | spin_unlock_irqrestore(&dev->slock,flags); |
244 | } | |
245 | ||
246 | void cx8802_cancel_buffers(struct cx8802_dev *dev) | |
247 | { | |
248 | struct cx88_dmaqueue *q = &dev->mpegq; | |
249 | ||
b45009b0 | 250 | dprintk( 1, "cx8802_cancel_buffers" ); |
1da177e4 LT |
251 | del_timer_sync(&q->timeout); |
252 | cx8802_stop_dma(dev); | |
253 | do_cancel_buffers(dev,"cancel",0); | |
254 | } | |
255 | ||
256 | static void cx8802_timeout(unsigned long data) | |
257 | { | |
258 | struct cx8802_dev *dev = (struct cx8802_dev*)data; | |
259 | ||
b45009b0 | 260 | dprintk(0, "%s\n",__FUNCTION__); |
1da177e4 LT |
261 | |
262 | if (debug) | |
263 | cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]); | |
264 | cx8802_stop_dma(dev); | |
265 | do_cancel_buffers(dev,"timeout",1); | |
266 | } | |
267 | ||
268 | static void cx8802_mpeg_irq(struct cx8802_dev *dev) | |
269 | { | |
270 | struct cx88_core *core = dev->core; | |
271 | u32 status, mask, count; | |
272 | ||
b45009b0 | 273 | dprintk( 1, "cx8802_mpeg_irq\n" ); |
1da177e4 LT |
274 | status = cx_read(MO_TS_INTSTAT); |
275 | mask = cx_read(MO_TS_INTMSK); | |
276 | if (0 == (status & mask)) | |
277 | return; | |
278 | ||
279 | cx_write(MO_TS_INTSTAT, status); | |
b45009b0 MCC |
280 | #if 0 |
281 | cx88_print_irqbits(core->name, "irq mpeg ", | |
282 | cx88_mpeg_irqs, status, mask); | |
283 | #endif | |
1da177e4 LT |
284 | if (debug || (status & mask & ~0xff)) |
285 | cx88_print_irqbits(core->name, "irq mpeg ", | |
286 | cx88_mpeg_irqs, status, mask); | |
287 | ||
288 | /* risc op code error */ | |
289 | if (status & (1 << 16)) { | |
290 | printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name); | |
291 | cx_clear(MO_TS_DMACNTRL, 0x11); | |
292 | cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]); | |
293 | } | |
294 | ||
295 | /* risc1 y */ | |
296 | if (status & 0x01) { | |
b45009b0 | 297 | dprintk( 1, "wake up\n" ); |
1da177e4 LT |
298 | spin_lock(&dev->slock); |
299 | count = cx_read(MO_TS_GPCNT); | |
300 | cx88_wakeup(dev->core, &dev->mpegq, count); | |
301 | spin_unlock(&dev->slock); | |
302 | } | |
303 | ||
304 | /* risc2 y */ | |
305 | if (status & 0x10) { | |
306 | spin_lock(&dev->slock); | |
307 | cx8802_restart_queue(dev,&dev->mpegq); | |
308 | spin_unlock(&dev->slock); | |
309 | } | |
310 | ||
311 | /* other general errors */ | |
312 | if (status & 0x1f0100) { | |
b45009b0 | 313 | dprintk( 0, "general errors: 0x%08x\n", status & 0x1f0100 ); |
1da177e4 LT |
314 | spin_lock(&dev->slock); |
315 | cx8802_stop_dma(dev); | |
316 | cx8802_restart_queue(dev,&dev->mpegq); | |
317 | spin_unlock(&dev->slock); | |
318 | } | |
319 | } | |
320 | ||
b45009b0 MCC |
321 | #define MAX_IRQ_LOOP 10 |
322 | ||
1da177e4 LT |
323 | static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs) |
324 | { | |
325 | struct cx8802_dev *dev = dev_id; | |
326 | struct cx88_core *core = dev->core; | |
327 | u32 status; | |
328 | int loop, handled = 0; | |
329 | ||
b45009b0 | 330 | for (loop = 0; loop < MAX_IRQ_LOOP; loop++) { |
1da177e4 LT |
331 | status = cx_read(MO_PCI_INTSTAT) & (core->pci_irqmask | 0x04); |
332 | if (0 == status) | |
333 | goto out; | |
b45009b0 MCC |
334 | dprintk( 1, "cx8802_irq\n" ); |
335 | dprintk( 1, " loop: %d/%d\n", loop, MAX_IRQ_LOOP ); | |
336 | dprintk( 1, " status: %d\n", status ); | |
1da177e4 LT |
337 | handled = 1; |
338 | cx_write(MO_PCI_INTSTAT, status); | |
339 | ||
340 | if (status & core->pci_irqmask) | |
341 | cx88_core_irq(core,status); | |
342 | if (status & 0x04) | |
343 | cx8802_mpeg_irq(dev); | |
344 | }; | |
b45009b0 MCC |
345 | if (MAX_IRQ_LOOP == loop) { |
346 | dprintk( 0, "clearing mask\n" ); | |
1da177e4 LT |
347 | printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n", |
348 | core->name); | |
349 | cx_write(MO_PCI_INTMSK,0); | |
350 | } | |
351 | ||
352 | out: | |
353 | return IRQ_RETVAL(handled); | |
354 | } | |
355 | ||
356 | /* ----------------------------------------------------------- */ | |
357 | /* exported stuff */ | |
358 | ||
359 | int cx8802_init_common(struct cx8802_dev *dev) | |
360 | { | |
361 | struct cx88_core *core = dev->core; | |
362 | int err; | |
363 | ||
364 | /* pci init */ | |
365 | if (pci_enable_device(dev->pci)) | |
366 | return -EIO; | |
367 | pci_set_master(dev->pci); | |
368 | if (!pci_dma_supported(dev->pci,0xffffffff)) { | |
369 | printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name); | |
370 | return -EIO; | |
371 | } | |
372 | ||
373 | pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev); | |
374 | pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat); | |
375 | printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, " | |
376 | "latency: %d, mmio: 0x%lx\n", dev->core->name, | |
377 | pci_name(dev->pci), dev->pci_rev, dev->pci->irq, | |
378 | dev->pci_lat,pci_resource_start(dev->pci,0)); | |
379 | ||
380 | /* initialize driver struct */ | |
381 | init_MUTEX(&dev->lock); | |
382 | spin_lock_init(&dev->slock); | |
383 | ||
384 | /* init dma queue */ | |
385 | INIT_LIST_HEAD(&dev->mpegq.active); | |
386 | INIT_LIST_HEAD(&dev->mpegq.queued); | |
387 | dev->mpegq.timeout.function = cx8802_timeout; | |
388 | dev->mpegq.timeout.data = (unsigned long)dev; | |
389 | init_timer(&dev->mpegq.timeout); | |
390 | cx88_risc_stopper(dev->pci,&dev->mpegq.stopper, | |
391 | MO_TS_DMACNTRL,0x11,0x00); | |
392 | ||
393 | /* get irq */ | |
394 | err = request_irq(dev->pci->irq, cx8802_irq, | |
395 | SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev); | |
396 | if (err < 0) { | |
397 | printk(KERN_ERR "%s: can't get IRQ %d\n", | |
398 | dev->core->name, dev->pci->irq); | |
399 | return err; | |
400 | } | |
401 | cx_set(MO_PCI_INTMSK, core->pci_irqmask); | |
402 | ||
403 | /* everything worked */ | |
404 | pci_set_drvdata(dev->pci,dev); | |
405 | return 0; | |
406 | } | |
407 | ||
408 | void cx8802_fini_common(struct cx8802_dev *dev) | |
409 | { | |
b45009b0 | 410 | dprintk( 2, "cx8802_fini_common\n" ); |
1da177e4 LT |
411 | cx8802_stop_dma(dev); |
412 | pci_disable_device(dev->pci); | |
413 | ||
414 | /* unregister stuff */ | |
415 | free_irq(dev->pci->irq, dev); | |
416 | pci_set_drvdata(dev->pci, NULL); | |
417 | ||
418 | /* free memory */ | |
419 | btcx_riscmem_free(dev->pci,&dev->mpegq.stopper); | |
420 | } | |
421 | ||
422 | /* ----------------------------------------------------------- */ | |
423 | ||
424 | int cx8802_suspend_common(struct pci_dev *pci_dev, pm_message_t state) | |
425 | { | |
426 | struct cx8802_dev *dev = pci_get_drvdata(pci_dev); | |
427 | struct cx88_core *core = dev->core; | |
428 | ||
429 | /* stop mpeg dma */ | |
430 | spin_lock(&dev->slock); | |
431 | if (!list_empty(&dev->mpegq.active)) { | |
b45009b0 | 432 | dprintk( 2, "suspend\n" ); |
1da177e4 LT |
433 | printk("%s: suspend mpeg\n", core->name); |
434 | cx8802_stop_dma(dev); | |
435 | del_timer(&dev->mpegq.timeout); | |
436 | } | |
437 | spin_unlock(&dev->slock); | |
438 | ||
439 | #if 1 | |
440 | /* FIXME -- shutdown device */ | |
441 | cx88_shutdown(dev->core); | |
442 | #endif | |
443 | ||
444 | pci_save_state(pci_dev); | |
445 | if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) { | |
446 | pci_disable_device(pci_dev); | |
447 | dev->state.disabled = 1; | |
448 | } | |
449 | return 0; | |
450 | } | |
451 | ||
452 | int cx8802_resume_common(struct pci_dev *pci_dev) | |
453 | { | |
454 | struct cx8802_dev *dev = pci_get_drvdata(pci_dev); | |
455 | struct cx88_core *core = dev->core; | |
456 | ||
457 | if (dev->state.disabled) { | |
458 | pci_enable_device(pci_dev); | |
459 | dev->state.disabled = 0; | |
460 | } | |
461 | pci_set_power_state(pci_dev, PCI_D0); | |
462 | pci_restore_state(pci_dev); | |
463 | ||
464 | #if 1 | |
465 | /* FIXME: re-initialize hardware */ | |
466 | cx88_reset(dev->core); | |
467 | #endif | |
468 | ||
469 | /* restart video+vbi capture */ | |
470 | spin_lock(&dev->slock); | |
471 | if (!list_empty(&dev->mpegq.active)) { | |
472 | printk("%s: resume mpeg\n", core->name); | |
473 | cx8802_restart_queue(dev,&dev->mpegq); | |
474 | } | |
475 | spin_unlock(&dev->slock); | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | /* ----------------------------------------------------------- */ | |
481 | ||
482 | EXPORT_SYMBOL(cx8802_buf_prepare); | |
483 | EXPORT_SYMBOL(cx8802_buf_queue); | |
484 | EXPORT_SYMBOL(cx8802_cancel_buffers); | |
485 | ||
486 | EXPORT_SYMBOL(cx8802_init_common); | |
487 | EXPORT_SYMBOL(cx8802_fini_common); | |
488 | ||
489 | EXPORT_SYMBOL(cx8802_suspend_common); | |
490 | EXPORT_SYMBOL(cx8802_resume_common); | |
491 | ||
492 | /* ----------------------------------------------------------- */ | |
493 | /* | |
494 | * Local variables: | |
495 | * c-basic-offset: 8 | |
496 | * End: | |
b45009b0 | 497 | * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off |
1da177e4 | 498 | */ |