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[media] em28xx: pre-allocate DVB isoc transfer buffers
[deliverable/linux.git] / drivers / media / video / em28xx / em28xx-core.c
CommitLineData
a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
5a0e3ad6 27#include <linux/slab.h>
a6c2ba28 28#include <linux/usb.h>
29#include <linux/vmalloc.h>
1a23f81b 30#include <media/v4l2-common.h>
a6c2ba28 31
f7abcd38 32#include "em28xx.h"
a6c2ba28 33
34/* #define ENABLE_DEBUG_ISOC_FRAMES */
35
ff699e6b 36static unsigned int core_debug;
a1a6ee74
NS		 37module_param(core_debug, int, 0644);
38MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
a6c2ba28 39
3acf2809 40#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 41 if (core_debug) \
42 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 43 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 44
ff699e6b 45static unsigned int reg_debug;
a1a6ee74
NS		 46module_param(reg_debug, int, 0644);
47MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
a6c2ba28 48
3acf2809 49#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 50 if (reg_debug) \
51 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 52 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 53
fc099f0e 54static int alt;
a6c2ba28 55module_param(alt, int, 0644);
56MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
57
da52a55c
DH		 58static unsigned int disable_vbi;
59module_param(disable_vbi, int, 0644);
60MODULE_PARM_DESC(disable_vbi, "disable vbi support");
61
579f72e4
AT		 62/* FIXME */
63#define em28xx_isocdbg(fmt, arg...) do {\
64 if (core_debug) \
65 printk(KERN_INFO "%s %s :"fmt, \
66 dev->name, __func__ , ##arg); } while (0)
67
a6c2ba28 68/*
3acf2809 69 * em28xx_read_reg_req()
a6c2ba28 70 * reads data from the usb device specifying bRequest
71 */
3acf2809 72int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28 73 char *buf, int len)
74{
9e5d6760
MCC		 75 int ret;
76 int pipe = usb_rcvctrlpipe(dev->udev, 0);
a6c2ba28 77
9f38724a 78 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 79 return -ENODEV;
80
81 if (len > URB_MAX_CTRL_SIZE)
82 return -EINVAL;
9f38724a 83
9e5d6760 84 if (reg_debug) {
a1a6ee74 85 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 86 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
87 pipe,
88 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
89 req, 0, 0,
90 reg & 0xff, reg >> 8,
91 len & 0xff, len >> 8);
92 }
a6c2ba28 93
f2a2e491 94 mutex_lock(&dev->ctrl_urb_lock);
9e5d6760 95 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 96 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 97 0x0000, reg, dev->urb_buf, len, HZ);
98 if (ret < 0) {
99 if (reg_debug)
100 printk(" failed!\n");
f2a2e491 101 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 102 return ret;
103 }
104
105 if (len)
106 memcpy(buf, dev->urb_buf, len);
a6c2ba28 107
f2a2e491
MCC		 108 mutex_unlock(&dev->ctrl_urb_lock);
109
6ea54d93 110 if (reg_debug) {
9e5d6760
MCC		 111 int byte;
112
113 printk("<<<");
6ea54d93 114 for (byte = 0; byte < len; byte++)
82ac4f87 115 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 116 printk("\n");
a6c2ba28 117 }
118
119 return ret;
120}
121
122/*
3acf2809 123 * em28xx_read_reg_req()
a6c2ba28 124 * reads data from the usb device specifying bRequest
125 */
3acf2809 126int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 127{
a6c2ba28 128 int ret;
9e5d6760 129 u8 val;
a6c2ba28 130
9e5d6760
MCC		 131 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
132 if (ret < 0)
c4a98793 133 return ret;
a6c2ba28 134
135 return val;
136}
137
3acf2809 138int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 139{
3acf2809 140 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28 141}
142
143/*
3acf2809 144 * em28xx_write_regs_req()
a6c2ba28 145 * sends data to the usb device, specifying bRequest
146 */
3acf2809 147int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28 148 int len)
149{
150 int ret;
9e5d6760 151 int pipe = usb_sndctrlpipe(dev->udev, 0);
a6c2ba28 152
9f38724a 153 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 154 return -ENODEV;
155
c4a98793 156 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 157 return -EINVAL;
9f38724a 158
a6c2ba28 159 if (reg_debug) {
9e5d6760
MCC		 160 int byte;
161
a1a6ee74 162 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 163 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
164 pipe,
165 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
166 req, 0, 0,
167 reg & 0xff, reg >> 8,
168 len & 0xff, len >> 8);
169
170 for (byte = 0; byte < len; byte++)
171 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 172 printk("\n");
a6c2ba28 173 }
174
f2a2e491 175 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 176 memcpy(dev->urb_buf, buf, len);
9e5d6760 177 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 178 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 179 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 180 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 181
89b329ef
MCC		 182 if (dev->wait_after_write)
183 msleep(dev->wait_after_write);
184
a6c2ba28 185 return ret;
186}
187
3acf2809 188int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 189{
c67ec53f
MCC		 190 int rc;
191
192 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
193
194 /* Stores GPO/GPIO values at the cache, if changed
195 Only write values should be stored, since input on a GPIO
196 register will return the input bits.
197 Not sure what happens on reading GPO register.
198 */
199 if (rc >= 0) {
6a1acc3b 200 if (reg == dev->reg_gpo_num)
c67ec53f 201 dev->reg_gpo = buf[0];
6a1acc3b 202 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 203 dev->reg_gpio = buf[0];
204 }
205
206 return rc;
a6c2ba28 207}
208
b6972489
DH		 209/* Write a single register */
210int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
211{
212 return em28xx_write_regs(dev, reg, &val, 1);
213}
fec528b7 214EXPORT_SYMBOL_GPL(em28xx_write_reg);
b6972489 215
a6c2ba28 216/*
3acf2809 217 * em28xx_write_reg_bits()
a6c2ba28 218 * sets only some bits (specified by bitmask) of a register, by first reading
219 * the actual value
220 */
1bad429e 221int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28 222 u8 bitmask)
223{
224 int oldval;
225 u8 newval;
6ea54d93 226
c67ec53f 227 /* Uses cache for gpo/gpio registers */
6a1acc3b 228 if (reg == dev->reg_gpo_num)
c67ec53f 229 oldval = dev->reg_gpo;
6a1acc3b 230 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 231 oldval = dev->reg_gpio;
232 else
233 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 234
235 if (oldval < 0)
a6c2ba28 236 return oldval;
6ea54d93 237
a6c2ba28 238 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 239
3acf2809 240 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28 241}
242
35643943
MCC		 243/*
244 * em28xx_is_ac97_ready()
245 * Checks if ac97 is ready
246 */
247static int em28xx_is_ac97_ready(struct em28xx *dev)
248{
249 int ret, i;
250
251 /* Wait up to 50 ms for AC97 command to complete */
252 for (i = 0; i < 10; i++, msleep(5)) {
253 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
254 if (ret < 0)
255 return ret;
256
257 if (!(ret & 0x01))
258 return 0;
259 }
260
261 em28xx_warn("AC97 command still being executed: not handled properly!\n");
262 return -EBUSY;
263}
264
265/*
266 * em28xx_read_ac97()
267 * write a 16 bit value to the specified AC97 address (LSB first!)
268 */
531c98e7 269int em28xx_read_ac97(struct em28xx *dev, u8 reg)
35643943
MCC		 270{
271 int ret;
272 u8 addr = (reg & 0x7f) | 0x80;
273 u16 val;
274
275 ret = em28xx_is_ac97_ready(dev);
276 if (ret < 0)
277 return ret;
278
279 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
280 if (ret < 0)
281 return ret;
282
283 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
284 (u8 *)&val, sizeof(val));
285
286 if (ret < 0)
287 return ret;
288 return le16_to_cpu(val);
289}
850d24a5 290EXPORT_SYMBOL_GPL(em28xx_read_ac97);
35643943 291
a6c2ba28 292/*
3acf2809 293 * em28xx_write_ac97()
a6c2ba28 294 * write a 16 bit value to the specified AC97 address (LSB first!)
295 */
531c98e7 296int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 297{
35643943 298 int ret;
a6c2ba28 299 u8 addr = reg & 0x7f;
35643943
MCC		 300 __le16 value;
301
302 value = cpu_to_le16(val);
303
304 ret = em28xx_is_ac97_ready(dev);
305 if (ret < 0)
306 return ret;
6ea54d93 307
35643943 308 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 309 if (ret < 0)
a6c2ba28 310 return ret;
6ea54d93 311
41facaa4 312 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 313 if (ret < 0)
a6c2ba28 314 return ret;
00b8730f 315
35643943
MCC		 316 return 0;
317}
850d24a5 318EXPORT_SYMBOL_GPL(em28xx_write_ac97);
6ea54d93 319
0f8a61fc 320struct em28xx_vol_itable {
e879b8eb 321 enum em28xx_amux mux;
5faff789
MCC		 322 u8 reg;
323};
324
0f8a61fc 325static struct em28xx_vol_itable inputs[] = {
5faff789
MCC		 326 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
327 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
328 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
329 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
330 { EM28XX_AMUX_CD, AC97_CD_VOL },
331 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
332 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
333};
334
335static int set_ac97_input(struct em28xx *dev)
35643943 336{
5faff789
MCC		 337 int ret, i;
338 enum em28xx_amux amux = dev->ctl_ainput;
35643943 339
5faff789
MCC		 340 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
341 em28xx should point to LINE IN, while AC97 should use VIDEO
342 */
343 if (amux == EM28XX_AMUX_VIDEO2)
f1990a9c 344 amux = EM28XX_AMUX_VIDEO;
35643943 345
5faff789
MCC		 346 /* Mute all entres but the one that were selected */
347 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
e879b8eb 348 if (amux == inputs[i].mux)
5faff789
MCC		 349 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
350 else
351 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
35643943 352
5faff789
MCC		 353 if (ret < 0)
354 em28xx_warn("couldn't setup AC97 register %d\n",
355 inputs[i].reg);
356 }
357 return 0;
a6c2ba28 358}
359
00b8730f 360static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 361{
1685a6fe 362 int ret;
539c96d0
MCC		 363 u8 input;
364
505b6d0b 365 if (dev->board.is_em2800) {
5faff789 366 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
539c96d0 367 input = EM2800_AUDIO_SRC_TUNER;
5faff789
MCC		 368 else
369 input = EM2800_AUDIO_SRC_LINE;
539c96d0 370
41facaa4 371 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 372 if (ret < 0)
373 return ret;
374 }
375
505b6d0b 376 if (dev->board.has_msp34xx)
539c96d0
MCC		 377 input = EM28XX_AUDIO_SRC_TUNER;
378 else {
379 switch (dev->ctl_ainput) {
380 case EM28XX_AMUX_VIDEO:
381 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 382 break;
35643943 383 default:
539c96d0 384 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 385 break;
386 }
387 }
388
2bd1d9eb
VW		 389 if (dev->board.mute_gpio && dev->mute)
390 em28xx_gpio_set(dev, dev->board.mute_gpio);
391 else
392 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
393
41facaa4 394 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 395 if (ret < 0)
396 return ret;
00b8730f 397 msleep(5);
539c96d0 398
35643943
MCC		 399 switch (dev->audio_mode.ac97) {
400 case EM28XX_NO_AC97:
401 break;
5faff789
MCC		 402 default:
403 ret = set_ac97_input(dev);
35643943 404 }
539c96d0 405
5faff789 406 return ret;
539c96d0
MCC		 407}
408
0f8a61fc
MCC		 409struct em28xx_vol_otable {
410 enum em28xx_aout mux;
411 u8 reg;
412};
413
414static const struct em28xx_vol_otable outputs[] = {
e879b8eb
MCC		 415 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
416 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
417 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
418 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
419 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
35ae6f04
MCC		 420};
421
3acf2809 422int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 423{
35ae6f04 424 int ret, i;
a2070c66 425 u8 xclk;
539c96d0 426
35643943
MCC		 427 if (!dev->audio_mode.has_audio)
428 return 0;
539c96d0 429
5faff789
MCC		 430 /* It is assumed that all devices use master volume for output.
431 It would be possible to use also line output.
432 */
35643943 433 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
35ae6f04
MCC		 434 /* Mute all outputs */
435 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
e879b8eb 436 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
35ae6f04
MCC		 437 if (ret < 0)
438 em28xx_warn("couldn't setup AC97 register %d\n",
e879b8eb 439 outputs[i].reg);
35ae6f04 440 }
35643943 441 }
539c96d0 442
505b6d0b 443 xclk = dev->board.xclk & 0x7f;
3abee53e 444 if (!dev->mute)
8ed06fd4 445 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
3abee53e 446
a2070c66 447 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
539c96d0
MCC		 448 if (ret < 0)
449 return ret;
3abee53e 450 msleep(10);
539c96d0
MCC		 451
452 /* Selects the proper audio input */
453 ret = em28xx_set_audio_source(dev);
a6c2ba28 454
35643943
MCC		 455 /* Sets volume */
456 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
457 int vol;
458
7e4b15e4
RK		 459 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
460 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
461 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
462
35643943
MCC		 463 /* LSB: left channel - both channels with the same level */
464 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
465
466 /* Mute device, if needed */
467 if (dev->mute)
468 vol |= 0x8000;
469
470 /* Sets volume */
e879b8eb
MCC		 471 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
472 if (dev->ctl_aoutput & outputs[i].mux)
473 ret = em28xx_write_ac97(dev, outputs[i].reg,
474 vol);
475 if (ret < 0)
476 em28xx_warn("couldn't setup AC97 register %d\n",
477 outputs[i].reg);
478 }
8866f9cf
MCC		 479
480 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
481 int sel = ac97_return_record_select(dev->ctl_aoutput);
482
a1a6ee74
NS		 483 /* Use the same input for both left and right
484 channels */
8866f9cf
MCC		 485 sel |= (sel << 8);
486
487 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
488 }
35643943 489 }
00b8730f 490
539c96d0
MCC		 491 return ret;
492}
493EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 494
35643943
MCC		 495int em28xx_audio_setup(struct em28xx *dev)
496{
497 int vid1, vid2, feat, cfg;
16c7bcad 498 u32 vid;
35643943 499
2892bd0d
SK		 500 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874
501 || dev->chip_id == CHIP_ID_EM28174) {
35643943 502 /* Digital only device - don't load any alsa module */
4f83e7b3
MCC		 503 dev->audio_mode.has_audio = false;
504 dev->has_audio_class = false;
505 dev->has_alsa_audio = false;
35643943
MCC		 506 return 0;
507 }
508
4f83e7b3 509 dev->audio_mode.has_audio = true;
35643943
MCC		 510
511 /* See how this device is configured */
512 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
1cdc6392
DH		 513 em28xx_info("Config register raw data: 0x%02x\n", cfg);
514 if (cfg < 0) {
515 /* Register read error? */
35643943 516 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
1cdc6392
DH		 517 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
518 /* The device doesn't have vendor audio at all */
4f83e7b3
MCC		 519 dev->has_alsa_audio = false;
520 dev->audio_mode.has_audio = false;
1cdc6392
DH		 521 return 0;
522 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
523 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
35643943
MCC		 524 em28xx_info("I2S Audio (3 sample rates)\n");
525 dev->audio_mode.i2s_3rates = 1;
1cdc6392
DH		 526 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
527 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
35643943
MCC		 528 em28xx_info("I2S Audio (5 sample rates)\n");
529 dev->audio_mode.i2s_5rates = 1;
530 }
531
de84830e
DH		 532 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
533 /* Skip the code that does AC97 vendor detection */
35643943
MCC		 534 dev->audio_mode.ac97 = EM28XX_NO_AC97;
535 goto init_audio;
536 }
537
538 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
539
540 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
541 if (vid1 < 0) {
0731160a
MCC		 542 /*
543 * Device likely doesn't support AC97
544 * Note: (some) em2800 devices without eeprom reports 0x91 on
545 * CHIPCFG register, even not having an AC97 chip
546 */
35643943 547 em28xx_warn("AC97 chip type couldn't be determined\n");
0731160a 548 dev->audio_mode.ac97 = EM28XX_NO_AC97;
4f83e7b3
MCC		 549 dev->has_alsa_audio = false;
550 dev->audio_mode.has_audio = false;
35643943
MCC		 551 goto init_audio;
552 }
553
554 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
555 if (vid2 < 0)
556 goto init_audio;
557
16c7bcad
MCC		 558 vid = vid1 << 16 | vid2;
559
560 dev->audio_mode.ac97_vendor_id = vid;
561 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 562
563 feat = em28xx_read_ac97(dev, AC97_RESET);
564 if (feat < 0)
565 goto init_audio;
566
567 dev->audio_mode.ac97_feat = feat;
568 em28xx_warn("AC97 features = 0x%04x\n", feat);
569
16c7bcad 570 /* Try to identify what audio processor we have */
2a5fc873 571 if (((vid == 0xffffffff) || (vid == 0x83847650)) && (feat == 0x6a90))
35643943 572 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
209acc02
MCC		 573 else if ((vid >> 8) == 0x838476)
574 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
35643943
MCC		 575
576init_audio:
577 /* Reports detected AC97 processor */
578 switch (dev->audio_mode.ac97) {
579 case EM28XX_NO_AC97:
580 em28xx_info("No AC97 audio processor\n");
581 break;
582 case EM28XX_AC97_EM202:
583 em28xx_info("Empia 202 AC97 audio processor detected\n");
584 break;
209acc02
MCC		 585 case EM28XX_AC97_SIGMATEL:
586 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
587 dev->audio_mode.ac97_vendor_id & 0xff);
588 break;
35643943
MCC		 589 case EM28XX_AC97_OTHER:
590 em28xx_warn("Unknown AC97 audio processor detected!\n");
591 break;
592 default:
593 break;
594 }
595
596 return em28xx_audio_analog_set(dev);
597}
598EXPORT_SYMBOL_GPL(em28xx_audio_setup);
599
3acf2809 600int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 601{
2a29a0d7
MCC		 602 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
603 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
604 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
605 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
606 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
607 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
608
609 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
610 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
611 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
612 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
613 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
614 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
615 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
a6c2ba28 616}
617
3acf2809 618int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 619{
ee6e3a86 620 int rc;
ebef13d4 621
fec528b7
MCC		 622 if (dev->chip_id == CHIP_ID_EM2874 ||
623 dev->chip_id == CHIP_ID_EM2884 ||
624 dev->chip_id == CHIP_ID_EM28174) {
ebef13d4
DH		 625 /* The Transport Stream Enable Register moved in em2874 */
626 if (!start) {
627 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
628 0x00,
629 EM2874_TS1_CAPTURE_ENABLE);
630 return rc;
631 }
632
633 /* Enable Transport Stream */
634 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
635 EM2874_TS1_CAPTURE_ENABLE,
636 EM2874_TS1_CAPTURE_ENABLE);
637 return rc;
638 }
639
640
a6c2ba28 641 /* FIXME: which is the best order? */
642 /* video registers are sampled by VREF */
41facaa4 643 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 644 start ? 0x10 : 0x00, 0x10);
645 if (rc < 0)
646 return rc;
647
648 if (!start) {
649 /* disable video capture */
2a29a0d7 650 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
102a0b08 651 return rc;
ee6e3a86
MCC		 652 }
653
d7612c86
MCC		 654 if (dev->board.is_webcam)
655 rc = em28xx_write_reg(dev, 0x13, 0x0c);
656
a6c2ba28 657 /* enable video capture */
2a29a0d7 658 rc = em28xx_write_reg(dev, 0x48, 0x00);
102a0b08 659
ee6e3a86 660 if (dev->mode == EM28XX_ANALOG_MODE)
2a29a0d7 661 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
ee6e3a86 662 else
2a29a0d7 663 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
ee6e3a86 664
6ea54d93 665 msleep(6);
ee6e3a86
MCC		 666
667 return rc;
a6c2ba28 668}
86d38d1e 669EXPORT_SYMBOL_GPL(em28xx_capture_start);
a6c2ba28 670
da52a55c
DH		 671int em28xx_vbi_supported(struct em28xx *dev)
672{
673 /* Modprobe option to manually disable */
674 if (disable_vbi == 1)
675 return 0;
676
677 if (dev->chip_id == CHIP_ID_EM2860 ||
678 dev->chip_id == CHIP_ID_EM2883)
679 return 1;
680
681 /* Version of em28xx that does not support VBI */
682 return 0;
683}
684
bddcf633 685int em28xx_set_outfmt(struct em28xx *dev)
a6c2ba28 686{
bddcf633 687 int ret;
da52a55c 688 u8 vinctrl;
bddcf633
MCC		 689
690 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
579d3152 691 dev->format->reg | 0x20, 0xff);
bddcf633 692 if (ret < 0)
02e7804b 693 return ret;
bddcf633 694
579d3152 695 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
bddcf633
MCC		 696 if (ret < 0)
697 return ret;
698
da52a55c
DH		 699 vinctrl = dev->vinctl;
700 if (em28xx_vbi_supported(dev) == 1) {
701 vinctrl |= EM28XX_VINCTRL_VBI_RAW;
702 em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
66d9cbad
DH		 703 em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
704 em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
705 if (dev->norm & V4L2_STD_525_60) {
706 /* NTSC */
707 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
708 } else if (dev->norm & V4L2_STD_625_50) {
709 /* PAL */
710 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
711 }
da52a55c
DH		 712 }
713
714 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
a6c2ba28 715}
716
adcb0fa2
AB		 717static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
718 u8 ymin, u8 ymax)
a6c2ba28 719{
6ea54d93
DSL		 720 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
721 xmin, ymin, xmax, ymax);
a6c2ba28 722
41facaa4
MCC		 723 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
724 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
725 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
726 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28 727}
728
adcb0fa2 729static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28 730 u16 width, u16 height)
731{
732 u8 cwidth = width;
733 u8 cheight = height;
734 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
735
6ea54d93
DSL		 736 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
737 (width | (overflow & 2) << 7),
a6c2ba28 738 (height | (overflow & 1) << 8));
739
41facaa4
MCC		 740 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
741 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
742 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
743 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
744 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28 745}
746
adcb0fa2 747static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 748{
52c02fcd
SS		 749 u8 mode;
750 /* the em2800 scaler only supports scaling down to 50% */
02e7804b 751
55699964 752 if (dev->board.is_em2800) {
52c02fcd 753 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
02e7804b 754 } else {
52c02fcd 755 u8 buf[2];
02e7804b 756
52c02fcd
SS		 757 buf[0] = h;
758 buf[1] = h >> 8;
41facaa4 759 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
02e7804b 760
52c02fcd
SS		 761 buf[0] = v;
762 buf[1] = v >> 8;
41facaa4 763 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 764 /* it seems that both H and V scalers must be active
765 to work correctly */
a1a6ee74 766 mode = (h || v) ? 0x30 : 0x00;
74458e6c 767 }
41facaa4 768 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28 769}
770
771/* FIXME: this only function read values from dev */
3acf2809 772int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28 773{
774 int width, height;
775 width = norm_maxw(dev);
c2a6b54a
MCC		 776 height = norm_maxh(dev);
777
66d9cbad
DH		 778 /* Properly setup VBI */
779 dev->vbi_width = 720;
780 if (dev->norm & V4L2_STD_525_60)
781 dev->vbi_height = 12;
782 else
783 dev->vbi_height = 18;
784
c2a6b54a
MCC		 785 if (!dev->progressive)
786 height >>= norm_maxh(dev);
a6c2ba28 787
bddcf633 788 em28xx_set_outfmt(dev);
02e7804b
MCC		 789
790
3acf2809 791 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
da52a55c 792
1744feab
DH		 793 /* If we don't set the start position to 2 in VBI mode, we end up
794 with line 20/21 being YUYV encoded instead of being in 8-bit
795 greyscale. The core of the issue is that line 21 (and line 23 for
796 PAL WSS) are inside of active video region, and as a result they
797 get the pixelformatting associated with that area. So by cropping
798 it out, we end up with the same format as the rest of the VBI
799 region */
da52a55c 800 if (em28xx_vbi_supported(dev) == 1)
1744feab 801 em28xx_capture_area_set(dev, 0, 2, width >> 2, height >> 2);
da52a55c
DH		 802 else
803 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
02e7804b 804
3acf2809 805 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28 806}
807
3acf2809 808int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28 809{
810 int errCode, prev_alt = dev->alt;
3687e1e6 811 int i;
44dc733c 812 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 813
fc099f0e
MCC		 814 /*
815 * alt = 0 is used only for control messages, so, only values
816 * greater than 0 can be used for streaming.
817 */
818 if (alt && alt < dev->num_alt) {
819 em28xx_coredbg("alternate forced to %d\n", dev->alt);
820 dev->alt = alt;
821 goto set_alt;
822 }
823
2c4a07b2 824 /* When image size is bigger than a certain value,
3687e1e6
MCC		 825 the frame size should be increased, otherwise, only
826 green screen will be received.
827 */
44dc733c 828 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 829 min_pkt_size *= 2;
830
2c4a07b2
SS		 831 for (i = 0; i < dev->num_alt; i++) {
832 /* stop when the selected alt setting offers enough bandwidth */
833 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
834 dev->alt = i;
3687e1e6 835 break;
2c4a07b2
SS		 836 /* otherwise make sure that we end up with the maximum bandwidth
837 because the min_pkt_size equation might be wrong...
838 */
839 } else if (dev->alt_max_pkt_size[i] >
840 dev->alt_max_pkt_size[dev->alt])
841 dev->alt = i;
842 }
a6c2ba28 843
fc099f0e 844set_alt:
a6c2ba28 845 if (dev->alt != prev_alt) {
3687e1e6
MCC		 846 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
847 min_pkt_size, dev->alt);
a6c2ba28 848 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 849 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
850 dev->alt, dev->max_pkt_size);
a6c2ba28 851 errCode = usb_set_interface(dev->udev, 0, dev->alt);
852 if (errCode < 0) {
6ea54d93 853 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 854 dev->alt, errCode);
a6c2ba28 855 return errCode;
856 }
857 }
858 return 0;
859}
579f72e4 860
c67ec53f
MCC		 861int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
862{
863 int rc = 0;
864
865 if (!gpio)
866 return rc;
867
2fe3e2ee
MCC		 868 if (dev->mode != EM28XX_SUSPEND) {
869 em28xx_write_reg(dev, 0x48, 0x00);
870 if (dev->mode == EM28XX_ANALOG_MODE)
871 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
872 else
873 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
874 msleep(6);
875 }
c67ec53f
MCC		 876
877 /* Send GPIO reset sequences specified at board entry */
878 while (gpio->sleep >= 0) {
879 if (gpio->reg >= 0) {
880 rc = em28xx_write_reg_bits(dev,
881 gpio->reg,
882 gpio->val,
883 gpio->mask);
884 if (rc < 0)
885 return rc;
886 }
887 if (gpio->sleep > 0)
888 msleep(gpio->sleep);
889
890 gpio++;
891 }
892 return rc;
893}
fec528b7 894EXPORT_SYMBOL_GPL(em28xx_gpio_set);
c67ec53f
MCC		 895
896int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
897{
898 if (dev->mode == set_mode)
899 return 0;
900
2fe3e2ee 901 if (set_mode == EM28XX_SUSPEND) {
c67ec53f 902 dev->mode = set_mode;
2fe3e2ee
MCC		 903
904 /* FIXME: add suspend support for ac97 */
905
906 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
c67ec53f
MCC		 907 }
908
909 dev->mode = set_mode;
910
911 if (dev->mode == EM28XX_DIGITAL_MODE)
f502e861 912 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
c67ec53f 913 else
f502e861 914 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
c67ec53f
MCC		 915}
916EXPORT_SYMBOL_GPL(em28xx_set_mode);
917
579f72e4
AT		 918/* ------------------------------------------------------------------
919 URB control
920 ------------------------------------------------------------------*/
921
922/*
923 * IRQ callback, called by URB callback
924 */
925static void em28xx_irq_callback(struct urb *urb)
926{
da52a55c 927 struct em28xx *dev = urb->context;
00d2e7ad 928 int i;
579f72e4 929
aa5a1821
RK		 930 switch (urb->status) {
931 case 0: /* success */
932 case -ETIMEDOUT: /* NAK */
933 break;
934 case -ECONNRESET: /* kill */
935 case -ENOENT:
936 case -ESHUTDOWN:
937 return;
938 default: /* error */
939 em28xx_isocdbg("urb completition error %d.\n", urb->status);
940 break;
941 }
942
579f72e4
AT		 943 /* Copy data from URB */
944 spin_lock(&dev->slock);
00d2e7ad 945 dev->isoc_ctl.isoc_copy(dev, urb);
579f72e4
AT		 946 spin_unlock(&dev->slock);
947
948 /* Reset urb buffers */
949 for (i = 0; i < urb->number_of_packets; i++) {
950 urb->iso_frame_desc[i].status = 0;
951 urb->iso_frame_desc[i].actual_length = 0;
952 }
953 urb->status = 0;
954
955 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
956 if (urb->status) {
4269a8ee
DH		 957 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
958 urb->status);
579f72e4
AT		 959 }
960}
961
962/*
963 * Stop and Deallocate URBs
964 */
86d38d1e 965void em28xx_uninit_isoc(struct em28xx *dev, enum em28xx_mode mode)
579f72e4
AT		 966{
967 struct urb *urb;
86d38d1e 968 struct em28xx_usb_isoc_bufs *isoc_bufs;
579f72e4
AT		 969 int i;
970
86d38d1e
GG		 971 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc in mode %d\n", mode);
972
973 if (mode == EM28XX_DIGITAL_MODE)
974 isoc_bufs = &dev->isoc_ctl.digital_bufs;
975 else
976 isoc_bufs = &dev->isoc_ctl.analog_bufs;
579f72e4
AT		 977
978 dev->isoc_ctl.nfields = -1;
86d38d1e
GG		 979 for (i = 0; i < isoc_bufs->num_bufs; i++) {
980 urb = isoc_bufs->urb[i];
579f72e4 981 if (urb) {
9c06210b
RK		 982 if (!irqs_disabled())
983 usb_kill_urb(urb);
984 else
985 usb_unlink_urb(urb);
986
86d38d1e 987 if (isoc_bufs->transfer_buffer[i]) {
997ea58e 988 usb_free_coherent(dev->udev,
6ea54d93 989 urb->transfer_buffer_length,
86d38d1e 990 isoc_bufs->transfer_buffer[i],
6ea54d93 991 urb->transfer_dma);
579f72e4
AT		 992 }
993 usb_free_urb(urb);
86d38d1e 994 isoc_bufs->urb[i] = NULL;
579f72e4 995 }
86d38d1e 996 isoc_bufs->transfer_buffer[i] = NULL;
579f72e4
AT		 997 }
998
86d38d1e
GG		 999 kfree(isoc_bufs->urb);
1000 kfree(isoc_bufs->transfer_buffer);
579f72e4 1001
86d38d1e
GG		 1002 isoc_bufs->urb = NULL;
1003 isoc_bufs->transfer_buffer = NULL;
1004 isoc_bufs->num_bufs = 0;
579f72e4
AT		 1005
1006 em28xx_capture_start(dev, 0);
1007}
1008EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
1009
1010/*
86d38d1e 1011 * Allocate URBs
579f72e4 1012 */
86d38d1e
GG		 1013int em28xx_alloc_isoc(struct em28xx *dev, enum em28xx_mode mode,
1014 int max_packets, int num_bufs, int max_pkt_size)
579f72e4 1015{
86d38d1e 1016 struct em28xx_usb_isoc_bufs *isoc_bufs;
579f72e4
AT		 1017 int i;
1018 int sb_size, pipe;
1019 struct urb *urb;
1020 int j, k;
579f72e4 1021
86d38d1e
GG		 1022 em28xx_isocdbg("em28xx: called em28xx_alloc_isoc in mode %d\n", mode);
1023
1024 if (mode == EM28XX_DIGITAL_MODE)
1025 isoc_bufs = &dev->isoc_ctl.digital_bufs;
1026 else
1027 isoc_bufs = &dev->isoc_ctl.analog_bufs;
579f72e4
AT		 1028
1029 /* De-allocates all pending stuff */
86d38d1e 1030 em28xx_uninit_isoc(dev, mode);
579f72e4 1031
86d38d1e 1032 isoc_bufs->num_bufs = num_bufs;
579f72e4 1033
86d38d1e
GG		 1034 isoc_bufs->urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
1035 if (!isoc_bufs->urb) {
579f72e4
AT		 1036 em28xx_errdev("cannot alloc memory for usb buffers\n");
1037 return -ENOMEM;
1038 }
1039
86d38d1e
GG		 1040 isoc_bufs->transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
1041 GFP_KERNEL);
1042 if (!isoc_bufs->transfer_buffer) {
42ef4632 1043 em28xx_errdev("cannot allocate memory for usb transfer\n");
86d38d1e 1044 kfree(isoc_bufs->urb);
579f72e4
AT		 1045 return -ENOMEM;
1046 }
1047
86d38d1e
GG		 1048 isoc_bufs->max_pkt_size = max_pkt_size;
1049 isoc_bufs->num_packets = max_packets;
28abf083
DH		 1050 dev->isoc_ctl.vid_buf = NULL;
1051 dev->isoc_ctl.vbi_buf = NULL;
579f72e4 1052
86d38d1e 1053 sb_size = isoc_bufs->num_packets * isoc_bufs->max_pkt_size;
579f72e4
AT		 1054
1055 /* allocate urbs and transfer buffers */
86d38d1e
GG		 1056 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1057 urb = usb_alloc_urb(isoc_bufs->num_packets, GFP_KERNEL);
579f72e4
AT		 1058 if (!urb) {
1059 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
86d38d1e 1060 em28xx_uninit_isoc(dev, mode);
579f72e4
AT		 1061 return -ENOMEM;
1062 }
86d38d1e 1063 isoc_bufs->urb[i] = urb;
579f72e4 1064
86d38d1e 1065 isoc_bufs->transfer_buffer[i] = usb_alloc_coherent(dev->udev,
579f72e4 1066 sb_size, GFP_KERNEL, &urb->transfer_dma);
86d38d1e 1067 if (!isoc_bufs->transfer_buffer[i]) {
579f72e4
AT		 1068 em28xx_err("unable to allocate %i bytes for transfer"
1069 " buffer %i%s\n",
1070 sb_size, i,
a1a6ee74 1071 in_interrupt() ? " while in int" : "");
86d38d1e 1072 em28xx_uninit_isoc(dev, mode);
579f72e4
AT		 1073 return -ENOMEM;
1074 }
86d38d1e 1075 memset(isoc_bufs->transfer_buffer[i], 0, sb_size);
579f72e4
AT		 1076
1077 /* FIXME: this is a hack - should be
1078 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
1079 should also be using 'desc.bInterval'
1080 */
6ea54d93 1081 pipe = usb_rcvisocpipe(dev->udev,
86d38d1e 1082 mode == EM28XX_ANALOG_MODE ?
8ab33626 1083 EM28XX_EP_ANALOG : EM28XX_EP_DIGITAL);
6ea54d93 1084
579f72e4 1085 usb_fill_int_urb(urb, dev->udev, pipe,
86d38d1e 1086 isoc_bufs->transfer_buffer[i], sb_size,
da52a55c 1087 em28xx_irq_callback, dev, 1);
579f72e4 1088
86d38d1e 1089 urb->number_of_packets = isoc_bufs->num_packets;
9a4f8201 1090 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
579f72e4
AT		 1091
1092 k = 0;
86d38d1e 1093 for (j = 0; j < isoc_bufs->num_packets; j++) {
579f72e4
AT		 1094 urb->iso_frame_desc[j].offset = k;
1095 urb->iso_frame_desc[j].length =
86d38d1e
GG		 1096 isoc_bufs->max_pkt_size;
1097 k += isoc_bufs->max_pkt_size;
579f72e4
AT		 1098 }
1099 }
1100
86d38d1e
GG		 1101 return 0;
1102}
1103EXPORT_SYMBOL_GPL(em28xx_alloc_isoc);
1104
1105/*
1106 * Allocate URBs and start IRQ
1107 */
1108int em28xx_init_isoc(struct em28xx *dev, enum em28xx_mode mode,
1109 int max_packets, int num_bufs, int max_pkt_size,
1110 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
1111{
1112 struct em28xx_dmaqueue *dma_q = &dev->vidq;
1113 struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
1114 struct em28xx_usb_isoc_bufs *isoc_bufs;
1115 int i;
1116 int rc;
1117 int alloc;
1118
1119 em28xx_isocdbg("em28xx: called em28xx_init_isoc in mode %d\n", mode);
1120
1121 dev->isoc_ctl.isoc_copy = isoc_copy;
1122
1123 if (mode == EM28XX_DIGITAL_MODE) {
1124 isoc_bufs = &dev->isoc_ctl.digital_bufs;
1125 /* no need to free/alloc isoc buffers in digital mode */
1126 alloc = 0;
1127 } else {
1128 isoc_bufs = &dev->isoc_ctl.analog_bufs;
1129 alloc = 1;
1130 }
1131
1132 if (alloc) {
1133 rc = em28xx_alloc_isoc(dev, mode, max_packets,
1134 num_bufs, max_pkt_size);
1135 if (rc)
1136 return rc;
1137 }
1138
579f72e4 1139 init_waitqueue_head(&dma_q->wq);
28abf083 1140 init_waitqueue_head(&vbi_dma_q->wq);
579f72e4 1141
c67ec53f 1142 em28xx_capture_start(dev, 1);
579f72e4
AT		 1143
1144 /* submit urbs and enables IRQ */
86d38d1e
GG		 1145 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1146 rc = usb_submit_urb(isoc_bufs->urb[i], GFP_ATOMIC);
579f72e4
AT		 1147 if (rc) {
1148 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1149 rc);
86d38d1e 1150 em28xx_uninit_isoc(dev, mode);
579f72e4
AT		 1151 return rc;
1152 }
1153 }
1154
1155 return 0;
1156}
1157EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1a23f81b
MCC		 1158
1159/*
1160 * em28xx_wake_i2c()
1161 * configure i2c attached devices
1162 */
1163void em28xx_wake_i2c(struct em28xx *dev)
1164{
5325b427
HV		 1165 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1166 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1167 INPUT(dev->ctl_input)->vmux, 0, 0);
f2cf250a 1168 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1a23f81b
MCC		 1169}
1170
1171/*
1172 * Device control list
1173 */
1174
1175static LIST_HEAD(em28xx_devlist);
1176static DEFINE_MUTEX(em28xx_devlist_mutex);
1177
1a23f81b
MCC		 1178/*
1179 * Extension interface
1180 */
1181
1182static LIST_HEAD(em28xx_extension_devlist);
1a23f81b
MCC		 1183
1184int em28xx_register_extension(struct em28xx_ops *ops)
1185{
1186 struct em28xx *dev = NULL;
1187
1188 mutex_lock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1189 list_add_tail(&ops->next, &em28xx_extension_devlist);
1190 list_for_each_entry(dev, &em28xx_devlist, devlist) {
517521e4 1191 ops->init(dev);
1a23f81b 1192 }
1a23f81b 1193 mutex_unlock(&em28xx_devlist_mutex);
76424a0a 1194 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1a23f81b
MCC		 1195 return 0;
1196}
1197EXPORT_SYMBOL(em28xx_register_extension);
1198
1199void em28xx_unregister_extension(struct em28xx_ops *ops)
1200{
1201 struct em28xx *dev = NULL;
1202
1203 mutex_lock(&em28xx_devlist_mutex);
1204 list_for_each_entry(dev, &em28xx_devlist, devlist) {
517521e4 1205 ops->fini(dev);
1a23f81b 1206 }
1a23f81b 1207 list_del(&ops->next);
1a23f81b 1208 mutex_unlock(&em28xx_devlist_mutex);
76424a0a 1209 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1a23f81b
MCC		 1210}
1211EXPORT_SYMBOL(em28xx_unregister_extension);
1212
1213void em28xx_init_extension(struct em28xx *dev)
1214{
6c03e38b 1215 const struct em28xx_ops *ops = NULL;
1a23f81b 1216
5013318c 1217 mutex_lock(&em28xx_devlist_mutex);
6c03e38b
CR		 1218 list_add_tail(&dev->devlist, &em28xx_devlist);
1219 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1220 if (ops->init)
1221 ops->init(dev);
1a23f81b 1222 }
5013318c 1223 mutex_unlock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1224}
1225
1226void em28xx_close_extension(struct em28xx *dev)
1227{
d7222e7d 1228 const struct em28xx_ops *ops = NULL;
1a23f81b 1229
5013318c 1230 mutex_lock(&em28xx_devlist_mutex);
d7222e7d
CR		 1231 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1232 if (ops->fini)
1233 ops->fini(dev);
1a23f81b 1234 }
d7222e7d 1235 list_del(&dev->devlist);
5013318c 1236 mutex_unlock(&em28xx_devlist_mutex);
1a23f81b 1237}
Linux kernel - Deliverables
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