Commit | Line | Data |
---|---|---|
a6c2ba28 | 1 | /* |
3acf2809 | 2 | em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices |
a6c2ba28 | 3 | |
f7abcd38 MCC |
4 | Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it> |
5 | Markus Rechberger <mrechberger@gmail.com> | |
2e7c6dc3 | 6 | Mauro Carvalho Chehab <mchehab@infradead.org> |
f7abcd38 | 7 | Sascha Sommer <saschasommer@freenet.de> |
a6c2ba28 | 8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
a6c2ba28 | 27 | #include <linux/usb.h> |
28 | #include <linux/vmalloc.h> | |
1a23f81b | 29 | #include <media/v4l2-common.h> |
a6c2ba28 | 30 | |
f7abcd38 | 31 | #include "em28xx.h" |
a6c2ba28 | 32 | |
33 | /* #define ENABLE_DEBUG_ISOC_FRAMES */ | |
34 | ||
ff699e6b | 35 | static unsigned int core_debug; |
a1a6ee74 NS |
36 | module_param(core_debug, int, 0644); |
37 | MODULE_PARM_DESC(core_debug, "enable debug messages [core]"); | |
a6c2ba28 | 38 | |
3acf2809 | 39 | #define em28xx_coredbg(fmt, arg...) do {\ |
4ac97914 MCC |
40 | if (core_debug) \ |
41 | printk(KERN_INFO "%s %s :"fmt, \ | |
d80e134d | 42 | dev->name, __func__ , ##arg); } while (0) |
a6c2ba28 | 43 | |
ff699e6b | 44 | static unsigned int reg_debug; |
a1a6ee74 NS |
45 | module_param(reg_debug, int, 0644); |
46 | MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]"); | |
a6c2ba28 | 47 | |
3acf2809 | 48 | #define em28xx_regdbg(fmt, arg...) do {\ |
4ac97914 MCC |
49 | if (reg_debug) \ |
50 | printk(KERN_INFO "%s %s :"fmt, \ | |
d80e134d | 51 | dev->name, __func__ , ##arg); } while (0) |
a6c2ba28 | 52 | |
3acf2809 | 53 | static int alt = EM28XX_PINOUT; |
a6c2ba28 | 54 | module_param(alt, int, 0644); |
55 | MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint"); | |
56 | ||
579f72e4 AT |
57 | /* FIXME */ |
58 | #define em28xx_isocdbg(fmt, arg...) do {\ | |
59 | if (core_debug) \ | |
60 | printk(KERN_INFO "%s %s :"fmt, \ | |
61 | dev->name, __func__ , ##arg); } while (0) | |
62 | ||
a6c2ba28 | 63 | /* |
3acf2809 | 64 | * em28xx_read_reg_req() |
a6c2ba28 | 65 | * reads data from the usb device specifying bRequest |
66 | */ | |
3acf2809 | 67 | int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg, |
a6c2ba28 | 68 | char *buf, int len) |
69 | { | |
9e5d6760 MCC |
70 | int ret; |
71 | int pipe = usb_rcvctrlpipe(dev->udev, 0); | |
a6c2ba28 | 72 | |
9f38724a | 73 | if (dev->state & DEV_DISCONNECTED) |
c4a98793 MCC |
74 | return -ENODEV; |
75 | ||
76 | if (len > URB_MAX_CTRL_SIZE) | |
77 | return -EINVAL; | |
9f38724a | 78 | |
9e5d6760 | 79 | if (reg_debug) { |
a1a6ee74 | 80 | printk(KERN_DEBUG "(pipe 0x%08x): " |
9e5d6760 MCC |
81 | "IN: %02x %02x %02x %02x %02x %02x %02x %02x ", |
82 | pipe, | |
83 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
84 | req, 0, 0, | |
85 | reg & 0xff, reg >> 8, | |
86 | len & 0xff, len >> 8); | |
87 | } | |
a6c2ba28 | 88 | |
f2a2e491 | 89 | mutex_lock(&dev->ctrl_urb_lock); |
9e5d6760 | 90 | ret = usb_control_msg(dev->udev, pipe, req, |
a6c2ba28 | 91 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, |
c4a98793 MCC |
92 | 0x0000, reg, dev->urb_buf, len, HZ); |
93 | if (ret < 0) { | |
94 | if (reg_debug) | |
95 | printk(" failed!\n"); | |
f2a2e491 | 96 | mutex_unlock(&dev->ctrl_urb_lock); |
c4a98793 MCC |
97 | return ret; |
98 | } | |
99 | ||
100 | if (len) | |
101 | memcpy(buf, dev->urb_buf, len); | |
a6c2ba28 | 102 | |
f2a2e491 MCC |
103 | mutex_unlock(&dev->ctrl_urb_lock); |
104 | ||
6ea54d93 | 105 | if (reg_debug) { |
9e5d6760 MCC |
106 | int byte; |
107 | ||
108 | printk("<<<"); | |
6ea54d93 | 109 | for (byte = 0; byte < len; byte++) |
82ac4f87 | 110 | printk(" %02x", (unsigned char)buf[byte]); |
82ac4f87 | 111 | printk("\n"); |
a6c2ba28 | 112 | } |
113 | ||
114 | return ret; | |
115 | } | |
116 | ||
117 | /* | |
3acf2809 | 118 | * em28xx_read_reg_req() |
a6c2ba28 | 119 | * reads data from the usb device specifying bRequest |
120 | */ | |
3acf2809 | 121 | int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg) |
a6c2ba28 | 122 | { |
a6c2ba28 | 123 | int ret; |
9e5d6760 | 124 | u8 val; |
a6c2ba28 | 125 | |
9e5d6760 MCC |
126 | ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1); |
127 | if (ret < 0) | |
c4a98793 | 128 | return ret; |
a6c2ba28 | 129 | |
130 | return val; | |
131 | } | |
132 | ||
3acf2809 | 133 | int em28xx_read_reg(struct em28xx *dev, u16 reg) |
a6c2ba28 | 134 | { |
3acf2809 | 135 | return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg); |
a6c2ba28 | 136 | } |
137 | ||
138 | /* | |
3acf2809 | 139 | * em28xx_write_regs_req() |
a6c2ba28 | 140 | * sends data to the usb device, specifying bRequest |
141 | */ | |
3acf2809 | 142 | int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, |
a6c2ba28 | 143 | int len) |
144 | { | |
145 | int ret; | |
9e5d6760 | 146 | int pipe = usb_sndctrlpipe(dev->udev, 0); |
a6c2ba28 | 147 | |
9f38724a | 148 | if (dev->state & DEV_DISCONNECTED) |
c67ec53f MCC |
149 | return -ENODEV; |
150 | ||
c4a98793 | 151 | if ((len < 1) || (len > URB_MAX_CTRL_SIZE)) |
c67ec53f | 152 | return -EINVAL; |
9f38724a | 153 | |
a6c2ba28 | 154 | if (reg_debug) { |
9e5d6760 MCC |
155 | int byte; |
156 | ||
a1a6ee74 | 157 | printk(KERN_DEBUG "(pipe 0x%08x): " |
9e5d6760 MCC |
158 | "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>", |
159 | pipe, | |
160 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
161 | req, 0, 0, | |
162 | reg & 0xff, reg >> 8, | |
163 | len & 0xff, len >> 8); | |
164 | ||
165 | for (byte = 0; byte < len; byte++) | |
166 | printk(" %02x", (unsigned char)buf[byte]); | |
82ac4f87 | 167 | printk("\n"); |
a6c2ba28 | 168 | } |
169 | ||
f2a2e491 | 170 | mutex_lock(&dev->ctrl_urb_lock); |
c4a98793 | 171 | memcpy(dev->urb_buf, buf, len); |
9e5d6760 | 172 | ret = usb_control_msg(dev->udev, pipe, req, |
a6c2ba28 | 173 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, |
c4a98793 | 174 | 0x0000, reg, dev->urb_buf, len, HZ); |
f2a2e491 | 175 | mutex_unlock(&dev->ctrl_urb_lock); |
c4a98793 | 176 | |
89b329ef MCC |
177 | if (dev->wait_after_write) |
178 | msleep(dev->wait_after_write); | |
179 | ||
a6c2ba28 | 180 | return ret; |
181 | } | |
182 | ||
3acf2809 | 183 | int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len) |
a6c2ba28 | 184 | { |
c67ec53f MCC |
185 | int rc; |
186 | ||
187 | rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len); | |
188 | ||
189 | /* Stores GPO/GPIO values at the cache, if changed | |
190 | Only write values should be stored, since input on a GPIO | |
191 | register will return the input bits. | |
192 | Not sure what happens on reading GPO register. | |
193 | */ | |
194 | if (rc >= 0) { | |
6a1acc3b | 195 | if (reg == dev->reg_gpo_num) |
c67ec53f | 196 | dev->reg_gpo = buf[0]; |
6a1acc3b | 197 | else if (reg == dev->reg_gpio_num) |
c67ec53f MCC |
198 | dev->reg_gpio = buf[0]; |
199 | } | |
200 | ||
201 | return rc; | |
a6c2ba28 | 202 | } |
203 | ||
b6972489 DH |
204 | /* Write a single register */ |
205 | int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val) | |
206 | { | |
207 | return em28xx_write_regs(dev, reg, &val, 1); | |
208 | } | |
209 | ||
a6c2ba28 | 210 | /* |
3acf2809 | 211 | * em28xx_write_reg_bits() |
a6c2ba28 | 212 | * sets only some bits (specified by bitmask) of a register, by first reading |
213 | * the actual value | |
214 | */ | |
532fe652 | 215 | static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, |
a6c2ba28 | 216 | u8 bitmask) |
217 | { | |
218 | int oldval; | |
219 | u8 newval; | |
6ea54d93 | 220 | |
c67ec53f | 221 | /* Uses cache for gpo/gpio registers */ |
6a1acc3b | 222 | if (reg == dev->reg_gpo_num) |
c67ec53f | 223 | oldval = dev->reg_gpo; |
6a1acc3b | 224 | else if (reg == dev->reg_gpio_num) |
c67ec53f MCC |
225 | oldval = dev->reg_gpio; |
226 | else | |
227 | oldval = em28xx_read_reg(dev, reg); | |
6ea54d93 DSL |
228 | |
229 | if (oldval < 0) | |
a6c2ba28 | 230 | return oldval; |
6ea54d93 | 231 | |
a6c2ba28 | 232 | newval = (((u8) oldval) & ~bitmask) | (val & bitmask); |
c67ec53f | 233 | |
3acf2809 | 234 | return em28xx_write_regs(dev, reg, &newval, 1); |
a6c2ba28 | 235 | } |
236 | ||
35643943 MCC |
237 | /* |
238 | * em28xx_is_ac97_ready() | |
239 | * Checks if ac97 is ready | |
240 | */ | |
241 | static int em28xx_is_ac97_ready(struct em28xx *dev) | |
242 | { | |
243 | int ret, i; | |
244 | ||
245 | /* Wait up to 50 ms for AC97 command to complete */ | |
246 | for (i = 0; i < 10; i++, msleep(5)) { | |
247 | ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY); | |
248 | if (ret < 0) | |
249 | return ret; | |
250 | ||
251 | if (!(ret & 0x01)) | |
252 | return 0; | |
253 | } | |
254 | ||
255 | em28xx_warn("AC97 command still being executed: not handled properly!\n"); | |
256 | return -EBUSY; | |
257 | } | |
258 | ||
259 | /* | |
260 | * em28xx_read_ac97() | |
261 | * write a 16 bit value to the specified AC97 address (LSB first!) | |
262 | */ | |
531c98e7 | 263 | int em28xx_read_ac97(struct em28xx *dev, u8 reg) |
35643943 MCC |
264 | { |
265 | int ret; | |
266 | u8 addr = (reg & 0x7f) | 0x80; | |
267 | u16 val; | |
268 | ||
269 | ret = em28xx_is_ac97_ready(dev); | |
270 | if (ret < 0) | |
271 | return ret; | |
272 | ||
273 | ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1); | |
274 | if (ret < 0) | |
275 | return ret; | |
276 | ||
277 | ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB, | |
278 | (u8 *)&val, sizeof(val)); | |
279 | ||
280 | if (ret < 0) | |
281 | return ret; | |
282 | return le16_to_cpu(val); | |
283 | } | |
284 | ||
a6c2ba28 | 285 | /* |
3acf2809 | 286 | * em28xx_write_ac97() |
a6c2ba28 | 287 | * write a 16 bit value to the specified AC97 address (LSB first!) |
288 | */ | |
531c98e7 | 289 | int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val) |
a6c2ba28 | 290 | { |
35643943 | 291 | int ret; |
a6c2ba28 | 292 | u8 addr = reg & 0x7f; |
35643943 MCC |
293 | __le16 value; |
294 | ||
295 | value = cpu_to_le16(val); | |
296 | ||
297 | ret = em28xx_is_ac97_ready(dev); | |
298 | if (ret < 0) | |
299 | return ret; | |
6ea54d93 | 300 | |
35643943 | 301 | ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2); |
6ea54d93 | 302 | if (ret < 0) |
a6c2ba28 | 303 | return ret; |
6ea54d93 | 304 | |
41facaa4 | 305 | ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1); |
6ea54d93 | 306 | if (ret < 0) |
a6c2ba28 | 307 | return ret; |
00b8730f | 308 | |
35643943 MCC |
309 | return 0; |
310 | } | |
6ea54d93 | 311 | |
e879b8eb MCC |
312 | struct em28xx_vol_table { |
313 | enum em28xx_amux mux; | |
5faff789 MCC |
314 | u8 reg; |
315 | }; | |
316 | ||
e879b8eb | 317 | static struct em28xx_vol_table inputs[] = { |
5faff789 MCC |
318 | { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL }, |
319 | { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL }, | |
320 | { EM28XX_AMUX_PHONE, AC97_PHONE_VOL }, | |
321 | { EM28XX_AMUX_MIC, AC97_MIC_VOL }, | |
322 | { EM28XX_AMUX_CD, AC97_CD_VOL }, | |
323 | { EM28XX_AMUX_AUX, AC97_AUX_VOL }, | |
324 | { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL }, | |
325 | }; | |
326 | ||
327 | static int set_ac97_input(struct em28xx *dev) | |
35643943 | 328 | { |
5faff789 MCC |
329 | int ret, i; |
330 | enum em28xx_amux amux = dev->ctl_ainput; | |
35643943 | 331 | |
5faff789 MCC |
332 | /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that |
333 | em28xx should point to LINE IN, while AC97 should use VIDEO | |
334 | */ | |
335 | if (amux == EM28XX_AMUX_VIDEO2) | |
f1990a9c | 336 | amux = EM28XX_AMUX_VIDEO; |
35643943 | 337 | |
5faff789 MCC |
338 | /* Mute all entres but the one that were selected */ |
339 | for (i = 0; i < ARRAY_SIZE(inputs); i++) { | |
e879b8eb | 340 | if (amux == inputs[i].mux) |
5faff789 MCC |
341 | ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808); |
342 | else | |
343 | ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000); | |
35643943 | 344 | |
5faff789 MCC |
345 | if (ret < 0) |
346 | em28xx_warn("couldn't setup AC97 register %d\n", | |
347 | inputs[i].reg); | |
348 | } | |
349 | return 0; | |
a6c2ba28 | 350 | } |
351 | ||
00b8730f | 352 | static int em28xx_set_audio_source(struct em28xx *dev) |
539c96d0 | 353 | { |
1685a6fe | 354 | int ret; |
539c96d0 MCC |
355 | u8 input; |
356 | ||
505b6d0b | 357 | if (dev->board.is_em2800) { |
5faff789 | 358 | if (dev->ctl_ainput == EM28XX_AMUX_VIDEO) |
539c96d0 | 359 | input = EM2800_AUDIO_SRC_TUNER; |
5faff789 MCC |
360 | else |
361 | input = EM2800_AUDIO_SRC_LINE; | |
539c96d0 | 362 | |
41facaa4 | 363 | ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1); |
539c96d0 MCC |
364 | if (ret < 0) |
365 | return ret; | |
366 | } | |
367 | ||
505b6d0b | 368 | if (dev->board.has_msp34xx) |
539c96d0 MCC |
369 | input = EM28XX_AUDIO_SRC_TUNER; |
370 | else { | |
371 | switch (dev->ctl_ainput) { | |
372 | case EM28XX_AMUX_VIDEO: | |
373 | input = EM28XX_AUDIO_SRC_TUNER; | |
539c96d0 | 374 | break; |
35643943 | 375 | default: |
539c96d0 | 376 | input = EM28XX_AUDIO_SRC_LINE; |
539c96d0 MCC |
377 | break; |
378 | } | |
379 | } | |
380 | ||
41facaa4 | 381 | ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0); |
539c96d0 MCC |
382 | if (ret < 0) |
383 | return ret; | |
00b8730f | 384 | msleep(5); |
539c96d0 | 385 | |
35643943 MCC |
386 | switch (dev->audio_mode.ac97) { |
387 | case EM28XX_NO_AC97: | |
388 | break; | |
5faff789 MCC |
389 | default: |
390 | ret = set_ac97_input(dev); | |
35643943 | 391 | } |
539c96d0 | 392 | |
5faff789 | 393 | return ret; |
539c96d0 MCC |
394 | } |
395 | ||
26cdc76b | 396 | static const struct em28xx_vol_table outputs[] = { |
e879b8eb MCC |
397 | { EM28XX_AOUT_MASTER, AC97_MASTER_VOL }, |
398 | { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL }, | |
399 | { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL }, | |
400 | { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL }, | |
401 | { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL }, | |
35ae6f04 MCC |
402 | }; |
403 | ||
3acf2809 | 404 | int em28xx_audio_analog_set(struct em28xx *dev) |
a6c2ba28 | 405 | { |
35ae6f04 | 406 | int ret, i; |
a2070c66 | 407 | u8 xclk; |
539c96d0 | 408 | |
35643943 MCC |
409 | if (!dev->audio_mode.has_audio) |
410 | return 0; | |
539c96d0 | 411 | |
5faff789 MCC |
412 | /* It is assumed that all devices use master volume for output. |
413 | It would be possible to use also line output. | |
414 | */ | |
35643943 | 415 | if (dev->audio_mode.ac97 != EM28XX_NO_AC97) { |
35ae6f04 MCC |
416 | /* Mute all outputs */ |
417 | for (i = 0; i < ARRAY_SIZE(outputs); i++) { | |
e879b8eb | 418 | ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000); |
35ae6f04 MCC |
419 | if (ret < 0) |
420 | em28xx_warn("couldn't setup AC97 register %d\n", | |
e879b8eb | 421 | outputs[i].reg); |
35ae6f04 | 422 | } |
35643943 | 423 | } |
539c96d0 | 424 | |
505b6d0b | 425 | xclk = dev->board.xclk & 0x7f; |
3abee53e | 426 | if (!dev->mute) |
8ed06fd4 | 427 | xclk |= EM28XX_XCLK_AUDIO_UNMUTE; |
3abee53e | 428 | |
a2070c66 | 429 | ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk); |
539c96d0 MCC |
430 | if (ret < 0) |
431 | return ret; | |
3abee53e | 432 | msleep(10); |
539c96d0 MCC |
433 | |
434 | /* Selects the proper audio input */ | |
435 | ret = em28xx_set_audio_source(dev); | |
a6c2ba28 | 436 | |
35643943 MCC |
437 | /* Sets volume */ |
438 | if (dev->audio_mode.ac97 != EM28XX_NO_AC97) { | |
439 | int vol; | |
440 | ||
7e4b15e4 RK |
441 | em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200); |
442 | em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031); | |
443 | em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80); | |
444 | ||
35643943 MCC |
445 | /* LSB: left channel - both channels with the same level */ |
446 | vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8); | |
447 | ||
448 | /* Mute device, if needed */ | |
449 | if (dev->mute) | |
450 | vol |= 0x8000; | |
451 | ||
452 | /* Sets volume */ | |
e879b8eb MCC |
453 | for (i = 0; i < ARRAY_SIZE(outputs); i++) { |
454 | if (dev->ctl_aoutput & outputs[i].mux) | |
455 | ret = em28xx_write_ac97(dev, outputs[i].reg, | |
456 | vol); | |
457 | if (ret < 0) | |
458 | em28xx_warn("couldn't setup AC97 register %d\n", | |
459 | outputs[i].reg); | |
460 | } | |
8866f9cf MCC |
461 | |
462 | if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) { | |
463 | int sel = ac97_return_record_select(dev->ctl_aoutput); | |
464 | ||
a1a6ee74 NS |
465 | /* Use the same input for both left and right |
466 | channels */ | |
8866f9cf MCC |
467 | sel |= (sel << 8); |
468 | ||
469 | em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel); | |
470 | } | |
35643943 | 471 | } |
00b8730f | 472 | |
539c96d0 MCC |
473 | return ret; |
474 | } | |
475 | EXPORT_SYMBOL_GPL(em28xx_audio_analog_set); | |
a6c2ba28 | 476 | |
35643943 MCC |
477 | int em28xx_audio_setup(struct em28xx *dev) |
478 | { | |
479 | int vid1, vid2, feat, cfg; | |
16c7bcad | 480 | u32 vid; |
35643943 | 481 | |
62f3e69b | 482 | if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) { |
35643943 MCC |
483 | /* Digital only device - don't load any alsa module */ |
484 | dev->audio_mode.has_audio = 0; | |
485 | dev->has_audio_class = 0; | |
486 | dev->has_alsa_audio = 0; | |
487 | return 0; | |
488 | } | |
489 | ||
490 | /* If device doesn't support Usb Audio Class, use vendor class */ | |
491 | if (!dev->has_audio_class) | |
492 | dev->has_alsa_audio = 1; | |
493 | ||
494 | dev->audio_mode.has_audio = 1; | |
495 | ||
496 | /* See how this device is configured */ | |
497 | cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG); | |
498 | if (cfg < 0) | |
499 | cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */ | |
500 | else | |
501 | em28xx_info("Config register raw data: 0x%02x\n", cfg); | |
502 | ||
503 | if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == | |
504 | EM28XX_CHIPCFG_I2S_3_SAMPRATES) { | |
505 | em28xx_info("I2S Audio (3 sample rates)\n"); | |
506 | dev->audio_mode.i2s_3rates = 1; | |
507 | } | |
508 | if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == | |
509 | EM28XX_CHIPCFG_I2S_5_SAMPRATES) { | |
510 | em28xx_info("I2S Audio (5 sample rates)\n"); | |
511 | dev->audio_mode.i2s_5rates = 1; | |
512 | } | |
513 | ||
de84830e DH |
514 | if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) { |
515 | /* Skip the code that does AC97 vendor detection */ | |
35643943 MCC |
516 | dev->audio_mode.ac97 = EM28XX_NO_AC97; |
517 | goto init_audio; | |
518 | } | |
519 | ||
520 | dev->audio_mode.ac97 = EM28XX_AC97_OTHER; | |
521 | ||
522 | vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1); | |
523 | if (vid1 < 0) { | |
524 | /* Device likely doesn't support AC97 */ | |
525 | em28xx_warn("AC97 chip type couldn't be determined\n"); | |
526 | goto init_audio; | |
527 | } | |
528 | ||
529 | vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2); | |
530 | if (vid2 < 0) | |
531 | goto init_audio; | |
532 | ||
16c7bcad MCC |
533 | vid = vid1 << 16 | vid2; |
534 | ||
535 | dev->audio_mode.ac97_vendor_id = vid; | |
536 | em28xx_warn("AC97 vendor ID = 0x%08x\n", vid); | |
35643943 MCC |
537 | |
538 | feat = em28xx_read_ac97(dev, AC97_RESET); | |
539 | if (feat < 0) | |
540 | goto init_audio; | |
541 | ||
542 | dev->audio_mode.ac97_feat = feat; | |
543 | em28xx_warn("AC97 features = 0x%04x\n", feat); | |
544 | ||
16c7bcad MCC |
545 | /* Try to identify what audio processor we have */ |
546 | if ((vid == 0xffffffff) && (feat == 0x6a90)) | |
35643943 | 547 | dev->audio_mode.ac97 = EM28XX_AC97_EM202; |
209acc02 MCC |
548 | else if ((vid >> 8) == 0x838476) |
549 | dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL; | |
35643943 MCC |
550 | |
551 | init_audio: | |
552 | /* Reports detected AC97 processor */ | |
553 | switch (dev->audio_mode.ac97) { | |
554 | case EM28XX_NO_AC97: | |
555 | em28xx_info("No AC97 audio processor\n"); | |
556 | break; | |
557 | case EM28XX_AC97_EM202: | |
558 | em28xx_info("Empia 202 AC97 audio processor detected\n"); | |
559 | break; | |
209acc02 MCC |
560 | case EM28XX_AC97_SIGMATEL: |
561 | em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n", | |
562 | dev->audio_mode.ac97_vendor_id & 0xff); | |
563 | break; | |
35643943 MCC |
564 | case EM28XX_AC97_OTHER: |
565 | em28xx_warn("Unknown AC97 audio processor detected!\n"); | |
566 | break; | |
567 | default: | |
568 | break; | |
569 | } | |
570 | ||
571 | return em28xx_audio_analog_set(dev); | |
572 | } | |
573 | EXPORT_SYMBOL_GPL(em28xx_audio_setup); | |
574 | ||
3acf2809 | 575 | int em28xx_colorlevels_set_default(struct em28xx *dev) |
a6c2ba28 | 576 | { |
2a29a0d7 MCC |
577 | em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */ |
578 | em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */ | |
579 | em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */ | |
580 | em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00); | |
581 | em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00); | |
582 | em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00); | |
583 | ||
584 | em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20); | |
585 | em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20); | |
586 | em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20); | |
587 | em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20); | |
588 | em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00); | |
589 | em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00); | |
590 | return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00); | |
a6c2ba28 | 591 | } |
592 | ||
3acf2809 | 593 | int em28xx_capture_start(struct em28xx *dev, int start) |
a6c2ba28 | 594 | { |
ee6e3a86 | 595 | int rc; |
ebef13d4 DH |
596 | |
597 | if (dev->chip_id == CHIP_ID_EM2874) { | |
598 | /* The Transport Stream Enable Register moved in em2874 */ | |
599 | if (!start) { | |
600 | rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE, | |
601 | 0x00, | |
602 | EM2874_TS1_CAPTURE_ENABLE); | |
603 | return rc; | |
604 | } | |
605 | ||
606 | /* Enable Transport Stream */ | |
607 | rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE, | |
608 | EM2874_TS1_CAPTURE_ENABLE, | |
609 | EM2874_TS1_CAPTURE_ENABLE); | |
610 | return rc; | |
611 | } | |
612 | ||
613 | ||
a6c2ba28 | 614 | /* FIXME: which is the best order? */ |
615 | /* video registers are sampled by VREF */ | |
41facaa4 | 616 | rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP, |
ee6e3a86 MCC |
617 | start ? 0x10 : 0x00, 0x10); |
618 | if (rc < 0) | |
619 | return rc; | |
620 | ||
621 | if (!start) { | |
622 | /* disable video capture */ | |
2a29a0d7 | 623 | rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27); |
102a0b08 | 624 | return rc; |
ee6e3a86 MCC |
625 | } |
626 | ||
a6c2ba28 | 627 | /* enable video capture */ |
2a29a0d7 | 628 | rc = em28xx_write_reg(dev, 0x48, 0x00); |
102a0b08 | 629 | |
ee6e3a86 | 630 | if (dev->mode == EM28XX_ANALOG_MODE) |
2a29a0d7 | 631 | rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67); |
ee6e3a86 | 632 | else |
2a29a0d7 | 633 | rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37); |
ee6e3a86 | 634 | |
6ea54d93 | 635 | msleep(6); |
ee6e3a86 MCC |
636 | |
637 | return rc; | |
a6c2ba28 | 638 | } |
639 | ||
bddcf633 | 640 | int em28xx_set_outfmt(struct em28xx *dev) |
a6c2ba28 | 641 | { |
bddcf633 MCC |
642 | int ret; |
643 | ||
644 | ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT, | |
645 | dev->format->reg | 0x20, 0x3f); | |
646 | if (ret < 0) | |
647 | return ret; | |
648 | ||
649 | ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, 0x10); | |
650 | if (ret < 0) | |
651 | return ret; | |
652 | ||
2a29a0d7 | 653 | return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, 0x11); |
a6c2ba28 | 654 | } |
655 | ||
adcb0fa2 AB |
656 | static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax, |
657 | u8 ymin, u8 ymax) | |
a6c2ba28 | 658 | { |
6ea54d93 DSL |
659 | em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n", |
660 | xmin, ymin, xmax, ymax); | |
a6c2ba28 | 661 | |
41facaa4 MCC |
662 | em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1); |
663 | em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1); | |
664 | em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1); | |
665 | return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1); | |
a6c2ba28 | 666 | } |
667 | ||
adcb0fa2 | 668 | static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart, |
a6c2ba28 | 669 | u16 width, u16 height) |
670 | { | |
671 | u8 cwidth = width; | |
672 | u8 cheight = height; | |
673 | u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01); | |
674 | ||
6ea54d93 DSL |
675 | em28xx_coredbg("em28xx Area Set: (%d,%d)\n", |
676 | (width | (overflow & 2) << 7), | |
a6c2ba28 | 677 | (height | (overflow & 1) << 8)); |
678 | ||
41facaa4 MCC |
679 | em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1); |
680 | em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1); | |
681 | em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1); | |
682 | em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1); | |
683 | return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1); | |
a6c2ba28 | 684 | } |
685 | ||
adcb0fa2 | 686 | static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v) |
a6c2ba28 | 687 | { |
52c02fcd SS |
688 | u8 mode; |
689 | /* the em2800 scaler only supports scaling down to 50% */ | |
505b6d0b | 690 | if (dev->board.is_em2800) |
52c02fcd SS |
691 | mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00); |
692 | else { | |
693 | u8 buf[2]; | |
694 | buf[0] = h; | |
695 | buf[1] = h >> 8; | |
41facaa4 | 696 | em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2); |
52c02fcd SS |
697 | buf[0] = v; |
698 | buf[1] = v >> 8; | |
41facaa4 | 699 | em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2); |
6ea54d93 DSL |
700 | /* it seems that both H and V scalers must be active |
701 | to work correctly */ | |
a1a6ee74 | 702 | mode = (h || v) ? 0x30 : 0x00; |
74458e6c | 703 | } |
41facaa4 | 704 | return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30); |
a6c2ba28 | 705 | } |
706 | ||
707 | /* FIXME: this only function read values from dev */ | |
3acf2809 | 708 | int em28xx_resolution_set(struct em28xx *dev) |
a6c2ba28 | 709 | { |
710 | int width, height; | |
711 | width = norm_maxw(dev); | |
712 | height = norm_maxh(dev) >> 1; | |
713 | ||
bddcf633 | 714 | em28xx_set_outfmt(dev); |
3acf2809 MCC |
715 | em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2); |
716 | em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2); | |
717 | return em28xx_scaler_set(dev, dev->hscale, dev->vscale); | |
a6c2ba28 | 718 | } |
719 | ||
3acf2809 | 720 | int em28xx_set_alternate(struct em28xx *dev) |
a6c2ba28 | 721 | { |
722 | int errCode, prev_alt = dev->alt; | |
3687e1e6 | 723 | int i; |
44dc733c | 724 | unsigned int min_pkt_size = dev->width * 2 + 4; |
3687e1e6 | 725 | |
2c4a07b2 | 726 | /* When image size is bigger than a certain value, |
3687e1e6 MCC |
727 | the frame size should be increased, otherwise, only |
728 | green screen will be received. | |
729 | */ | |
44dc733c | 730 | if (dev->width * 2 * dev->height > 720 * 240 * 2) |
3687e1e6 MCC |
731 | min_pkt_size *= 2; |
732 | ||
2c4a07b2 SS |
733 | for (i = 0; i < dev->num_alt; i++) { |
734 | /* stop when the selected alt setting offers enough bandwidth */ | |
735 | if (dev->alt_max_pkt_size[i] >= min_pkt_size) { | |
736 | dev->alt = i; | |
3687e1e6 | 737 | break; |
2c4a07b2 SS |
738 | /* otherwise make sure that we end up with the maximum bandwidth |
739 | because the min_pkt_size equation might be wrong... | |
740 | */ | |
741 | } else if (dev->alt_max_pkt_size[i] > | |
742 | dev->alt_max_pkt_size[dev->alt]) | |
743 | dev->alt = i; | |
744 | } | |
a6c2ba28 | 745 | |
746 | if (dev->alt != prev_alt) { | |
3687e1e6 MCC |
747 | em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n", |
748 | min_pkt_size, dev->alt); | |
a6c2ba28 | 749 | dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt]; |
3687e1e6 MCC |
750 | em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n", |
751 | dev->alt, dev->max_pkt_size); | |
a6c2ba28 | 752 | errCode = usb_set_interface(dev->udev, 0, dev->alt); |
753 | if (errCode < 0) { | |
6ea54d93 | 754 | em28xx_errdev("cannot change alternate number to %d (error=%i)\n", |
3687e1e6 | 755 | dev->alt, errCode); |
a6c2ba28 | 756 | return errCode; |
757 | } | |
758 | } | |
759 | return 0; | |
760 | } | |
579f72e4 | 761 | |
c67ec53f MCC |
762 | int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio) |
763 | { | |
764 | int rc = 0; | |
765 | ||
766 | if (!gpio) | |
767 | return rc; | |
768 | ||
2fe3e2ee MCC |
769 | if (dev->mode != EM28XX_SUSPEND) { |
770 | em28xx_write_reg(dev, 0x48, 0x00); | |
771 | if (dev->mode == EM28XX_ANALOG_MODE) | |
772 | em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67); | |
773 | else | |
774 | em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37); | |
775 | msleep(6); | |
776 | } | |
c67ec53f MCC |
777 | |
778 | /* Send GPIO reset sequences specified at board entry */ | |
779 | while (gpio->sleep >= 0) { | |
780 | if (gpio->reg >= 0) { | |
781 | rc = em28xx_write_reg_bits(dev, | |
782 | gpio->reg, | |
783 | gpio->val, | |
784 | gpio->mask); | |
785 | if (rc < 0) | |
786 | return rc; | |
787 | } | |
788 | if (gpio->sleep > 0) | |
789 | msleep(gpio->sleep); | |
790 | ||
791 | gpio++; | |
792 | } | |
793 | return rc; | |
794 | } | |
795 | ||
796 | int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode) | |
797 | { | |
798 | if (dev->mode == set_mode) | |
799 | return 0; | |
800 | ||
2fe3e2ee | 801 | if (set_mode == EM28XX_SUSPEND) { |
c67ec53f | 802 | dev->mode = set_mode; |
2fe3e2ee MCC |
803 | |
804 | /* FIXME: add suspend support for ac97 */ | |
805 | ||
806 | return em28xx_gpio_set(dev, dev->board.suspend_gpio); | |
c67ec53f MCC |
807 | } |
808 | ||
809 | dev->mode = set_mode; | |
810 | ||
811 | if (dev->mode == EM28XX_DIGITAL_MODE) | |
f502e861 | 812 | return em28xx_gpio_set(dev, dev->board.dvb_gpio); |
c67ec53f | 813 | else |
f502e861 | 814 | return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio); |
c67ec53f MCC |
815 | } |
816 | EXPORT_SYMBOL_GPL(em28xx_set_mode); | |
817 | ||
579f72e4 AT |
818 | /* ------------------------------------------------------------------ |
819 | URB control | |
820 | ------------------------------------------------------------------*/ | |
821 | ||
822 | /* | |
823 | * IRQ callback, called by URB callback | |
824 | */ | |
825 | static void em28xx_irq_callback(struct urb *urb) | |
826 | { | |
827 | struct em28xx_dmaqueue *dma_q = urb->context; | |
828 | struct em28xx *dev = container_of(dma_q, struct em28xx, vidq); | |
829 | int rc, i; | |
830 | ||
aa5a1821 RK |
831 | switch (urb->status) { |
832 | case 0: /* success */ | |
833 | case -ETIMEDOUT: /* NAK */ | |
834 | break; | |
835 | case -ECONNRESET: /* kill */ | |
836 | case -ENOENT: | |
837 | case -ESHUTDOWN: | |
838 | return; | |
839 | default: /* error */ | |
840 | em28xx_isocdbg("urb completition error %d.\n", urb->status); | |
841 | break; | |
842 | } | |
843 | ||
579f72e4 AT |
844 | /* Copy data from URB */ |
845 | spin_lock(&dev->slock); | |
846 | rc = dev->isoc_ctl.isoc_copy(dev, urb); | |
847 | spin_unlock(&dev->slock); | |
848 | ||
849 | /* Reset urb buffers */ | |
850 | for (i = 0; i < urb->number_of_packets; i++) { | |
851 | urb->iso_frame_desc[i].status = 0; | |
852 | urb->iso_frame_desc[i].actual_length = 0; | |
853 | } | |
854 | urb->status = 0; | |
855 | ||
856 | urb->status = usb_submit_urb(urb, GFP_ATOMIC); | |
857 | if (urb->status) { | |
4269a8ee DH |
858 | em28xx_isocdbg("urb resubmit failed (error=%i)\n", |
859 | urb->status); | |
579f72e4 AT |
860 | } |
861 | } | |
862 | ||
863 | /* | |
864 | * Stop and Deallocate URBs | |
865 | */ | |
866 | void em28xx_uninit_isoc(struct em28xx *dev) | |
867 | { | |
868 | struct urb *urb; | |
869 | int i; | |
870 | ||
871 | em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n"); | |
872 | ||
873 | dev->isoc_ctl.nfields = -1; | |
874 | for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { | |
875 | urb = dev->isoc_ctl.urb[i]; | |
876 | if (urb) { | |
9c06210b RK |
877 | if (!irqs_disabled()) |
878 | usb_kill_urb(urb); | |
879 | else | |
880 | usb_unlink_urb(urb); | |
881 | ||
579f72e4 AT |
882 | if (dev->isoc_ctl.transfer_buffer[i]) { |
883 | usb_buffer_free(dev->udev, | |
6ea54d93 DSL |
884 | urb->transfer_buffer_length, |
885 | dev->isoc_ctl.transfer_buffer[i], | |
886 | urb->transfer_dma); | |
579f72e4 AT |
887 | } |
888 | usb_free_urb(urb); | |
889 | dev->isoc_ctl.urb[i] = NULL; | |
890 | } | |
891 | dev->isoc_ctl.transfer_buffer[i] = NULL; | |
892 | } | |
893 | ||
894 | kfree(dev->isoc_ctl.urb); | |
895 | kfree(dev->isoc_ctl.transfer_buffer); | |
896 | ||
897 | dev->isoc_ctl.urb = NULL; | |
898 | dev->isoc_ctl.transfer_buffer = NULL; | |
899 | dev->isoc_ctl.num_bufs = 0; | |
900 | ||
901 | em28xx_capture_start(dev, 0); | |
902 | } | |
903 | EXPORT_SYMBOL_GPL(em28xx_uninit_isoc); | |
904 | ||
905 | /* | |
906 | * Allocate URBs and start IRQ | |
907 | */ | |
908 | int em28xx_init_isoc(struct em28xx *dev, int max_packets, | |
909 | int num_bufs, int max_pkt_size, | |
c67ec53f | 910 | int (*isoc_copy) (struct em28xx *dev, struct urb *urb)) |
579f72e4 AT |
911 | { |
912 | struct em28xx_dmaqueue *dma_q = &dev->vidq; | |
913 | int i; | |
914 | int sb_size, pipe; | |
915 | struct urb *urb; | |
916 | int j, k; | |
917 | int rc; | |
918 | ||
919 | em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n"); | |
920 | ||
921 | /* De-allocates all pending stuff */ | |
922 | em28xx_uninit_isoc(dev); | |
923 | ||
924 | dev->isoc_ctl.isoc_copy = isoc_copy; | |
925 | dev->isoc_ctl.num_bufs = num_bufs; | |
926 | ||
927 | dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL); | |
928 | if (!dev->isoc_ctl.urb) { | |
929 | em28xx_errdev("cannot alloc memory for usb buffers\n"); | |
930 | return -ENOMEM; | |
931 | } | |
932 | ||
933 | dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs, | |
934 | GFP_KERNEL); | |
094f9b4b | 935 | if (!dev->isoc_ctl.transfer_buffer) { |
579f72e4 AT |
936 | em28xx_errdev("cannot allocate memory for usbtransfer\n"); |
937 | kfree(dev->isoc_ctl.urb); | |
938 | return -ENOMEM; | |
939 | } | |
940 | ||
941 | dev->isoc_ctl.max_pkt_size = max_pkt_size; | |
942 | dev->isoc_ctl.buf = NULL; | |
943 | ||
944 | sb_size = max_packets * dev->isoc_ctl.max_pkt_size; | |
945 | ||
946 | /* allocate urbs and transfer buffers */ | |
947 | for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { | |
948 | urb = usb_alloc_urb(max_packets, GFP_KERNEL); | |
949 | if (!urb) { | |
950 | em28xx_err("cannot alloc isoc_ctl.urb %i\n", i); | |
951 | em28xx_uninit_isoc(dev); | |
952 | return -ENOMEM; | |
953 | } | |
954 | dev->isoc_ctl.urb[i] = urb; | |
955 | ||
956 | dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev, | |
957 | sb_size, GFP_KERNEL, &urb->transfer_dma); | |
958 | if (!dev->isoc_ctl.transfer_buffer[i]) { | |
959 | em28xx_err("unable to allocate %i bytes for transfer" | |
960 | " buffer %i%s\n", | |
961 | sb_size, i, | |
a1a6ee74 | 962 | in_interrupt() ? " while in int" : ""); |
579f72e4 AT |
963 | em28xx_uninit_isoc(dev); |
964 | return -ENOMEM; | |
965 | } | |
966 | memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size); | |
967 | ||
968 | /* FIXME: this is a hack - should be | |
969 | 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK' | |
970 | should also be using 'desc.bInterval' | |
971 | */ | |
6ea54d93 | 972 | pipe = usb_rcvisocpipe(dev->udev, |
c67ec53f | 973 | dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84); |
6ea54d93 | 974 | |
579f72e4 AT |
975 | usb_fill_int_urb(urb, dev->udev, pipe, |
976 | dev->isoc_ctl.transfer_buffer[i], sb_size, | |
977 | em28xx_irq_callback, dma_q, 1); | |
978 | ||
979 | urb->number_of_packets = max_packets; | |
980 | urb->transfer_flags = URB_ISO_ASAP; | |
981 | ||
982 | k = 0; | |
983 | for (j = 0; j < max_packets; j++) { | |
984 | urb->iso_frame_desc[j].offset = k; | |
985 | urb->iso_frame_desc[j].length = | |
986 | dev->isoc_ctl.max_pkt_size; | |
987 | k += dev->isoc_ctl.max_pkt_size; | |
988 | } | |
989 | } | |
990 | ||
991 | init_waitqueue_head(&dma_q->wq); | |
992 | ||
c67ec53f | 993 | em28xx_capture_start(dev, 1); |
579f72e4 AT |
994 | |
995 | /* submit urbs and enables IRQ */ | |
996 | for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { | |
997 | rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC); | |
998 | if (rc) { | |
999 | em28xx_err("submit of urb %i failed (error=%i)\n", i, | |
1000 | rc); | |
1001 | em28xx_uninit_isoc(dev); | |
1002 | return rc; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | EXPORT_SYMBOL_GPL(em28xx_init_isoc); | |
1a23f81b MCC |
1009 | |
1010 | /* | |
1011 | * em28xx_wake_i2c() | |
1012 | * configure i2c attached devices | |
1013 | */ | |
1014 | void em28xx_wake_i2c(struct em28xx *dev) | |
1015 | { | |
1016 | struct v4l2_routing route; | |
1017 | int zero = 0; | |
1018 | ||
1019 | route.input = INPUT(dev->ctl_input)->vmux; | |
1020 | route.output = 0; | |
1021 | em28xx_i2c_call_clients(dev, VIDIOC_INT_RESET, &zero); | |
1022 | em28xx_i2c_call_clients(dev, VIDIOC_INT_S_VIDEO_ROUTING, &route); | |
1023 | em28xx_i2c_call_clients(dev, VIDIOC_STREAMON, NULL); | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * Device control list | |
1028 | */ | |
1029 | ||
1030 | static LIST_HEAD(em28xx_devlist); | |
1031 | static DEFINE_MUTEX(em28xx_devlist_mutex); | |
1032 | ||
bec43661 | 1033 | struct em28xx *em28xx_get_device(int minor, |
1a23f81b MCC |
1034 | enum v4l2_buf_type *fh_type, |
1035 | int *has_radio) | |
1036 | { | |
1037 | struct em28xx *h, *dev = NULL; | |
1a23f81b MCC |
1038 | |
1039 | *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
1040 | *has_radio = 0; | |
1041 | ||
1042 | mutex_lock(&em28xx_devlist_mutex); | |
1043 | list_for_each_entry(h, &em28xx_devlist, devlist) { | |
1044 | if (h->vdev->minor == minor) | |
1045 | dev = h; | |
1046 | if (h->vbi_dev->minor == minor) { | |
1047 | dev = h; | |
1048 | *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE; | |
1049 | } | |
1050 | if (h->radio_dev && | |
1051 | h->radio_dev->minor == minor) { | |
1052 | dev = h; | |
1053 | *has_radio = 1; | |
1054 | } | |
1055 | } | |
1056 | mutex_unlock(&em28xx_devlist_mutex); | |
1057 | ||
1058 | return dev; | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * em28xx_realease_resources() | |
1063 | * unregisters the v4l2,i2c and usb devices | |
1064 | * called when the device gets disconected or at module unload | |
1065 | */ | |
1066 | void em28xx_remove_from_devlist(struct em28xx *dev) | |
1067 | { | |
1068 | mutex_lock(&em28xx_devlist_mutex); | |
1069 | list_del(&dev->devlist); | |
1070 | mutex_unlock(&em28xx_devlist_mutex); | |
1071 | }; | |
1072 | ||
1073 | void em28xx_add_into_devlist(struct em28xx *dev) | |
1074 | { | |
1075 | mutex_lock(&em28xx_devlist_mutex); | |
1076 | list_add_tail(&dev->devlist, &em28xx_devlist); | |
1077 | mutex_unlock(&em28xx_devlist_mutex); | |
1078 | }; | |
1079 | ||
1080 | /* | |
1081 | * Extension interface | |
1082 | */ | |
1083 | ||
1084 | static LIST_HEAD(em28xx_extension_devlist); | |
1085 | static DEFINE_MUTEX(em28xx_extension_devlist_lock); | |
1086 | ||
1087 | int em28xx_register_extension(struct em28xx_ops *ops) | |
1088 | { | |
1089 | struct em28xx *dev = NULL; | |
1090 | ||
1091 | mutex_lock(&em28xx_devlist_mutex); | |
1092 | mutex_lock(&em28xx_extension_devlist_lock); | |
1093 | list_add_tail(&ops->next, &em28xx_extension_devlist); | |
1094 | list_for_each_entry(dev, &em28xx_devlist, devlist) { | |
1095 | if (dev) | |
1096 | ops->init(dev); | |
1097 | } | |
1098 | printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name); | |
1099 | mutex_unlock(&em28xx_extension_devlist_lock); | |
1100 | mutex_unlock(&em28xx_devlist_mutex); | |
1101 | return 0; | |
1102 | } | |
1103 | EXPORT_SYMBOL(em28xx_register_extension); | |
1104 | ||
1105 | void em28xx_unregister_extension(struct em28xx_ops *ops) | |
1106 | { | |
1107 | struct em28xx *dev = NULL; | |
1108 | ||
1109 | mutex_lock(&em28xx_devlist_mutex); | |
1110 | list_for_each_entry(dev, &em28xx_devlist, devlist) { | |
1111 | if (dev) | |
1112 | ops->fini(dev); | |
1113 | } | |
1114 | ||
1115 | mutex_lock(&em28xx_extension_devlist_lock); | |
1116 | printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name); | |
1117 | list_del(&ops->next); | |
1118 | mutex_unlock(&em28xx_extension_devlist_lock); | |
1119 | mutex_unlock(&em28xx_devlist_mutex); | |
1120 | } | |
1121 | EXPORT_SYMBOL(em28xx_unregister_extension); | |
1122 | ||
1123 | void em28xx_init_extension(struct em28xx *dev) | |
1124 | { | |
1125 | struct em28xx_ops *ops = NULL; | |
1126 | ||
1127 | mutex_lock(&em28xx_extension_devlist_lock); | |
1128 | if (!list_empty(&em28xx_extension_devlist)) { | |
1129 | list_for_each_entry(ops, &em28xx_extension_devlist, next) { | |
1130 | if (ops->init) | |
1131 | ops->init(dev); | |
1132 | } | |
1133 | } | |
1134 | mutex_unlock(&em28xx_extension_devlist_lock); | |
1135 | } | |
1136 | ||
1137 | void em28xx_close_extension(struct em28xx *dev) | |
1138 | { | |
1139 | struct em28xx_ops *ops = NULL; | |
1140 | ||
1141 | mutex_lock(&em28xx_extension_devlist_lock); | |
1142 | if (!list_empty(&em28xx_extension_devlist)) { | |
1143 | list_for_each_entry(ops, &em28xx_extension_devlist, next) { | |
1144 | if (ops->fini) | |
1145 | ops->fini(dev); | |
1146 | } | |
1147 | } | |
1148 | mutex_unlock(&em28xx_extension_devlist_lock); | |
1149 | } |