[media] em28xx: disable LNA - PCTV QuatroStick nano (520e)
[deliverable/linux.git] / drivers / media / video / em28xx / em28xx-dvb.c
CommitLineData
3aefb79a
MCC
1/*
2 DVB device driver for em28xx
3
fec528b7 4 (c) 2008-2011 Mauro Carvalho Chehab <mchehab@infradead.org>
3aefb79a 5
bdfbf952
DH
6 (c) 2008 Devin Heitmueller <devin.heitmueller@gmail.com>
7 - Fixes for the driver to properly work with HVR-950
4fd305b2 8 - Fixes for the driver to properly work with Pinnacle PCTV HD Pro Stick
e14b3658 9 - Fixes for the driver to properly work with AMD ATI TV Wonder HD 600
bdfbf952 10
3421b778
AT
11 (c) 2008 Aidan Thornton <makosoft@googlemail.com>
12
13 Based on cx88-dvb, saa7134-dvb and videobuf-dvb originally written by:
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MCC
14 (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
15 (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License.
20 */
21
22#include <linux/kernel.h>
5a0e3ad6 23#include <linux/slab.h>
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MCC
24#include <linux/usb.h>
25
26#include "em28xx.h"
27#include <media/v4l2-common.h>
28#include <media/videobuf-vmalloc.h>
d7de5d8f
FM
29#include <media/tuner.h>
30#include "tuner-simple.h"
3aefb79a
MCC
31
32#include "lgdt330x.h"
7e48b30a 33#include "lgdt3305.h"
7e6388a1 34#include "zl10353.h"
6e7b9ea0 35#include "s5h1409.h"
4fb202a8
DH
36#include "mt352.h"
37#include "mt352_priv.h" /* FIXME */
285eb1a4 38#include "tda1002x.h"
7e48b30a 39#include "tda18271.h"
ca3dfd6a 40#include "s921.h"
75e2b869 41#include "drxd.h"
d6a5f921 42#include "cxd2820r.h"
fec528b7
MCC
43#include "tda18271c2dd.h"
44#include "drxk.h"
36588715
AP
45#include "tda10071.h"
46#include "a8293.h"
1985f6fb 47#include "qt1010.h"
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MCC
48
49MODULE_DESCRIPTION("driver for em28xx based DVB cards");
50MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@infradead.org>");
51MODULE_LICENSE("GPL");
52
53static unsigned int debug;
54module_param(debug, int, 0644);
55MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
56
57DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
58
59#define dprintk(level, fmt, arg...) do { \
60if (debug >= level) \
3421b778 61 printk(KERN_DEBUG "%s/2-dvb: " fmt, dev->name, ## arg); \
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MCC
62} while (0)
63
3421b778 64struct em28xx_dvb {
f71095be 65 struct dvb_frontend *fe[2];
3421b778
AT
66
67 /* feed count management */
68 struct mutex lock;
69 int nfeeds;
70
71 /* general boilerplate stuff */
72 struct dvb_adapter adapter;
73 struct dvb_demux demux;
74 struct dmxdev dmxdev;
75 struct dmx_frontend fe_hw;
76 struct dmx_frontend fe_mem;
77 struct dvb_net net;
fec528b7 78
c4c3a3d3 79 /* Due to DRX-K - probably need changes */
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MCC
80 int (*gate_ctrl)(struct dvb_frontend *, int);
81 struct semaphore pll_mutex;
c4c3a3d3 82 bool dont_attach_fe1;
3421b778
AT
83};
84
85
86static inline void print_err_status(struct em28xx *dev,
87 int packet, int status)
3aefb79a 88{
3421b778 89 char *errmsg = "Unknown";
3aefb79a 90
3421b778
AT
91 switch (status) {
92 case -ENOENT:
93 errmsg = "unlinked synchronuously";
94 break;
95 case -ECONNRESET:
96 errmsg = "unlinked asynchronuously";
97 break;
98 case -ENOSR:
99 errmsg = "Buffer error (overrun)";
100 break;
101 case -EPIPE:
102 errmsg = "Stalled (device not responding)";
103 break;
104 case -EOVERFLOW:
105 errmsg = "Babble (bad cable?)";
106 break;
107 case -EPROTO:
108 errmsg = "Bit-stuff error (bad cable?)";
109 break;
110 case -EILSEQ:
111 errmsg = "CRC/Timeout (could be anything)";
112 break;
113 case -ETIME:
114 errmsg = "Device does not respond";
115 break;
116 }
117 if (packet < 0) {
118 dprintk(1, "URB status %d [%s].\n", status, errmsg);
119 } else {
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DSL
120 dprintk(1, "URB packet %d, status %d [%s].\n",
121 packet, status, errmsg);
3421b778
AT
122 }
123}
3aefb79a 124
f2d0c1c6 125static inline int em28xx_dvb_isoc_copy(struct em28xx *dev, struct urb *urb)
3421b778
AT
126{
127 int i;
3aefb79a 128
3421b778
AT
129 if (!dev)
130 return 0;
3aefb79a 131
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AT
132 if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED))
133 return 0;
134
135 if (urb->status < 0) {
136 print_err_status(dev, -1, urb->status);
137 if (urb->status == -ENOENT)
138 return 0;
139 }
140
141 for (i = 0; i < urb->number_of_packets; i++) {
142 int status = urb->iso_frame_desc[i].status;
143
144 if (status < 0) {
145 print_err_status(dev, i, status);
146 if (urb->iso_frame_desc[i].status != -EPROTO)
147 continue;
148 }
149
150 dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer +
151 urb->iso_frame_desc[i].offset,
152 urb->iso_frame_desc[i].actual_length);
153 }
154
155 return 0;
156}
157
f2d0c1c6 158static int em28xx_start_streaming(struct em28xx_dvb *dvb)
6ea54d93 159{
c67ec53f 160 int rc;
3421b778 161 struct em28xx *dev = dvb->adapter.priv;
d18e2fda 162 int max_dvb_packet_size;
3421b778 163
8ab33626 164 usb_set_interface(dev->udev, 0, dev->dvb_alt);
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MCC
165 rc = em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
166 if (rc < 0)
167 return rc;
3421b778 168
8ab33626 169 max_dvb_packet_size = dev->dvb_max_pkt_size;
f7acc4bb
MCC
170 if (max_dvb_packet_size < 0)
171 return max_dvb_packet_size;
86d38d1e 172 dprintk(1, "Using %d buffers each with %d x %d bytes\n",
f7acc4bb 173 EM28XX_DVB_NUM_BUFS,
86d38d1e 174 EM28XX_DVB_MAX_PACKETS,
f7acc4bb 175 max_dvb_packet_size);
d18e2fda 176
86d38d1e
GG
177 return em28xx_init_isoc(dev, EM28XX_DIGITAL_MODE,
178 EM28XX_DVB_MAX_PACKETS, EM28XX_DVB_NUM_BUFS,
179 max_dvb_packet_size, em28xx_dvb_isoc_copy);
3421b778
AT
180}
181
f2d0c1c6 182static int em28xx_stop_streaming(struct em28xx_dvb *dvb)
6ea54d93 183{
3421b778
AT
184 struct em28xx *dev = dvb->adapter.priv;
185
5f5f147f 186 em28xx_stop_urbs(dev);
c67ec53f 187
2fe3e2ee 188 em28xx_set_mode(dev, EM28XX_SUSPEND);
c67ec53f 189
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MCC
190 return 0;
191}
192
f2d0c1c6 193static int em28xx_start_feed(struct dvb_demux_feed *feed)
3421b778
AT
194{
195 struct dvb_demux *demux = feed->demux;
196 struct em28xx_dvb *dvb = demux->priv;
197 int rc, ret;
198
199 if (!demux->dmx.frontend)
200 return -EINVAL;
201
202 mutex_lock(&dvb->lock);
203 dvb->nfeeds++;
204 rc = dvb->nfeeds;
205
206 if (dvb->nfeeds == 1) {
f2d0c1c6 207 ret = em28xx_start_streaming(dvb);
6ea54d93
DSL
208 if (ret < 0)
209 rc = ret;
3421b778
AT
210 }
211
212 mutex_unlock(&dvb->lock);
213 return rc;
214}
215
f2d0c1c6 216static int em28xx_stop_feed(struct dvb_demux_feed *feed)
3421b778
AT
217{
218 struct dvb_demux *demux = feed->demux;
219 struct em28xx_dvb *dvb = demux->priv;
220 int err = 0;
221
222 mutex_lock(&dvb->lock);
223 dvb->nfeeds--;
6ea54d93
DSL
224
225 if (0 == dvb->nfeeds)
f2d0c1c6 226 err = em28xx_stop_streaming(dvb);
6ea54d93 227
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AT
228 mutex_unlock(&dvb->lock);
229 return err;
230}
231
232
e3569abc
MCC
233
234/* ------------------------------------------------------------------ */
235static int em28xx_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
236{
237 struct em28xx *dev = fe->dvb->priv;
238
239 if (acquire)
240 return em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
241 else
2fe3e2ee 242 return em28xx_set_mode(dev, EM28XX_SUSPEND);
e3569abc
MCC
243}
244
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MCC
245/* ------------------------------------------------------------------ */
246
227ad4ab
MCC
247static struct lgdt330x_config em2880_lgdt3303_dev = {
248 .demod_address = 0x0e,
249 .demod_chip = LGDT3303,
250};
3aefb79a 251
7e48b30a
JW
252static struct lgdt3305_config em2870_lgdt3304_dev = {
253 .i2c_addr = 0x0e,
254 .demod_chip = LGDT3304,
255 .spectral_inversion = 1,
256 .deny_i2c_rptr = 1,
257 .mpeg_mode = LGDT3305_MPEG_PARALLEL,
258 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
259 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
260 .vsb_if_khz = 3250,
261 .qam_if_khz = 4000,
262};
263
ca3dfd6a
MCC
264static struct s921_config sharp_isdbt = {
265 .demod_address = 0x30 >> 1
266};
267
7e6388a1
AT
268static struct zl10353_config em28xx_zl10353_with_xc3028 = {
269 .demod_address = (0x1e >> 1),
270 .no_tuner = 1,
271 .parallel_ts = 1,
272 .if2 = 45600,
273};
274
6e7b9ea0
RK
275static struct s5h1409_config em28xx_s5h1409_with_xc3028 = {
276 .demod_address = 0x32 >> 1,
277 .output_mode = S5H1409_PARALLEL_OUTPUT,
278 .gpio = S5H1409_GPIO_OFF,
279 .inversion = S5H1409_INVERSION_OFF,
280 .status_mode = S5H1409_DEMODLOCKING,
281 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK
282};
283
7e48b30a
JW
284static struct tda18271_std_map kworld_a340_std_map = {
285 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 0,
286 .if_lvl = 1, .rfagc_top = 0x37, },
287 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 1,
288 .if_lvl = 1, .rfagc_top = 0x37, },
289};
290
291static struct tda18271_config kworld_a340_config = {
292 .std_map = &kworld_a340_std_map,
293};
294
a84f79ae 295static struct zl10353_config em28xx_zl10353_xc3028_no_i2c_gate = {
f797608c
DH
296 .demod_address = (0x1e >> 1),
297 .no_tuner = 1,
298 .disable_i2c_gate_ctrl = 1,
299 .parallel_ts = 1,
300 .if2 = 45600,
301};
302
75e2b869 303static struct drxd_config em28xx_drxd = {
aac865f7
MCC
304 .demod_address = 0x70,
305 .demod_revision = 0xa2,
306 .pll_type = DRXD_PLL_NONE,
307 .clock = 12000,
308 .insert_rs_byte = 1,
309 .IF = 42800000,
6b142b3c 310 .disable_i2c_gate_ctrl = 1,
17d9d558 311};
17d9d558 312
fec528b7
MCC
313struct drxk_config terratec_h5_drxk = {
314 .adr = 0x29,
e4f4f875 315 .single_master = 1,
f1fe1b75 316 .no_i2c_bridge = 1,
8b9456ae 317 .microcode_name = "dvb-usb-terratec-h5-drxk.fw",
fec528b7
MCC
318};
319
82e7dbbd
EDP
320struct drxk_config hauppauge_930c_drxk = {
321 .adr = 0x29,
322 .single_master = 1,
323 .no_i2c_bridge = 1,
324 .microcode_name = "dvb-usb-hauppauge-hvr930c-drxk.fw",
325 .chunk_size = 56,
326};
327
3553085c
AP
328struct drxk_config maxmedia_ub425_tc_drxk = {
329 .adr = 0x29,
330 .single_master = 1,
331 .no_i2c_bridge = 1,
332};
333
c247d7b1
AP
334struct drxk_config pctv_520e_drxk = {
335 .adr = 0x29,
336 .single_master = 1,
337 .microcode_name = "dvb-demod-drxk-pctv.fw",
338 .chunk_size = 58,
f6f379df
AP
339 .antenna_dvbt = true, /* disable LNA */
340 .antenna_gpio = (1 << 2), /* disable LNA */
c247d7b1
AP
341};
342
fec528b7
MCC
343static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
344{
345 struct em28xx_dvb *dvb = fe->sec_priv;
346 int status;
347
348 if (!dvb)
349 return -EINVAL;
350
351 if (enable) {
352 down(&dvb->pll_mutex);
353 status = dvb->gate_ctrl(fe, 1);
354 } else {
355 status = dvb->gate_ctrl(fe, 0);
356 up(&dvb->pll_mutex);
357 }
358 return status;
359}
360
82e7dbbd
EDP
361static void hauppauge_hvr930c_init(struct em28xx *dev)
362{
363 int i;
364
365 struct em28xx_reg_seq hauppauge_hvr930c_init[] = {
de72405f
MCC
366 {EM2874_R80_GPIO, 0xff, 0xff, 0x65},
367 {EM2874_R80_GPIO, 0xfb, 0xff, 0x32},
368 {EM2874_R80_GPIO, 0xff, 0xff, 0xb8},
82e7dbbd
EDP
369 { -1, -1, -1, -1},
370 };
371 struct em28xx_reg_seq hauppauge_hvr930c_end[] = {
de72405f
MCC
372 {EM2874_R80_GPIO, 0xef, 0xff, 0x01},
373 {EM2874_R80_GPIO, 0xaf, 0xff, 0x65},
374 {EM2874_R80_GPIO, 0xef, 0xff, 0x76},
375 {EM2874_R80_GPIO, 0xef, 0xff, 0x01},
376 {EM2874_R80_GPIO, 0xcf, 0xff, 0x0b},
377 {EM2874_R80_GPIO, 0xef, 0xff, 0x40},
378
379 {EM2874_R80_GPIO, 0xcf, 0xff, 0x65},
380 {EM2874_R80_GPIO, 0xef, 0xff, 0x65},
381 {EM2874_R80_GPIO, 0xcf, 0xff, 0x0b},
382 {EM2874_R80_GPIO, 0xef, 0xff, 0x65},
82e7dbbd 383
82e7dbbd
EDP
384 { -1, -1, -1, -1},
385 };
386
82e7dbbd
EDP
387 struct {
388 unsigned char r[4];
389 int len;
390 } regs[] = {
391 {{ 0x06, 0x02, 0x00, 0x31 }, 4},
392 {{ 0x01, 0x02 }, 2},
393 {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
394 {{ 0x01, 0x00 }, 2},
395 {{ 0x01, 0x00, 0xff, 0xaf }, 4},
396 {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
397 {{ 0x01, 0x00 }, 2},
398 {{ 0x01, 0x00, 0x73, 0xaf }, 4},
399 {{ 0x04, 0x00 }, 2},
400 {{ 0x00, 0x04 }, 2},
401 {{ 0x00, 0x04, 0x00, 0x0a }, 4},
402 {{ 0x04, 0x14 }, 2},
403 {{ 0x04, 0x14, 0x00, 0x00 }, 4},
404 };
405
406 em28xx_gpio_set(dev, hauppauge_hvr930c_init);
407 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
408 msleep(10);
409 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
410 msleep(10);
411
412 dev->i2c_client.addr = 0x82 >> 1;
413
414 for (i = 0; i < ARRAY_SIZE(regs); i++)
415 i2c_master_send(&dev->i2c_client, regs[i].r, regs[i].len);
416 em28xx_gpio_set(dev, hauppauge_hvr930c_end);
417
418 msleep(100);
419
420 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
421 msleep(30);
422
82e7dbbd
EDP
423 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x45);
424 msleep(10);
425
426}
427
fec528b7
MCC
428static void terratec_h5_init(struct em28xx *dev)
429{
430 int i;
431 struct em28xx_reg_seq terratec_h5_init[] = {
432 {EM28XX_R08_GPIO, 0xff, 0xff, 10},
433 {EM2874_R80_GPIO, 0xf6, 0xff, 100},
434 {EM2874_R80_GPIO, 0xf2, 0xff, 50},
435 {EM2874_R80_GPIO, 0xf6, 0xff, 100},
436 { -1, -1, -1, -1},
437 };
438 struct em28xx_reg_seq terratec_h5_end[] = {
439 {EM2874_R80_GPIO, 0xe6, 0xff, 100},
440 {EM2874_R80_GPIO, 0xa6, 0xff, 50},
441 {EM2874_R80_GPIO, 0xe6, 0xff, 100},
442 { -1, -1, -1, -1},
443 };
444 struct {
445 unsigned char r[4];
446 int len;
447 } regs[] = {
448 {{ 0x06, 0x02, 0x00, 0x31 }, 4},
449 {{ 0x01, 0x02 }, 2},
450 {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
451 {{ 0x01, 0x00 }, 2},
452 {{ 0x01, 0x00, 0xff, 0xaf }, 4},
453 {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
454 {{ 0x01, 0x00 }, 2},
455 {{ 0x01, 0x00, 0x73, 0xaf }, 4},
456 {{ 0x04, 0x00 }, 2},
457 {{ 0x00, 0x04 }, 2},
458 {{ 0x00, 0x04, 0x00, 0x0a }, 4},
459 {{ 0x04, 0x14 }, 2},
460 {{ 0x04, 0x14, 0x00, 0x00 }, 4},
461 };
462
463 em28xx_gpio_set(dev, terratec_h5_init);
464 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
465 msleep(10);
466 em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x45);
467 msleep(10);
468
469 dev->i2c_client.addr = 0x82 >> 1;
470
471 for (i = 0; i < ARRAY_SIZE(regs); i++)
472 i2c_master_send(&dev->i2c_client, regs[i].r, regs[i].len);
473 em28xx_gpio_set(dev, terratec_h5_end);
474};
475
c247d7b1
AP
476static void pctv_520e_init(struct em28xx *dev)
477{
478 /*
479 * Init TDA8295(?) analog demodulator. Looks like I2C traffic to
480 * digital demodulator and tuner are routed via TDA8295.
481 */
482 int i;
483 struct {
484 unsigned char r[4];
485 int len;
486 } regs[] = {
487 {{ 0x06, 0x02, 0x00, 0x31 }, 4},
488 {{ 0x01, 0x02 }, 2},
489 {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
490 {{ 0x01, 0x00 }, 2},
491 {{ 0x01, 0x00, 0xff, 0xaf }, 4},
492 {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
493 {{ 0x01, 0x00 }, 2},
494 {{ 0x01, 0x00, 0x73, 0xaf }, 4},
495 };
496
497 dev->i2c_client.addr = 0x82 >> 1; /* 0x41 */
498
499 for (i = 0; i < ARRAY_SIZE(regs); i++)
500 i2c_master_send(&dev->i2c_client, regs[i].r, regs[i].len);
501};
502
f2d0c1c6 503static int em28xx_mt352_terratec_xs_init(struct dvb_frontend *fe)
4fb202a8
DH
504{
505 /* Values extracted from a USB trace of the Terratec Windows driver */
506 static u8 clock_config[] = { CLOCK_CTL, 0x38, 0x2c };
507 static u8 reset[] = { RESET, 0x80 };
508 static u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
509 static u8 agc_cfg[] = { AGC_TARGET, 0x28, 0xa0 };
510 static u8 input_freq_cfg[] = { INPUT_FREQ_1, 0x31, 0xb8 };
511 static u8 rs_err_cfg[] = { RS_ERR_PER_1, 0x00, 0x4d };
512 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
513 static u8 trl_nom_cfg[] = { TRL_NOMINAL_RATE_1, 0x64, 0x00 };
514 static u8 tps_given_cfg[] = { TPS_GIVEN_1, 0x40, 0x80, 0x50 };
ff69786b 515 static u8 tuner_go[] = { TUNER_GO, 0x01};
4fb202a8
DH
516
517 mt352_write(fe, clock_config, sizeof(clock_config));
518 udelay(200);
519 mt352_write(fe, reset, sizeof(reset));
520 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
521 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
522 mt352_write(fe, input_freq_cfg, sizeof(input_freq_cfg));
523 mt352_write(fe, rs_err_cfg, sizeof(rs_err_cfg));
524 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
525 mt352_write(fe, trl_nom_cfg, sizeof(trl_nom_cfg));
526 mt352_write(fe, tps_given_cfg, sizeof(tps_given_cfg));
527 mt352_write(fe, tuner_go, sizeof(tuner_go));
528 return 0;
529}
530
531static struct mt352_config terratec_xs_mt352_cfg = {
532 .demod_address = (0x1e >> 1),
533 .no_tuner = 1,
534 .if2 = 45600,
f2d0c1c6 535 .demod_init = em28xx_mt352_terratec_xs_init,
4fb202a8
DH
536};
537
285eb1a4
AP
538static struct tda10023_config em28xx_tda10023_config = {
539 .demod_address = 0x0c,
540 .invert = 1,
541};
542
d6a5f921
AP
543static struct cxd2820r_config em28xx_cxd2820r_config = {
544 .i2c_address = (0xd8 >> 1),
545 .ts_mode = CXD2820R_TS_SERIAL,
d6a5f921 546
38f0fe23
GG
547 /* enable LNA for DVB-T, DVB-T2 and DVB-C */
548 .gpio_dvbt[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L,
d6a5f921
AP
549 .gpio_dvbt2[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L,
550 .gpio_dvbc[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L,
551};
552
553static struct tda18271_config em28xx_cxd2820r_tda18271_config = {
554 .output_opt = TDA18271_OUTPUT_LT_OFF,
0db4bf42 555 .gate = TDA18271_GATE_DIGITAL,
d6a5f921
AP
556};
557
36588715
AP
558static const struct tda10071_config em28xx_tda10071_config = {
559 .i2c_address = 0x55, /* (0xaa >> 1) */
560 .i2c_wr_max = 64,
561 .ts_mode = TDA10071_TS_SERIAL,
562 .spec_inv = 0,
563 .xtal = 40444000, /* 40.444 MHz */
564 .pll_multiplier = 20,
565};
566
567static const struct a8293_config em28xx_a8293_config = {
568 .i2c_addr = 0x08, /* (0x10 >> 1) */
569};
570
1985f6fb
AP
571static struct zl10353_config em28xx_zl10353_no_i2c_gate_dev = {
572 .demod_address = (0x1e >> 1),
573 .disable_i2c_gate_ctrl = 1,
574 .no_tuner = 1,
575 .parallel_ts = 1,
576};
577static struct qt1010_config em28xx_qt1010_config = {
578 .i2c_address = 0x62
579
580};
581
3aefb79a
MCC
582/* ------------------------------------------------------------------ */
583
f2d0c1c6 584static int em28xx_attach_xc3028(u8 addr, struct em28xx *dev)
3aefb79a
MCC
585{
586 struct dvb_frontend *fe;
3ca9c093
MCC
587 struct xc2028_config cfg;
588
6ea54d93 589 memset(&cfg, 0, sizeof(cfg));
3ca9c093
MCC
590 cfg.i2c_adap = &dev->i2c_adap;
591 cfg.i2c_addr = addr;
3ca9c093 592
f71095be 593 if (!dev->dvb->fe[0]) {
480be185
FR
594 em28xx_errdev("/2: dvb frontend not attached. "
595 "Can't attach xc3028\n");
3aefb79a
MCC
596 return -EINVAL;
597 }
598
f71095be 599 fe = dvb_attach(xc2028_attach, dev->dvb->fe[0], &cfg);
3aefb79a 600 if (!fe) {
480be185 601 em28xx_errdev("/2: xc3028 attach failed\n");
f71095be
AP
602 dvb_frontend_detach(dev->dvb->fe[0]);
603 dev->dvb->fe[0] = NULL;
3aefb79a
MCC
604 return -EINVAL;
605 }
606
480be185 607 em28xx_info("%s/2: xc3028 attached\n", dev->name);
3aefb79a
MCC
608
609 return 0;
610}
611
3421b778
AT
612/* ------------------------------------------------------------------ */
613
f2d0c1c6
JW
614static int em28xx_register_dvb(struct em28xx_dvb *dvb, struct module *module,
615 struct em28xx *dev, struct device *device)
3aefb79a 616{
3421b778 617 int result;
3aefb79a 618
3421b778 619 mutex_init(&dvb->lock);
3aefb79a 620
3421b778
AT
621 /* register adapter */
622 result = dvb_register_adapter(&dvb->adapter, dev->name, module, device,
623 adapter_nr);
624 if (result < 0) {
625 printk(KERN_WARNING "%s: dvb_register_adapter failed (errno = %d)\n",
626 dev->name, result);
627 goto fail_adapter;
628 }
e3569abc
MCC
629
630 /* Ensure all frontends negotiate bus access */
f71095be
AP
631 dvb->fe[0]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
632 if (dvb->fe[1])
633 dvb->fe[1]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
e3569abc 634
3421b778
AT
635 dvb->adapter.priv = dev;
636
637 /* register frontend */
f71095be 638 result = dvb_register_frontend(&dvb->adapter, dvb->fe[0]);
3421b778
AT
639 if (result < 0) {
640 printk(KERN_WARNING "%s: dvb_register_frontend failed (errno = %d)\n",
641 dev->name, result);
f71095be
AP
642 goto fail_frontend0;
643 }
644
645 /* register 2nd frontend */
646 if (dvb->fe[1]) {
647 result = dvb_register_frontend(&dvb->adapter, dvb->fe[1]);
648 if (result < 0) {
649 printk(KERN_WARNING "%s: 2nd dvb_register_frontend failed (errno = %d)\n",
650 dev->name, result);
651 goto fail_frontend1;
652 }
3421b778
AT
653 }
654
655 /* register demux stuff */
656 dvb->demux.dmx.capabilities =
657 DMX_TS_FILTERING | DMX_SECTION_FILTERING |
658 DMX_MEMORY_BASED_FILTERING;
659 dvb->demux.priv = dvb;
660 dvb->demux.filternum = 256;
661 dvb->demux.feednum = 256;
f2d0c1c6
JW
662 dvb->demux.start_feed = em28xx_start_feed;
663 dvb->demux.stop_feed = em28xx_stop_feed;
e3569abc 664
3421b778
AT
665 result = dvb_dmx_init(&dvb->demux);
666 if (result < 0) {
667 printk(KERN_WARNING "%s: dvb_dmx_init failed (errno = %d)\n",
668 dev->name, result);
669 goto fail_dmx;
670 }
671
672 dvb->dmxdev.filternum = 256;
673 dvb->dmxdev.demux = &dvb->demux.dmx;
674 dvb->dmxdev.capabilities = 0;
675 result = dvb_dmxdev_init(&dvb->dmxdev, &dvb->adapter);
676 if (result < 0) {
677 printk(KERN_WARNING "%s: dvb_dmxdev_init failed (errno = %d)\n",
678 dev->name, result);
679 goto fail_dmxdev;
680 }
52284c3e 681
3421b778
AT
682 dvb->fe_hw.source = DMX_FRONTEND_0;
683 result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_hw);
684 if (result < 0) {
685 printk(KERN_WARNING "%s: add_frontend failed (DMX_FRONTEND_0, errno = %d)\n",
686 dev->name, result);
687 goto fail_fe_hw;
688 }
689
690 dvb->fe_mem.source = DMX_MEMORY_FE;
691 result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_mem);
692 if (result < 0) {
693 printk(KERN_WARNING "%s: add_frontend failed (DMX_MEMORY_FE, errno = %d)\n",
694 dev->name, result);
695 goto fail_fe_mem;
696 }
697
698 result = dvb->demux.dmx.connect_frontend(&dvb->demux.dmx, &dvb->fe_hw);
699 if (result < 0) {
700 printk(KERN_WARNING "%s: connect_frontend failed (errno = %d)\n",
701 dev->name, result);
702 goto fail_fe_conn;
703 }
704
705 /* register network adapter */
706 dvb_net_init(&dvb->adapter, &dvb->net, &dvb->demux.dmx);
707 return 0;
708
709fail_fe_conn:
710 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
711fail_fe_mem:
712 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
713fail_fe_hw:
714 dvb_dmxdev_release(&dvb->dmxdev);
715fail_dmxdev:
716 dvb_dmx_release(&dvb->demux);
717fail_dmx:
f71095be
AP
718 if (dvb->fe[1])
719 dvb_unregister_frontend(dvb->fe[1]);
720 dvb_unregister_frontend(dvb->fe[0]);
721fail_frontend1:
722 if (dvb->fe[1])
723 dvb_frontend_detach(dvb->fe[1]);
724fail_frontend0:
725 dvb_frontend_detach(dvb->fe[0]);
3421b778
AT
726 dvb_unregister_adapter(&dvb->adapter);
727fail_adapter:
728 return result;
729}
730
f2d0c1c6 731static void em28xx_unregister_dvb(struct em28xx_dvb *dvb)
3421b778
AT
732{
733 dvb_net_release(&dvb->net);
734 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
735 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
736 dvb_dmxdev_release(&dvb->dmxdev);
737 dvb_dmx_release(&dvb->demux);
f71095be
AP
738 if (dvb->fe[1])
739 dvb_unregister_frontend(dvb->fe[1]);
740 dvb_unregister_frontend(dvb->fe[0]);
c4c3a3d3 741 if (dvb->fe[1] && !dvb->dont_attach_fe1)
f71095be
AP
742 dvb_frontend_detach(dvb->fe[1]);
743 dvb_frontend_detach(dvb->fe[0]);
3421b778
AT
744 dvb_unregister_adapter(&dvb->adapter);
745}
746
f2d0c1c6 747static int em28xx_dvb_init(struct em28xx *dev)
3421b778 748{
e3645437 749 int result = 0, mfe_shared = 0;
3421b778
AT
750 struct em28xx_dvb *dvb;
751
505b6d0b 752 if (!dev->board.has_dvb) {
df619181 753 /* This device does not support the extension */
ca3dfd6a 754 printk(KERN_INFO "em28xx_dvb: This device does not support the extension\n");
df619181
DH
755 return 0;
756 }
757
3421b778 758 dvb = kzalloc(sizeof(struct em28xx_dvb), GFP_KERNEL);
6ea54d93
DSL
759
760 if (dvb == NULL) {
480be185 761 em28xx_info("em28xx_dvb: memory allocation failed\n");
3421b778
AT
762 return -ENOMEM;
763 }
764 dev->dvb = dvb;
f71095be 765 dvb->fe[0] = dvb->fe[1] = NULL;
3aefb79a 766
5013318c 767 mutex_lock(&dev->lock);
c67ec53f 768 em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
3aefb79a
MCC
769 /* init frontend */
770 switch (dev->model) {
ebaefdb7 771 case EM2874_BOARD_LEADERSHIP_ISDBT:
f71095be 772 dvb->fe[0] = dvb_attach(s921_attach,
ca3dfd6a
MCC
773 &sharp_isdbt, &dev->i2c_adap);
774
f71095be 775 if (!dvb->fe[0]) {
ca3dfd6a
MCC
776 result = -EINVAL;
777 goto out_free;
778 }
779
780 break;
f89bc329 781 case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850:
10ac6603 782 case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
4fd305b2 783 case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
e14b3658 784 case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
f71095be 785 dvb->fe[0] = dvb_attach(lgdt330x_attach,
3421b778
AT
786 &em2880_lgdt3303_dev,
787 &dev->i2c_adap);
f2d0c1c6 788 if (em28xx_attach_xc3028(0x61, dev) < 0) {
3421b778
AT
789 result = -EINVAL;
790 goto out_free;
791 }
227ad4ab 792 break;
46510b56 793 case EM2880_BOARD_KWORLD_DVB_310U:
f71095be 794 dvb->fe[0] = dvb_attach(zl10353_attach,
3421b778
AT
795 &em28xx_zl10353_with_xc3028,
796 &dev->i2c_adap);
f2d0c1c6 797 if (em28xx_attach_xc3028(0x61, dev) < 0) {
3421b778
AT
798 result = -EINVAL;
799 goto out_free;
800 }
7e6388a1 801 break;
a84f79ae 802 case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
ec994d05 803 case EM2882_BOARD_TERRATEC_HYBRID_XS:
01a5fd6f 804 case EM2880_BOARD_EMPIRE_DUAL_TV:
f71095be 805 dvb->fe[0] = dvb_attach(zl10353_attach,
a84f79ae
DH
806 &em28xx_zl10353_xc3028_no_i2c_gate,
807 &dev->i2c_adap);
f2d0c1c6 808 if (em28xx_attach_xc3028(0x61, dev) < 0) {
a84f79ae
DH
809 result = -EINVAL;
810 goto out_free;
811 }
812 break;
f797608c 813 case EM2880_BOARD_TERRATEC_HYBRID_XS:
65638011 814 case EM2880_BOARD_TERRATEC_HYBRID_XS_FR:
d5b3ba9c 815 case EM2881_BOARD_PINNACLE_HYBRID_PRO:
7ca7ef60 816 case EM2882_BOARD_DIKOM_DK300:
811fab62 817 case EM2882_BOARD_KWORLD_VS_DVBT:
f71095be 818 dvb->fe[0] = dvb_attach(zl10353_attach,
a84f79ae 819 &em28xx_zl10353_xc3028_no_i2c_gate,
f797608c 820 &dev->i2c_adap);
f71095be 821 if (dvb->fe[0] == NULL) {
f797608c
DH
822 /* This board could have either a zl10353 or a mt352.
823 If the chip id isn't for zl10353, try mt352 */
f71095be 824 dvb->fe[0] = dvb_attach(mt352_attach,
4fb202a8
DH
825 &terratec_xs_mt352_cfg,
826 &dev->i2c_adap);
f797608c 827 }
4fb202a8 828
f2d0c1c6 829 if (em28xx_attach_xc3028(0x61, dev) < 0) {
f797608c
DH
830 result = -EINVAL;
831 goto out_free;
832 }
833 break;
1985f6fb
AP
834 case EM2870_BOARD_KWORLD_355U:
835 dvb->fe[0] = dvb_attach(zl10353_attach,
836 &em28xx_zl10353_no_i2c_gate_dev,
837 &dev->i2c_adap);
838 if (dvb->fe[0] != NULL)
839 dvb_attach(qt1010_attach, dvb->fe[0],
840 &dev->i2c_adap, &em28xx_qt1010_config);
841 break;
6e7b9ea0 842 case EM2883_BOARD_KWORLD_HYBRID_330U:
19859229 843 case EM2882_BOARD_EVGA_INDTUBE:
f71095be 844 dvb->fe[0] = dvb_attach(s5h1409_attach,
6e7b9ea0
RK
845 &em28xx_s5h1409_with_xc3028,
846 &dev->i2c_adap);
f2d0c1c6 847 if (em28xx_attach_xc3028(0x61, dev) < 0) {
6e7b9ea0
RK
848 result = -EINVAL;
849 goto out_free;
850 }
851 break;
d7de5d8f 852 case EM2882_BOARD_KWORLD_ATSC_315U:
f71095be 853 dvb->fe[0] = dvb_attach(lgdt330x_attach,
d7de5d8f
FM
854 &em2880_lgdt3303_dev,
855 &dev->i2c_adap);
f71095be
AP
856 if (dvb->fe[0] != NULL) {
857 if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
d7de5d8f
FM
858 &dev->i2c_adap, 0x61, TUNER_THOMSON_DTT761X)) {
859 result = -EINVAL;
860 goto out_free;
861 }
862 }
863 break;
17d9d558 864 case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
ad9b4bb2 865 case EM2882_BOARD_PINNACLE_HYBRID_PRO_330E:
f71095be 866 dvb->fe[0] = dvb_attach(drxd_attach, &em28xx_drxd, NULL,
75e2b869 867 &dev->i2c_adap, &dev->udev->dev);
f2d0c1c6 868 if (em28xx_attach_xc3028(0x61, dev) < 0) {
17d9d558
DH
869 result = -EINVAL;
870 goto out_free;
871 }
872 break;
285eb1a4
AP
873 case EM2870_BOARD_REDDO_DVB_C_USB_BOX:
874 /* Philips CU1216L NIM (Philips TDA10023 + Infineon TUA6034) */
f71095be 875 dvb->fe[0] = dvb_attach(tda10023_attach,
285eb1a4
AP
876 &em28xx_tda10023_config,
877 &dev->i2c_adap, 0x48);
f71095be
AP
878 if (dvb->fe[0]) {
879 if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
285eb1a4
AP
880 &dev->i2c_adap, 0x60, TUNER_PHILIPS_CU1216L)) {
881 result = -EINVAL;
882 goto out_free;
883 }
884 }
885 break;
7e48b30a 886 case EM2870_BOARD_KWORLD_A340:
f71095be 887 dvb->fe[0] = dvb_attach(lgdt3305_attach,
7e48b30a
JW
888 &em2870_lgdt3304_dev,
889 &dev->i2c_adap);
f71095be
AP
890 if (dvb->fe[0] != NULL)
891 dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
7e48b30a
JW
892 &dev->i2c_adap, &kworld_a340_config);
893 break;
d6a5f921 894 case EM28174_BOARD_PCTV_290E:
d6a5f921 895 dvb->fe[0] = dvb_attach(cxd2820r_attach,
7e7b8287 896 &em28xx_cxd2820r_config,
c2bbbe7b 897 &dev->i2c_adap);
d6a5f921 898 if (dvb->fe[0]) {
d6a5f921 899 /* FE 0 attach tuner */
7e7b8287
MA
900 if (!dvb_attach(tda18271_attach,
901 dvb->fe[0],
902 0x60,
903 &dev->i2c_adap,
904 &em28xx_cxd2820r_tda18271_config)) {
905
d6a5f921
AP
906 dvb_frontend_detach(dvb->fe[0]);
907 result = -EINVAL;
908 goto out_free;
909 }
d6a5f921 910 }
82e7dbbd
EDP
911 break;
912 case EM2884_BOARD_HAUPPAUGE_WINTV_HVR_930C:
8503232f
MCC
913 {
914 struct xc5000_config cfg;
82e7dbbd
EDP
915 hauppauge_hvr930c_init(dev);
916
de72405f 917 dvb->fe[0] = dvb_attach(drxk_attach,
fa4b2a17 918 &hauppauge_930c_drxk, &dev->i2c_adap);
82e7dbbd
EDP
919 if (!dvb->fe[0]) {
920 result = -EINVAL;
921 goto out_free;
922 }
923 /* FIXME: do we need a pll semaphore? */
924 dvb->fe[0]->sec_priv = dvb;
925 sema_init(&dvb->pll_mutex, 1);
926 dvb->gate_ctrl = dvb->fe[0]->ops.i2c_gate_ctrl;
927 dvb->fe[0]->ops.i2c_gate_ctrl = drxk_gate_ctrl;
82e7dbbd
EDP
928
929 /* Attach xc5000 */
82e7dbbd
EDP
930 memset(&cfg, 0, sizeof(cfg));
931 cfg.i2c_address = 0x61;
de72405f 932 cfg.if_khz = 4000;
82e7dbbd
EDP
933
934 if (dvb->fe[0]->ops.i2c_gate_ctrl)
935 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 1);
de72405f
MCC
936 if (!dvb_attach(xc5000_attach, dvb->fe[0], &dev->i2c_adap,
937 &cfg)) {
82e7dbbd
EDP
938 result = -EINVAL;
939 goto out_free;
940 }
82e7dbbd
EDP
941 if (dvb->fe[0]->ops.i2c_gate_ctrl)
942 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 0);
943
fec528b7 944 break;
8503232f 945 }
fec528b7 946 case EM2884_BOARD_TERRATEC_H5:
a1ed02e9 947 case EM2884_BOARD_CINERGY_HTC_STICK:
fec528b7
MCC
948 terratec_h5_init(dev);
949
fa4b2a17 950 dvb->fe[0] = dvb_attach(drxk_attach, &terratec_h5_drxk, &dev->i2c_adap);
c4c3a3d3 951 if (!dvb->fe[0]) {
fec528b7
MCC
952 result = -EINVAL;
953 goto out_free;
954 }
955 /* FIXME: do we need a pll semaphore? */
956 dvb->fe[0]->sec_priv = dvb;
957 sema_init(&dvb->pll_mutex, 1);
958 dvb->gate_ctrl = dvb->fe[0]->ops.i2c_gate_ctrl;
959 dvb->fe[0]->ops.i2c_gate_ctrl = drxk_gate_ctrl;
fec528b7 960
c4c3a3d3 961 /* Attach tda18271 to DVB-C frontend */
fec528b7
MCC
962 if (dvb->fe[0]->ops.i2c_gate_ctrl)
963 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 1);
964 if (!dvb_attach(tda18271c2dd_attach, dvb->fe[0], &dev->i2c_adap, 0x60)) {
965 result = -EINVAL;
966 goto out_free;
967 }
968 if (dvb->fe[0]->ops.i2c_gate_ctrl)
969 dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 0);
c4c3a3d3 970
d6a5f921 971 break;
36588715
AP
972 case EM28174_BOARD_PCTV_460E:
973 /* attach demod */
974 dvb->fe[0] = dvb_attach(tda10071_attach,
975 &em28xx_tda10071_config, &dev->i2c_adap);
976
977 /* attach SEC */
978 if (dvb->fe[0])
979 dvb_attach(a8293_attach, dvb->fe[0], &dev->i2c_adap,
980 &em28xx_a8293_config);
981 break;
3553085c
AP
982 case EM2874_BOARD_MAXMEDIA_UB425_TC:
983 /* attach demodulator */
984 dvb->fe[0] = dvb_attach(drxk_attach, &maxmedia_ub425_tc_drxk,
985 &dev->i2c_adap);
986
987 if (dvb->fe[0]) {
988 /* disable I2C-gate */
989 dvb->fe[0]->ops.i2c_gate_ctrl = NULL;
990
991 /* attach tuner */
992 if (!dvb_attach(tda18271c2dd_attach, dvb->fe[0],
993 &dev->i2c_adap, 0x60)) {
994 dvb_frontend_detach(dvb->fe[0]);
995 result = -EINVAL;
996 goto out_free;
997 }
998 }
999
1000 /* TODO: we need drx-3913k firmware in order to support DVB-T */
1001 em28xx_info("MaxMedia UB425-TC: only DVB-C supported by that " \
1002 "driver version\n");
1003
c247d7b1 1004 break;
fa5527cd
IK
1005 case EM2884_BOARD_PCTV_510E:
1006 case EM2884_BOARD_PCTV_520E:
1007 pctv_520e_init(dev);
1008
c247d7b1
AP
1009 /* attach demodulator */
1010 dvb->fe[0] = dvb_attach(drxk_attach, &pctv_520e_drxk,
1011 &dev->i2c_adap);
1012
1013 if (dvb->fe[0]) {
1014 /* attach tuner */
1015 if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
1016 &dev->i2c_adap,
1017 &em28xx_cxd2820r_tda18271_config)) {
1018 dvb_frontend_detach(dvb->fe[0]);
1019 result = -EINVAL;
1020 goto out_free;
1021 }
1022 }
3553085c 1023 break;
3aefb79a 1024 default:
480be185
FR
1025 em28xx_errdev("/2: The frontend of your DVB/ATSC card"
1026 " isn't supported yet\n");
3aefb79a
MCC
1027 break;
1028 }
f71095be 1029 if (NULL == dvb->fe[0]) {
480be185 1030 em28xx_errdev("/2: frontend initialization failed\n");
3421b778
AT
1031 result = -EINVAL;
1032 goto out_free;
3aefb79a 1033 }
d7cba043 1034 /* define general-purpose callback pointer */
f71095be 1035 dvb->fe[0]->callback = em28xx_tuner_callback;
82e7dbbd 1036 if (dvb->fe[1])
de72405f 1037 dvb->fe[1]->callback = em28xx_tuner_callback;
3aefb79a
MCC
1038
1039 /* register everything */
f2d0c1c6 1040 result = em28xx_register_dvb(dvb, THIS_MODULE, dev, &dev->udev->dev);
3421b778 1041
6ea54d93 1042 if (result < 0)
3421b778 1043 goto out_free;
3421b778 1044
e3645437
AP
1045 /* MFE lock */
1046 dvb->adapter.mfe_shared = mfe_shared;
1047
480be185 1048 em28xx_info("Successfully loaded em28xx-dvb\n");
5013318c
MCC
1049ret:
1050 em28xx_set_mode(dev, EM28XX_SUSPEND);
1051 mutex_unlock(&dev->lock);
1052 return result;
3421b778
AT
1053
1054out_free:
1055 kfree(dvb);
1056 dev->dvb = NULL;
5013318c 1057 goto ret;
3aefb79a
MCC
1058}
1059
0b8bd83c
CR
1060static inline void prevent_sleep(struct dvb_frontend_ops *ops)
1061{
1062 ops->set_voltage = NULL;
1063 ops->sleep = NULL;
1064 ops->tuner_ops.sleep = NULL;
1065}
1066
f2d0c1c6 1067static int em28xx_dvb_fini(struct em28xx *dev)
3aefb79a 1068{
505b6d0b 1069 if (!dev->board.has_dvb) {
df619181
DH
1070 /* This device does not support the extension */
1071 return 0;
1072 }
1073
3421b778 1074 if (dev->dvb) {
0b8bd83c
CR
1075 struct em28xx_dvb *dvb = dev->dvb;
1076
1077 if (dev->state & DEV_DISCONNECTED) {
1078 /* We cannot tell the device to sleep
1079 * once it has been unplugged. */
1080 if (dvb->fe[0])
1081 prevent_sleep(&dvb->fe[0]->ops);
1082 if (dvb->fe[1])
1083 prevent_sleep(&dvb->fe[1]->ops);
1084 }
1085
1086 em28xx_unregister_dvb(dvb);
1087 kfree(dvb);
3421b778
AT
1088 dev->dvb = NULL;
1089 }
3aefb79a
MCC
1090
1091 return 0;
1092}
1093
1094static struct em28xx_ops dvb_ops = {
1095 .id = EM28XX_DVB,
1096 .name = "Em28xx dvb Extension",
f2d0c1c6
JW
1097 .init = em28xx_dvb_init,
1098 .fini = em28xx_dvb_fini,
3aefb79a
MCC
1099};
1100
1101static int __init em28xx_dvb_register(void)
1102{
1103 return em28xx_register_extension(&dvb_ops);
1104}
1105
1106static void __exit em28xx_dvb_unregister(void)
1107{
1108 em28xx_unregister_extension(&dvb_ops);
1109}
1110
1111module_init(em28xx_dvb_register);
1112module_exit(em28xx_dvb_unregister);
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