Commit | Line | Data |
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c109f816 EA |
1 | /* |
2 | * Driver for the ov9650 sensor | |
3 | * | |
0c505e68 | 4 | * Copyright (C) 2008 Erik Andrén |
c109f816 EA |
5 | * Copyright (C) 2007 Ilyes Gouta. Based on the m5603x Linux Driver Project. |
6 | * Copyright (C) 2005 m5603x Linux Driver Project <m5602@x3ng.com.br> | |
7 | * | |
8 | * Portions of code to USB interface and ALi driver software, | |
9 | * Copyright (c) 2006 Willem Duinker | |
10 | * v4l2 interface modeled after the V4L2 driver | |
11 | * for SN9C10x PC Camera Controllers | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation, version 2. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include "m5602_ov9650.h" | |
20 | ||
cf811d50 EA |
21 | static int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val); |
22 | static int ov9650_get_exposure(struct gspca_dev *gspca_dev, __s32 *val); | |
23 | static int ov9650_get_gain(struct gspca_dev *gspca_dev, __s32 *val); | |
24 | static int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val); | |
25 | static int ov9650_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val); | |
26 | static int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val); | |
27 | static int ov9650_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val); | |
28 | static int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val); | |
29 | static int ov9650_get_hflip(struct gspca_dev *gspca_dev, __s32 *val); | |
30 | static int ov9650_set_hflip(struct gspca_dev *gspca_dev, __s32 val); | |
31 | static int ov9650_get_vflip(struct gspca_dev *gspca_dev, __s32 *val); | |
32 | static int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val); | |
33 | static int ov9650_get_auto_white_balance(struct gspca_dev *gspca_dev, | |
34 | __s32 *val); | |
35 | static int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev, | |
36 | __s32 val); | |
37 | static int ov9650_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val); | |
38 | static int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val); | |
9ae16577 EA |
39 | static int ov9650_get_auto_exposure(struct gspca_dev *gspca_dev, __s32 *val); |
40 | static int ov9650_set_auto_exposure(struct gspca_dev *gspca_dev, __s32 val); | |
cf811d50 | 41 | |
30881ab7 EA |
42 | /* Vertically and horizontally flips the image if matched, needed for machines |
43 | where the sensor is mounted upside down */ | |
44 | static | |
45 | const | |
46 | struct dmi_system_id ov9650_flip_dmi_table[] = { | |
47 | { | |
926b3b41 | 48 | .ident = "ASUS A6Ja", |
201a8a6c JK |
49 | .matches = { |
50 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 51 | DMI_MATCH(DMI_PRODUCT_NAME, "A6J") |
201a8a6c JK |
52 | } |
53 | }, | |
54 | { | |
926b3b41 | 55 | .ident = "ASUS A6JC", |
30881ab7 EA |
56 | .matches = { |
57 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 58 | DMI_MATCH(DMI_PRODUCT_NAME, "A6JC") |
30881ab7 EA |
59 | } |
60 | }, | |
61 | { | |
926b3b41 | 62 | .ident = "ASUS A6K", |
30881ab7 EA |
63 | .matches = { |
64 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 65 | DMI_MATCH(DMI_PRODUCT_NAME, "A6K") |
30881ab7 EA |
66 | } |
67 | }, | |
68 | { | |
926b3b41 | 69 | .ident = "ASUS A6Kt", |
30881ab7 EA |
70 | .matches = { |
71 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 72 | DMI_MATCH(DMI_PRODUCT_NAME, "A6Kt") |
30881ab7 EA |
73 | } |
74 | }, | |
3efb6bda | 75 | { |
926b3b41 | 76 | .ident = "ASUS A6VA", |
3efb6bda EA |
77 | .matches = { |
78 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 79 | DMI_MATCH(DMI_PRODUCT_NAME, "A6VA") |
3efb6bda EA |
80 | } |
81 | }, | |
30881ab7 | 82 | { |
926b3b41 EA |
83 | |
84 | .ident = "ASUS A6VC", | |
30881ab7 EA |
85 | .matches = { |
86 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 87 | DMI_MATCH(DMI_PRODUCT_NAME, "A6VC") |
30881ab7 EA |
88 | } |
89 | }, | |
951872a8 | 90 | { |
926b3b41 | 91 | .ident = "ASUS A6VM", |
951872a8 EA |
92 | .matches = { |
93 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 94 | DMI_MATCH(DMI_PRODUCT_NAME, "A6VM") |
951872a8 EA |
95 | } |
96 | }, | |
40a4f2fc | 97 | { |
926b3b41 | 98 | .ident = "ASUS A7V", |
40a4f2fc EA |
99 | .matches = { |
100 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
926b3b41 | 101 | DMI_MATCH(DMI_PRODUCT_NAME, "A7V") |
40a4f2fc EA |
102 | } |
103 | }, | |
7e08e66a EA |
104 | { |
105 | .ident = "Alienware Aurora m9700", | |
106 | .matches = { | |
107 | DMI_MATCH(DMI_SYS_VENDOR, "alienware"), | |
108 | DMI_MATCH(DMI_PRODUCT_NAME, "Aurora m9700") | |
109 | } | |
110 | }, | |
7460f524 | 111 | {} |
30881ab7 EA |
112 | }; |
113 | ||
2e03669d | 114 | static const struct ctrl ov9650_ctrls[] = { |
be63b722 | 115 | #define EXPOSURE_IDX 0 |
e17cc08c EA |
116 | { |
117 | { | |
118 | .id = V4L2_CID_EXPOSURE, | |
119 | .type = V4L2_CTRL_TYPE_INTEGER, | |
120 | .name = "exposure", | |
121 | .minimum = 0x00, | |
7136e705 EA |
122 | .maximum = 0x1ff, |
123 | .step = 0x4, | |
780e3121 JFM |
124 | .default_value = EXPOSURE_DEFAULT, |
125 | .flags = V4L2_CTRL_FLAG_SLIDER | |
e17cc08c EA |
126 | }, |
127 | .set = ov9650_set_exposure, | |
128 | .get = ov9650_get_exposure | |
be63b722 EA |
129 | }, |
130 | #define GAIN_IDX 1 | |
131 | { | |
e17cc08c EA |
132 | { |
133 | .id = V4L2_CID_GAIN, | |
134 | .type = V4L2_CTRL_TYPE_INTEGER, | |
135 | .name = "gain", | |
136 | .minimum = 0x00, | |
137 | .maximum = 0x3ff, | |
138 | .step = 0x1, | |
139 | .default_value = GAIN_DEFAULT, | |
140 | .flags = V4L2_CTRL_FLAG_SLIDER | |
141 | }, | |
142 | .set = ov9650_set_gain, | |
143 | .get = ov9650_get_gain | |
be63b722 EA |
144 | }, |
145 | #define RED_BALANCE_IDX 2 | |
146 | { | |
e17cc08c | 147 | { |
4db120bc | 148 | .id = V4L2_CID_RED_BALANCE, |
780e3121 JFM |
149 | .type = V4L2_CTRL_TYPE_INTEGER, |
150 | .name = "red balance", | |
151 | .minimum = 0x00, | |
152 | .maximum = 0xff, | |
153 | .step = 0x1, | |
154 | .default_value = RED_GAIN_DEFAULT, | |
155 | .flags = V4L2_CTRL_FLAG_SLIDER | |
e17cc08c EA |
156 | }, |
157 | .set = ov9650_set_red_balance, | |
158 | .get = ov9650_get_red_balance | |
be63b722 EA |
159 | }, |
160 | #define BLUE_BALANCE_IDX 3 | |
161 | { | |
e17cc08c | 162 | { |
4db120bc | 163 | .id = V4L2_CID_BLUE_BALANCE, |
780e3121 JFM |
164 | .type = V4L2_CTRL_TYPE_INTEGER, |
165 | .name = "blue balance", | |
166 | .minimum = 0x00, | |
167 | .maximum = 0xff, | |
168 | .step = 0x1, | |
169 | .default_value = BLUE_GAIN_DEFAULT, | |
170 | .flags = V4L2_CTRL_FLAG_SLIDER | |
e17cc08c EA |
171 | }, |
172 | .set = ov9650_set_blue_balance, | |
173 | .get = ov9650_get_blue_balance | |
be63b722 EA |
174 | }, |
175 | #define HFLIP_IDX 4 | |
176 | { | |
e17cc08c | 177 | { |
780e3121 JFM |
178 | .id = V4L2_CID_HFLIP, |
179 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
180 | .name = "horizontal flip", | |
181 | .minimum = 0, | |
182 | .maximum = 1, | |
183 | .step = 1, | |
184 | .default_value = 0 | |
e17cc08c EA |
185 | }, |
186 | .set = ov9650_set_hflip, | |
187 | .get = ov9650_get_hflip | |
be63b722 EA |
188 | }, |
189 | #define VFLIP_IDX 5 | |
190 | { | |
e17cc08c | 191 | { |
780e3121 JFM |
192 | .id = V4L2_CID_VFLIP, |
193 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
194 | .name = "vertical flip", | |
195 | .minimum = 0, | |
196 | .maximum = 1, | |
197 | .step = 1, | |
198 | .default_value = 0 | |
e17cc08c EA |
199 | }, |
200 | .set = ov9650_set_vflip, | |
201 | .get = ov9650_get_vflip | |
be63b722 EA |
202 | }, |
203 | #define AUTO_WHITE_BALANCE_IDX 6 | |
204 | { | |
e17cc08c | 205 | { |
780e3121 JFM |
206 | .id = V4L2_CID_AUTO_WHITE_BALANCE, |
207 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
208 | .name = "auto white balance", | |
209 | .minimum = 0, | |
210 | .maximum = 1, | |
211 | .step = 1, | |
212 | .default_value = 1 | |
e17cc08c EA |
213 | }, |
214 | .set = ov9650_set_auto_white_balance, | |
215 | .get = ov9650_get_auto_white_balance | |
be63b722 EA |
216 | }, |
217 | #define AUTO_GAIN_CTRL_IDX 7 | |
218 | { | |
e17cc08c | 219 | { |
780e3121 JFM |
220 | .id = V4L2_CID_AUTOGAIN, |
221 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
222 | .name = "auto gain control", | |
223 | .minimum = 0, | |
224 | .maximum = 1, | |
225 | .step = 1, | |
226 | .default_value = 1 | |
e17cc08c EA |
227 | }, |
228 | .set = ov9650_set_auto_gain, | |
229 | .get = ov9650_get_auto_gain | |
9ae16577 EA |
230 | }, |
231 | #define AUTO_EXPOSURE_IDX 8 | |
232 | { | |
233 | { | |
780e3121 JFM |
234 | .id = V4L2_CID_EXPOSURE_AUTO, |
235 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
236 | .name = "auto exposure", | |
237 | .minimum = 0, | |
238 | .maximum = 1, | |
239 | .step = 1, | |
240 | .default_value = 1 | |
9ae16577 EA |
241 | }, |
242 | .set = ov9650_set_auto_exposure, | |
243 | .get = ov9650_get_auto_exposure | |
e17cc08c | 244 | } |
9ae16577 | 245 | |
e17cc08c EA |
246 | }; |
247 | ||
74cadfe1 EA |
248 | static struct v4l2_pix_format ov9650_modes[] = { |
249 | { | |
250 | 176, | |
251 | 144, | |
252 | V4L2_PIX_FMT_SBGGR8, | |
253 | V4L2_FIELD_NONE, | |
254 | .sizeimage = | |
255 | 176 * 144, | |
256 | .bytesperline = 176, | |
257 | .colorspace = V4L2_COLORSPACE_SRGB, | |
bd99ffbd | 258 | .priv = 9 |
74cadfe1 EA |
259 | }, { |
260 | 320, | |
261 | 240, | |
262 | V4L2_PIX_FMT_SBGGR8, | |
263 | V4L2_FIELD_NONE, | |
264 | .sizeimage = | |
265 | 320 * 240, | |
266 | .bytesperline = 320, | |
267 | .colorspace = V4L2_COLORSPACE_SRGB, | |
bd99ffbd | 268 | .priv = 8 |
74cadfe1 EA |
269 | }, { |
270 | 352, | |
271 | 288, | |
272 | V4L2_PIX_FMT_SBGGR8, | |
273 | V4L2_FIELD_NONE, | |
274 | .sizeimage = | |
275 | 352 * 288, | |
276 | .bytesperline = 352, | |
277 | .colorspace = V4L2_COLORSPACE_SRGB, | |
bd99ffbd | 278 | .priv = 9 |
74cadfe1 EA |
279 | }, { |
280 | 640, | |
281 | 480, | |
282 | V4L2_PIX_FMT_SBGGR8, | |
283 | V4L2_FIELD_NONE, | |
284 | .sizeimage = | |
285 | 640 * 480, | |
286 | .bytesperline = 640, | |
287 | .colorspace = V4L2_COLORSPACE_SRGB, | |
bd99ffbd | 288 | .priv = 9 |
74cadfe1 EA |
289 | } |
290 | }; | |
291 | ||
658efb63 EA |
292 | static void ov9650_dump_registers(struct sd *sd); |
293 | ||
c109f816 EA |
294 | int ov9650_probe(struct sd *sd) |
295 | { | |
6b055500 | 296 | int err = 0; |
c109f816 | 297 | u8 prod_id = 0, ver_id = 0, i; |
d9c700d4 | 298 | s32 *sensor_settings; |
c109f816 EA |
299 | |
300 | if (force_sensor) { | |
301 | if (force_sensor == OV9650_SENSOR) { | |
302 | info("Forcing an %s sensor", ov9650.name); | |
303 | goto sensor_found; | |
304 | } | |
305 | /* If we want to force another sensor, | |
306 | don't try to probe this one */ | |
307 | return -ENODEV; | |
308 | } | |
309 | ||
969cc926 | 310 | PDEBUG(D_PROBE, "Probing for an ov9650 sensor"); |
c109f816 | 311 | |
7460f524 | 312 | /* Run the pre-init before probing the sensor */ |
6b055500 | 313 | for (i = 0; i < ARRAY_SIZE(preinit_ov9650) && !err; i++) { |
c109f816 EA |
314 | u8 data = preinit_ov9650[i][2]; |
315 | if (preinit_ov9650[i][0] == SENSOR) | |
6b055500 | 316 | err = m5602_write_sensor(sd, |
d9c700d4 | 317 | preinit_ov9650[i][1], &data, 1); |
c109f816 | 318 | else |
d9c700d4 EA |
319 | err = m5602_write_bridge(sd, |
320 | preinit_ov9650[i][1], data); | |
c109f816 EA |
321 | } |
322 | ||
6b055500 EA |
323 | if (err < 0) |
324 | return err; | |
325 | ||
905aabaf | 326 | if (m5602_read_sensor(sd, OV9650_PID, &prod_id, 1)) |
c109f816 EA |
327 | return -ENODEV; |
328 | ||
905aabaf | 329 | if (m5602_read_sensor(sd, OV9650_VER, &ver_id, 1)) |
c109f816 EA |
330 | return -ENODEV; |
331 | ||
332 | if ((prod_id == 0x96) && (ver_id == 0x52)) { | |
333 | info("Detected an ov9650 sensor"); | |
334 | goto sensor_found; | |
335 | } | |
c109f816 EA |
336 | return -ENODEV; |
337 | ||
338 | sensor_found: | |
d9c700d4 EA |
339 | sensor_settings = kmalloc( |
340 | ARRAY_SIZE(ov9650_ctrls) * sizeof(s32), GFP_KERNEL); | |
341 | if (!sensor_settings) | |
342 | return -ENOMEM; | |
343 | ||
74cadfe1 EA |
344 | sd->gspca_dev.cam.cam_mode = ov9650_modes; |
345 | sd->gspca_dev.cam.nmodes = ARRAY_SIZE(ov9650_modes); | |
e17cc08c | 346 | sd->desc->ctrls = ov9650_ctrls; |
e4cc4fcc | 347 | sd->desc->nctrls = ARRAY_SIZE(ov9650_ctrls); |
d9c700d4 EA |
348 | |
349 | for (i = 0; i < ARRAY_SIZE(ov9650_ctrls); i++) | |
350 | sensor_settings[i] = ov9650_ctrls[i].qctrl.default_value; | |
351 | sd->sensor_priv = sensor_settings; | |
c109f816 EA |
352 | return 0; |
353 | } | |
354 | ||
355 | int ov9650_init(struct sd *sd) | |
356 | { | |
357 | int i, err = 0; | |
358 | u8 data; | |
7460f524 | 359 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 EA |
360 | |
361 | if (dump_sensor) | |
362 | ov9650_dump_registers(sd); | |
363 | ||
364 | for (i = 0; i < ARRAY_SIZE(init_ov9650) && !err; i++) { | |
365 | data = init_ov9650[i][2]; | |
366 | if (init_ov9650[i][0] == SENSOR) | |
6dc4cff0 | 367 | err = m5602_write_sensor(sd, init_ov9650[i][1], |
c109f816 EA |
368 | &data, 1); |
369 | else | |
370 | err = m5602_write_bridge(sd, init_ov9650[i][1], data); | |
371 | } | |
372 | ||
cf811d50 EA |
373 | err = ov9650_set_exposure(&sd->gspca_dev, |
374 | sensor_settings[EXPOSURE_IDX]); | |
7460f524 EA |
375 | if (err < 0) |
376 | return err; | |
377 | ||
378 | err = ov9650_set_gain(&sd->gspca_dev, sensor_settings[GAIN_IDX]); | |
379 | if (err < 0) | |
380 | return err; | |
381 | ||
cf811d50 EA |
382 | err = ov9650_set_red_balance(&sd->gspca_dev, |
383 | sensor_settings[RED_BALANCE_IDX]); | |
7460f524 EA |
384 | if (err < 0) |
385 | return err; | |
386 | ||
cf811d50 EA |
387 | err = ov9650_set_blue_balance(&sd->gspca_dev, |
388 | sensor_settings[BLUE_BALANCE_IDX]); | |
7460f524 EA |
389 | if (err < 0) |
390 | return err; | |
391 | ||
392 | err = ov9650_set_hflip(&sd->gspca_dev, sensor_settings[HFLIP_IDX]); | |
393 | if (err < 0) | |
394 | return err; | |
395 | ||
396 | err = ov9650_set_vflip(&sd->gspca_dev, sensor_settings[VFLIP_IDX]); | |
397 | if (err < 0) | |
398 | return err; | |
399 | ||
9ae16577 EA |
400 | err = ov9650_set_auto_exposure(&sd->gspca_dev, |
401 | sensor_settings[AUTO_EXPOSURE_IDX]); | |
402 | if (err < 0) | |
403 | return err; | |
404 | ||
cf811d50 EA |
405 | err = ov9650_set_auto_white_balance(&sd->gspca_dev, |
406 | sensor_settings[AUTO_WHITE_BALANCE_IDX]); | |
7460f524 EA |
407 | if (err < 0) |
408 | return err; | |
409 | ||
cf811d50 | 410 | err = ov9650_set_auto_gain(&sd->gspca_dev, |
9ae16577 | 411 | sensor_settings[AUTO_GAIN_CTRL_IDX]); |
e07b14e8 | 412 | return err; |
c109f816 EA |
413 | } |
414 | ||
082aa893 EA |
415 | int ov9650_start(struct sd *sd) |
416 | { | |
bd99ffbd | 417 | u8 data; |
082aa893 EA |
418 | int i, err = 0; |
419 | struct cam *cam = &sd->gspca_dev.cam; | |
be63b722 EA |
420 | s32 *sensor_settings = sd->sensor_priv; |
421 | ||
bd99ffbd EA |
422 | int width = cam->cam_mode[sd->gspca_dev.curr_mode].width; |
423 | int height = cam->cam_mode[sd->gspca_dev.curr_mode].height; | |
424 | int ver_offs = cam->cam_mode[sd->gspca_dev.curr_mode].priv; | |
425 | int hor_offs = OV9650_LEFT_OFFSET; | |
426 | ||
6f02d761 EA |
427 | if ((!dmi_check_system(ov9650_flip_dmi_table) && |
428 | sensor_settings[VFLIP_IDX]) || | |
429 | (dmi_check_system(ov9650_flip_dmi_table) && | |
430 | !sensor_settings[VFLIP_IDX])) | |
be63b722 EA |
431 | ver_offs--; |
432 | ||
bd99ffbd EA |
433 | if (width <= 320) |
434 | hor_offs /= 2; | |
082aa893 | 435 | |
bd99ffbd | 436 | /* Synthesize the vsync/hsync setup */ |
3d3ec926 EA |
437 | for (i = 0; i < ARRAY_SIZE(res_init_ov9650) && !err; i++) { |
438 | if (res_init_ov9650[i][0] == BRIDGE) | |
4eecb176 EA |
439 | err = m5602_write_bridge(sd, res_init_ov9650[i][1], |
440 | res_init_ov9650[i][2]); | |
3d3ec926 | 441 | else if (res_init_ov9650[i][0] == SENSOR) { |
83955556 | 442 | data = res_init_ov9650[i][2]; |
4eecb176 EA |
443 | err = m5602_write_sensor(sd, |
444 | res_init_ov9650[i][1], &data, 1); | |
3d3ec926 EA |
445 | } |
446 | } | |
27b1e4ca EA |
447 | if (err < 0) |
448 | return err; | |
449 | ||
d9c700d4 EA |
450 | err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, |
451 | ((ver_offs >> 8) & 0xff)); | |
bd99ffbd EA |
452 | if (err < 0) |
453 | return err; | |
454 | ||
455 | err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (ver_offs & 0xff)); | |
456 | if (err < 0) | |
457 | return err; | |
458 | ||
459 | err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, 0); | |
460 | if (err < 0) | |
461 | return err; | |
462 | ||
463 | err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height >> 8) & 0xff); | |
464 | if (err < 0) | |
465 | return err; | |
466 | ||
467 | err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height & 0xff)); | |
468 | if (err < 0) | |
469 | return err; | |
470 | ||
d9c700d4 | 471 | for (i = 0; i < 2 && !err; i++) |
bd99ffbd | 472 | err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, 0); |
bd99ffbd EA |
473 | if (err < 0) |
474 | return err; | |
475 | ||
b05a4ad9 EA |
476 | err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0); |
477 | if (err < 0) | |
478 | return err; | |
479 | ||
480 | err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 2); | |
481 | if (err < 0) | |
482 | return err; | |
483 | ||
d9c700d4 EA |
484 | err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, |
485 | (hor_offs >> 8) & 0xff); | |
bd99ffbd EA |
486 | if (err < 0) |
487 | return err; | |
488 | ||
489 | err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, hor_offs & 0xff); | |
490 | if (err < 0) | |
491 | return err; | |
492 | ||
d9c700d4 EA |
493 | err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, |
494 | ((width + hor_offs) >> 8) & 0xff); | |
bd99ffbd EA |
495 | if (err < 0) |
496 | return err; | |
497 | ||
d9c700d4 EA |
498 | err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, |
499 | ((width + hor_offs) & 0xff)); | |
bd99ffbd EA |
500 | if (err < 0) |
501 | return err; | |
502 | ||
b05a4ad9 EA |
503 | err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0); |
504 | if (err < 0) | |
505 | return err; | |
506 | ||
bd99ffbd | 507 | switch (width) { |
082aa893 EA |
508 | case 640: |
509 | PDEBUG(D_V4L2, "Configuring camera for VGA mode"); | |
510 | ||
bd99ffbd EA |
511 | data = OV9650_VGA_SELECT | OV9650_RGB_SELECT | |
512 | OV9650_RAW_RGB_SELECT; | |
bd99ffbd | 513 | err = m5602_write_sensor(sd, OV9650_COM7, &data, 1); |
082aa893 | 514 | break; |
3b2f3327 | 515 | |
03f46de9 EA |
516 | case 352: |
517 | PDEBUG(D_V4L2, "Configuring camera for CIF mode"); | |
518 | ||
bd99ffbd EA |
519 | data = OV9650_CIF_SELECT | OV9650_RGB_SELECT | |
520 | OV9650_RAW_RGB_SELECT; | |
bd99ffbd | 521 | err = m5602_write_sensor(sd, OV9650_COM7, &data, 1); |
03f46de9 EA |
522 | break; |
523 | ||
3b2f3327 EA |
524 | case 320: |
525 | PDEBUG(D_V4L2, "Configuring camera for QVGA mode"); | |
526 | ||
bd99ffbd EA |
527 | data = OV9650_QVGA_SELECT | OV9650_RGB_SELECT | |
528 | OV9650_RAW_RGB_SELECT; | |
bd99ffbd | 529 | err = m5602_write_sensor(sd, OV9650_COM7, &data, 1); |
3b2f3327 | 530 | break; |
e31f9dd6 EA |
531 | |
532 | case 176: | |
533 | PDEBUG(D_V4L2, "Configuring camera for QCIF mode"); | |
534 | ||
bd99ffbd EA |
535 | data = OV9650_QCIF_SELECT | OV9650_RGB_SELECT | |
536 | OV9650_RAW_RGB_SELECT; | |
bd99ffbd EA |
537 | err = m5602_write_sensor(sd, OV9650_COM7, &data, 1); |
538 | break; | |
082aa893 EA |
539 | } |
540 | return err; | |
541 | } | |
542 | ||
3d3ec926 EA |
543 | int ov9650_stop(struct sd *sd) |
544 | { | |
545 | u8 data = OV9650_SOFT_SLEEP | OV9650_OUTPUT_DRIVE_2X; | |
546 | return m5602_write_sensor(sd, OV9650_COM2, &data, 1); | |
547 | } | |
548 | ||
d9c700d4 EA |
549 | void ov9650_disconnect(struct sd *sd) |
550 | { | |
551 | ov9650_stop(sd); | |
d9c700d4 EA |
552 | |
553 | sd->sensor = NULL; | |
d9c700d4 EA |
554 | kfree(sd->sensor_priv); |
555 | } | |
556 | ||
cf811d50 | 557 | static int ov9650_get_exposure(struct gspca_dev *gspca_dev, __s32 *val) |
c109f816 EA |
558 | { |
559 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 | 560 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 561 | |
be63b722 | 562 | *val = sensor_settings[EXPOSURE_IDX]; |
17ea88ae | 563 | PDEBUG(D_V4L2, "Read exposure %d", *val); |
be63b722 | 564 | return 0; |
c109f816 EA |
565 | } |
566 | ||
cf811d50 | 567 | static int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val) |
c109f816 EA |
568 | { |
569 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 | 570 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 EA |
571 | u8 i2c_data; |
572 | int err; | |
573 | ||
be63b722 EA |
574 | PDEBUG(D_V4L2, "Set exposure to %d", val); |
575 | ||
576 | sensor_settings[EXPOSURE_IDX] = val; | |
c109f816 EA |
577 | /* The 6 MSBs */ |
578 | i2c_data = (val >> 10) & 0x3f; | |
6dc4cff0 | 579 | err = m5602_write_sensor(sd, OV9650_AECHM, |
c109f816 EA |
580 | &i2c_data, 1); |
581 | if (err < 0) | |
051781b3 | 582 | return err; |
c109f816 EA |
583 | |
584 | /* The 8 middle bits */ | |
585 | i2c_data = (val >> 2) & 0xff; | |
6dc4cff0 | 586 | err = m5602_write_sensor(sd, OV9650_AECH, |
c109f816 EA |
587 | &i2c_data, 1); |
588 | if (err < 0) | |
051781b3 | 589 | return err; |
c109f816 EA |
590 | |
591 | /* The 2 LSBs */ | |
592 | i2c_data = val & 0x03; | |
6dc4cff0 | 593 | err = m5602_write_sensor(sd, OV9650_COM1, &i2c_data, 1); |
e07b14e8 | 594 | return err; |
c109f816 EA |
595 | } |
596 | ||
cf811d50 | 597 | static int ov9650_get_gain(struct gspca_dev *gspca_dev, __s32 *val) |
c109f816 | 598 | { |
c109f816 | 599 | struct sd *sd = (struct sd *) gspca_dev; |
be63b722 | 600 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 601 | |
be63b722 | 602 | *val = sensor_settings[GAIN_IDX]; |
17ea88ae | 603 | PDEBUG(D_V4L2, "Read gain %d", *val); |
be63b722 | 604 | return 0; |
c109f816 EA |
605 | } |
606 | ||
cf811d50 | 607 | static int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val) |
c109f816 EA |
608 | { |
609 | int err; | |
610 | u8 i2c_data; | |
611 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 EA |
612 | s32 *sensor_settings = sd->sensor_priv; |
613 | ||
614 | PDEBUG(D_V4L2, "Setting gain to %d", val); | |
615 | ||
616 | sensor_settings[GAIN_IDX] = val; | |
c109f816 EA |
617 | |
618 | /* The 2 MSB */ | |
619 | /* Read the OV9650_VREF register first to avoid | |
620 | corrupting the VREF high and low bits */ | |
6b055500 EA |
621 | err = m5602_read_sensor(sd, OV9650_VREF, &i2c_data, 1); |
622 | if (err < 0) | |
623 | return err; | |
624 | ||
c109f816 EA |
625 | /* Mask away all uninteresting bits */ |
626 | i2c_data = ((val & 0x0300) >> 2) | | |
627 | (i2c_data & 0x3F); | |
6dc4cff0 | 628 | err = m5602_write_sensor(sd, OV9650_VREF, &i2c_data, 1); |
6b055500 EA |
629 | if (err < 0) |
630 | return err; | |
c109f816 EA |
631 | |
632 | /* The 8 LSBs */ | |
633 | i2c_data = val & 0xff; | |
6dc4cff0 | 634 | err = m5602_write_sensor(sd, OV9650_GAIN, &i2c_data, 1); |
e07b14e8 | 635 | return err; |
c109f816 EA |
636 | } |
637 | ||
cf811d50 | 638 | static int ov9650_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val) |
c109f816 | 639 | { |
c109f816 | 640 | struct sd *sd = (struct sd *) gspca_dev; |
be63b722 | 641 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 642 | |
be63b722 | 643 | *val = sensor_settings[RED_BALANCE_IDX]; |
17ea88ae | 644 | PDEBUG(D_V4L2, "Read red gain %d", *val); |
be63b722 | 645 | return 0; |
c109f816 EA |
646 | } |
647 | ||
cf811d50 | 648 | static int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val) |
c109f816 EA |
649 | { |
650 | int err; | |
651 | u8 i2c_data; | |
652 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 | 653 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 654 | |
be63b722 EA |
655 | PDEBUG(D_V4L2, "Set red gain to %d", val); |
656 | ||
657 | sensor_settings[RED_BALANCE_IDX] = val; | |
c109f816 EA |
658 | |
659 | i2c_data = val & 0xff; | |
6dc4cff0 | 660 | err = m5602_write_sensor(sd, OV9650_RED, &i2c_data, 1); |
e07b14e8 | 661 | return err; |
c109f816 EA |
662 | } |
663 | ||
cf811d50 | 664 | static int ov9650_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val) |
c109f816 | 665 | { |
c109f816 | 666 | struct sd *sd = (struct sd *) gspca_dev; |
be63b722 | 667 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 668 | |
be63b722 | 669 | *val = sensor_settings[BLUE_BALANCE_IDX]; |
17ea88ae | 670 | PDEBUG(D_V4L2, "Read blue gain %d", *val); |
c109f816 | 671 | |
be63b722 | 672 | return 0; |
c109f816 EA |
673 | } |
674 | ||
cf811d50 | 675 | static int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val) |
c109f816 EA |
676 | { |
677 | int err; | |
678 | u8 i2c_data; | |
679 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 EA |
680 | s32 *sensor_settings = sd->sensor_priv; |
681 | ||
682 | PDEBUG(D_V4L2, "Set blue gain to %d", val); | |
c109f816 | 683 | |
be63b722 | 684 | sensor_settings[BLUE_BALANCE_IDX] = val; |
c109f816 EA |
685 | |
686 | i2c_data = val & 0xff; | |
6dc4cff0 | 687 | err = m5602_write_sensor(sd, OV9650_BLUE, &i2c_data, 1); |
e07b14e8 | 688 | return err; |
c109f816 EA |
689 | } |
690 | ||
cf811d50 | 691 | static int ov9650_get_hflip(struct gspca_dev *gspca_dev, __s32 *val) |
c109f816 | 692 | { |
c109f816 | 693 | struct sd *sd = (struct sd *) gspca_dev; |
be63b722 | 694 | s32 *sensor_settings = sd->sensor_priv; |
3c19a954 | 695 | |
be63b722 | 696 | *val = sensor_settings[HFLIP_IDX]; |
17ea88ae | 697 | PDEBUG(D_V4L2, "Read horizontal flip %d", *val); |
be63b722 | 698 | return 0; |
c109f816 EA |
699 | } |
700 | ||
cf811d50 | 701 | static int ov9650_set_hflip(struct gspca_dev *gspca_dev, __s32 val) |
c109f816 EA |
702 | { |
703 | int err; | |
704 | u8 i2c_data; | |
705 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 | 706 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 707 | |
17ea88ae | 708 | PDEBUG(D_V4L2, "Set horizontal flip to %d", val); |
be63b722 EA |
709 | |
710 | sensor_settings[HFLIP_IDX] = val; | |
6f02d761 EA |
711 | |
712 | if (!dmi_check_system(ov9650_flip_dmi_table)) | |
cf811d50 EA |
713 | i2c_data = ((val & 0x01) << 5) | |
714 | (sensor_settings[VFLIP_IDX] << 4); | |
6f02d761 | 715 | else |
cf811d50 EA |
716 | i2c_data = ((val & 0x01) << 5) | |
717 | (!sensor_settings[VFLIP_IDX] << 4); | |
6f02d761 | 718 | |
6dc4cff0 | 719 | err = m5602_write_sensor(sd, OV9650_MVFP, &i2c_data, 1); |
051781b3 | 720 | |
e07b14e8 | 721 | return err; |
c109f816 EA |
722 | } |
723 | ||
cf811d50 | 724 | static int ov9650_get_vflip(struct gspca_dev *gspca_dev, __s32 *val) |
c109f816 | 725 | { |
c109f816 | 726 | struct sd *sd = (struct sd *) gspca_dev; |
be63b722 | 727 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 728 | |
be63b722 | 729 | *val = sensor_settings[VFLIP_IDX]; |
17ea88ae | 730 | PDEBUG(D_V4L2, "Read vertical flip %d", *val); |
c109f816 | 731 | |
be63b722 | 732 | return 0; |
c109f816 EA |
733 | } |
734 | ||
cf811d50 | 735 | static int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val) |
c109f816 EA |
736 | { |
737 | int err; | |
738 | u8 i2c_data; | |
739 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 | 740 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 741 | |
17ea88ae | 742 | PDEBUG(D_V4L2, "Set vertical flip to %d", val); |
be63b722 | 743 | sensor_settings[VFLIP_IDX] = val; |
c109f816 | 744 | |
6f02d761 EA |
745 | if (dmi_check_system(ov9650_flip_dmi_table)) |
746 | val = !val; | |
747 | ||
5196d7c6 | 748 | i2c_data = ((val & 0x01) << 4) | (sensor_settings[VFLIP_IDX] << 5); |
6dc4cff0 | 749 | err = m5602_write_sensor(sd, OV9650_MVFP, &i2c_data, 1); |
be63b722 EA |
750 | if (err < 0) |
751 | return err; | |
752 | ||
5196d7c6 | 753 | /* When vflip is toggled we need to readjust the bridge hsync/vsync */ |
be63b722 EA |
754 | if (gspca_dev->streaming) |
755 | err = ov9650_start(sd); | |
756 | ||
e07b14e8 | 757 | return err; |
c109f816 EA |
758 | } |
759 | ||
9ae16577 EA |
760 | static int ov9650_get_auto_exposure(struct gspca_dev *gspca_dev, __s32 *val) |
761 | { | |
762 | struct sd *sd = (struct sd *) gspca_dev; | |
763 | s32 *sensor_settings = sd->sensor_priv; | |
764 | ||
765 | *val = sensor_settings[AUTO_EXPOSURE_IDX]; | |
766 | PDEBUG(D_V4L2, "Read auto exposure control %d", *val); | |
767 | return 0; | |
768 | } | |
769 | ||
770 | static int ov9650_set_auto_exposure(struct gspca_dev *gspca_dev, | |
771 | __s32 val) | |
772 | { | |
773 | int err; | |
774 | u8 i2c_data; | |
775 | struct sd *sd = (struct sd *) gspca_dev; | |
776 | s32 *sensor_settings = sd->sensor_priv; | |
777 | ||
778 | PDEBUG(D_V4L2, "Set auto exposure control to %d", val); | |
779 | ||
780 | sensor_settings[AUTO_EXPOSURE_IDX] = val; | |
781 | err = m5602_read_sensor(sd, OV9650_COM8, &i2c_data, 1); | |
782 | if (err < 0) | |
783 | return err; | |
784 | ||
785 | i2c_data = ((i2c_data & 0xfe) | ((val & 0x01) << 0)); | |
786 | ||
787 | return m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1); | |
788 | } | |
789 | ||
cf811d50 EA |
790 | static int ov9650_get_auto_white_balance(struct gspca_dev *gspca_dev, |
791 | __s32 *val) | |
c109f816 | 792 | { |
c109f816 | 793 | struct sd *sd = (struct sd *) gspca_dev; |
be63b722 | 794 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 795 | |
be63b722 EA |
796 | *val = sensor_settings[AUTO_WHITE_BALANCE_IDX]; |
797 | return 0; | |
c109f816 EA |
798 | } |
799 | ||
cf811d50 EA |
800 | static int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev, |
801 | __s32 val) | |
c109f816 EA |
802 | { |
803 | int err; | |
804 | u8 i2c_data; | |
805 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 | 806 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 807 | |
17ea88ae | 808 | PDEBUG(D_V4L2, "Set auto white balance to %d", val); |
be63b722 EA |
809 | |
810 | sensor_settings[AUTO_WHITE_BALANCE_IDX] = val; | |
905aabaf | 811 | err = m5602_read_sensor(sd, OV9650_COM8, &i2c_data, 1); |
c109f816 | 812 | if (err < 0) |
051781b3 | 813 | return err; |
c109f816 EA |
814 | |
815 | i2c_data = ((i2c_data & 0xfd) | ((val & 0x01) << 1)); | |
6dc4cff0 | 816 | err = m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1); |
051781b3 | 817 | |
e07b14e8 | 818 | return err; |
c109f816 EA |
819 | } |
820 | ||
cf811d50 | 821 | static int ov9650_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val) |
c109f816 | 822 | { |
c109f816 | 823 | struct sd *sd = (struct sd *) gspca_dev; |
be63b722 | 824 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 825 | |
be63b722 | 826 | *val = sensor_settings[AUTO_GAIN_CTRL_IDX]; |
17ea88ae | 827 | PDEBUG(D_V4L2, "Read auto gain control %d", *val); |
be63b722 | 828 | return 0; |
c109f816 EA |
829 | } |
830 | ||
cf811d50 | 831 | static int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val) |
c109f816 EA |
832 | { |
833 | int err; | |
834 | u8 i2c_data; | |
835 | struct sd *sd = (struct sd *) gspca_dev; | |
be63b722 | 836 | s32 *sensor_settings = sd->sensor_priv; |
c109f816 | 837 | |
17ea88ae | 838 | PDEBUG(D_V4L2, "Set auto gain control to %d", val); |
be63b722 EA |
839 | |
840 | sensor_settings[AUTO_GAIN_CTRL_IDX] = val; | |
905aabaf | 841 | err = m5602_read_sensor(sd, OV9650_COM8, &i2c_data, 1); |
c109f816 | 842 | if (err < 0) |
051781b3 | 843 | return err; |
c109f816 EA |
844 | |
845 | i2c_data = ((i2c_data & 0xfb) | ((val & 0x01) << 2)); | |
051781b3 | 846 | |
9ae16577 | 847 | return m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1); |
c109f816 EA |
848 | } |
849 | ||
658efb63 | 850 | static void ov9650_dump_registers(struct sd *sd) |
c109f816 EA |
851 | { |
852 | int address; | |
853 | info("Dumping the ov9650 register state"); | |
854 | for (address = 0; address < 0xa9; address++) { | |
855 | u8 value; | |
905aabaf | 856 | m5602_read_sensor(sd, address, &value, 1); |
c109f816 EA |
857 | info("register 0x%x contains 0x%x", |
858 | address, value); | |
859 | } | |
860 | ||
861 | info("ov9650 register state dump complete"); | |
862 | ||
863 | info("Probing for which registers that are read/write"); | |
864 | for (address = 0; address < 0xff; address++) { | |
865 | u8 old_value, ctrl_value; | |
866 | u8 test_value[2] = {0xff, 0xff}; | |
867 | ||
905aabaf | 868 | m5602_read_sensor(sd, address, &old_value, 1); |
6dc4cff0 | 869 | m5602_write_sensor(sd, address, test_value, 1); |
905aabaf | 870 | m5602_read_sensor(sd, address, &ctrl_value, 1); |
c109f816 EA |
871 | |
872 | if (ctrl_value == test_value[0]) | |
873 | info("register 0x%x is writeable", address); | |
874 | else | |
875 | info("register 0x%x is read only", address); | |
876 | ||
877 | /* Restore original value */ | |
6dc4cff0 | 878 | m5602_write_sensor(sd, address, &old_value, 1); |
c109f816 EA |
879 | } |
880 | } |