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[media] gspca: Remove __devinit, __devinitconst and __devinitdata
[deliverable/linux.git] / drivers / media / video / gspca / ov519.c
CommitLineData
6a7eba24
JFM		 1/**
2 * OV519 driver
3 *
4 * Copyright (C) 2008 Jean-Francois Moine (http://moinejf.free.fr)
b46aaa02 5 * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
6a7eba24 6 *
2961e875
RB		 7 * This module is adapted from the ov51x-jpeg package, which itself
8 * was adapted from the ov511 driver.
9 *
10 * Original copyright for the ov511 driver is:
11 *
b46aaa02 12 * Copyright (c) 1999-2006 Mark W. McClelland
2961e875 13 * Support for OV519, OV8610 Copyright (c) 2003 Joerg Heckenbach
b46aaa02
HG		 14 * Many improvements by Bret Wallach <bwallac1@san.rr.com>
15 * Color fixes by by Orion Sky Lawlor <olawlor@acm.org> (2/26/2000)
16 * OV7620 fixes by Charl P. Botha <cpbotha@ieee.org>
17 * Changes by Claudio Matsuoka <claudio@conectiva.com>
2961e875
RB		 18 *
19 * ov51x-jpeg original copyright is:
20 *
21 * Copyright (c) 2004-2007 Romain Beauxis <toots@rastageeks.org>
22 * Support for OV7670 sensors was contributed by Sam Skipsey <aoanla@yahoo.com>
6a7eba24
JFM		 23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37 *
38 */
39#define MODULE_NAME "ov519"
40
417a4d26 41#include <linux/input.h>
6a7eba24
JFM		 42#include "gspca.h"
43
9a731a32
JFM		 44/* The jpeg_hdr is used by w996Xcf only */
45/* The CONEX_CAM define for jpeg.h needs renaming, now its used here too */
46#define CONEX_CAM
47#include "jpeg.h"
48
6a7eba24
JFM		 49MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
50MODULE_DESCRIPTION("OV519 USB Camera Driver");
51MODULE_LICENSE("GPL");
52
53/* global parameters */
54static int frame_rate;
55
56/* Number of times to retry a failed I2C transaction. Increase this if you
57 * are getting "Failed to read sensor ID..." */
58static int i2c_detect_tries = 10;
59
62833acd
JFM		 60/* controls */
61enum e_ctrl {
62 BRIGHTNESS,
63 CONTRAST,
64 COLORS,
65 HFLIP,
66 VFLIP,
67 AUTOBRIGHT,
68 FREQ,
69 NCTRL /* number of controls */
70};
71
6a7eba24
JFM		 72/* ov519 device descriptor */
73struct sd {
74 struct gspca_dev gspca_dev; /* !! must be the first item */
75
62833acd
JFM		 76 struct gspca_ctrl ctrls[NCTRL];
77
9d1593a8 78 u8 packet_nr;
92918a53 79
49809d6a
HG		 80 char bridge;
81#define BRIDGE_OV511 0
82#define BRIDGE_OV511PLUS 1
83#define BRIDGE_OV518 2
84#define BRIDGE_OV518PLUS 3
42e142f6 85#define BRIDGE_OV519 4 /* = ov530 */
635118d5 86#define BRIDGE_OVFX2 5
a511ba94 87#define BRIDGE_W9968CF 6
9e4d8258
HG		 88#define BRIDGE_MASK 7
89
90 char invert_led;
91#define BRIDGE_INVERT_LED 8
49809d6a 92
417a4d26
HG		 93 char snapshot_pressed;
94 char snapshot_needs_reset;
95
6a7eba24 96 /* Determined by sensor type */
9d1593a8 97 u8 sif;
6a7eba24 98
9d1593a8 99 u8 quality;
79b35902
HG		 100#define QUALITY_MIN 50
101#define QUALITY_MAX 70
102#define QUALITY_DEF 50
6a7eba24 103
9d1593a8
JFM		 104 u8 stopped; /* Streaming is temporarily paused */
105 u8 first_frame;
6a7eba24 106
9d1593a8
JFM		 107 u8 frame_rate; /* current Framerate */
108 u8 clockdiv; /* clockdiv override */
6a7eba24 109
7bbe6b8d 110 s8 sensor; /* Type of image sensor chip (SEN_*) */
a511ba94
HG		 111
112 u8 sensor_addr;
d6fa6638
JFM		 113 u16 sensor_width;
114 u16 sensor_height;
115 s16 sensor_reg_cache[256];
79b35902 116
9a731a32 117 u8 jpeg_hdr[JPEG_HDR_SZ];
6a7eba24 118};
7bbe6b8d
JFM		 119enum sensors {
120 SEN_OV2610,
121 SEN_OV3610,
122 SEN_OV6620,
123 SEN_OV6630,
124 SEN_OV66308AF,
125 SEN_OV7610,
126 SEN_OV7620,
127 SEN_OV7620AE,
128 SEN_OV7640,
129 SEN_OV7648,
42e142f6 130 SEN_OV7660,
7bbe6b8d
JFM		 131 SEN_OV7670,
132 SEN_OV76BE,
133 SEN_OV8610,
134};
6a7eba24 135
a511ba94
HG		 136/* Note this is a bit of a hack, but the w9968cf driver needs the code for all
137 the ov sensors which is already present here. When we have the time we
138 really should move the sensor drivers to v4l2 sub drivers. */
139#include "w996Xcf.c"
140
6a7eba24 141/* V4L2 controls supported by the driver */
49809d6a
HG		 142static void setbrightness(struct gspca_dev *gspca_dev);
143static void setcontrast(struct gspca_dev *gspca_dev);
144static void setcolors(struct gspca_dev *gspca_dev);
62833acd
JFM		 145static void sethvflip(struct gspca_dev *gspca_dev);
146static void setautobright(struct gspca_dev *gspca_dev);
147static void setfreq(struct gspca_dev *gspca_dev);
148static void setfreq_i(struct sd *sd);
6a7eba24 149
02ab18b0 150static const struct ctrl sd_ctrls[] = {
62833acd 151[BRIGHTNESS] = {
6a7eba24
JFM		 152 {
153 .id = V4L2_CID_BRIGHTNESS,
154 .type = V4L2_CTRL_TYPE_INTEGER,
155 .name = "Brightness",
156 .minimum = 0,
157 .maximum = 255,
158 .step = 1,
62833acd 159 .default_value = 127,
6a7eba24 160 },
62833acd 161 .set_control = setbrightness,
6a7eba24 162 },
62833acd 163[CONTRAST] = {
6a7eba24
JFM		 164 {
165 .id = V4L2_CID_CONTRAST,
166 .type = V4L2_CTRL_TYPE_INTEGER,
167 .name = "Contrast",
168 .minimum = 0,
169 .maximum = 255,
170 .step = 1,
62833acd 171 .default_value = 127,
6a7eba24 172 },
62833acd 173 .set_control = setcontrast,
6a7eba24 174 },
62833acd 175[COLORS] = {
6a7eba24
JFM		 176 {
177 .id = V4L2_CID_SATURATION,
178 .type = V4L2_CTRL_TYPE_INTEGER,
594f5b8b 179 .name = "Color",
6a7eba24
JFM		 180 .minimum = 0,
181 .maximum = 255,
182 .step = 1,
62833acd 183 .default_value = 127,
6a7eba24 184 },
62833acd 185 .set_control = setcolors,
6a7eba24 186 },
42e142f6 187/* The flip controls work for sensors ov7660 and ov7670 only */
62833acd 188[HFLIP] = {
0cd6759d
JFM		 189 {
190 .id = V4L2_CID_HFLIP,
191 .type = V4L2_CTRL_TYPE_BOOLEAN,
192 .name = "Mirror",
193 .minimum = 0,
194 .maximum = 1,
195 .step = 1,
62833acd 196 .default_value = 0,
0cd6759d 197 },
62833acd 198 .set_control = sethvflip,
0cd6759d 199 },
62833acd 200[VFLIP] = {
0cd6759d
JFM		 201 {
202 .id = V4L2_CID_VFLIP,
203 .type = V4L2_CTRL_TYPE_BOOLEAN,
204 .name = "Vflip",
205 .minimum = 0,
206 .maximum = 1,
207 .step = 1,
62833acd 208 .default_value = 0,
0cd6759d 209 },
62833acd 210 .set_control = sethvflip,
0cd6759d 211 },
62833acd 212[AUTOBRIGHT] = {
02ab18b0
HG		 213 {
214 .id = V4L2_CID_AUTOBRIGHTNESS,
215 .type = V4L2_CTRL_TYPE_BOOLEAN,
216 .name = "Auto Brightness",
217 .minimum = 0,
218 .maximum = 1,
219 .step = 1,
62833acd 220 .default_value = 1,
02ab18b0 221 },
62833acd 222 .set_control = setautobright,
02ab18b0 223 },
62833acd 224[FREQ] = {
02ab18b0
HG		 225 {
226 .id = V4L2_CID_POWER_LINE_FREQUENCY,
227 .type = V4L2_CTRL_TYPE_MENU,
228 .name = "Light frequency filter",
229 .minimum = 0,
87bae740 230 .maximum = 2, /* 0: no flicker, 1: 50Hz, 2:60Hz, 3: auto */
02ab18b0 231 .step = 1,
62833acd 232 .default_value = 0,
02ab18b0 233 },
62833acd 234 .set_control = setfreq,
02ab18b0 235 },
6a7eba24
JFM		 236};
237
83db7688
JFM		 238/* table of the disabled controls */
239static const unsigned ctrl_dis[] = {
240[SEN_OV2610] = (1 << NCTRL) - 1, /* no control */
241
242[SEN_OV3610] = (1 << NCTRL) - 1, /* no control */
243
244[SEN_OV6620] = (1 << HFLIP) |
245 (1 << VFLIP),
246
247[SEN_OV6630] = (1 << HFLIP) |
248 (1 << VFLIP),
249
250[SEN_OV66308AF] = (1 << HFLIP) |
251 (1 << VFLIP),
252
253[SEN_OV7610] = (1 << HFLIP) |
254 (1 << VFLIP),
255
256[SEN_OV7620] = (1 << HFLIP) |
257 (1 << VFLIP),
258
259[SEN_OV7620AE] = (1 << HFLIP) |
260 (1 << VFLIP),
261
262[SEN_OV7640] = (1 << HFLIP) |
263 (1 << VFLIP) |
264 (1 << AUTOBRIGHT) |
265 (1 << CONTRAST),
266
267[SEN_OV7648] = (1 << HFLIP) |
268 (1 << VFLIP) |
269 (1 << AUTOBRIGHT) |
270 (1 << CONTRAST),
271
42e142f6
JFM		 272[SEN_OV7660] = (1 << AUTOBRIGHT),
273
83db7688
JFM		 274[SEN_OV7670] = (1 << COLORS) |
275 (1 << AUTOBRIGHT),
276
277[SEN_OV76BE] = (1 << HFLIP) |
278 (1 << VFLIP),
279
280[SEN_OV8610] = (1 << HFLIP) |
281 (1 << VFLIP) |
282 (1 << FREQ),
283};
284
49809d6a 285static const struct v4l2_pix_format ov519_vga_mode[] = {
c2446b3e
JFM		 286 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
287 .bytesperline = 320,
594f5b8b 288 .sizeimage = 320 * 240 * 3 / 8 + 590,
c2446b3e
JFM		 289 .colorspace = V4L2_COLORSPACE_JPEG,
290 .priv = 1},
291 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
292 .bytesperline = 640,
293 .sizeimage = 640 * 480 * 3 / 8 + 590,
294 .colorspace = V4L2_COLORSPACE_JPEG,
295 .priv = 0},
6a7eba24 296};
49809d6a 297static const struct v4l2_pix_format ov519_sif_mode[] = {
124cc9c0
HG		 298 {160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
299 .bytesperline = 160,
300 .sizeimage = 160 * 120 * 3 / 8 + 590,
301 .colorspace = V4L2_COLORSPACE_JPEG,
302 .priv = 3},
c2446b3e
JFM		 303 {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
304 .bytesperline = 176,
594f5b8b 305 .sizeimage = 176 * 144 * 3 / 8 + 590,
c2446b3e
JFM		 306 .colorspace = V4L2_COLORSPACE_JPEG,
307 .priv = 1},
124cc9c0
HG		 308 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
309 .bytesperline = 320,
310 .sizeimage = 320 * 240 * 3 / 8 + 590,
311 .colorspace = V4L2_COLORSPACE_JPEG,
312 .priv = 2},
c2446b3e
JFM		 313 {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
314 .bytesperline = 352,
594f5b8b 315 .sizeimage = 352 * 288 * 3 / 8 + 590,
c2446b3e
JFM		 316 .colorspace = V4L2_COLORSPACE_JPEG,
317 .priv = 0},
6a7eba24
JFM		 318};
319
b282d873
HG		 320/* Note some of the sizeimage values for the ov511 / ov518 may seem
321 larger then necessary, however they need to be this big as the ov511 /
322 ov518 always fills the entire isoc frame, using 0 padding bytes when
323 it doesn't have any data. So with low framerates the amount of data
324 transfered can become quite large (libv4l will remove all the 0 padding
325 in userspace). */
49809d6a
HG		 326static const struct v4l2_pix_format ov518_vga_mode[] = {
327 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
328 .bytesperline = 320,
b282d873 329 .sizeimage = 320 * 240 * 3,
49809d6a
HG		 330 .colorspace = V4L2_COLORSPACE_JPEG,
331 .priv = 1},
332 {640, 480, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
333 .bytesperline = 640,
b282d873 334 .sizeimage = 640 * 480 * 2,
49809d6a
HG		 335 .colorspace = V4L2_COLORSPACE_JPEG,
336 .priv = 0},
337};
338static const struct v4l2_pix_format ov518_sif_mode[] = {
124cc9c0
HG		 339 {160, 120, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
340 .bytesperline = 160,
b282d873 341 .sizeimage = 70000,
124cc9c0
HG		 342 .colorspace = V4L2_COLORSPACE_JPEG,
343 .priv = 3},
49809d6a
HG		 344 {176, 144, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
345 .bytesperline = 176,
b282d873 346 .sizeimage = 70000,
49809d6a
HG		 347 .colorspace = V4L2_COLORSPACE_JPEG,
348 .priv = 1},
124cc9c0
HG		 349 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
350 .bytesperline = 320,
b282d873 351 .sizeimage = 320 * 240 * 3,
124cc9c0
HG		 352 .colorspace = V4L2_COLORSPACE_JPEG,
353 .priv = 2},
49809d6a
HG		 354 {352, 288, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
355 .bytesperline = 352,
b282d873 356 .sizeimage = 352 * 288 * 3,
49809d6a
HG		 357 .colorspace = V4L2_COLORSPACE_JPEG,
358 .priv = 0},
359};
360
1876bb92
HG		 361static const struct v4l2_pix_format ov511_vga_mode[] = {
362 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
363 .bytesperline = 320,
364 .sizeimage = 320 * 240 * 3,
365 .colorspace = V4L2_COLORSPACE_JPEG,
366 .priv = 1},
367 {640, 480, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
368 .bytesperline = 640,
369 .sizeimage = 640 * 480 * 2,
370 .colorspace = V4L2_COLORSPACE_JPEG,
371 .priv = 0},
372};
373static const struct v4l2_pix_format ov511_sif_mode[] = {
374 {160, 120, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
375 .bytesperline = 160,
b282d873 376 .sizeimage = 70000,
1876bb92
HG		 377 .colorspace = V4L2_COLORSPACE_JPEG,
378 .priv = 3},
379 {176, 144, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
380 .bytesperline = 176,
b282d873 381 .sizeimage = 70000,
1876bb92
HG		 382 .colorspace = V4L2_COLORSPACE_JPEG,
383 .priv = 1},
384 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
385 .bytesperline = 320,
386 .sizeimage = 320 * 240 * 3,
387 .colorspace = V4L2_COLORSPACE_JPEG,
388 .priv = 2},
389 {352, 288, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
390 .bytesperline = 352,
391 .sizeimage = 352 * 288 * 3,
392 .colorspace = V4L2_COLORSPACE_JPEG,
393 .priv = 0},
394};
49809d6a 395
635118d5
HG		 396static const struct v4l2_pix_format ovfx2_vga_mode[] = {
397 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
398 .bytesperline = 320,
399 .sizeimage = 320 * 240,
400 .colorspace = V4L2_COLORSPACE_SRGB,
401 .priv = 1},
402 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
403 .bytesperline = 640,
404 .sizeimage = 640 * 480,
405 .colorspace = V4L2_COLORSPACE_SRGB,
406 .priv = 0},
407};
408static const struct v4l2_pix_format ovfx2_cif_mode[] = {
409 {160, 120, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
410 .bytesperline = 160,
411 .sizeimage = 160 * 120,
412 .colorspace = V4L2_COLORSPACE_SRGB,
413 .priv = 3},
414 {176, 144, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
415 .bytesperline = 176,
416 .sizeimage = 176 * 144,
417 .colorspace = V4L2_COLORSPACE_SRGB,
418 .priv = 1},
419 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
420 .bytesperline = 320,
421 .sizeimage = 320 * 240,
422 .colorspace = V4L2_COLORSPACE_SRGB,
423 .priv = 2},
424 {352, 288, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
425 .bytesperline = 352,
426 .sizeimage = 352 * 288,
427 .colorspace = V4L2_COLORSPACE_SRGB,
428 .priv = 0},
429};
430static const struct v4l2_pix_format ovfx2_ov2610_mode[] = {
431 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
432 .bytesperline = 1600,
433 .sizeimage = 1600 * 1200,
434 .colorspace = V4L2_COLORSPACE_SRGB},
435};
436static const struct v4l2_pix_format ovfx2_ov3610_mode[] = {
635118d5
HG		 437 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
438 .bytesperline = 640,
439 .sizeimage = 640 * 480,
b46aaa02
HG		 440 .colorspace = V4L2_COLORSPACE_SRGB,
441 .priv = 1},
442 {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
443 .bytesperline = 800,
444 .sizeimage = 800 * 600,
445 .colorspace = V4L2_COLORSPACE_SRGB,
446 .priv = 1},
447 {1024, 768, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
448 .bytesperline = 1024,
449 .sizeimage = 1024 * 768,
450 .colorspace = V4L2_COLORSPACE_SRGB,
451 .priv = 1},
452 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
453 .bytesperline = 1600,
454 .sizeimage = 1600 * 1200,
455 .colorspace = V4L2_COLORSPACE_SRGB,
456 .priv = 0},
457 {2048, 1536, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
458 .bytesperline = 2048,
459 .sizeimage = 2048 * 1536,
460 .colorspace = V4L2_COLORSPACE_SRGB,
461 .priv = 0},
635118d5
HG		 462};
463
49809d6a 464/* Registers common to OV511 / OV518 */
1876bb92 465#define R51x_FIFO_PSIZE 0x30 /* 2 bytes wide w/ OV518(+) */
780e3121 466#define R51x_SYS_RESET 0x50
1876bb92
HG		 467 /* Reset type flags */
468 #define OV511_RESET_OMNICE 0x08
780e3121 469#define R51x_SYS_INIT 0x53
49809d6a 470#define R51x_SYS_SNAP 0x52
87bae740 471#define R51x_SYS_CUST_ID 0x5f
49809d6a
HG		 472#define R51x_COMP_LUT_BEGIN 0x80
473
474/* OV511 Camera interface register numbers */
1876bb92
HG		 475#define R511_CAM_DELAY 0x10
476#define R511_CAM_EDGE 0x11
477#define R511_CAM_PXCNT 0x12
478#define R511_CAM_LNCNT 0x13
479#define R511_CAM_PXDIV 0x14
480#define R511_CAM_LNDIV 0x15
481#define R511_CAM_UV_EN 0x16
482#define R511_CAM_LINE_MODE 0x17
483#define R511_CAM_OPTS 0x18
484
485#define R511_SNAP_FRAME 0x19
87bae740
JFM		 486#define R511_SNAP_PXCNT 0x1a
487#define R511_SNAP_LNCNT 0x1b
488#define R511_SNAP_PXDIV 0x1c
489#define R511_SNAP_LNDIV 0x1d
490#define R511_SNAP_UV_EN 0x1e
491#define R511_SNAP_UV_EN 0x1e
492#define R511_SNAP_OPTS 0x1f
1876bb92
HG		 493
494#define R511_DRAM_FLOW_CTL 0x20
495#define R511_FIFO_OPTS 0x31
496#define R511_I2C_CTL 0x40
49809d6a 497#define R511_SYS_LED_CTL 0x55 /* OV511+ only */
1876bb92
HG		 498#define R511_COMP_EN 0x78
499#define R511_COMP_LUT_EN 0x79
49809d6a
HG		 500
501/* OV518 Camera interface register numbers */
502#define R518_GPIO_OUT 0x56 /* OV518(+) only */
503#define R518_GPIO_CTL 0x57 /* OV518(+) only */
504
6a7eba24 505/* OV519 Camera interface register numbers */
ac40b1fa
JFM		 506#define OV519_R10_H_SIZE 0x10
507#define OV519_R11_V_SIZE 0x11
508#define OV519_R12_X_OFFSETL 0x12
509#define OV519_R13_X_OFFSETH 0x13
510#define OV519_R14_Y_OFFSETL 0x14
511#define OV519_R15_Y_OFFSETH 0x15
512#define OV519_R16_DIVIDER 0x16
513#define OV519_R20_DFR 0x20
514#define OV519_R25_FORMAT 0x25
6a7eba24
JFM		 515
516/* OV519 System Controller register numbers */
21867803
JFM		 517#define OV519_R51_RESET1 0x51
518#define OV519_R54_EN_CLK1 0x54
b4e96ea3 519#define OV519_R57_SNAPSHOT 0x57
6a7eba24
JFM		 520
521#define OV519_GPIO_DATA_OUT0 0x71
522#define OV519_GPIO_IO_CTRL0 0x72
523
87bae740 524/*#define OV511_ENDPOINT_ADDRESS 1 * Isoc endpoint number */
6a7eba24 525
b46aaa02
HG		 526/*
527 * The FX2 chip does not give us a zero length read at end of frame.
528 * It does, however, give a short read at the end of a frame, if
3ad2f3fb 529 * necessary, rather than run two frames together.
b46aaa02
HG		 530 *
531 * By choosing the right bulk transfer size, we are guaranteed to always
532 * get a short read for the last read of each frame. Frame sizes are
533 * always a composite number (width * height, or a multiple) so if we
534 * choose a prime number, we are guaranteed that the last read of a
535 * frame will be short.
536 *
537 * But it isn't that easy: the 2.6 kernel requires a multiple of 4KB,
538 * otherwise EOVERFLOW "babbling" errors occur. I have not been able
539 * to figure out why. [PMiller]
540 *
541 * The constant (13 * 4096) is the largest "prime enough" number less than 64KB.
542 *
543 * It isn't enough to know the number of bytes per frame, in case we
544 * have data dropouts or buffer overruns (even though the FX2 double
545 * buffers, there are some pretty strict real time constraints for
546 * isochronous transfer for larger frame sizes).
547 */
548#define OVFX2_BULK_SIZE (13 * 4096)
549
6a7eba24
JFM		 550/* I2C registers */
551#define R51x_I2C_W_SID 0x41
552#define R51x_I2C_SADDR_3 0x42
553#define R51x_I2C_SADDR_2 0x43
554#define R51x_I2C_R_SID 0x44
555#define R51x_I2C_DATA 0x45
556#define R518_I2C_CTL 0x47 /* OV518(+) only */
b46aaa02 557#define OVFX2_I2C_ADDR 0x00
6a7eba24
JFM		 558
559/* I2C ADDRESSES */
560#define OV7xx0_SID 0x42
229bb7dc 561#define OV_HIRES_SID 0x60 /* OV9xxx / OV2xxx / OV3xxx */
6a7eba24
JFM		 562#define OV8xx0_SID 0xa0
563#define OV6xx0_SID 0xc0
564
565/* OV7610 registers */
566#define OV7610_REG_GAIN 0x00 /* gain setting (5:0) */
49809d6a
HG		 567#define OV7610_REG_BLUE 0x01 /* blue channel balance */
568#define OV7610_REG_RED 0x02 /* red channel balance */
6a7eba24
JFM		 569#define OV7610_REG_SAT 0x03 /* saturation */
570#define OV8610_REG_HUE 0x04 /* 04 reserved */
571#define OV7610_REG_CNT 0x05 /* Y contrast */
572#define OV7610_REG_BRT 0x06 /* Y brightness */
573#define OV7610_REG_COM_C 0x14 /* misc common regs */
574#define OV7610_REG_ID_HIGH 0x1c /* manufacturer ID MSB */
575#define OV7610_REG_ID_LOW 0x1d /* manufacturer ID LSB */
576#define OV7610_REG_COM_I 0x29 /* misc settings */
577
42e142f6 578/* OV7660 and OV7670 registers */
21867803
JFM		 579#define OV7670_R00_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
580#define OV7670_R01_BLUE 0x01 /* blue gain */
581#define OV7670_R02_RED 0x02 /* red gain */
582#define OV7670_R03_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
583#define OV7670_R04_COM1 0x04 /* Control 1 */
584/*#define OV7670_R07_AECHH 0x07 * AEC MS 5 bits */
585#define OV7670_R0C_COM3 0x0c /* Control 3 */
586#define OV7670_R0D_COM4 0x0d /* Control 4 */
587#define OV7670_R0E_COM5 0x0e /* All "reserved" */
588#define OV7670_R0F_COM6 0x0f /* Control 6 */
589#define OV7670_R10_AECH 0x10 /* More bits of AEC value */
590#define OV7670_R11_CLKRC 0x11 /* Clock control */
591#define OV7670_R12_COM7 0x12 /* Control 7 */
87bae740
JFM		 592#define OV7670_COM7_FMT_VGA 0x00
593/*#define OV7670_COM7_YUV 0x00 * YUV */
594#define OV7670_COM7_FMT_QVGA 0x10 /* QVGA format */
595#define OV7670_COM7_FMT_MASK 0x38
596#define OV7670_COM7_RESET 0x80 /* Register reset */
21867803 597#define OV7670_R13_COM8 0x13 /* Control 8 */
87bae740
JFM		 598#define OV7670_COM8_AEC 0x01 /* Auto exposure enable */
599#define OV7670_COM8_AWB 0x02 /* White balance enable */
600#define OV7670_COM8_AGC 0x04 /* Auto gain enable */
601#define OV7670_COM8_BFILT 0x20 /* Band filter enable */
602#define OV7670_COM8_AECSTEP 0x40 /* Unlimited AEC step size */
603#define OV7670_COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
21867803
JFM		 604#define OV7670_R14_COM9 0x14 /* Control 9 - gain ceiling */
605#define OV7670_R15_COM10 0x15 /* Control 10 */
606#define OV7670_R17_HSTART 0x17 /* Horiz start high bits */
607#define OV7670_R18_HSTOP 0x18 /* Horiz stop high bits */
608#define OV7670_R19_VSTART 0x19 /* Vert start high bits */
609#define OV7670_R1A_VSTOP 0x1a /* Vert stop high bits */
610#define OV7670_R1E_MVFP 0x1e /* Mirror / vflip */
87bae740
JFM		 611#define OV7670_MVFP_VFLIP 0x10 /* vertical flip */
612#define OV7670_MVFP_MIRROR 0x20 /* Mirror image */
21867803
JFM		 613#define OV7670_R24_AEW 0x24 /* AGC upper limit */
614#define OV7670_R25_AEB 0x25 /* AGC lower limit */
615#define OV7670_R26_VPT 0x26 /* AGC/AEC fast mode op region */
616#define OV7670_R32_HREF 0x32 /* HREF pieces */
617#define OV7670_R3A_TSLB 0x3a /* lots of stuff */
618#define OV7670_R3B_COM11 0x3b /* Control 11 */
87bae740
JFM		 619#define OV7670_COM11_EXP 0x02
620#define OV7670_COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
21867803
JFM		 621#define OV7670_R3C_COM12 0x3c /* Control 12 */
622#define OV7670_R3D_COM13 0x3d /* Control 13 */
87bae740
JFM		 623#define OV7670_COM13_GAMMA 0x80 /* Gamma enable */
624#define OV7670_COM13_UVSAT 0x40 /* UV saturation auto adjustment */
21867803
JFM		 625#define OV7670_R3E_COM14 0x3e /* Control 14 */
626#define OV7670_R3F_EDGE 0x3f /* Edge enhancement factor */
627#define OV7670_R40_COM15 0x40 /* Control 15 */
87bae740 628/*#define OV7670_COM15_R00FF 0xc0 * 00 to FF */
21867803 629#define OV7670_R41_COM16 0x41 /* Control 16 */
87bae740 630#define OV7670_COM16_AWBGAIN 0x08 /* AWB gain enable */
42e142f6 631/* end of ov7660 common registers */
21867803
JFM		 632#define OV7670_R55_BRIGHT 0x55 /* Brightness */
633#define OV7670_R56_CONTRAS 0x56 /* Contrast control */
634#define OV7670_R69_GFIX 0x69 /* Fix gain control */
635/*#define OV7670_R8C_RGB444 0x8c * RGB 444 control */
636#define OV7670_R9F_HAECC1 0x9f /* Hist AEC/AGC control 1 */
637#define OV7670_RA0_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
638#define OV7670_RA5_BD50MAX 0xa5 /* 50hz banding step limit */
639#define OV7670_RA6_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
640#define OV7670_RA7_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
641#define OV7670_RA8_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
642#define OV7670_RA9_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
643#define OV7670_RAA_HAECC7 0xaa /* Hist AEC/AGC control 7 */
644#define OV7670_RAB_BD60MAX 0xab /* 60hz banding step limit */
6a7eba24 645
4202f71c 646struct ov_regvals {
9d1593a8
JFM		 647 u8 reg;
648 u8 val;
4202f71c
JFM		 649};
650struct ov_i2c_regvals {
9d1593a8
JFM		 651 u8 reg;
652 u8 val;
4202f71c
JFM		 653};
654
635118d5 655/* Settings for OV2610 camera chip */
780e3121 656static const struct ov_i2c_regvals norm_2610[] = {
b46aaa02 657 { 0x12, 0x80 }, /* reset */
635118d5
HG		 658};
659
780e3121 660static const struct ov_i2c_regvals norm_3620b[] = {
635118d5
HG		 661 /*
662 * From the datasheet: "Note that after writing to register COMH
663 * (0x12) to change the sensor mode, registers related to the
664 * sensor’s cropping window will be reset back to their default
665 * values."
666 *
667 * "wait 4096 external clock ... to make sure the sensor is
668 * stable and ready to access registers" i.e. 160us at 24MHz
669 */
635118d5
HG		 670 { 0x12, 0x80 }, /* COMH reset */
671 { 0x12, 0x00 }, /* QXGA, master */
672
673 /*
674 * 11 CLKRC "Clock Rate Control"
675 * [7] internal frequency doublers: on
676 * [6] video port mode: master
677 * [5:0] clock divider: 1
678 */
679 { 0x11, 0x80 },
680
681 /*
682 * 13 COMI "Common Control I"
683 * = 192 (0xC0) 11000000
684 * COMI[7] "AEC speed selection"
685 * = 1 (0x01) 1....... "Faster AEC correction"
686 * COMI[6] "AEC speed step selection"
687 * = 1 (0x01) .1...... "Big steps, fast"
688 * COMI[5] "Banding filter on off"
689 * = 0 (0x00) ..0..... "Off"
690 * COMI[4] "Banding filter option"
691 * = 0 (0x00) ...0.... "Main clock is 48 MHz and
692 * the PLL is ON"
693 * COMI[3] "Reserved"
694 * = 0 (0x00) ....0...
695 * COMI[2] "AGC auto manual control selection"
696 * = 0 (0x00) .....0.. "Manual"
697 * COMI[1] "AWB auto manual control selection"
698 * = 0 (0x00) ......0. "Manual"
699 * COMI[0] "Exposure control"
700 * = 0 (0x00) .......0 "Manual"
701 */
87bae740 702 { 0x13, 0xc0 },
635118d5
HG		 703
704 /*
705 * 09 COMC "Common Control C"
706 * = 8 (0x08) 00001000
707 * COMC[7:5] "Reserved"
708 * = 0 (0x00) 000.....
709 * COMC[4] "Sleep Mode Enable"
710 * = 0 (0x00) ...0.... "Normal mode"
711 * COMC[3:2] "Sensor sampling reset timing selection"
712 * = 2 (0x02) ....10.. "Longer reset time"
713 * COMC[1:0] "Output drive current select"
714 * = 0 (0x00) ......00 "Weakest"
715 */
716 { 0x09, 0x08 },
717
718 /*
719 * 0C COMD "Common Control D"
720 * = 8 (0x08) 00001000
721 * COMD[7] "Reserved"
722 * = 0 (0x00) 0.......
723 * COMD[6] "Swap MSB and LSB at the output port"
724 * = 0 (0x00) .0...... "False"
725 * COMD[5:3] "Reserved"
726 * = 1 (0x01) ..001...
727 * COMD[2] "Output Average On Off"
728 * = 0 (0x00) .....0.. "Output Normal"
729 * COMD[1] "Sensor precharge voltage selection"
730 * = 0 (0x00) ......0. "Selects internal
731 * reference precharge
732 * voltage"
733 * COMD[0] "Snapshot option"
734 * = 0 (0x00) .......0 "Enable live video output
735 * after snapshot sequence"
736 */
737 { 0x0c, 0x08 },
738
739 /*
740 * 0D COME "Common Control E"
741 * = 161 (0xA1) 10100001
742 * COME[7] "Output average option"
743 * = 1 (0x01) 1....... "Output average of 4 pixels"
744 * COME[6] "Anti-blooming control"
745 * = 0 (0x00) .0...... "Off"
746 * COME[5:3] "Reserved"
747 * = 4 (0x04) ..100...
748 * COME[2] "Clock output power down pin status"
749 * = 0 (0x00) .....0.. "Tri-state data output pin
750 * on power down"
751 * COME[1] "Data output pin status selection at power down"
752 * = 0 (0x00) ......0. "Tri-state VSYNC, PCLK,
753 * HREF, and CHSYNC pins on
754 * power down"
755 * COME[0] "Auto zero circuit select"
756 * = 1 (0x01) .......1 "On"
757 */
87bae740 758 { 0x0d, 0xa1 },
635118d5
HG		 759
760 /*
761 * 0E COMF "Common Control F"
762 * = 112 (0x70) 01110000
763 * COMF[7] "System clock selection"
764 * = 0 (0x00) 0....... "Use 24 MHz system clock"
765 * COMF[6:4] "Reserved"
766 * = 7 (0x07) .111....
767 * COMF[3] "Manual auto negative offset canceling selection"
768 * = 0 (0x00) ....0... "Auto detect negative
769 * offset and cancel it"
770 * COMF[2:0] "Reserved"
771 * = 0 (0x00) .....000
772 */
773 { 0x0e, 0x70 },
774
775 /*
776 * 0F COMG "Common Control G"
777 * = 66 (0x42) 01000010
778 * COMG[7] "Optical black output selection"
779 * = 0 (0x00) 0....... "Disable"
780 * COMG[6] "Black level calibrate selection"
781 * = 1 (0x01) .1...... "Use optical black pixels
782 * to calibrate"
783 * COMG[5:4] "Reserved"
784 * = 0 (0x00) ..00....
785 * COMG[3] "Channel offset adjustment"
786 * = 0 (0x00) ....0... "Disable offset adjustment"
787 * COMG[2] "ADC black level calibration option"
788 * = 0 (0x00) .....0.. "Use B/G line and G/R
789 * line to calibrate each
790 * channel's black level"
791 * COMG[1] "Reserved"
792 * = 1 (0x01) ......1.
793 * COMG[0] "ADC black level calibration enable"
794 * = 0 (0x00) .......0 "Disable"
795 */
796 { 0x0f, 0x42 },
797
798 /*
799 * 14 COMJ "Common Control J"
800 * = 198 (0xC6) 11000110
801 * COMJ[7:6] "AGC gain ceiling"
802 * = 3 (0x03) 11...... "8x"
803 * COMJ[5:4] "Reserved"
804 * = 0 (0x00) ..00....
805 * COMJ[3] "Auto banding filter"
806 * = 0 (0x00) ....0... "Banding filter is always
807 * on off depending on
808 * COMI[5] setting"
809 * COMJ[2] "VSYNC drop option"
810 * = 1 (0x01) .....1.. "SYNC is dropped if frame
811 * data is dropped"
812 * COMJ[1] "Frame data drop"
813 * = 1 (0x01) ......1. "Drop frame data if
814 * exposure is not within
815 * tolerance. In AEC mode,
816 * data is normally dropped
817 * when data is out of
818 * range."
819 * COMJ[0] "Reserved"
820 * = 0 (0x00) .......0
821 */
87bae740 822 { 0x14, 0xc6 },
635118d5
HG		 823
824 /*
825 * 15 COMK "Common Control K"
826 * = 2 (0x02) 00000010
827 * COMK[7] "CHSYNC pin output swap"
828 * = 0 (0x00) 0....... "CHSYNC"
829 * COMK[6] "HREF pin output swap"
830 * = 0 (0x00) .0...... "HREF"
831 * COMK[5] "PCLK output selection"
832 * = 0 (0x00) ..0..... "PCLK always output"
833 * COMK[4] "PCLK edge selection"
834 * = 0 (0x00) ...0.... "Data valid on falling edge"
835 * COMK[3] "HREF output polarity"
836 * = 0 (0x00) ....0... "positive"
837 * COMK[2] "Reserved"
838 * = 0 (0x00) .....0..
839 * COMK[1] "VSYNC polarity"
840 * = 1 (0x01) ......1. "negative"
841 * COMK[0] "HSYNC polarity"
842 * = 0 (0x00) .......0 "positive"
843 */
844 { 0x15, 0x02 },
845
846 /*
847 * 33 CHLF "Current Control"
848 * = 9 (0x09) 00001001
849 * CHLF[7:6] "Sensor current control"
850 * = 0 (0x00) 00......
851 * CHLF[5] "Sensor current range control"
852 * = 0 (0x00) ..0..... "normal range"
853 * CHLF[4] "Sensor current"
854 * = 0 (0x00) ...0.... "normal current"
855 * CHLF[3] "Sensor buffer current control"
856 * = 1 (0x01) ....1... "half current"
857 * CHLF[2] "Column buffer current control"
858 * = 0 (0x00) .....0.. "normal current"
859 * CHLF[1] "Analog DSP current control"
860 * = 0 (0x00) ......0. "normal current"
861 * CHLF[1] "ADC current control"
862 * = 0 (0x00) ......0. "normal current"
863 */
864 { 0x33, 0x09 },
865
866 /*
867 * 34 VBLM "Blooming Control"
868 * = 80 (0x50) 01010000
869 * VBLM[7] "Hard soft reset switch"
870 * = 0 (0x00) 0....... "Hard reset"
871 * VBLM[6:4] "Blooming voltage selection"
872 * = 5 (0x05) .101....
873 * VBLM[3:0] "Sensor current control"
874 * = 0 (0x00) ....0000
875 */
876 { 0x34, 0x50 },
877
878 /*
879 * 36 VCHG "Sensor Precharge Voltage Control"
880 * = 0 (0x00) 00000000
881 * VCHG[7] "Reserved"
882 * = 0 (0x00) 0.......
883 * VCHG[6:4] "Sensor precharge voltage control"
884 * = 0 (0x00) .000....
885 * VCHG[3:0] "Sensor array common reference"
886 * = 0 (0x00) ....0000
887 */
888 { 0x36, 0x00 },
889
890 /*
891 * 37 ADC "ADC Reference Control"
892 * = 4 (0x04) 00000100
893 * ADC[7:4] "Reserved"
894 * = 0 (0x00) 0000....
895 * ADC[3] "ADC input signal range"
896 * = 0 (0x00) ....0... "Input signal 1.0x"
897 * ADC[2:0] "ADC range control"
898 * = 4 (0x04) .....100
899 */
900 { 0x37, 0x04 },
901
902 /*
903 * 38 ACOM "Analog Common Ground"
904 * = 82 (0x52) 01010010
905 * ACOM[7] "Analog gain control"
906 * = 0 (0x00) 0....... "Gain 1x"
907 * ACOM[6] "Analog black level calibration"
908 * = 1 (0x01) .1...... "On"
909 * ACOM[5:0] "Reserved"
910 * = 18 (0x12) ..010010
911 */
912 { 0x38, 0x52 },
913
914 /*
915 * 3A FREFA "Internal Reference Adjustment"
916 * = 0 (0x00) 00000000
917 * FREFA[7:0] "Range"
918 * = 0 (0x00) 00000000
919 */
920 { 0x3a, 0x00 },
921
922 /*
923 * 3C FVOPT "Internal Reference Adjustment"
924 * = 31 (0x1F) 00011111
925 * FVOPT[7:0] "Range"
926 * = 31 (0x1F) 00011111
927 */
87bae740 928 { 0x3c, 0x1f },
635118d5
HG		 929
930 /*
931 * 44 Undocumented = 0 (0x00) 00000000
932 * 44[7:0] "It's a secret"
933 * = 0 (0x00) 00000000
934 */
935 { 0x44, 0x00 },
936
937 /*
938 * 40 Undocumented = 0 (0x00) 00000000
939 * 40[7:0] "It's a secret"
940 * = 0 (0x00) 00000000
941 */
942 { 0x40, 0x00 },
943
944 /*
945 * 41 Undocumented = 0 (0x00) 00000000
946 * 41[7:0] "It's a secret"
947 * = 0 (0x00) 00000000
948 */
949 { 0x41, 0x00 },
950
951 /*
952 * 42 Undocumented = 0 (0x00) 00000000
953 * 42[7:0] "It's a secret"
954 * = 0 (0x00) 00000000
955 */
956 { 0x42, 0x00 },
957
958 /*
959 * 43 Undocumented = 0 (0x00) 00000000
960 * 43[7:0] "It's a secret"
961 * = 0 (0x00) 00000000
962 */
963 { 0x43, 0x00 },
964
965 /*
966 * 45 Undocumented = 128 (0x80) 10000000
967 * 45[7:0] "It's a secret"
968 * = 128 (0x80) 10000000
969 */
970 { 0x45, 0x80 },
971
972 /*
973 * 48 Undocumented = 192 (0xC0) 11000000
974 * 48[7:0] "It's a secret"
975 * = 192 (0xC0) 11000000
976 */
87bae740 977 { 0x48, 0xc0 },
635118d5
HG		 978
979 /*
980 * 49 Undocumented = 25 (0x19) 00011001
981 * 49[7:0] "It's a secret"
982 * = 25 (0x19) 00011001
983 */
984 { 0x49, 0x19 },
985
986 /*
987 * 4B Undocumented = 128 (0x80) 10000000
988 * 4B[7:0] "It's a secret"
989 * = 128 (0x80) 10000000
990 */
87bae740 991 { 0x4b, 0x80 },
635118d5
HG		 992
993 /*
994 * 4D Undocumented = 196 (0xC4) 11000100
995 * 4D[7:0] "It's a secret"
996 * = 196 (0xC4) 11000100
997 */
87bae740 998 { 0x4d, 0xc4 },
635118d5
HG		 999
1000 /*
1001 * 35 VREF "Reference Voltage Control"
87bae740 1002 * = 76 (0x4c) 01001100
635118d5
HG		 1003 * VREF[7:5] "Column high reference control"
1004 * = 2 (0x02) 010..... "higher voltage"
1005 * VREF[4:2] "Column low reference control"
1006 * = 3 (0x03) ...011.. "Highest voltage"
1007 * VREF[1:0] "Reserved"
1008 * = 0 (0x00) ......00
1009 */
87bae740 1010 { 0x35, 0x4c },
635118d5
HG		 1011
1012 /*
1013 * 3D Undocumented = 0 (0x00) 00000000
1014 * 3D[7:0] "It's a secret"
1015 * = 0 (0x00) 00000000
1016 */
87bae740 1017 { 0x3d, 0x00 },
635118d5
HG		 1018
1019 /*
1020 * 3E Undocumented = 0 (0x00) 00000000
1021 * 3E[7:0] "It's a secret"
1022 * = 0 (0x00) 00000000
1023 */
87bae740 1024 { 0x3e, 0x00 },
635118d5
HG		 1025
1026 /*
1027 * 3B FREFB "Internal Reference Adjustment"
1028 * = 24 (0x18) 00011000
1029 * FREFB[7:0] "Range"
1030 * = 24 (0x18) 00011000
1031 */
1032 { 0x3b, 0x18 },
1033
1034 /*
1035 * 33 CHLF "Current Control"
1036 * = 25 (0x19) 00011001
1037 * CHLF[7:6] "Sensor current control"
1038 * = 0 (0x00) 00......
1039 * CHLF[5] "Sensor current range control"
1040 * = 0 (0x00) ..0..... "normal range"
1041 * CHLF[4] "Sensor current"
1042 * = 1 (0x01) ...1.... "double current"
1043 * CHLF[3] "Sensor buffer current control"
1044 * = 1 (0x01) ....1... "half current"
1045 * CHLF[2] "Column buffer current control"
1046 * = 0 (0x00) .....0.. "normal current"
1047 * CHLF[1] "Analog DSP current control"
1048 * = 0 (0x00) ......0. "normal current"
1049 * CHLF[1] "ADC current control"
1050 * = 0 (0x00) ......0. "normal current"
1051 */
1052 { 0x33, 0x19 },
1053
1054 /*
1055 * 34 VBLM "Blooming Control"
1056 * = 90 (0x5A) 01011010
1057 * VBLM[7] "Hard soft reset switch"
1058 * = 0 (0x00) 0....... "Hard reset"
1059 * VBLM[6:4] "Blooming voltage selection"
1060 * = 5 (0x05) .101....
1061 * VBLM[3:0] "Sensor current control"
1062 * = 10 (0x0A) ....1010
1063 */
87bae740 1064 { 0x34, 0x5a },
635118d5
HG		 1065
1066 /*
1067 * 3B FREFB "Internal Reference Adjustment"
1068 * = 0 (0x00) 00000000
1069 * FREFB[7:0] "Range"
1070 * = 0 (0x00) 00000000
1071 */
1072 { 0x3b, 0x00 },
1073
1074 /*
1075 * 33 CHLF "Current Control"
1076 * = 9 (0x09) 00001001
1077 * CHLF[7:6] "Sensor current control"
1078 * = 0 (0x00) 00......
1079 * CHLF[5] "Sensor current range control"
1080 * = 0 (0x00) ..0..... "normal range"
1081 * CHLF[4] "Sensor current"
1082 * = 0 (0x00) ...0.... "normal current"
1083 * CHLF[3] "Sensor buffer current control"
1084 * = 1 (0x01) ....1... "half current"
1085 * CHLF[2] "Column buffer current control"
1086 * = 0 (0x00) .....0.. "normal current"
1087 * CHLF[1] "Analog DSP current control"
1088 * = 0 (0x00) ......0. "normal current"
1089 * CHLF[1] "ADC current control"
1090 * = 0 (0x00) ......0. "normal current"
1091 */
1092 { 0x33, 0x09 },
1093
1094 /*
1095 * 34 VBLM "Blooming Control"
1096 * = 80 (0x50) 01010000
1097 * VBLM[7] "Hard soft reset switch"
1098 * = 0 (0x00) 0....... "Hard reset"
1099 * VBLM[6:4] "Blooming voltage selection"
1100 * = 5 (0x05) .101....
1101 * VBLM[3:0] "Sensor current control"
1102 * = 0 (0x00) ....0000
1103 */
1104 { 0x34, 0x50 },
1105
1106 /*
1107 * 12 COMH "Common Control H"
1108 * = 64 (0x40) 01000000
1109 * COMH[7] "SRST"
1110 * = 0 (0x00) 0....... "No-op"
1111 * COMH[6:4] "Resolution selection"
1112 * = 4 (0x04) .100.... "XGA"
1113 * COMH[3] "Master slave selection"
1114 * = 0 (0x00) ....0... "Master mode"
1115 * COMH[2] "Internal B/R channel option"
1116 * = 0 (0x00) .....0.. "B/R use same channel"
1117 * COMH[1] "Color bar test pattern"
1118 * = 0 (0x00) ......0. "Off"
1119 * COMH[0] "Reserved"
1120 * = 0 (0x00) .......0
1121 */
1122 { 0x12, 0x40 },
1123
1124 /*
1125 * 17 HREFST "Horizontal window start"
1126 * = 31 (0x1F) 00011111
1127 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1128 * = 31 (0x1F) 00011111
1129 */
87bae740 1130 { 0x17, 0x1f },
635118d5
HG		 1131
1132 /*
1133 * 18 HREFEND "Horizontal window end"
1134 * = 95 (0x5F) 01011111
1135 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1136 * = 95 (0x5F) 01011111
1137 */
87bae740 1138 { 0x18, 0x5f },
635118d5
HG		 1139
1140 /*
1141 * 19 VSTRT "Vertical window start"
1142 * = 0 (0x00) 00000000
1143 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1144 * = 0 (0x00) 00000000
1145 */
1146 { 0x19, 0x00 },
1147
1148 /*
1149 * 1A VEND "Vertical window end"
1150 * = 96 (0x60) 01100000
1151 * VEND[7:0] "Vertical Window End, 8 MSBs"
1152 * = 96 (0x60) 01100000
1153 */
1154 { 0x1a, 0x60 },
1155
1156 /*
1157 * 32 COMM "Common Control M"
1158 * = 18 (0x12) 00010010
1159 * COMM[7:6] "Pixel clock divide option"
1160 * = 0 (0x00) 00...... "/1"
1161 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1162 * = 2 (0x02) ..010...
1163 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1164 * = 2 (0x02) .....010
1165 */
1166 { 0x32, 0x12 },
1167
1168 /*
1169 * 03 COMA "Common Control A"
1170 * = 74 (0x4A) 01001010
1171 * COMA[7:4] "AWB Update Threshold"
1172 * = 4 (0x04) 0100....
1173 * COMA[3:2] "Vertical window end line control 2 LSBs"
1174 * = 2 (0x02) ....10..
1175 * COMA[1:0] "Vertical window start line control 2 LSBs"
1176 * = 2 (0x02) ......10
1177 */
87bae740 1178 { 0x03, 0x4a },
635118d5
HG		 1179
1180 /*
1181 * 11 CLKRC "Clock Rate Control"
1182 * = 128 (0x80) 10000000
1183 * CLKRC[7] "Internal frequency doublers on off seclection"
1184 * = 1 (0x01) 1....... "On"
1185 * CLKRC[6] "Digital video master slave selection"
1186 * = 0 (0x00) .0...... "Master mode, sensor
1187 * provides PCLK"
1188 * CLKRC[5:0] "Clock divider { CLK = PCLK/(1+CLKRC[5:0]) }"
1189 * = 0 (0x00) ..000000
1190 */
1191 { 0x11, 0x80 },
1192
1193 /*
1194 * 12 COMH "Common Control H"
1195 * = 0 (0x00) 00000000
1196 * COMH[7] "SRST"
1197 * = 0 (0x00) 0....... "No-op"
1198 * COMH[6:4] "Resolution selection"
1199 * = 0 (0x00) .000.... "QXGA"
1200 * COMH[3] "Master slave selection"
1201 * = 0 (0x00) ....0... "Master mode"
1202 * COMH[2] "Internal B/R channel option"
1203 * = 0 (0x00) .....0.. "B/R use same channel"
1204 * COMH[1] "Color bar test pattern"
1205 * = 0 (0x00) ......0. "Off"
1206 * COMH[0] "Reserved"
1207 * = 0 (0x00) .......0
1208 */
1209 { 0x12, 0x00 },
1210
1211 /*
1212 * 12 COMH "Common Control H"
1213 * = 64 (0x40) 01000000
1214 * COMH[7] "SRST"
1215 * = 0 (0x00) 0....... "No-op"
1216 * COMH[6:4] "Resolution selection"
1217 * = 4 (0x04) .100.... "XGA"
1218 * COMH[3] "Master slave selection"
1219 * = 0 (0x00) ....0... "Master mode"
1220 * COMH[2] "Internal B/R channel option"
1221 * = 0 (0x00) .....0.. "B/R use same channel"
1222 * COMH[1] "Color bar test pattern"
1223 * = 0 (0x00) ......0. "Off"
1224 * COMH[0] "Reserved"
1225 * = 0 (0x00) .......0
1226 */
1227 { 0x12, 0x40 },
1228
1229 /*
1230 * 17 HREFST "Horizontal window start"
1231 * = 31 (0x1F) 00011111
1232 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1233 * = 31 (0x1F) 00011111
1234 */
87bae740 1235 { 0x17, 0x1f },
635118d5
HG		 1236
1237 /*
1238 * 18 HREFEND "Horizontal window end"
1239 * = 95 (0x5F) 01011111
1240 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1241 * = 95 (0x5F) 01011111
1242 */
87bae740 1243 { 0x18, 0x5f },
635118d5
HG		 1244
1245 /*
1246 * 19 VSTRT "Vertical window start"
1247 * = 0 (0x00) 00000000
1248 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1249 * = 0 (0x00) 00000000
1250 */
1251 { 0x19, 0x00 },
1252
1253 /*
1254 * 1A VEND "Vertical window end"
1255 * = 96 (0x60) 01100000
1256 * VEND[7:0] "Vertical Window End, 8 MSBs"
1257 * = 96 (0x60) 01100000
1258 */
1259 { 0x1a, 0x60 },
1260
1261 /*
1262 * 32 COMM "Common Control M"
1263 * = 18 (0x12) 00010010
1264 * COMM[7:6] "Pixel clock divide option"
1265 * = 0 (0x00) 00...... "/1"
1266 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1267 * = 2 (0x02) ..010...
1268 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1269 * = 2 (0x02) .....010
1270 */
1271 { 0x32, 0x12 },
1272
1273 /*
1274 * 03 COMA "Common Control A"
1275 * = 74 (0x4A) 01001010
1276 * COMA[7:4] "AWB Update Threshold"
1277 * = 4 (0x04) 0100....
1278 * COMA[3:2] "Vertical window end line control 2 LSBs"
1279 * = 2 (0x02) ....10..
1280 * COMA[1:0] "Vertical window start line control 2 LSBs"
1281 * = 2 (0x02) ......10
1282 */
87bae740 1283 { 0x03, 0x4a },
635118d5
HG		 1284
1285 /*
1286 * 02 RED "Red Gain Control"
1287 * = 175 (0xAF) 10101111
1288 * RED[7] "Action"
1289 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1290 * RED[6:0] "Value"
1291 * = 47 (0x2F) .0101111
1292 */
87bae740 1293 { 0x02, 0xaf },
635118d5
HG		 1294
1295 /*
1296 * 2D ADDVSL "VSYNC Pulse Width"
1297 * = 210 (0xD2) 11010010
1298 * ADDVSL[7:0] "VSYNC pulse width, LSB"
1299 * = 210 (0xD2) 11010010
1300 */
87bae740 1301 { 0x2d, 0xd2 },
635118d5
HG		 1302
1303 /*
1304 * 00 GAIN = 24 (0x18) 00011000
1305 * GAIN[7:6] "Reserved"
1306 * = 0 (0x00) 00......
1307 * GAIN[5] "Double"
1308 * = 0 (0x00) ..0..... "False"
1309 * GAIN[4] "Double"
1310 * = 1 (0x01) ...1.... "True"
1311 * GAIN[3:0] "Range"
1312 * = 8 (0x08) ....1000
1313 */
1314 { 0x00, 0x18 },
1315
1316 /*
1317 * 01 BLUE "Blue Gain Control"
1318 * = 240 (0xF0) 11110000
1319 * BLUE[7] "Action"
1320 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1321 * BLUE[6:0] "Value"
1322 * = 112 (0x70) .1110000
1323 */
87bae740 1324 { 0x01, 0xf0 },
635118d5
HG		 1325
1326 /*
1327 * 10 AEC "Automatic Exposure Control"
1328 * = 10 (0x0A) 00001010
1329 * AEC[7:0] "Automatic Exposure Control, 8 MSBs"
1330 * = 10 (0x0A) 00001010
1331 */
87bae740
JFM		 1332 { 0x10, 0x0a },
1333
1334 { 0xe1, 0x67 },
1335 { 0xe3, 0x03 },
1336 { 0xe4, 0x26 },
1337 { 0xe5, 0x3e },
1338 { 0xf8, 0x01 },
1339 { 0xff, 0x01 },
635118d5
HG		 1340};
1341
4202f71c
JFM		 1342static const struct ov_i2c_regvals norm_6x20[] = {
1343 { 0x12, 0x80 }, /* reset */
1344 { 0x11, 0x01 },
1345 { 0x03, 0x60 },
1346 { 0x05, 0x7f }, /* For when autoadjust is off */
1347 { 0x07, 0xa8 },
87bae740 1348 /* The ratio of 0x0c and 0x0d controls the white point */
4202f71c
JFM		 1349 { 0x0c, 0x24 },
1350 { 0x0d, 0x24 },
1351 { 0x0f, 0x15 }, /* COMS */
1352 { 0x10, 0x75 }, /* AEC Exposure time */
1353 { 0x12, 0x24 }, /* Enable AGC */
1354 { 0x14, 0x04 },
1355 /* 0x16: 0x06 helps frame stability with moving objects */
1356 { 0x16, 0x06 },
1357/* { 0x20, 0x30 }, * Aperture correction enable */
1358 { 0x26, 0xb2 }, /* BLC enable */
1359 /* 0x28: 0x05 Selects RGB format if RGB on */
1360 { 0x28, 0x05 },
1361 { 0x2a, 0x04 }, /* Disable framerate adjust */
1362/* { 0x2b, 0xac }, * Framerate; Set 2a[7] first */
ae49c404 1363 { 0x2d, 0x85 },
4202f71c
JFM		 1364 { 0x33, 0xa0 }, /* Color Processing Parameter */
1365 { 0x34, 0xd2 }, /* Max A/D range */
1366 { 0x38, 0x8b },
1367 { 0x39, 0x40 },
1368
1369 { 0x3c, 0x39 }, /* Enable AEC mode changing */
1370 { 0x3c, 0x3c }, /* Change AEC mode */
1371 { 0x3c, 0x24 }, /* Disable AEC mode changing */
1372
1373 { 0x3d, 0x80 },
1374 /* These next two registers (0x4a, 0x4b) are undocumented.
1375 * They control the color balance */
1376 { 0x4a, 0x80 },
1377 { 0x4b, 0x80 },
1378 { 0x4d, 0xd2 }, /* This reduces noise a bit */
1379 { 0x4e, 0xc1 },
1380 { 0x4f, 0x04 },
1381/* Do 50-53 have any effect? */
1382/* Toggle 0x12[2] off and on here? */
1383};
1384
1385static const struct ov_i2c_regvals norm_6x30[] = {
1386 { 0x12, 0x80 }, /* Reset */
1387 { 0x00, 0x1f }, /* Gain */
1388 { 0x01, 0x99 }, /* Blue gain */
1389 { 0x02, 0x7c }, /* Red gain */
1390 { 0x03, 0xc0 }, /* Saturation */
1391 { 0x05, 0x0a }, /* Contrast */
1392 { 0x06, 0x95 }, /* Brightness */
1393 { 0x07, 0x2d }, /* Sharpness */
1394 { 0x0c, 0x20 },
1395 { 0x0d, 0x20 },
02ab18b0 1396 { 0x0e, 0xa0 }, /* Was 0x20, bit7 enables a 2x gain which we need */
4202f71c
JFM		 1397 { 0x0f, 0x05 },
1398 { 0x10, 0x9a },
1399 { 0x11, 0x00 }, /* Pixel clock = fastest */
1400 { 0x12, 0x24 }, /* Enable AGC and AWB */
1401 { 0x13, 0x21 },
1402 { 0x14, 0x80 },
1403 { 0x15, 0x01 },
1404 { 0x16, 0x03 },
1405 { 0x17, 0x38 },
1406 { 0x18, 0xea },
1407 { 0x19, 0x04 },
1408 { 0x1a, 0x93 },
1409 { 0x1b, 0x00 },
1410 { 0x1e, 0xc4 },
1411 { 0x1f, 0x04 },
1412 { 0x20, 0x20 },
1413 { 0x21, 0x10 },
1414 { 0x22, 0x88 },
1415 { 0x23, 0xc0 }, /* Crystal circuit power level */
1416 { 0x25, 0x9a }, /* Increase AEC black ratio */
1417 { 0x26, 0xb2 }, /* BLC enable */
1418 { 0x27, 0xa2 },
1419 { 0x28, 0x00 },
1420 { 0x29, 0x00 },
1421 { 0x2a, 0x84 }, /* 60 Hz power */
1422 { 0x2b, 0xa8 }, /* 60 Hz power */
1423 { 0x2c, 0xa0 },
1424 { 0x2d, 0x95 }, /* Enable auto-brightness */
1425 { 0x2e, 0x88 },
1426 { 0x33, 0x26 },
1427 { 0x34, 0x03 },
1428 { 0x36, 0x8f },
1429 { 0x37, 0x80 },
1430 { 0x38, 0x83 },
1431 { 0x39, 0x80 },
1432 { 0x3a, 0x0f },
1433 { 0x3b, 0x3c },
1434 { 0x3c, 0x1a },
1435 { 0x3d, 0x80 },
1436 { 0x3e, 0x80 },
1437 { 0x3f, 0x0e },
1438 { 0x40, 0x00 }, /* White bal */
1439 { 0x41, 0x00 }, /* White bal */
1440 { 0x42, 0x80 },
1441 { 0x43, 0x3f }, /* White bal */
1442 { 0x44, 0x80 },
1443 { 0x45, 0x20 },
1444 { 0x46, 0x20 },
1445 { 0x47, 0x80 },
1446 { 0x48, 0x7f },
1447 { 0x49, 0x00 },
1448 { 0x4a, 0x00 },
1449 { 0x4b, 0x80 },
1450 { 0x4c, 0xd0 },
1451 { 0x4d, 0x10 }, /* U = 0.563u, V = 0.714v */
1452 { 0x4e, 0x40 },
1453 { 0x4f, 0x07 }, /* UV avg., col. killer: max */
1454 { 0x50, 0xff },
1455 { 0x54, 0x23 }, /* Max AGC gain: 18dB */
1456 { 0x55, 0xff },
1457 { 0x56, 0x12 },
1458 { 0x57, 0x81 },
1459 { 0x58, 0x75 },
1460 { 0x59, 0x01 }, /* AGC dark current comp.: +1 */
1461 { 0x5a, 0x2c },
1462 { 0x5b, 0x0f }, /* AWB chrominance levels */
1463 { 0x5c, 0x10 },
1464 { 0x3d, 0x80 },
1465 { 0x27, 0xa6 },
1466 { 0x12, 0x20 }, /* Toggle AWB */
1467 { 0x12, 0x24 },
1468};
1469
1470/* Lawrence Glaister <lg@jfm.bc.ca> reports:
1471 *
1472 * Register 0x0f in the 7610 has the following effects:
1473 *
1474 * 0x85 (AEC method 1): Best overall, good contrast range
1475 * 0x45 (AEC method 2): Very overexposed
1476 * 0xa5 (spec sheet default): Ok, but the black level is
1477 * shifted resulting in loss of contrast
1478 * 0x05 (old driver setting): very overexposed, too much
1479 * contrast
1480 */
1481static const struct ov_i2c_regvals norm_7610[] = {
1482 { 0x10, 0xff },
1483 { 0x16, 0x06 },
1484 { 0x28, 0x24 },
1485 { 0x2b, 0xac },
1486 { 0x12, 0x00 },
1487 { 0x38, 0x81 },
1488 { 0x28, 0x24 }, /* 0c */
1489 { 0x0f, 0x85 }, /* lg's setting */
1490 { 0x15, 0x01 },
1491 { 0x20, 0x1c },
1492 { 0x23, 0x2a },
1493 { 0x24, 0x10 },
1494 { 0x25, 0x8a },
1495 { 0x26, 0xa2 },
1496 { 0x27, 0xc2 },
1497 { 0x2a, 0x04 },
1498 { 0x2c, 0xfe },
1499 { 0x2d, 0x93 },
1500 { 0x30, 0x71 },
1501 { 0x31, 0x60 },
1502 { 0x32, 0x26 },
1503 { 0x33, 0x20 },
1504 { 0x34, 0x48 },
1505 { 0x12, 0x24 },
1506 { 0x11, 0x01 },
1507 { 0x0c, 0x24 },
1508 { 0x0d, 0x24 },
1509};
1510
1511static const struct ov_i2c_regvals norm_7620[] = {
a511ba94 1512 { 0x12, 0x80 }, /* reset */
4202f71c
JFM		 1513 { 0x00, 0x00 }, /* gain */
1514 { 0x01, 0x80 }, /* blue gain */
1515 { 0x02, 0x80 }, /* red gain */
21867803 1516 { 0x03, 0xc0 }, /* OV7670_R03_VREF */
4202f71c
JFM		 1517 { 0x06, 0x60 },
1518 { 0x07, 0x00 },
1519 { 0x0c, 0x24 },
1520 { 0x0c, 0x24 },
1521 { 0x0d, 0x24 },
1522 { 0x11, 0x01 },
1523 { 0x12, 0x24 },
1524 { 0x13, 0x01 },
1525 { 0x14, 0x84 },
1526 { 0x15, 0x01 },
1527 { 0x16, 0x03 },
1528 { 0x17, 0x2f },
1529 { 0x18, 0xcf },
1530 { 0x19, 0x06 },
1531 { 0x1a, 0xf5 },
1532 { 0x1b, 0x00 },
1533 { 0x20, 0x18 },
1534 { 0x21, 0x80 },
1535 { 0x22, 0x80 },
1536 { 0x23, 0x00 },
1537 { 0x26, 0xa2 },
1538 { 0x27, 0xea },
b282d873 1539 { 0x28, 0x22 }, /* Was 0x20, bit1 enables a 2x gain which we need */
4202f71c
JFM		 1540 { 0x29, 0x00 },
1541 { 0x2a, 0x10 },
1542 { 0x2b, 0x00 },
1543 { 0x2c, 0x88 },
1544 { 0x2d, 0x91 },
1545 { 0x2e, 0x80 },
1546 { 0x2f, 0x44 },
1547 { 0x60, 0x27 },
1548 { 0x61, 0x02 },
1549 { 0x62, 0x5f },
1550 { 0x63, 0xd5 },
1551 { 0x64, 0x57 },
1552 { 0x65, 0x83 },
1553 { 0x66, 0x55 },
1554 { 0x67, 0x92 },
1555 { 0x68, 0xcf },
1556 { 0x69, 0x76 },
1557 { 0x6a, 0x22 },
1558 { 0x6b, 0x00 },
1559 { 0x6c, 0x02 },
1560 { 0x6d, 0x44 },
1561 { 0x6e, 0x80 },
1562 { 0x6f, 0x1d },
1563 { 0x70, 0x8b },
1564 { 0x71, 0x00 },
1565 { 0x72, 0x14 },
1566 { 0x73, 0x54 },
1567 { 0x74, 0x00 },
1568 { 0x75, 0x8e },
1569 { 0x76, 0x00 },
1570 { 0x77, 0xff },
1571 { 0x78, 0x80 },
1572 { 0x79, 0x80 },
1573 { 0x7a, 0x80 },
1574 { 0x7b, 0xe2 },
1575 { 0x7c, 0x00 },
1576};
1577
1578/* 7640 and 7648. The defaults should be OK for most registers. */
1579static const struct ov_i2c_regvals norm_7640[] = {
1580 { 0x12, 0x80 },
1581 { 0x12, 0x14 },
1582};
1583
42e142f6
JFM		 1584static const struct ov_regvals init_519_ov7660[] = {
1585 { 0x5d, 0x03 }, /* Turn off suspend mode */
1586 { 0x53, 0x9b }, /* 0x9f enables the (unused) microcontroller */
1587 { 0x54, 0x0f }, /* bit2 (jpeg enable) */
1588 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
1589 { 0xa3, 0x18 },
1590 { 0xa4, 0x04 },
1591 { 0xa5, 0x28 },
1592 { 0x37, 0x00 }, /* SetUsbInit */
1593 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
1594 /* Enable both fields, YUV Input, disable defect comp (why?) */
1595 { 0x20, 0x0c }, /* 0x0d does U <-> V swap */
1596 { 0x21, 0x38 },
1597 { 0x22, 0x1d },
1598 { 0x17, 0x50 }, /* undocumented */
1599 { 0x37, 0x00 }, /* undocumented */
1600 { 0x40, 0xff }, /* I2C timeout counter */
1601 { 0x46, 0x00 }, /* I2C clock prescaler */
1602};
1603static const struct ov_i2c_regvals norm_7660[] = {
1604 {OV7670_R12_COM7, OV7670_COM7_RESET},
1605 {OV7670_R11_CLKRC, 0x81},
1606 {0x92, 0x00}, /* DM_LNL */
1607 {0x93, 0x00}, /* DM_LNH */
1608 {0x9d, 0x4c}, /* BD50ST */
1609 {0x9e, 0x3f}, /* BD60ST */
1610 {OV7670_R3B_COM11, 0x02},
1611 {OV7670_R13_COM8, 0xf5},
1612 {OV7670_R10_AECH, 0x00},
1613 {OV7670_R00_GAIN, 0x00},
1614 {OV7670_R01_BLUE, 0x7c},
1615 {OV7670_R02_RED, 0x9d},
1616 {OV7670_R12_COM7, 0x00},
1617 {OV7670_R04_COM1, 00},
1618 {OV7670_R18_HSTOP, 0x01},
1619 {OV7670_R17_HSTART, 0x13},
1620 {OV7670_R32_HREF, 0x92},
1621 {OV7670_R19_VSTART, 0x02},
1622 {OV7670_R1A_VSTOP, 0x7a},
1623 {OV7670_R03_VREF, 0x00},
1624 {OV7670_R0E_COM5, 0x04},
1625 {OV7670_R0F_COM6, 0x62},
1626 {OV7670_R15_COM10, 0x00},
1627 {0x16, 0x02}, /* RSVD */
1628 {0x1b, 0x00}, /* PSHFT */
1629 {OV7670_R1E_MVFP, 0x01},
1630 {0x29, 0x3c}, /* RSVD */
1631 {0x33, 0x00}, /* CHLF */
1632 {0x34, 0x07}, /* ARBLM */
1633 {0x35, 0x84}, /* RSVD */
1634 {0x36, 0x00}, /* RSVD */
1635 {0x37, 0x04}, /* ADC */
1636 {0x39, 0x43}, /* OFON */
1637 {OV7670_R3A_TSLB, 0x00},
1638 {OV7670_R3C_COM12, 0x6c},
1639 {OV7670_R3D_COM13, 0x98},
1640 {OV7670_R3F_EDGE, 0x23},
1641 {OV7670_R40_COM15, 0xc1},
1642 {OV7670_R41_COM16, 0x22},
1643 {0x6b, 0x0a}, /* DBLV */
1644 {0xa1, 0x08}, /* RSVD */
1645 {0x69, 0x80}, /* HV */
1646 {0x43, 0xf0}, /* RSVD.. */
1647 {0x44, 0x10},
1648 {0x45, 0x78},
1649 {0x46, 0xa8},
1650 {0x47, 0x60},
1651 {0x48, 0x80},
1652 {0x59, 0xba},
1653 {0x5a, 0x9a},
1654 {0x5b, 0x22},
1655 {0x5c, 0xb9},
1656 {0x5d, 0x9b},
1657 {0x5e, 0x10},
1658 {0x5f, 0xe0},
1659 {0x60, 0x85},
1660 {0x61, 0x60},
1661 {0x9f, 0x9d}, /* RSVD */
1662 {0xa0, 0xa0}, /* DSPC2 */
1663 {0x4f, 0x60}, /* matrix */
1664 {0x50, 0x64},
1665 {0x51, 0x04},
1666 {0x52, 0x18},
1667 {0x53, 0x3c},
1668 {0x54, 0x54},
1669 {0x55, 0x40},
1670 {0x56, 0x40},
1671 {0x57, 0x40},
1672 {0x58, 0x0d}, /* matrix sign */
1673 {0x8b, 0xcc}, /* RSVD */
1674 {0x8c, 0xcc},
1675 {0x8d, 0xcf},
1676 {0x6c, 0x40}, /* gamma curve */
1677 {0x6d, 0xe0},
1678 {0x6e, 0xa0},
1679 {0x6f, 0x80},
1680 {0x70, 0x70},
1681 {0x71, 0x80},
1682 {0x72, 0x60},
1683 {0x73, 0x60},
1684 {0x74, 0x50},
1685 {0x75, 0x40},
1686 {0x76, 0x38},
1687 {0x77, 0x3c},
1688 {0x78, 0x32},
1689 {0x79, 0x1a},
1690 {0x7a, 0x28},
1691 {0x7b, 0x24},
1692 {0x7c, 0x04}, /* gamma curve */
1693 {0x7d, 0x12},
1694 {0x7e, 0x26},
1695 {0x7f, 0x46},
1696 {0x80, 0x54},
1697 {0x81, 0x64},
1698 {0x82, 0x70},
1699 {0x83, 0x7c},
1700 {0x84, 0x86},
1701 {0x85, 0x8e},
1702 {0x86, 0x9c},
1703 {0x87, 0xab},
1704 {0x88, 0xc4},
1705 {0x89, 0xd1},
1706 {0x8a, 0xe5},
1707 {OV7670_R14_COM9, 0x1e},
1708 {OV7670_R24_AEW, 0x80},
1709 {OV7670_R25_AEB, 0x72},
1710 {OV7670_R26_VPT, 0xb3},
1711 {0x62, 0x80}, /* LCC1 */
1712 {0x63, 0x80}, /* LCC2 */
1713 {0x64, 0x06}, /* LCC3 */
1714 {0x65, 0x00}, /* LCC4 */
1715 {0x66, 0x01}, /* LCC5 */
1716 {0x94, 0x0e}, /* RSVD.. */
1717 {0x95, 0x14},
1718 {OV7670_R13_COM8, OV7670_COM8_FASTAEC
1719 | OV7670_COM8_AECSTEP
1720 | OV7670_COM8_BFILT
1721 | 0x10
1722 | OV7670_COM8_AGC
1723 | OV7670_COM8_AWB
1724 | OV7670_COM8_AEC},
1725 {0xa1, 0xc8}
1726};
1727
4202f71c
JFM		 1728/* 7670. Defaults taken from OmniVision provided data,
1729* as provided by Jonathan Corbet of OLPC */
1730static const struct ov_i2c_regvals norm_7670[] = {
21867803
JFM		 1731 { OV7670_R12_COM7, OV7670_COM7_RESET },
1732 { OV7670_R3A_TSLB, 0x04 }, /* OV */
1733 { OV7670_R12_COM7, OV7670_COM7_FMT_VGA }, /* VGA */
1734 { OV7670_R11_CLKRC, 0x01 },
4202f71c
JFM		 1735/*
1736 * Set the hardware window. These values from OV don't entirely
1737 * make sense - hstop is less than hstart. But they work...
1738 */
21867803
JFM		 1739 { OV7670_R17_HSTART, 0x13 },
1740 { OV7670_R18_HSTOP, 0x01 },
1741 { OV7670_R32_HREF, 0xb6 },
1742 { OV7670_R19_VSTART, 0x02 },
1743 { OV7670_R1A_VSTOP, 0x7a },
1744 { OV7670_R03_VREF, 0x0a },
1745
1746 { OV7670_R0C_COM3, 0x00 },
1747 { OV7670_R3E_COM14, 0x00 },
4202f71c
JFM		 1748/* Mystery scaling numbers */
1749 { 0x70, 0x3a },
1750 { 0x71, 0x35 },
1751 { 0x72, 0x11 },
1752 { 0x73, 0xf0 },
1753 { 0xa2, 0x02 },
21867803 1754/* { OV7670_R15_COM10, 0x0 }, */
4202f71c
JFM		 1755
1756/* Gamma curve values */
1757 { 0x7a, 0x20 },
1758 { 0x7b, 0x10 },
1759 { 0x7c, 0x1e },
1760 { 0x7d, 0x35 },
1761 { 0x7e, 0x5a },
1762 { 0x7f, 0x69 },
1763 { 0x80, 0x76 },
1764 { 0x81, 0x80 },
1765 { 0x82, 0x88 },
1766 { 0x83, 0x8f },
1767 { 0x84, 0x96 },
1768 { 0x85, 0xa3 },
1769 { 0x86, 0xaf },
1770 { 0x87, 0xc4 },
1771 { 0x88, 0xd7 },
1772 { 0x89, 0xe8 },
1773
1774/* AGC and AEC parameters. Note we start by disabling those features,
1775 then turn them only after tweaking the values. */
21867803 1776 { OV7670_R13_COM8, OV7670_COM8_FASTAEC
4202f71c
JFM		 1777 | OV7670_COM8_AECSTEP
1778 | OV7670_COM8_BFILT },
21867803
JFM		 1779 { OV7670_R00_GAIN, 0x00 },
1780 { OV7670_R10_AECH, 0x00 },
1781 { OV7670_R0D_COM4, 0x40 }, /* magic reserved bit */
1782 { OV7670_R14_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
1783 { OV7670_RA5_BD50MAX, 0x05 },
1784 { OV7670_RAB_BD60MAX, 0x07 },
1785 { OV7670_R24_AEW, 0x95 },
1786 { OV7670_R25_AEB, 0x33 },
1787 { OV7670_R26_VPT, 0xe3 },
1788 { OV7670_R9F_HAECC1, 0x78 },
1789 { OV7670_RA0_HAECC2, 0x68 },
4202f71c 1790 { 0xa1, 0x03 }, /* magic */
21867803
JFM		 1791 { OV7670_RA6_HAECC3, 0xd8 },
1792 { OV7670_RA7_HAECC4, 0xd8 },
1793 { OV7670_RA8_HAECC5, 0xf0 },
1794 { OV7670_RA9_HAECC6, 0x90 },
1795 { OV7670_RAA_HAECC7, 0x94 },
1796 { OV7670_R13_COM8, OV7670_COM8_FASTAEC
4202f71c
JFM		 1797 | OV7670_COM8_AECSTEP
1798 | OV7670_COM8_BFILT
1799 | OV7670_COM8_AGC
1800 | OV7670_COM8_AEC },
1801
1802/* Almost all of these are magic "reserved" values. */
21867803
JFM		 1803 { OV7670_R0E_COM5, 0x61 },
1804 { OV7670_R0F_COM6, 0x4b },
4202f71c 1805 { 0x16, 0x02 },
21867803 1806 { OV7670_R1E_MVFP, 0x07 },
4202f71c
JFM		 1807 { 0x21, 0x02 },
1808 { 0x22, 0x91 },
1809 { 0x29, 0x07 },
1810 { 0x33, 0x0b },
1811 { 0x35, 0x0b },
1812 { 0x37, 0x1d },
1813 { 0x38, 0x71 },
1814 { 0x39, 0x2a },
21867803 1815 { OV7670_R3C_COM12, 0x78 },
4202f71c
JFM		 1816 { 0x4d, 0x40 },
1817 { 0x4e, 0x20 },
21867803 1818 { OV7670_R69_GFIX, 0x00 },
4202f71c
JFM		 1819 { 0x6b, 0x4a },
1820 { 0x74, 0x10 },
1821 { 0x8d, 0x4f },
ac40b1fa
JFM		 1822 { 0x8e, 0x00 },
1823 { 0x8f, 0x00 },
1824 { 0x90, 0x00 },
1825 { 0x91, 0x00 },
1826 { 0x96, 0x00 },
1827 { 0x9a, 0x00 },
4202f71c
JFM		 1828 { 0xb0, 0x84 },
1829 { 0xb1, 0x0c },
1830 { 0xb2, 0x0e },
1831 { 0xb3, 0x82 },
1832 { 0xb8, 0x0a },
1833
1834/* More reserved magic, some of which tweaks white balance */
1835 { 0x43, 0x0a },
1836 { 0x44, 0xf0 },
1837 { 0x45, 0x34 },
1838 { 0x46, 0x58 },
1839 { 0x47, 0x28 },
1840 { 0x48, 0x3a },
1841 { 0x59, 0x88 },
1842 { 0x5a, 0x88 },
1843 { 0x5b, 0x44 },
1844 { 0x5c, 0x67 },
1845 { 0x5d, 0x49 },
1846 { 0x5e, 0x0e },
1847 { 0x6c, 0x0a },
1848 { 0x6d, 0x55 },
1849 { 0x6e, 0x11 },
1850 { 0x6f, 0x9f },
1851 /* "9e for advance AWB" */
1852 { 0x6a, 0x40 },
21867803
JFM		 1853 { OV7670_R01_BLUE, 0x40 },
1854 { OV7670_R02_RED, 0x60 },
1855 { OV7670_R13_COM8, OV7670_COM8_FASTAEC
4202f71c
JFM		 1856 | OV7670_COM8_AECSTEP
1857 | OV7670_COM8_BFILT
1858 | OV7670_COM8_AGC
1859 | OV7670_COM8_AEC
1860 | OV7670_COM8_AWB },
1861
1862/* Matrix coefficients */
1863 { 0x4f, 0x80 },
1864 { 0x50, 0x80 },
ac40b1fa 1865 { 0x51, 0x00 },
4202f71c
JFM		 1866 { 0x52, 0x22 },
1867 { 0x53, 0x5e },
1868 { 0x54, 0x80 },
1869 { 0x58, 0x9e },
1870
21867803
JFM		 1871 { OV7670_R41_COM16, OV7670_COM16_AWBGAIN },
1872 { OV7670_R3F_EDGE, 0x00 },
4202f71c
JFM		 1873 { 0x75, 0x05 },
1874 { 0x76, 0xe1 },
ac40b1fa 1875 { 0x4c, 0x00 },
4202f71c 1876 { 0x77, 0x01 },
21867803 1877 { OV7670_R3D_COM13, OV7670_COM13_GAMMA
4202f71c
JFM		 1878 | OV7670_COM13_UVSAT
1879 | 2}, /* was 3 */
1880 { 0x4b, 0x09 },
1881 { 0xc9, 0x60 },
21867803 1882 { OV7670_R41_COM16, 0x38 },
4202f71c
JFM		 1883 { 0x56, 0x40 },
1884
1885 { 0x34, 0x11 },
21867803 1886 { OV7670_R3B_COM11, OV7670_COM11_EXP|OV7670_COM11_HZAUTO },
4202f71c 1887 { 0xa4, 0x88 },
ac40b1fa 1888 { 0x96, 0x00 },
4202f71c
JFM		 1889 { 0x97, 0x30 },
1890 { 0x98, 0x20 },
1891 { 0x99, 0x30 },
1892 { 0x9a, 0x84 },
1893 { 0x9b, 0x29 },
1894 { 0x9c, 0x03 },
1895 { 0x9d, 0x4c },
1896 { 0x9e, 0x3f },
1897 { 0x78, 0x04 },
1898
1899/* Extra-weird stuff. Some sort of multiplexor register */
1900 { 0x79, 0x01 },
1901 { 0xc8, 0xf0 },
1902 { 0x79, 0x0f },
1903 { 0xc8, 0x00 },
1904 { 0x79, 0x10 },
1905 { 0xc8, 0x7e },
1906 { 0x79, 0x0a },
1907 { 0xc8, 0x80 },
1908 { 0x79, 0x0b },
1909 { 0xc8, 0x01 },
1910 { 0x79, 0x0c },
1911 { 0xc8, 0x0f },
1912 { 0x79, 0x0d },
1913 { 0xc8, 0x20 },
1914 { 0x79, 0x09 },
1915 { 0xc8, 0x80 },
1916 { 0x79, 0x02 },
1917 { 0xc8, 0xc0 },
1918 { 0x79, 0x03 },
1919 { 0xc8, 0x40 },
1920 { 0x79, 0x05 },
1921 { 0xc8, 0x30 },
1922 { 0x79, 0x26 },
1923};
1924
1925static const struct ov_i2c_regvals norm_8610[] = {
1926 { 0x12, 0x80 },
1927 { 0x00, 0x00 },
1928 { 0x01, 0x80 },
1929 { 0x02, 0x80 },
1930 { 0x03, 0xc0 },
1931 { 0x04, 0x30 },
1932 { 0x05, 0x30 }, /* was 0x10, new from windrv 090403 */
1933 { 0x06, 0x70 }, /* was 0x80, new from windrv 090403 */
1934 { 0x0a, 0x86 },
1935 { 0x0b, 0xb0 },
1936 { 0x0c, 0x20 },
1937 { 0x0d, 0x20 },
1938 { 0x11, 0x01 },
1939 { 0x12, 0x25 },
1940 { 0x13, 0x01 },
1941 { 0x14, 0x04 },
1942 { 0x15, 0x01 }, /* Lin and Win think different about UV order */
1943 { 0x16, 0x03 },
1944 { 0x17, 0x38 }, /* was 0x2f, new from windrv 090403 */
1945 { 0x18, 0xea }, /* was 0xcf, new from windrv 090403 */
1946 { 0x19, 0x02 }, /* was 0x06, new from windrv 090403 */
1947 { 0x1a, 0xf5 },
1948 { 0x1b, 0x00 },
1949 { 0x20, 0xd0 }, /* was 0x90, new from windrv 090403 */
1950 { 0x23, 0xc0 }, /* was 0x00, new from windrv 090403 */
1951 { 0x24, 0x30 }, /* was 0x1d, new from windrv 090403 */
1952 { 0x25, 0x50 }, /* was 0x57, new from windrv 090403 */
1953 { 0x26, 0xa2 },
1954 { 0x27, 0xea },
1955 { 0x28, 0x00 },
1956 { 0x29, 0x00 },
1957 { 0x2a, 0x80 },
1958 { 0x2b, 0xc8 }, /* was 0xcc, new from windrv 090403 */
1959 { 0x2c, 0xac },
1960 { 0x2d, 0x45 }, /* was 0xd5, new from windrv 090403 */
1961 { 0x2e, 0x80 },
1962 { 0x2f, 0x14 }, /* was 0x01, new from windrv 090403 */
1963 { 0x4c, 0x00 },
1964 { 0x4d, 0x30 }, /* was 0x10, new from windrv 090403 */
1965 { 0x60, 0x02 }, /* was 0x01, new from windrv 090403 */
1966 { 0x61, 0x00 }, /* was 0x09, new from windrv 090403 */
1967 { 0x62, 0x5f }, /* was 0xd7, new from windrv 090403 */
1968 { 0x63, 0xff },
1969 { 0x64, 0x53 }, /* new windrv 090403 says 0x57,
1970 * maybe thats wrong */
1971 { 0x65, 0x00 },
1972 { 0x66, 0x55 },
1973 { 0x67, 0xb0 },
1974 { 0x68, 0xc0 }, /* was 0xaf, new from windrv 090403 */
1975 { 0x69, 0x02 },
1976 { 0x6a, 0x22 },
1977 { 0x6b, 0x00 },
1978 { 0x6c, 0x99 }, /* was 0x80, old windrv says 0x00, but
1979 * deleting bit7 colors the first images red */
1980 { 0x6d, 0x11 }, /* was 0x00, new from windrv 090403 */
1981 { 0x6e, 0x11 }, /* was 0x00, new from windrv 090403 */
1982 { 0x6f, 0x01 },
1983 { 0x70, 0x8b },
1984 { 0x71, 0x00 },
1985 { 0x72, 0x14 },
1986 { 0x73, 0x54 },
1987 { 0x74, 0x00 },/* 0x60? - was 0x00, new from windrv 090403 */
1988 { 0x75, 0x0e },
1989 { 0x76, 0x02 }, /* was 0x02, new from windrv 090403 */
1990 { 0x77, 0xff },
1991 { 0x78, 0x80 },
1992 { 0x79, 0x80 },
1993 { 0x7a, 0x80 },
1994 { 0x7b, 0x10 }, /* was 0x13, new from windrv 090403 */
1995 { 0x7c, 0x00 },
1996 { 0x7d, 0x08 }, /* was 0x09, new from windrv 090403 */
1997 { 0x7e, 0x08 }, /* was 0xc0, new from windrv 090403 */
1998 { 0x7f, 0xfb },
1999 { 0x80, 0x28 },
2000 { 0x81, 0x00 },
2001 { 0x82, 0x23 },
2002 { 0x83, 0x0b },
2003 { 0x84, 0x00 },
2004 { 0x85, 0x62 }, /* was 0x61, new from windrv 090403 */
2005 { 0x86, 0xc9 },
2006 { 0x87, 0x00 },
2007 { 0x88, 0x00 },
2008 { 0x89, 0x01 },
2009 { 0x12, 0x20 },
2010 { 0x12, 0x25 }, /* was 0x24, new from windrv 090403 */
2011};
2012
6a7eba24
JFM		 2013static unsigned char ov7670_abs_to_sm(unsigned char v)
2014{
2015 if (v > 127)
2016 return v & 0x7f;
2017 return (128 - v) | 0x80;
2018}
2019
2020/* Write a OV519 register */
f8f20188 2021static void reg_w(struct sd *sd, u16 index, u16 value)
6a7eba24 2022{
a511ba94 2023 int ret, req = 0;
b46aaa02 2024
f8f20188
JFM		 2025 if (sd->gspca_dev.usb_err < 0)
2026 return;
2027
b46aaa02
HG		 2028 switch (sd->bridge) {
2029 case BRIDGE_OV511:
2030 case BRIDGE_OV511PLUS:
2031 req = 2;
2032 break;
2033 case BRIDGE_OVFX2:
a511ba94
HG		 2034 req = 0x0a;
2035 /* fall through */
2036 case BRIDGE_W9968CF:
858ea5e9
JFM		 2037 PDEBUG(D_USBO, "SET %02x %04x %04x",
2038 req, value, index);
b46aaa02
HG		 2039 ret = usb_control_msg(sd->gspca_dev.dev,
2040 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
a511ba94 2041 req,
b46aaa02 2042 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
a511ba94 2043 value, index, NULL, 0, 500);
b46aaa02
HG		 2044 goto leave;
2045 default:
2046 req = 1;
2047 }
6a7eba24 2048
858ea5e9
JFM		 2049 PDEBUG(D_USBO, "SET %02x 0000 %04x %02x",
2050 req, index, value);
739570bb 2051 sd->gspca_dev.usb_buf[0] = value;
6a7eba24
JFM		 2052 ret = usb_control_msg(sd->gspca_dev.dev,
2053 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 2054 req,
6a7eba24
JFM		 2055 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2056 0, index,
739570bb 2057 sd->gspca_dev.usb_buf, 1, 500);
b46aaa02 2058leave:
a511ba94 2059 if (ret < 0) {
858ea5e9 2060 err("reg_w %02x failed %d", index, ret);
f8f20188
JFM		 2061 sd->gspca_dev.usb_err = ret;
2062 return;
a511ba94 2063 }
6a7eba24
JFM		 2064}
2065
a511ba94 2066/* Read from a OV519 register, note not valid for the w9968cf!! */
6a7eba24 2067/* returns: negative is error, pos or zero is data */
9d1593a8 2068static int reg_r(struct sd *sd, u16 index)
6a7eba24
JFM		 2069{
2070 int ret;
b46aaa02
HG		 2071 int req;
2072
f8f20188
JFM		 2073 if (sd->gspca_dev.usb_err < 0)
2074 return -1;
2075
b46aaa02
HG		 2076 switch (sd->bridge) {
2077 case BRIDGE_OV511:
2078 case BRIDGE_OV511PLUS:
2079 req = 3;
2080 break;
2081 case BRIDGE_OVFX2:
2082 req = 0x0b;
2083 break;
2084 default:
2085 req = 1;
2086 }
6a7eba24
JFM		 2087
2088 ret = usb_control_msg(sd->gspca_dev.dev,
2089 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 2090 req,
6a7eba24 2091 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 2092 0, index, sd->gspca_dev.usb_buf, 1, 500);
6a7eba24 2093
a511ba94 2094 if (ret >= 0) {
739570bb 2095 ret = sd->gspca_dev.usb_buf[0];
858ea5e9
JFM		 2096 PDEBUG(D_USBI, "GET %02x 0000 %04x %02x",
2097 req, index, ret);
f8f20188 2098 } else {
858ea5e9 2099 err("reg_r %02x failed %d", index, ret);
f8f20188
JFM		 2100 sd->gspca_dev.usb_err = ret;
2101 }
a511ba94 2102
6a7eba24
JFM		 2103 return ret;
2104}
2105
2106/* Read 8 values from a OV519 register */
2107static int reg_r8(struct sd *sd,
9d1593a8 2108 u16 index)
6a7eba24
JFM		 2109{
2110 int ret;
6a7eba24 2111
f8f20188
JFM		 2112 if (sd->gspca_dev.usb_err < 0)
2113 return -1;
2114
6a7eba24
JFM		 2115 ret = usb_control_msg(sd->gspca_dev.dev,
2116 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2117 1, /* REQ_IO */
2118 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 2119 0, index, sd->gspca_dev.usb_buf, 8, 500);
6a7eba24 2120
f8f20188 2121 if (ret >= 0) {
739570bb 2122 ret = sd->gspca_dev.usb_buf[0];
f8f20188 2123 } else {
858ea5e9 2124 err("reg_r8 %02x failed %d", index, ret);
f8f20188
JFM		 2125 sd->gspca_dev.usb_err = ret;
2126 }
a511ba94 2127
6a7eba24
JFM		 2128 return ret;
2129}
2130
2131/*
2132 * Writes bits at positions specified by mask to an OV51x reg. Bits that are in
2133 * the same position as 1's in "mask" are cleared and set to "value". Bits
2134 * that are in the same position as 0's in "mask" are preserved, regardless
2135 * of their respective state in "value".
2136 */
f8f20188 2137static void reg_w_mask(struct sd *sd,
9d1593a8
JFM		 2138 u16 index,
2139 u8 value,
2140 u8 mask)
6a7eba24
JFM		 2141{
2142 int ret;
9d1593a8 2143 u8 oldval;
6a7eba24
JFM		 2144
2145 if (mask != 0xff) {
2146 value &= mask; /* Enforce mask on value */
2147 ret = reg_r(sd, index);
2148 if (ret < 0)
f8f20188 2149 return;
6a7eba24
JFM		 2150
2151 oldval = ret & ~mask; /* Clear the masked bits */
2152 value |= oldval; /* Set the desired bits */
2153 }
f8f20188 2154 reg_w(sd, index, value);
6a7eba24
JFM		 2155}
2156
49809d6a
HG		 2157/*
2158 * Writes multiple (n) byte value to a single register. Only valid with certain
2159 * registers (0x30 and 0xc4 - 0xce).
2160 */
f8f20188 2161static void ov518_reg_w32(struct sd *sd, u16 index, u32 value, int n)
49809d6a
HG		 2162{
2163 int ret;
2164
f8f20188
JFM		 2165 if (sd->gspca_dev.usb_err < 0)
2166 return;
2167
83955556 2168 *((__le32 *) sd->gspca_dev.usb_buf) = __cpu_to_le32(value);
49809d6a
HG		 2169
2170 ret = usb_control_msg(sd->gspca_dev.dev,
2171 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2172 1 /* REG_IO */,
2173 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2174 0, index,
2175 sd->gspca_dev.usb_buf, n, 500);
a511ba94 2176 if (ret < 0) {
858ea5e9 2177 err("reg_w32 %02x failed %d", index, ret);
f8f20188 2178 sd->gspca_dev.usb_err = ret;
a511ba94 2179 }
49809d6a
HG		 2180}
2181
f8f20188 2182static void ov511_i2c_w(struct sd *sd, u8 reg, u8 value)
1876bb92
HG		 2183{
2184 int rc, retries;
2185
858ea5e9 2186 PDEBUG(D_USBO, "ov511_i2c_w %02x %02x", reg, value);
1876bb92
HG		 2187
2188 /* Three byte write cycle */
2189 for (retries = 6; ; ) {
2190 /* Select camera register */
f8f20188 2191 reg_w(sd, R51x_I2C_SADDR_3, reg);
1876bb92
HG		 2192
2193 /* Write "value" to I2C data port of OV511 */
f8f20188 2194 reg_w(sd, R51x_I2C_DATA, value);
1876bb92
HG		 2195
2196 /* Initiate 3-byte write cycle */
f8f20188 2197 reg_w(sd, R511_I2C_CTL, 0x01);
1876bb92 2198
83955556 2199 do {
1876bb92 2200 rc = reg_r(sd, R511_I2C_CTL);
83955556 2201 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2202
2203 if (rc < 0)
f8f20188 2204 return;
1876bb92
HG		 2205
2206 if ((rc & 2) == 0) /* Ack? */
2207 break;
2208 if (--retries < 0) {
2209 PDEBUG(D_USBO, "i2c write retries exhausted");
f8f20188 2210 return;
1876bb92
HG		 2211 }
2212 }
1876bb92
HG		 2213}
2214
9d1593a8 2215static int ov511_i2c_r(struct sd *sd, u8 reg)
1876bb92
HG		 2216{
2217 int rc, value, retries;
2218
2219 /* Two byte write cycle */
2220 for (retries = 6; ; ) {
2221 /* Select camera register */
f8f20188 2222 reg_w(sd, R51x_I2C_SADDR_2, reg);
1876bb92
HG		 2223
2224 /* Initiate 2-byte write cycle */
f8f20188 2225 reg_w(sd, R511_I2C_CTL, 0x03);
1876bb92 2226
83955556 2227 do {
1876bb92 2228 rc = reg_r(sd, R511_I2C_CTL);
83955556 2229 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2230
2231 if (rc < 0)
2232 return rc;
2233
2234 if ((rc & 2) == 0) /* Ack? */
2235 break;
2236
2237 /* I2C abort */
2238 reg_w(sd, R511_I2C_CTL, 0x10);
2239
2240 if (--retries < 0) {
2241 PDEBUG(D_USBI, "i2c write retries exhausted");
2242 return -1;
2243 }
2244 }
2245
2246 /* Two byte read cycle */
2247 for (retries = 6; ; ) {
2248 /* Initiate 2-byte read cycle */
f8f20188 2249 reg_w(sd, R511_I2C_CTL, 0x05);
1876bb92 2250
83955556 2251 do {
1876bb92 2252 rc = reg_r(sd, R511_I2C_CTL);
83955556 2253 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2254
2255 if (rc < 0)
2256 return rc;
2257
2258 if ((rc & 2) == 0) /* Ack? */
2259 break;
2260
2261 /* I2C abort */
f8f20188 2262 reg_w(sd, R511_I2C_CTL, 0x10);
1876bb92
HG		 2263
2264 if (--retries < 0) {
2265 PDEBUG(D_USBI, "i2c read retries exhausted");
2266 return -1;
2267 }
2268 }
2269
2270 value = reg_r(sd, R51x_I2C_DATA);
2271
858ea5e9 2272 PDEBUG(D_USBI, "ov511_i2c_r %02x %02x", reg, value);
1876bb92
HG		 2273
2274 /* This is needed to make i2c_w() work */
f8f20188 2275 reg_w(sd, R511_I2C_CTL, 0x05);
1876bb92
HG		 2276
2277 return value;
2278}
49809d6a 2279
6a7eba24
JFM		 2280/*
2281 * The OV518 I2C I/O procedure is different, hence, this function.
2282 * This is normally only called from i2c_w(). Note that this function
2283 * always succeeds regardless of whether the sensor is present and working.
2284 */
f8f20188 2285static void ov518_i2c_w(struct sd *sd,
9d1593a8
JFM		 2286 u8 reg,
2287 u8 value)
6a7eba24 2288{
858ea5e9 2289 PDEBUG(D_USBO, "ov518_i2c_w %02x %02x", reg, value);
6a7eba24
JFM		 2290
2291 /* Select camera register */
f8f20188 2292 reg_w(sd, R51x_I2C_SADDR_3, reg);
6a7eba24
JFM		 2293
2294 /* Write "value" to I2C data port of OV511 */
f8f20188 2295 reg_w(sd, R51x_I2C_DATA, value);
6a7eba24
JFM		 2296
2297 /* Initiate 3-byte write cycle */
f8f20188 2298 reg_w(sd, R518_I2C_CTL, 0x01);
6a7eba24
JFM		 2299
2300 /* wait for write complete */
2301 msleep(4);
f8f20188 2302 reg_r8(sd, R518_I2C_CTL);
6a7eba24
JFM		 2303}
2304
2305/*
2306 * returns: negative is error, pos or zero is data
2307 *
2308 * The OV518 I2C I/O procedure is different, hence, this function.
2309 * This is normally only called from i2c_r(). Note that this function
2310 * always succeeds regardless of whether the sensor is present and working.
2311 */
9d1593a8 2312static int ov518_i2c_r(struct sd *sd, u8 reg)
6a7eba24 2313{
f8f20188 2314 int value;
6a7eba24
JFM		 2315
2316 /* Select camera register */
f8f20188 2317 reg_w(sd, R51x_I2C_SADDR_2, reg);
6a7eba24
JFM		 2318
2319 /* Initiate 2-byte write cycle */
f8f20188 2320 reg_w(sd, R518_I2C_CTL, 0x03);
6a7eba24
JFM		 2321
2322 /* Initiate 2-byte read cycle */
f8f20188 2323 reg_w(sd, R518_I2C_CTL, 0x05);
6a7eba24 2324 value = reg_r(sd, R51x_I2C_DATA);
858ea5e9 2325 PDEBUG(D_USBI, "ov518_i2c_r %02x %02x", reg, value);
6a7eba24
JFM		 2326 return value;
2327}
2328
f8f20188 2329static void ovfx2_i2c_w(struct sd *sd, u8 reg, u8 value)
b46aaa02
HG		 2330{
2331 int ret;
2332
f8f20188
JFM		 2333 if (sd->gspca_dev.usb_err < 0)
2334 return;
2335
b46aaa02
HG		 2336 ret = usb_control_msg(sd->gspca_dev.dev,
2337 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2338 0x02,
2339 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
9d1593a8 2340 (u16) value, (u16) reg, NULL, 0, 500);
b46aaa02 2341
a511ba94 2342 if (ret < 0) {
858ea5e9 2343 err("ovfx2_i2c_w %02x failed %d", reg, ret);
f8f20188 2344 sd->gspca_dev.usb_err = ret;
a511ba94 2345 }
b46aaa02 2346
858ea5e9 2347 PDEBUG(D_USBO, "ovfx2_i2c_w %02x %02x", reg, value);
b46aaa02
HG		 2348}
2349
9d1593a8 2350static int ovfx2_i2c_r(struct sd *sd, u8 reg)
b46aaa02
HG		 2351{
2352 int ret;
2353
f8f20188
JFM		 2354 if (sd->gspca_dev.usb_err < 0)
2355 return -1;
2356
b46aaa02
HG		 2357 ret = usb_control_msg(sd->gspca_dev.dev,
2358 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2359 0x03,
2360 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
9d1593a8 2361 0, (u16) reg, sd->gspca_dev.usb_buf, 1, 500);
b46aaa02
HG		 2362
2363 if (ret >= 0) {
2364 ret = sd->gspca_dev.usb_buf[0];
858ea5e9 2365 PDEBUG(D_USBI, "ovfx2_i2c_r %02x %02x", reg, ret);
f8f20188 2366 } else {
858ea5e9 2367 err("ovfx2_i2c_r %02x failed %d", reg, ret);
f8f20188
JFM		 2368 sd->gspca_dev.usb_err = ret;
2369 }
b46aaa02
HG		 2370
2371 return ret;
2372}
2373
f8f20188 2374static void i2c_w(struct sd *sd, u8 reg, u8 value)
1876bb92 2375{
fb1f9020 2376 if (sd->sensor_reg_cache[reg] == value)
f8f20188 2377 return;
fb1f9020 2378
1876bb92
HG		 2379 switch (sd->bridge) {
2380 case BRIDGE_OV511:
2381 case BRIDGE_OV511PLUS:
f8f20188 2382 ov511_i2c_w(sd, reg, value);
fb1f9020 2383 break;
1876bb92
HG		 2384 case BRIDGE_OV518:
2385 case BRIDGE_OV518PLUS:
2386 case BRIDGE_OV519:
f8f20188 2387 ov518_i2c_w(sd, reg, value);
fb1f9020 2388 break;
b46aaa02 2389 case BRIDGE_OVFX2:
f8f20188 2390 ovfx2_i2c_w(sd, reg, value);
fb1f9020 2391 break;
a511ba94 2392 case BRIDGE_W9968CF:
f8f20188 2393 w9968cf_i2c_w(sd, reg, value);
fb1f9020 2394 break;
1876bb92 2395 }
fb1f9020 2396
f8f20188 2397 if (sd->gspca_dev.usb_err >= 0) {
fb1f9020
HG		 2398 /* Up on sensor reset empty the register cache */
2399 if (reg == 0x12 && (value & 0x80))
2400 memset(sd->sensor_reg_cache, -1,
87bae740 2401 sizeof(sd->sensor_reg_cache));
fb1f9020
HG		 2402 else
2403 sd->sensor_reg_cache[reg] = value;
2404 }
1876bb92
HG		 2405}
2406
9d1593a8 2407static int i2c_r(struct sd *sd, u8 reg)
1876bb92 2408{
8394bcf3 2409 int ret = -1;
fb1f9020
HG		 2410
2411 if (sd->sensor_reg_cache[reg] != -1)
2412 return sd->sensor_reg_cache[reg];
2413
1876bb92
HG		 2414 switch (sd->bridge) {
2415 case BRIDGE_OV511:
2416 case BRIDGE_OV511PLUS:
fb1f9020
HG		 2417 ret = ov511_i2c_r(sd, reg);
2418 break;
1876bb92
HG		 2419 case BRIDGE_OV518:
2420 case BRIDGE_OV518PLUS:
2421 case BRIDGE_OV519:
fb1f9020
HG		 2422 ret = ov518_i2c_r(sd, reg);
2423 break;
b46aaa02 2424 case BRIDGE_OVFX2:
fb1f9020
HG		 2425 ret = ovfx2_i2c_r(sd, reg);
2426 break;
a511ba94 2427 case BRIDGE_W9968CF:
fb1f9020
HG		 2428 ret = w9968cf_i2c_r(sd, reg);
2429 break;
1876bb92 2430 }
fb1f9020
HG		 2431
2432 if (ret >= 0)
2433 sd->sensor_reg_cache[reg] = ret;
2434
2435 return ret;
1876bb92
HG		 2436}
2437
6a7eba24
JFM		 2438/* Writes bits at positions specified by mask to an I2C reg. Bits that are in
2439 * the same position as 1's in "mask" are cleared and set to "value". Bits
2440 * that are in the same position as 0's in "mask" are preserved, regardless
2441 * of their respective state in "value".
2442 */
f8f20188 2443static void i2c_w_mask(struct sd *sd,
9d1593a8
JFM		 2444 u8 reg,
2445 u8 value,
2446 u8 mask)
6a7eba24
JFM		 2447{
2448 int rc;
9d1593a8 2449 u8 oldval;
6a7eba24
JFM		 2450
2451 value &= mask; /* Enforce mask on value */
2452 rc = i2c_r(sd, reg);
2453 if (rc < 0)
f8f20188 2454 return;
6a7eba24
JFM		 2455 oldval = rc & ~mask; /* Clear the masked bits */
2456 value |= oldval; /* Set the desired bits */
f8f20188 2457 i2c_w(sd, reg, value);
6a7eba24
JFM		 2458}
2459
2460/* Temporarily stops OV511 from functioning. Must do this before changing
2461 * registers while the camera is streaming */
f8f20188 2462static inline void ov51x_stop(struct sd *sd)
6a7eba24
JFM		 2463{
2464 PDEBUG(D_STREAM, "stopping");
2465 sd->stopped = 1;
49809d6a
HG		 2466 switch (sd->bridge) {
2467 case BRIDGE_OV511:
2468 case BRIDGE_OV511PLUS:
f8f20188
JFM		 2469 reg_w(sd, R51x_SYS_RESET, 0x3d);
2470 break;
49809d6a
HG		 2471 case BRIDGE_OV518:
2472 case BRIDGE_OV518PLUS:
f8f20188
JFM		 2473 reg_w_mask(sd, R51x_SYS_RESET, 0x3a, 0x3a);
2474 break;
49809d6a 2475 case BRIDGE_OV519:
f8f20188 2476 reg_w(sd, OV519_R51_RESET1, 0x0f);
5927abcb
JFM		 2477 reg_w(sd, OV519_R51_RESET1, 0x00);
2478 reg_w(sd, 0x22, 0x00); /* FRAR */
f8f20188 2479 break;
b46aaa02 2480 case BRIDGE_OVFX2:
f8f20188
JFM		 2481 reg_w_mask(sd, 0x0f, 0x00, 0x02);
2482 break;
a511ba94 2483 case BRIDGE_W9968CF:
f8f20188
JFM		 2484 reg_w(sd, 0x3c, 0x0a05); /* stop USB transfer */
2485 break;
49809d6a 2486 }
6a7eba24
JFM		 2487}
2488
2489/* Restarts OV511 after ov511_stop() is called. Has no effect if it is not
2490 * actually stopped (for performance). */
f8f20188 2491static inline void ov51x_restart(struct sd *sd)
6a7eba24
JFM		 2492{
2493 PDEBUG(D_STREAM, "restarting");
2494 if (!sd->stopped)
f8f20188 2495 return;
6a7eba24
JFM		 2496 sd->stopped = 0;
2497
2498 /* Reinitialize the stream */
49809d6a
HG		 2499 switch (sd->bridge) {
2500 case BRIDGE_OV511:
2501 case BRIDGE_OV511PLUS:
f8f20188
JFM		 2502 reg_w(sd, R51x_SYS_RESET, 0x00);
2503 break;
49809d6a
HG		 2504 case BRIDGE_OV518:
2505 case BRIDGE_OV518PLUS:
f8f20188
JFM		 2506 reg_w(sd, 0x2f, 0x80);
2507 reg_w(sd, R51x_SYS_RESET, 0x00);
2508 break;
49809d6a 2509 case BRIDGE_OV519:
5927abcb 2510 reg_w(sd, OV519_R51_RESET1, 0x0f);
f8f20188 2511 reg_w(sd, OV519_R51_RESET1, 0x00);
5927abcb 2512 reg_w(sd, 0x22, 0x1d); /* FRAR */
f8f20188 2513 break;
b46aaa02 2514 case BRIDGE_OVFX2:
f8f20188
JFM		 2515 reg_w_mask(sd, 0x0f, 0x02, 0x02);
2516 break;
a511ba94 2517 case BRIDGE_W9968CF:
f8f20188
JFM		 2518 reg_w(sd, 0x3c, 0x8a05); /* USB FIFO enable */
2519 break;
49809d6a 2520 }
6a7eba24
JFM		 2521}
2522
f8f20188 2523static void ov51x_set_slave_ids(struct sd *sd, u8 slave);
229bb7dc 2524
6a7eba24
JFM		 2525/* This does an initial reset of an OmniVision sensor and ensures that I2C
2526 * is synchronized. Returns <0 on failure.
2527 */
9d1593a8 2528static int init_ov_sensor(struct sd *sd, u8 slave)
6a7eba24 2529{
ac40b1fa 2530 int i;
6a7eba24 2531
f8f20188 2532 ov51x_set_slave_ids(sd, slave);
229bb7dc 2533
6a7eba24 2534 /* Reset the sensor */
f8f20188 2535 i2c_w(sd, 0x12, 0x80);
6a7eba24
JFM		 2536
2537 /* Wait for it to initialize */
2538 msleep(150);
2539
ac40b1fa 2540 for (i = 0; i < i2c_detect_tries; i++) {
6a7eba24
JFM		 2541 if (i2c_r(sd, OV7610_REG_ID_HIGH) == 0x7f &&
2542 i2c_r(sd, OV7610_REG_ID_LOW) == 0xa2) {
ac40b1fa
JFM		 2543 PDEBUG(D_PROBE, "I2C synced in %d attempt(s)", i);
2544 return 0;
6a7eba24
JFM		 2545 }
2546
2547 /* Reset the sensor */
f8f20188
JFM		 2548 i2c_w(sd, 0x12, 0x80);
2549
6a7eba24
JFM		 2550 /* Wait for it to initialize */
2551 msleep(150);
87bae740 2552
6a7eba24
JFM		 2553 /* Dummy read to sync I2C */
2554 if (i2c_r(sd, 0x00) < 0)
f8f20188 2555 return -1;
6a7eba24 2556 }
f8f20188 2557 return -1;
6a7eba24
JFM		 2558}
2559
6a7eba24
JFM		 2560/* Set the read and write slave IDs. The "slave" argument is the write slave,
2561 * and the read slave will be set to (slave + 1).
2562 * This should not be called from outside the i2c I/O functions.
2563 * Sets I2C read and write slave IDs. Returns <0 for error
2564 */
f8f20188 2565static void ov51x_set_slave_ids(struct sd *sd,
9d1593a8 2566 u8 slave)
6a7eba24 2567{
a511ba94
HG		 2568 switch (sd->bridge) {
2569 case BRIDGE_OVFX2:
f8f20188
JFM		 2570 reg_w(sd, OVFX2_I2C_ADDR, slave);
2571 return;
a511ba94
HG		 2572 case BRIDGE_W9968CF:
2573 sd->sensor_addr = slave;
f8f20188 2574 return;
a511ba94 2575 }
b46aaa02 2576
f8f20188
JFM		 2577 reg_w(sd, R51x_I2C_W_SID, slave);
2578 reg_w(sd, R51x_I2C_R_SID, slave + 1);
6a7eba24
JFM		 2579}
2580
f8f20188 2581static void write_regvals(struct sd *sd,
a5ae2062 2582 const struct ov_regvals *regvals,
6a7eba24
JFM		 2583 int n)
2584{
6a7eba24 2585 while (--n >= 0) {
f8f20188 2586 reg_w(sd, regvals->reg, regvals->val);
6a7eba24
JFM		 2587 regvals++;
2588 }
6a7eba24
JFM		 2589}
2590
f8f20188
JFM		 2591static void write_i2c_regvals(struct sd *sd,
2592 const struct ov_i2c_regvals *regvals,
2593 int n)
6a7eba24 2594{
6a7eba24 2595 while (--n >= 0) {
f8f20188 2596 i2c_w(sd, regvals->reg, regvals->val);
6a7eba24
JFM		 2597 regvals++;
2598 }
6a7eba24
JFM		 2599}
2600
2601/****************************************************************************
2602 *
2603 * OV511 and sensor configuration
2604 *
2605 ***************************************************************************/
2606
635118d5 2607/* This initializes the OV2x10 / OV3610 / OV3620 */
f8f20188 2608static void ov_hires_configure(struct sd *sd)
635118d5
HG		 2609{
2610 int high, low;
2611
2612 if (sd->bridge != BRIDGE_OVFX2) {
0b656321 2613 err("error hires sensors only supported with ovfx2");
f8f20188 2614 return;
635118d5
HG		 2615 }
2616
2617 PDEBUG(D_PROBE, "starting ov hires configuration");
2618
2619 /* Detect sensor (sub)type */
2620 high = i2c_r(sd, 0x0a);
2621 low = i2c_r(sd, 0x0b);
2622 /* info("%x, %x", high, low); */
2623 if (high == 0x96 && low == 0x40) {
2624 PDEBUG(D_PROBE, "Sensor is an OV2610");
2625 sd->sensor = SEN_OV2610;
2626 } else if (high == 0x36 && (low & 0x0f) == 0x00) {
2627 PDEBUG(D_PROBE, "Sensor is an OV3610");
2628 sd->sensor = SEN_OV3610;
2629 } else {
858ea5e9 2630 err("Error unknown sensor type: %02x%02x",
87bae740 2631 high, low);
635118d5 2632 }
635118d5
HG		 2633}
2634
6a7eba24
JFM		 2635/* This initializes the OV8110, OV8610 sensor. The OV8110 uses
2636 * the same register settings as the OV8610, since they are very similar.
2637 */
f8f20188 2638static void ov8xx0_configure(struct sd *sd)
6a7eba24
JFM		 2639{
2640 int rc;
6a7eba24
JFM		 2641
2642 PDEBUG(D_PROBE, "starting ov8xx0 configuration");
2643
6a7eba24
JFM		 2644 /* Detect sensor (sub)type */
2645 rc = i2c_r(sd, OV7610_REG_COM_I);
2646 if (rc < 0) {
2647 PDEBUG(D_ERR, "Error detecting sensor type");
f8f20188 2648 return;
6a7eba24 2649 }
f8f20188 2650 if ((rc & 3) == 1)
6a7eba24 2651 sd->sensor = SEN_OV8610;
f8f20188 2652 else
0b656321 2653 err("Unknown image sensor version: %d", rc & 3);
6a7eba24
JFM		 2654}
2655
2656/* This initializes the OV7610, OV7620, or OV76BE sensor. The OV76BE uses
2657 * the same register settings as the OV7610, since they are very similar.
2658 */
f8f20188 2659static void ov7xx0_configure(struct sd *sd)
6a7eba24
JFM		 2660{
2661 int rc, high, low;
2662
6a7eba24
JFM		 2663 PDEBUG(D_PROBE, "starting OV7xx0 configuration");
2664
6a7eba24
JFM		 2665 /* Detect sensor (sub)type */
2666 rc = i2c_r(sd, OV7610_REG_COM_I);
2667
2668 /* add OV7670 here
2669 * it appears to be wrongly detected as a 7610 by default */
2670 if (rc < 0) {
2671 PDEBUG(D_ERR, "Error detecting sensor type");
f8f20188 2672 return;
6a7eba24
JFM		 2673 }
2674 if ((rc & 3) == 3) {
2675 /* quick hack to make OV7670s work */
2676 high = i2c_r(sd, 0x0a);
2677 low = i2c_r(sd, 0x0b);
2678 /* info("%x, %x", high, low); */
7a5a414c
JFM		 2679 if (high == 0x76 && (low & 0xf0) == 0x70) {
2680 PDEBUG(D_PROBE, "Sensor is an OV76%02x", low);
6a7eba24
JFM		 2681 sd->sensor = SEN_OV7670;
2682 } else {
2683 PDEBUG(D_PROBE, "Sensor is an OV7610");
2684 sd->sensor = SEN_OV7610;
2685 }
2686 } else if ((rc & 3) == 1) {
2687 /* I don't know what's different about the 76BE yet. */
b282d873 2688 if (i2c_r(sd, 0x15) & 1) {
6a7eba24 2689 PDEBUG(D_PROBE, "Sensor is an OV7620AE");
859cc470 2690 sd->sensor = SEN_OV7620AE;
b282d873 2691 } else {
6a7eba24 2692 PDEBUG(D_PROBE, "Sensor is an OV76BE");
b282d873
HG		 2693 sd->sensor = SEN_OV76BE;
2694 }
6a7eba24
JFM		 2695 } else if ((rc & 3) == 0) {
2696 /* try to read product id registers */
2697 high = i2c_r(sd, 0x0a);
2698 if (high < 0) {
2699 PDEBUG(D_ERR, "Error detecting camera chip PID");
f8f20188 2700 return;
6a7eba24
JFM		 2701 }
2702 low = i2c_r(sd, 0x0b);
2703 if (low < 0) {
2704 PDEBUG(D_ERR, "Error detecting camera chip VER");
f8f20188 2705 return;
6a7eba24
JFM		 2706 }
2707 if (high == 0x76) {
594f5b8b
JFM		 2708 switch (low) {
2709 case 0x30:
0b656321
JFM		 2710 err("Sensor is an OV7630/OV7635");
2711 err("7630 is not supported by this driver");
f8f20188 2712 return;
594f5b8b 2713 case 0x40:
6a7eba24
JFM		 2714 PDEBUG(D_PROBE, "Sensor is an OV7645");
2715 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2716 break;
2717 case 0x45:
6a7eba24
JFM		 2718 PDEBUG(D_PROBE, "Sensor is an OV7645B");
2719 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2720 break;
2721 case 0x48:
6a7eba24 2722 PDEBUG(D_PROBE, "Sensor is an OV7648");
035d3a3d 2723 sd->sensor = SEN_OV7648;
594f5b8b 2724 break;
42e142f6
JFM		 2725 case 0x60:
2726 PDEBUG(D_PROBE, "Sensor is a OV7660");
2727 sd->sensor = SEN_OV7660;
2728 sd->invert_led = 0;
2729 break;
594f5b8b
JFM		 2730 default:
2731 PDEBUG(D_PROBE, "Unknown sensor: 0x76%x", low);
f8f20188 2732 return;
6a7eba24
JFM		 2733 }
2734 } else {
2735 PDEBUG(D_PROBE, "Sensor is an OV7620");
2736 sd->sensor = SEN_OV7620;
2737 }
2738 } else {
0b656321 2739 err("Unknown image sensor version: %d", rc & 3);
6a7eba24 2740 }
6a7eba24
JFM		 2741}
2742
2743/* This initializes the OV6620, OV6630, OV6630AE, or OV6630AF sensor. */
f8f20188 2744static void ov6xx0_configure(struct sd *sd)
6a7eba24
JFM		 2745{
2746 int rc;
4202f71c 2747 PDEBUG(D_PROBE, "starting OV6xx0 configuration");
6a7eba24
JFM		 2748
2749 /* Detect sensor (sub)type */
2750 rc = i2c_r(sd, OV7610_REG_COM_I);
2751 if (rc < 0) {
2752 PDEBUG(D_ERR, "Error detecting sensor type");
f8f20188 2753 return;
6a7eba24
JFM		 2754 }
2755
2756 /* Ugh. The first two bits are the version bits, but
2757 * the entire register value must be used. I guess OVT
2758 * underestimated how many variants they would make. */
594f5b8b
JFM		 2759 switch (rc) {
2760 case 0x00:
6a7eba24 2761 sd->sensor = SEN_OV6630;
0b656321
JFM		 2762 warn("WARNING: Sensor is an OV66308. Your camera may have");
2763 warn("been misdetected in previous driver versions.");
594f5b8b
JFM		 2764 break;
2765 case 0x01:
6a7eba24 2766 sd->sensor = SEN_OV6620;
7d971373 2767 PDEBUG(D_PROBE, "Sensor is an OV6620");
594f5b8b
JFM		 2768 break;
2769 case 0x02:
6a7eba24
JFM		 2770 sd->sensor = SEN_OV6630;
2771 PDEBUG(D_PROBE, "Sensor is an OV66308AE");
594f5b8b
JFM		 2772 break;
2773 case 0x03:
7d971373 2774 sd->sensor = SEN_OV66308AF;
6a7eba24 2775 PDEBUG(D_PROBE, "Sensor is an OV66308AF");
594f5b8b
JFM		 2776 break;
2777 case 0x90:
6a7eba24 2778 sd->sensor = SEN_OV6630;
0b656321
JFM		 2779 warn("WARNING: Sensor is an OV66307. Your camera may have");
2780 warn("been misdetected in previous driver versions.");
594f5b8b
JFM		 2781 break;
2782 default:
0b656321 2783 err("FATAL: Unknown sensor version: 0x%02x", rc);
f8f20188 2784 return;
6a7eba24
JFM		 2785 }
2786
2787 /* Set sensor-specific vars */
594f5b8b 2788 sd->sif = 1;
6a7eba24
JFM		 2789}
2790
2791/* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */
2792static void ov51x_led_control(struct sd *sd, int on)
2793{
9e4d8258
HG		 2794 if (sd->invert_led)
2795 on = !on;
2796
49809d6a
HG		 2797 switch (sd->bridge) {
2798 /* OV511 has no LED control */
2799 case BRIDGE_OV511PLUS:
a23acec4 2800 reg_w(sd, R511_SYS_LED_CTL, on);
49809d6a
HG		 2801 break;
2802 case BRIDGE_OV518:
2803 case BRIDGE_OV518PLUS:
a23acec4 2804 reg_w_mask(sd, R518_GPIO_OUT, 0x02 * on, 0x02);
49809d6a
HG		 2805 break;
2806 case BRIDGE_OV519:
a23acec4 2807 reg_w_mask(sd, OV519_GPIO_DATA_OUT0, on, 1);
49809d6a
HG		 2808 break;
2809 }
6a7eba24
JFM		 2810}
2811
417a4d26
HG		 2812static void sd_reset_snapshot(struct gspca_dev *gspca_dev)
2813{
2814 struct sd *sd = (struct sd *) gspca_dev;
2815
2816 if (!sd->snapshot_needs_reset)
2817 return;
2818
2819 /* Note it is important that we clear sd->snapshot_needs_reset,
2820 before actually clearing the snapshot state in the bridge
2821 otherwise we might race with the pkt_scan interrupt handler */
2822 sd->snapshot_needs_reset = 0;
2823
2824 switch (sd->bridge) {
88e8d20a
HG		 2825 case BRIDGE_OV511:
2826 case BRIDGE_OV511PLUS:
2827 reg_w(sd, R51x_SYS_SNAP, 0x02);
2828 reg_w(sd, R51x_SYS_SNAP, 0x00);
2829 break;
92e232ac
HG		 2830 case BRIDGE_OV518:
2831 case BRIDGE_OV518PLUS:
2832 reg_w(sd, R51x_SYS_SNAP, 0x02); /* Reset */
2833 reg_w(sd, R51x_SYS_SNAP, 0x01); /* Enable */
2834 break;
417a4d26
HG		 2835 case BRIDGE_OV519:
2836 reg_w(sd, R51x_SYS_RESET, 0x40);
2837 reg_w(sd, R51x_SYS_RESET, 0x00);
2838 break;
2839 }
2840}
2841
f8f20188 2842static void ov51x_upload_quan_tables(struct sd *sd)
49809d6a 2843{
1876bb92
HG		 2844 const unsigned char yQuanTable511[] = {
2845 0, 1, 1, 2, 2, 3, 3, 4,
2846 1, 1, 1, 2, 2, 3, 4, 4,
2847 1, 1, 2, 2, 3, 4, 4, 4,
2848 2, 2, 2, 3, 4, 4, 4, 4,
2849 2, 2, 3, 4, 4, 5, 5, 5,
2850 3, 3, 4, 4, 5, 5, 5, 5,
2851 3, 4, 4, 4, 5, 5, 5, 5,
2852 4, 4, 4, 4, 5, 5, 5, 5
2853 };
2854
2855 const unsigned char uvQuanTable511[] = {
2856 0, 2, 2, 3, 4, 4, 4, 4,
2857 2, 2, 2, 4, 4, 4, 4, 4,
2858 2, 2, 3, 4, 4, 4, 4, 4,
2859 3, 4, 4, 4, 4, 4, 4, 4,
2860 4, 4, 4, 4, 4, 4, 4, 4,
2861 4, 4, 4, 4, 4, 4, 4, 4,
2862 4, 4, 4, 4, 4, 4, 4, 4,
2863 4, 4, 4, 4, 4, 4, 4, 4
2864 };
2865
2866 /* OV518 quantization tables are 8x4 (instead of 8x8) */
49809d6a
HG		 2867 const unsigned char yQuanTable518[] = {
2868 5, 4, 5, 6, 6, 7, 7, 7,
2869 5, 5, 5, 5, 6, 7, 7, 7,
2870 6, 6, 6, 6, 7, 7, 7, 8,
2871 7, 7, 6, 7, 7, 7, 8, 8
2872 };
49809d6a
HG		 2873 const unsigned char uvQuanTable518[] = {
2874 6, 6, 6, 7, 7, 7, 7, 7,
2875 6, 6, 6, 7, 7, 7, 7, 7,
2876 6, 6, 6, 7, 7, 7, 7, 8,
2877 7, 7, 7, 7, 7, 7, 8, 8
2878 };
2879
1876bb92 2880 const unsigned char *pYTable, *pUVTable;
49809d6a 2881 unsigned char val0, val1;
f8f20188 2882 int i, size, reg = R51x_COMP_LUT_BEGIN;
49809d6a
HG		 2883
2884 PDEBUG(D_PROBE, "Uploading quantization tables");
2885
1876bb92
HG		 2886 if (sd->bridge == BRIDGE_OV511 || sd->bridge == BRIDGE_OV511PLUS) {
2887 pYTable = yQuanTable511;
2888 pUVTable = uvQuanTable511;
87bae740 2889 size = 32;
1876bb92
HG		 2890 } else {
2891 pYTable = yQuanTable518;
2892 pUVTable = uvQuanTable518;
87bae740 2893 size = 16;
1876bb92
HG		 2894 }
2895
2896 for (i = 0; i < size; i++) {
49809d6a
HG		 2897 val0 = *pYTable++;
2898 val1 = *pYTable++;
2899 val0 &= 0x0f;
2900 val1 &= 0x0f;
2901 val0 |= val1 << 4;
f8f20188 2902 reg_w(sd, reg, val0);
49809d6a
HG		 2903
2904 val0 = *pUVTable++;
2905 val1 = *pUVTable++;
2906 val0 &= 0x0f;
2907 val1 &= 0x0f;
2908 val0 |= val1 << 4;
f8f20188 2909 reg_w(sd, reg + size, val0);
49809d6a
HG		 2910
2911 reg++;
2912 }
49809d6a
HG		 2913}
2914
1876bb92 2915/* This initializes the OV511/OV511+ and the sensor */
f8f20188 2916static void ov511_configure(struct gspca_dev *gspca_dev)
1876bb92
HG		 2917{
2918 struct sd *sd = (struct sd *) gspca_dev;
1876bb92
HG		 2919
2920 /* For 511 and 511+ */
2921 const struct ov_regvals init_511[] = {
2922 { R51x_SYS_RESET, 0x7f },
2923 { R51x_SYS_INIT, 0x01 },
2924 { R51x_SYS_RESET, 0x7f },
2925 { R51x_SYS_INIT, 0x01 },
2926 { R51x_SYS_RESET, 0x3f },
2927 { R51x_SYS_INIT, 0x01 },
2928 { R51x_SYS_RESET, 0x3d },
2929 };
2930
2931 const struct ov_regvals norm_511[] = {
780e3121 2932 { R511_DRAM_FLOW_CTL, 0x01 },
1876bb92
HG		 2933 { R51x_SYS_SNAP, 0x00 },
2934 { R51x_SYS_SNAP, 0x02 },
2935 { R51x_SYS_SNAP, 0x00 },
2936 { R511_FIFO_OPTS, 0x1f },
2937 { R511_COMP_EN, 0x00 },
2938 { R511_COMP_LUT_EN, 0x03 },
2939 };
2940
2941 const struct ov_regvals norm_511_p[] = {
2942 { R511_DRAM_FLOW_CTL, 0xff },
2943 { R51x_SYS_SNAP, 0x00 },
2944 { R51x_SYS_SNAP, 0x02 },
2945 { R51x_SYS_SNAP, 0x00 },
2946 { R511_FIFO_OPTS, 0xff },
2947 { R511_COMP_EN, 0x00 },
2948 { R511_COMP_LUT_EN, 0x03 },
2949 };
2950
2951 const struct ov_regvals compress_511[] = {
2952 { 0x70, 0x1f },
2953 { 0x71, 0x05 },
2954 { 0x72, 0x06 },
2955 { 0x73, 0x06 },
2956 { 0x74, 0x14 },
2957 { 0x75, 0x03 },
2958 { 0x76, 0x04 },
2959 { 0x77, 0x04 },
2960 };
2961
2962 PDEBUG(D_PROBE, "Device custom id %x", reg_r(sd, R51x_SYS_CUST_ID));
2963
f8f20188 2964 write_regvals(sd, init_511, ARRAY_SIZE(init_511));
1876bb92
HG		 2965
2966 switch (sd->bridge) {
2967 case BRIDGE_OV511:
f8f20188 2968 write_regvals(sd, norm_511, ARRAY_SIZE(norm_511));
1876bb92
HG		 2969 break;
2970 case BRIDGE_OV511PLUS:
f8f20188 2971 write_regvals(sd, norm_511_p, ARRAY_SIZE(norm_511_p));
1876bb92
HG		 2972 break;
2973 }
2974
2975 /* Init compression */
f8f20188 2976 write_regvals(sd, compress_511, ARRAY_SIZE(compress_511));
1876bb92 2977
f8f20188 2978 ov51x_upload_quan_tables(sd);
1876bb92
HG		 2979}
2980
49809d6a 2981/* This initializes the OV518/OV518+ and the sensor */
f8f20188 2982static void ov518_configure(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 2983{
2984 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 2985
2986 /* For 518 and 518+ */
e080fcd9 2987 const struct ov_regvals init_518[] = {
49809d6a
HG		 2988 { R51x_SYS_RESET, 0x40 },
2989 { R51x_SYS_INIT, 0xe1 },
2990 { R51x_SYS_RESET, 0x3e },
2991 { R51x_SYS_INIT, 0xe1 },
2992 { R51x_SYS_RESET, 0x00 },
2993 { R51x_SYS_INIT, 0xe1 },
2994 { 0x46, 0x00 },
2995 { 0x5d, 0x03 },
2996 };
2997
e080fcd9 2998 const struct ov_regvals norm_518[] = {
49809d6a
HG		 2999 { R51x_SYS_SNAP, 0x02 }, /* Reset */
3000 { R51x_SYS_SNAP, 0x01 }, /* Enable */
780e3121 3001 { 0x31, 0x0f },
49809d6a
HG		 3002 { 0x5d, 0x03 },
3003 { 0x24, 0x9f },
3004 { 0x25, 0x90 },
3005 { 0x20, 0x00 },
3006 { 0x51, 0x04 },
3007 { 0x71, 0x19 },
3008 { 0x2f, 0x80 },
3009 };
3010
e080fcd9 3011 const struct ov_regvals norm_518_p[] = {
49809d6a
HG		 3012 { R51x_SYS_SNAP, 0x02 }, /* Reset */
3013 { R51x_SYS_SNAP, 0x01 }, /* Enable */
780e3121 3014 { 0x31, 0x0f },
49809d6a
HG		 3015 { 0x5d, 0x03 },
3016 { 0x24, 0x9f },
3017 { 0x25, 0x90 },
3018 { 0x20, 0x60 },
3019 { 0x51, 0x02 },
3020 { 0x71, 0x19 },
3021 { 0x40, 0xff },
3022 { 0x41, 0x42 },
3023 { 0x46, 0x00 },
3024 { 0x33, 0x04 },
3025 { 0x21, 0x19 },
3026 { 0x3f, 0x10 },
3027 { 0x2f, 0x80 },
3028 };
3029
3030 /* First 5 bits of custom ID reg are a revision ID on OV518 */
3031 PDEBUG(D_PROBE, "Device revision %d",
87bae740 3032 0x1f & reg_r(sd, R51x_SYS_CUST_ID));
49809d6a 3033
f8f20188 3034 write_regvals(sd, init_518, ARRAY_SIZE(init_518));
49809d6a
HG		 3035
3036 /* Set LED GPIO pin to output mode */
f8f20188 3037 reg_w_mask(sd, R518_GPIO_CTL, 0x00, 0x02);
6a7eba24 3038
49809d6a
HG		 3039 switch (sd->bridge) {
3040 case BRIDGE_OV518:
f8f20188 3041 write_regvals(sd, norm_518, ARRAY_SIZE(norm_518));
49809d6a
HG		 3042 break;
3043 case BRIDGE_OV518PLUS:
f8f20188 3044 write_regvals(sd, norm_518_p, ARRAY_SIZE(norm_518_p));
49809d6a
HG		 3045 break;
3046 }
3047
f8f20188 3048 ov51x_upload_quan_tables(sd);
49809d6a 3049
f8f20188 3050 reg_w(sd, 0x2f, 0x80);
49809d6a
HG		 3051}
3052
f8f20188 3053static void ov519_configure(struct sd *sd)
49809d6a 3054{
a5ae2062 3055 static const struct ov_regvals init_519[] = {
87bae740
JFM		 3056 { 0x5a, 0x6d }, /* EnableSystem */
3057 { 0x53, 0x9b },
21867803 3058 { OV519_R54_EN_CLK1, 0xff }, /* set bit2 to enable jpeg */
87bae740
JFM		 3059 { 0x5d, 0x03 },
3060 { 0x49, 0x01 },
3061 { 0x48, 0x00 },
6a7eba24
JFM		 3062 /* Set LED pin to output mode. Bit 4 must be cleared or sensor
3063 * detection will fail. This deserves further investigation. */
3064 { OV519_GPIO_IO_CTRL0, 0xee },
21867803
JFM		 3065 { OV519_R51_RESET1, 0x0f },
3066 { OV519_R51_RESET1, 0x00 },
87bae740 3067 { 0x22, 0x00 },
6a7eba24
JFM		 3068 /* windows reads 0x55 at this point*/
3069 };
3070
f8f20188 3071 write_regvals(sd, init_519, ARRAY_SIZE(init_519));
49809d6a
HG		 3072}
3073
f8f20188 3074static void ovfx2_configure(struct sd *sd)
b46aaa02
HG		 3075{
3076 static const struct ov_regvals init_fx2[] = {
3077 { 0x00, 0x60 },
3078 { 0x02, 0x01 },
3079 { 0x0f, 0x1d },
3080 { 0xe9, 0x82 },
3081 { 0xea, 0xc7 },
3082 { 0xeb, 0x10 },
3083 { 0xec, 0xf6 },
3084 };
3085
3086 sd->stopped = 1;
3087
f8f20188 3088 write_regvals(sd, init_fx2, ARRAY_SIZE(init_fx2));
b46aaa02
HG		 3089}
3090
42e142f6
JFM		 3091/* set the mode */
3092/* This function works for ov7660 only */
3093static void ov519_set_mode(struct sd *sd)
3094{
3095 static const struct ov_regvals bridge_ov7660[2][10] = {
3096 {{0x10, 0x14}, {0x11, 0x1e}, {0x12, 0x00}, {0x13, 0x00},
3097 {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
3098 {0x25, 0x01}, {0x26, 0x00}},
3099 {{0x10, 0x28}, {0x11, 0x3c}, {0x12, 0x00}, {0x13, 0x00},
3100 {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
3101 {0x25, 0x03}, {0x26, 0x00}}
3102 };
3103 static const struct ov_i2c_regvals sensor_ov7660[2][3] = {
3104 {{0x12, 0x00}, {0x24, 0x00}, {0x0c, 0x0c}},
3105 {{0x12, 0x00}, {0x04, 0x00}, {0x0c, 0x00}}
3106 };
3107 static const struct ov_i2c_regvals sensor_ov7660_2[] = {
3108 {OV7670_R17_HSTART, 0x13},
3109 {OV7670_R18_HSTOP, 0x01},
3110 {OV7670_R32_HREF, 0x92},
3111 {OV7670_R19_VSTART, 0x02},
3112 {OV7670_R1A_VSTOP, 0x7a},
3113 {OV7670_R03_VREF, 0x00},
3114/* {0x33, 0x00}, */
3115/* {0x34, 0x07}, */
3116/* {0x36, 0x00}, */
3117/* {0x6b, 0x0a}, */
3118 };
3119
3120 write_regvals(sd, bridge_ov7660[sd->gspca_dev.curr_mode],
3121 ARRAY_SIZE(bridge_ov7660[0]));
3122 write_i2c_regvals(sd, sensor_ov7660[sd->gspca_dev.curr_mode],
3123 ARRAY_SIZE(sensor_ov7660[0]));
3124 write_i2c_regvals(sd, sensor_ov7660_2,
3125 ARRAY_SIZE(sensor_ov7660_2));
3126}
3127
3128/* set the frame rate */
3129/* This function works for sensors ov7640, ov7648 ov7660 and ov7670 only */
3130static void ov519_set_fr(struct sd *sd)
3131{
3132 int fr;
3133 u8 clock;
3134 /* frame rate table with indices:
3135 * - mode = 0: 320x240, 1: 640x480
3136 * - fr rate = 0: 30, 1: 25, 2: 20, 3: 15, 4: 10, 5: 5
3137 * - reg = 0: bridge a4, 1: bridge 23, 2: sensor 11 (clock)
3138 */
3139 static const u8 fr_tb[2][6][3] = {
3140 {{0x04, 0xff, 0x00},
3141 {0x04, 0x1f, 0x00},
3142 {0x04, 0x1b, 0x00},
3143 {0x04, 0x15, 0x00},
3144 {0x04, 0x09, 0x00},
3145 {0x04, 0x01, 0x00}},
3146 {{0x0c, 0xff, 0x00},
3147 {0x0c, 0x1f, 0x00},
3148 {0x0c, 0x1b, 0x00},
3149 {0x04, 0xff, 0x01},
3150 {0x04, 0x1f, 0x01},
3151 {0x04, 0x1b, 0x01}},
3152 };
3153
3154 if (frame_rate > 0)
3155 sd->frame_rate = frame_rate;
3156 if (sd->frame_rate >= 30)
3157 fr = 0;
3158 else if (sd->frame_rate >= 25)
3159 fr = 1;
3160 else if (sd->frame_rate >= 20)
3161 fr = 2;
3162 else if (sd->frame_rate >= 15)
3163 fr = 3;
3164 else if (sd->frame_rate >= 10)
3165 fr = 4;
3166 else
3167 fr = 5;
3168 reg_w(sd, 0xa4, fr_tb[sd->gspca_dev.curr_mode][fr][0]);
3169 reg_w(sd, 0x23, fr_tb[sd->gspca_dev.curr_mode][fr][1]);
3170 clock = fr_tb[sd->gspca_dev.curr_mode][fr][2];
3171 if (sd->sensor == SEN_OV7660)
3172 clock |= 0x80; /* enable double clock */
3173 ov518_i2c_w(sd, OV7670_R11_CLKRC, clock);
3174}
3175
49809d6a
HG		 3176/* this function is called at probe time */
3177static int sd_config(struct gspca_dev *gspca_dev,
3178 const struct usb_device_id *id)
3179{
3180 struct sd *sd = (struct sd *) gspca_dev;
b46aaa02 3181 struct cam *cam = &gspca_dev->cam;
49809d6a 3182
9e4d8258 3183 sd->bridge = id->driver_info & BRIDGE_MASK;
a23acec4 3184 sd->invert_led = (id->driver_info & BRIDGE_INVERT_LED) != 0;
49809d6a
HG		 3185
3186 switch (sd->bridge) {
1876bb92
HG		 3187 case BRIDGE_OV511:
3188 case BRIDGE_OV511PLUS:
7491f785
JFM		 3189 cam->cam_mode = ov511_vga_mode;
3190 cam->nmodes = ARRAY_SIZE(ov511_vga_mode);
1876bb92 3191 break;
49809d6a
HG		 3192 case BRIDGE_OV518:
3193 case BRIDGE_OV518PLUS:
7491f785
JFM		 3194 cam->cam_mode = ov518_vga_mode;
3195 cam->nmodes = ARRAY_SIZE(ov518_vga_mode);
49809d6a
HG		 3196 break;
3197 case BRIDGE_OV519:
7491f785
JFM		 3198 cam->cam_mode = ov519_vga_mode;
3199 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3200 sd->invert_led = !sd->invert_led;
49809d6a 3201 break;
b46aaa02 3202 case BRIDGE_OVFX2:
7491f785
JFM		 3203 cam->cam_mode = ov519_vga_mode;
3204 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
b46aaa02
HG		 3205 cam->bulk_size = OVFX2_BULK_SIZE;
3206 cam->bulk_nurbs = MAX_NURBS;
3207 cam->bulk = 1;
3208 break;
a511ba94 3209 case BRIDGE_W9968CF:
7491f785
JFM		 3210 cam->cam_mode = w9968cf_vga_mode;
3211 cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode);
a511ba94
HG		 3212 cam->reverse_alts = 1;
3213 break;
49809d6a
HG		 3214 }
3215
7491f785
JFM		 3216 gspca_dev->cam.ctrls = sd->ctrls;
3217 sd->quality = QUALITY_DEF;
3218
3219 return 0;
3220}
3221
3222/* this function is called at probe and resume time */
3223static int sd_init(struct gspca_dev *gspca_dev)
3224{
3225 struct sd *sd = (struct sd *) gspca_dev;
3226 struct cam *cam = &gspca_dev->cam;
3227
3228 switch (sd->bridge) {
3229 case BRIDGE_OV511:
3230 case BRIDGE_OV511PLUS:
3231 ov511_configure(gspca_dev);
3232 break;
3233 case BRIDGE_OV518:
3234 case BRIDGE_OV518PLUS:
3235 ov518_configure(gspca_dev);
3236 break;
3237 case BRIDGE_OV519:
3238 ov519_configure(sd);
3239 break;
3240 case BRIDGE_OVFX2:
3241 ovfx2_configure(sd);
3242 break;
3243 case BRIDGE_W9968CF:
3244 w9968cf_configure(sd);
3245 break;
3246 }
6a7eba24 3247
6a7eba24
JFM		 3248 /* The OV519 must be more aggressive about sensor detection since
3249 * I2C write will never fail if the sensor is not present. We have
3250 * to try to initialize the sensor to detect its presence */
7bbe6b8d 3251 sd->sensor = -1;
229bb7dc
HG		 3252
3253 /* Test for 76xx */
3254 if (init_ov_sensor(sd, OV7xx0_SID) >= 0) {
f8f20188
JFM		 3255 ov7xx0_configure(sd);
3256
229bb7dc
HG		 3257 /* Test for 6xx0 */
3258 } else if (init_ov_sensor(sd, OV6xx0_SID) >= 0) {
f8f20188
JFM		 3259 ov6xx0_configure(sd);
3260
229bb7dc
HG		 3261 /* Test for 8xx0 */
3262 } else if (init_ov_sensor(sd, OV8xx0_SID) >= 0) {
f8f20188
JFM		 3263 ov8xx0_configure(sd);
3264
635118d5
HG		 3265 /* Test for 3xxx / 2xxx */
3266 } else if (init_ov_sensor(sd, OV_HIRES_SID) >= 0) {
f8f20188 3267 ov_hires_configure(sd);
229bb7dc 3268 } else {
0b656321 3269 err("Can't determine sensor slave IDs");
229bb7dc 3270 goto error;
6a7eba24
JFM		 3271 }
3272
7bbe6b8d
JFM		 3273 if (sd->sensor < 0)
3274 goto error;
3275
7491f785
JFM		 3276 ov51x_led_control(sd, 0); /* turn LED off */
3277
49809d6a 3278 switch (sd->bridge) {
1876bb92
HG		 3279 case BRIDGE_OV511:
3280 case BRIDGE_OV511PLUS:
7491f785 3281 if (sd->sif) {
1876bb92
HG		 3282 cam->cam_mode = ov511_sif_mode;
3283 cam->nmodes = ARRAY_SIZE(ov511_sif_mode);
3284 }
3285 break;
49809d6a
HG		 3286 case BRIDGE_OV518:
3287 case BRIDGE_OV518PLUS:
7491f785 3288 if (sd->sif) {
49809d6a
HG		 3289 cam->cam_mode = ov518_sif_mode;
3290 cam->nmodes = ARRAY_SIZE(ov518_sif_mode);
3291 }
3292 break;
3293 case BRIDGE_OV519:
7491f785 3294 if (sd->sif) {
49809d6a
HG		 3295 cam->cam_mode = ov519_sif_mode;
3296 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3297 }
3298 break;
635118d5
HG		 3299 case BRIDGE_OVFX2:
3300 if (sd->sensor == SEN_OV2610) {
3301 cam->cam_mode = ovfx2_ov2610_mode;
3302 cam->nmodes = ARRAY_SIZE(ovfx2_ov2610_mode);
3303 } else if (sd->sensor == SEN_OV3610) {
3304 cam->cam_mode = ovfx2_ov3610_mode;
3305 cam->nmodes = ARRAY_SIZE(ovfx2_ov3610_mode);
7491f785 3306 } else if (sd->sif) {
635118d5
HG		 3307 cam->cam_mode = ov519_sif_mode;
3308 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3309 }
3310 break;
a511ba94 3311 case BRIDGE_W9968CF:
79b35902 3312 if (sd->sif)
7491f785 3313 cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode) - 1;
a511ba94
HG		 3314
3315 /* w9968cf needs initialisation once the sensor is known */
f8f20188 3316 w9968cf_init(sd);
a511ba94 3317 break;
6a7eba24 3318 }
83db7688
JFM		 3319
3320 gspca_dev->ctrl_dis = ctrl_dis[sd->sensor];
02ab18b0 3321
4202f71c
JFM		 3322 /* initialize the sensor */
3323 switch (sd->sensor) {
635118d5 3324 case SEN_OV2610:
f8f20188
JFM		 3325 write_i2c_regvals(sd, norm_2610, ARRAY_SIZE(norm_2610));
3326
635118d5 3327 /* Enable autogain, autoexpo, awb, bandfilter */
f8f20188 3328 i2c_w_mask(sd, 0x13, 0x27, 0x27);
635118d5
HG		 3329 break;
3330 case SEN_OV3610:
f8f20188
JFM		 3331 write_i2c_regvals(sd, norm_3620b, ARRAY_SIZE(norm_3620b));
3332
635118d5 3333 /* Enable autogain, autoexpo, awb, bandfilter */
f8f20188 3334 i2c_w_mask(sd, 0x13, 0x27, 0x27);
635118d5 3335 break;
4202f71c 3336 case SEN_OV6620:
f8f20188 3337 write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20));
4202f71c
JFM		 3338 break;
3339 case SEN_OV6630:
7d971373 3340 case SEN_OV66308AF:
62833acd
JFM		 3341 sd->ctrls[CONTRAST].def = 200;
3342 /* The default is too low for the ov6630 */
f8f20188 3343 write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30));
4202f71c
JFM		 3344 break;
3345 default:
3346/* case SEN_OV7610: */
3347/* case SEN_OV76BE: */
f8f20188
JFM		 3348 write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610));
3349 i2c_w_mask(sd, 0x0e, 0x00, 0x40);
4202f71c
JFM		 3350 break;
3351 case SEN_OV7620:
859cc470 3352 case SEN_OV7620AE:
f8f20188 3353 write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620));
4202f71c
JFM		 3354 break;
3355 case SEN_OV7640:
035d3a3d 3356 case SEN_OV7648:
f8f20188 3357 write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640));
4202f71c 3358 break;
42e142f6
JFM		 3359 case SEN_OV7660:
3360 i2c_w(sd, OV7670_R12_COM7, OV7670_COM7_RESET);
3361 msleep(14);
3362 reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
3363 write_regvals(sd, init_519_ov7660,
3364 ARRAY_SIZE(init_519_ov7660));
3365 write_i2c_regvals(sd, norm_7660, ARRAY_SIZE(norm_7660));
3366 sd->gspca_dev.curr_mode = 1; /* 640x480 */
3367 sd->frame_rate = 15;
3368 ov519_set_mode(sd);
3369 ov519_set_fr(sd);
3370 sd->ctrls[COLORS].max = 4; /* 0..4 */
3371 sd->ctrls[COLORS].val =
3372 sd->ctrls[COLORS].def = 2;
3373 setcolors(gspca_dev);
3374 sd->ctrls[CONTRAST].max = 6; /* 0..6 */
3375 sd->ctrls[CONTRAST].val =
3376 sd->ctrls[CONTRAST].def = 3;
3377 setcontrast(gspca_dev);
3378 sd->ctrls[BRIGHTNESS].max = 6; /* 0..6 */
3379 sd->ctrls[BRIGHTNESS].val =
3380 sd->ctrls[BRIGHTNESS].def = 3;
3381 setbrightness(gspca_dev);
3382 sd_reset_snapshot(gspca_dev);
3383 ov51x_restart(sd);
3384 ov51x_stop(sd); /* not in win traces */
3385 ov51x_led_control(sd, 0);
3386 break;
4202f71c 3387 case SEN_OV7670:
62833acd
JFM		 3388 sd->ctrls[FREQ].max = 3; /* auto */
3389 sd->ctrls[FREQ].def = 3;
f8f20188 3390 write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670));
4202f71c
JFM		 3391 break;
3392 case SEN_OV8610:
f8f20188 3393 write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610));
4202f71c
JFM		 3394 break;
3395 }
f8f20188 3396 return gspca_dev->usb_err;
7491f785
JFM		 3397error:
3398 PDEBUG(D_ERR, "OV519 Config failed");
3399 return -EINVAL;
6a7eba24
JFM		 3400}
3401
1876bb92
HG		 3402/* Set up the OV511/OV511+ with the given image parameters.
3403 *
3404 * Do not put any sensor-specific code in here (including I2C I/O functions)
3405 */
f8f20188 3406static void ov511_mode_init_regs(struct sd *sd)
1876bb92
HG		 3407{
3408 int hsegs, vsegs, packet_size, fps, needed;
3409 int interlaced = 0;
3410 struct usb_host_interface *alt;
3411 struct usb_interface *intf;
3412
3413 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3414 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3415 if (!alt) {
0b656321 3416 err("Couldn't get altsetting");
f8f20188
JFM		 3417 sd->gspca_dev.usb_err = -EIO;
3418 return;
1876bb92
HG		 3419 }
3420
3421 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3422 reg_w(sd, R51x_FIFO_PSIZE, packet_size >> 5);
3423
3424 reg_w(sd, R511_CAM_UV_EN, 0x01);
3425 reg_w(sd, R511_SNAP_UV_EN, 0x01);
3426 reg_w(sd, R511_SNAP_OPTS, 0x03);
3427
3428 /* Here I'm assuming that snapshot size == image size.
3429 * I hope that's always true. --claudio
3430 */
3431 hsegs = (sd->gspca_dev.width >> 3) - 1;
3432 vsegs = (sd->gspca_dev.height >> 3) - 1;
3433
3434 reg_w(sd, R511_CAM_PXCNT, hsegs);
3435 reg_w(sd, R511_CAM_LNCNT, vsegs);
3436 reg_w(sd, R511_CAM_PXDIV, 0x00);
3437 reg_w(sd, R511_CAM_LNDIV, 0x00);
3438
3439 /* YUV420, low pass filter on */
3440 reg_w(sd, R511_CAM_OPTS, 0x03);
3441
3442 /* Snapshot additions */
3443 reg_w(sd, R511_SNAP_PXCNT, hsegs);
3444 reg_w(sd, R511_SNAP_LNCNT, vsegs);
3445 reg_w(sd, R511_SNAP_PXDIV, 0x00);
3446 reg_w(sd, R511_SNAP_LNDIV, 0x00);
3447
3448 /******** Set the framerate ********/
3449 if (frame_rate > 0)
3450 sd->frame_rate = frame_rate;
3451
3452 switch (sd->sensor) {
3453 case SEN_OV6620:
3454 /* No framerate control, doesn't like higher rates yet */
3455 sd->clockdiv = 3;
3456 break;
3457
3458 /* Note once the FIXME's in mode_init_ov_sensor_regs() are fixed
3459 for more sensors we need to do this for them too */
3460 case SEN_OV7620:
859cc470 3461 case SEN_OV7620AE:
1876bb92 3462 case SEN_OV7640:
035d3a3d 3463 case SEN_OV7648:
b282d873 3464 case SEN_OV76BE:
1876bb92
HG		 3465 if (sd->gspca_dev.width == 320)
3466 interlaced = 1;
3467 /* Fall through */
3468 case SEN_OV6630:
1876bb92
HG		 3469 case SEN_OV7610:
3470 case SEN_OV7670:
3471 switch (sd->frame_rate) {
3472 case 30:
3473 case 25:
3474 /* Not enough bandwidth to do 640x480 @ 30 fps */
3475 if (sd->gspca_dev.width != 640) {
3476 sd->clockdiv = 0;
3477 break;
3478 }
3479 /* Fall through for 640x480 case */
3480 default:
3481/* case 20: */
3482/* case 15: */
3483 sd->clockdiv = 1;
3484 break;
3485 case 10:
3486 sd->clockdiv = 2;
3487 break;
3488 case 5:
3489 sd->clockdiv = 5;
3490 break;
3491 }
3492 if (interlaced) {
3493 sd->clockdiv = (sd->clockdiv + 1) * 2 - 1;
3494 /* Higher then 10 does not work */
3495 if (sd->clockdiv > 10)
3496 sd->clockdiv = 10;
3497 }
3498 break;
3499
3500 case SEN_OV8610:
3501 /* No framerate control ?? */
3502 sd->clockdiv = 0;
3503 break;
3504 }
3505
3506 /* Check if we have enough bandwidth to disable compression */
3507 fps = (interlaced ? 60 : 30) / (sd->clockdiv + 1) + 1;
3508 needed = fps * sd->gspca_dev.width * sd->gspca_dev.height * 3 / 2;
3509 /* 1400 is a conservative estimate of the max nr of isoc packets/sec */
3510 if (needed > 1400 * packet_size) {
3511 /* Enable Y and UV quantization and compression */
3512 reg_w(sd, R511_COMP_EN, 0x07);
3513 reg_w(sd, R511_COMP_LUT_EN, 0x03);
3514 } else {
3515 reg_w(sd, R511_COMP_EN, 0x06);
3516 reg_w(sd, R511_COMP_LUT_EN, 0x00);
3517 }
3518
3519 reg_w(sd, R51x_SYS_RESET, OV511_RESET_OMNICE);
3520 reg_w(sd, R51x_SYS_RESET, 0);
1876bb92
HG		 3521}
3522
49809d6a
HG		 3523/* Sets up the OV518/OV518+ with the given image parameters
3524 *
3525 * OV518 needs a completely different approach, until we can figure out what
3526 * the individual registers do. Also, only 15 FPS is supported now.
3527 *
3528 * Do not put any sensor-specific code in here (including I2C I/O functions)
3529 */
f8f20188 3530static void ov518_mode_init_regs(struct sd *sd)
49809d6a 3531{
b282d873
HG		 3532 int hsegs, vsegs, packet_size;
3533 struct usb_host_interface *alt;
3534 struct usb_interface *intf;
3535
3536 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3537 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3538 if (!alt) {
0b656321 3539 err("Couldn't get altsetting");
f8f20188
JFM		 3540 sd->gspca_dev.usb_err = -EIO;
3541 return;
b282d873
HG		 3542 }
3543
3544 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3545 ov518_reg_w32(sd, R51x_FIFO_PSIZE, packet_size & ~7, 2);
49809d6a
HG		 3546
3547 /******** Set the mode ********/
49809d6a
HG		 3548 reg_w(sd, 0x2b, 0);
3549 reg_w(sd, 0x2c, 0);
3550 reg_w(sd, 0x2d, 0);
3551 reg_w(sd, 0x2e, 0);
3552 reg_w(sd, 0x3b, 0);
3553 reg_w(sd, 0x3c, 0);
3554 reg_w(sd, 0x3d, 0);
3555 reg_w(sd, 0x3e, 0);
3556
3557 if (sd->bridge == BRIDGE_OV518) {
3558 /* Set 8-bit (YVYU) input format */
3559 reg_w_mask(sd, 0x20, 0x08, 0x08);
3560
3561 /* Set 12-bit (4:2:0) output format */
3562 reg_w_mask(sd, 0x28, 0x80, 0xf0);
3563 reg_w_mask(sd, 0x38, 0x80, 0xf0);
3564 } else {
3565 reg_w(sd, 0x28, 0x80);
3566 reg_w(sd, 0x38, 0x80);
3567 }
3568
3569 hsegs = sd->gspca_dev.width / 16;
3570 vsegs = sd->gspca_dev.height / 4;
3571
3572 reg_w(sd, 0x29, hsegs);
3573 reg_w(sd, 0x2a, vsegs);
3574
3575 reg_w(sd, 0x39, hsegs);
3576 reg_w(sd, 0x3a, vsegs);
3577
3578 /* Windows driver does this here; who knows why */
3579 reg_w(sd, 0x2f, 0x80);
3580
87bae740 3581 /******** Set the framerate ********/
b282d873 3582 sd->clockdiv = 1;
49809d6a
HG		 3583
3584 /* Mode independent, but framerate dependent, regs */
b282d873
HG		 3585 /* 0x51: Clock divider; Only works on some cams which use 2 crystals */
3586 reg_w(sd, 0x51, 0x04);
49809d6a
HG		 3587 reg_w(sd, 0x22, 0x18);
3588 reg_w(sd, 0x23, 0xff);
3589
b282d873
HG		 3590 if (sd->bridge == BRIDGE_OV518PLUS) {
3591 switch (sd->sensor) {
859cc470 3592 case SEN_OV7620AE:
b282d873
HG		 3593 if (sd->gspca_dev.width == 320) {
3594 reg_w(sd, 0x20, 0x00);
3595 reg_w(sd, 0x21, 0x19);
3596 } else {
3597 reg_w(sd, 0x20, 0x60);
3598 reg_w(sd, 0x21, 0x1f);
3599 }
3600 break;
859cc470
HG		 3601 case SEN_OV7620:
3602 reg_w(sd, 0x20, 0x00);
3603 reg_w(sd, 0x21, 0x19);
3604 break;
b282d873
HG		 3605 default:
3606 reg_w(sd, 0x21, 0x19);
3607 }
3608 } else
49809d6a
HG		 3609 reg_w(sd, 0x71, 0x17); /* Compression-related? */
3610
3611 /* FIXME: Sensor-specific */
3612 /* Bit 5 is what matters here. Of course, it is "reserved" */
3613 i2c_w(sd, 0x54, 0x23);
3614
3615 reg_w(sd, 0x2f, 0x80);
3616
3617 if (sd->bridge == BRIDGE_OV518PLUS) {
3618 reg_w(sd, 0x24, 0x94);
3619 reg_w(sd, 0x25, 0x90);
3620 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3621 ov518_reg_w32(sd, 0xc6, 540, 2); /* 21ch */
3622 ov518_reg_w32(sd, 0xc7, 540, 2); /* 21ch */
3623 ov518_reg_w32(sd, 0xc8, 108, 2); /* 6ch */
3624 ov518_reg_w32(sd, 0xca, 131098, 3); /* 2001ah */
3625 ov518_reg_w32(sd, 0xcb, 532, 2); /* 214h */
3626 ov518_reg_w32(sd, 0xcc, 2400, 2); /* 960h */
3627 ov518_reg_w32(sd, 0xcd, 32, 2); /* 20h */
3628 ov518_reg_w32(sd, 0xce, 608, 2); /* 260h */
3629 } else {
3630 reg_w(sd, 0x24, 0x9f);
3631 reg_w(sd, 0x25, 0x90);
3632 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3633 ov518_reg_w32(sd, 0xc6, 381, 2); /* 17dh */
3634 ov518_reg_w32(sd, 0xc7, 381, 2); /* 17dh */
3635 ov518_reg_w32(sd, 0xc8, 128, 2); /* 80h */
3636 ov518_reg_w32(sd, 0xca, 183331, 3); /* 2cc23h */
3637 ov518_reg_w32(sd, 0xcb, 746, 2); /* 2eah */
3638 ov518_reg_w32(sd, 0xcc, 1750, 2); /* 6d6h */
3639 ov518_reg_w32(sd, 0xcd, 45, 2); /* 2dh */
3640 ov518_reg_w32(sd, 0xce, 851, 2); /* 353h */
3641 }
3642
3643 reg_w(sd, 0x2f, 0x80);
49809d6a
HG		 3644}
3645
6a7eba24
JFM		 3646/* Sets up the OV519 with the given image parameters
3647 *
3648 * OV519 needs a completely different approach, until we can figure out what
3649 * the individual registers do.
3650 *
3651 * Do not put any sensor-specific code in here (including I2C I/O functions)
3652 */
f8f20188 3653static void ov519_mode_init_regs(struct sd *sd)
6a7eba24 3654{
a5ae2062 3655 static const struct ov_regvals mode_init_519_ov7670[] = {
6a7eba24
JFM		 3656 { 0x5d, 0x03 }, /* Turn off suspend mode */
3657 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
21867803 3658 { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
6a7eba24
JFM		 3659 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3660 { 0xa3, 0x18 },
3661 { 0xa4, 0x04 },
3662 { 0xa5, 0x28 },
3663 { 0x37, 0x00 }, /* SetUsbInit */
3664 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3665 /* Enable both fields, YUV Input, disable defect comp (why?) */
3666 { 0x20, 0x0c },
3667 { 0x21, 0x38 },
3668 { 0x22, 0x1d },
3669 { 0x17, 0x50 }, /* undocumented */
3670 { 0x37, 0x00 }, /* undocumented */
3671 { 0x40, 0xff }, /* I2C timeout counter */
3672 { 0x46, 0x00 }, /* I2C clock prescaler */
3673 { 0x59, 0x04 }, /* new from windrv 090403 */
3674 { 0xff, 0x00 }, /* undocumented */
3675 /* windows reads 0x55 at this point, why? */
3676 };
3677
a5ae2062 3678 static const struct ov_regvals mode_init_519[] = {
6a7eba24
JFM		 3679 { 0x5d, 0x03 }, /* Turn off suspend mode */
3680 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
21867803 3681 { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
6a7eba24
JFM		 3682 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3683 { 0xa3, 0x18 },
3684 { 0xa4, 0x04 },
3685 { 0xa5, 0x28 },
3686 { 0x37, 0x00 }, /* SetUsbInit */
3687 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3688 /* Enable both fields, YUV Input, disable defect comp (why?) */
3689 { 0x22, 0x1d },
3690 { 0x17, 0x50 }, /* undocumented */
3691 { 0x37, 0x00 }, /* undocumented */
3692 { 0x40, 0xff }, /* I2C timeout counter */
3693 { 0x46, 0x00 }, /* I2C clock prescaler */
3694 { 0x59, 0x04 }, /* new from windrv 090403 */
3695 { 0xff, 0x00 }, /* undocumented */
3696 /* windows reads 0x55 at this point, why? */
3697 };
3698
6a7eba24 3699 /******** Set the mode ********/
42e142f6
JFM		 3700 switch (sd->sensor) {
3701 default:
f8f20188 3702 write_regvals(sd, mode_init_519, ARRAY_SIZE(mode_init_519));
035d3a3d
HG		 3703 if (sd->sensor == SEN_OV7640 ||
3704 sd->sensor == SEN_OV7648) {
594f5b8b 3705 /* Select 8-bit input mode */
ac40b1fa 3706 reg_w_mask(sd, OV519_R20_DFR, 0x10, 0x10);
594f5b8b 3707 }
42e142f6
JFM		 3708 break;
3709 case SEN_OV7660:
3710 return; /* done by ov519_set_mode/fr() */
3711 case SEN_OV7670:
f8f20188
JFM		 3712 write_regvals(sd, mode_init_519_ov7670,
3713 ARRAY_SIZE(mode_init_519_ov7670));
42e142f6 3714 break;
6a7eba24
JFM		 3715 }
3716
ac40b1fa
JFM		 3717 reg_w(sd, OV519_R10_H_SIZE, sd->gspca_dev.width >> 4);
3718 reg_w(sd, OV519_R11_V_SIZE, sd->gspca_dev.height >> 3);
80142efa
HG		 3719 if (sd->sensor == SEN_OV7670 &&
3720 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3721 reg_w(sd, OV519_R12_X_OFFSETL, 0x04);
035d3a3d
HG		 3722 else if (sd->sensor == SEN_OV7648 &&
3723 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3724 reg_w(sd, OV519_R12_X_OFFSETL, 0x01);
80142efa
HG		 3725 else
3726 reg_w(sd, OV519_R12_X_OFFSETL, 0x00);
ac40b1fa
JFM		 3727 reg_w(sd, OV519_R13_X_OFFSETH, 0x00);
3728 reg_w(sd, OV519_R14_Y_OFFSETL, 0x00);
3729 reg_w(sd, OV519_R15_Y_OFFSETH, 0x00);
3730 reg_w(sd, OV519_R16_DIVIDER, 0x00);
3731 reg_w(sd, OV519_R25_FORMAT, 0x03); /* YUV422 */
6a7eba24
JFM		 3732 reg_w(sd, 0x26, 0x00); /* Undocumented */
3733
3734 /******** Set the framerate ********/
3735 if (frame_rate > 0)
3736 sd->frame_rate = frame_rate;
3737
3738/* FIXME: These are only valid at the max resolution. */
3739 sd->clockdiv = 0;
594f5b8b
JFM		 3740 switch (sd->sensor) {
3741 case SEN_OV7640:
035d3a3d 3742 case SEN_OV7648:
6a7eba24 3743 switch (sd->frame_rate) {
53e74515
JFM		 3744 default:
3745/* case 30: */
6a7eba24
JFM		 3746 reg_w(sd, 0xa4, 0x0c);
3747 reg_w(sd, 0x23, 0xff);
3748 break;
3749 case 25:
3750 reg_w(sd, 0xa4, 0x0c);
3751 reg_w(sd, 0x23, 0x1f);
3752 break;
3753 case 20:
3754 reg_w(sd, 0xa4, 0x0c);
3755 reg_w(sd, 0x23, 0x1b);
3756 break;
53e74515 3757 case 15:
6a7eba24
JFM		 3758 reg_w(sd, 0xa4, 0x04);
3759 reg_w(sd, 0x23, 0xff);
3760 sd->clockdiv = 1;
3761 break;
3762 case 10:
3763 reg_w(sd, 0xa4, 0x04);
3764 reg_w(sd, 0x23, 0x1f);
3765 sd->clockdiv = 1;
3766 break;
3767 case 5:
3768 reg_w(sd, 0xa4, 0x04);
3769 reg_w(sd, 0x23, 0x1b);
3770 sd->clockdiv = 1;
3771 break;
3772 }
594f5b8b
JFM		 3773 break;
3774 case SEN_OV8610:
6a7eba24
JFM		 3775 switch (sd->frame_rate) {
3776 default: /* 15 fps */
3777/* case 15: */
3778 reg_w(sd, 0xa4, 0x06);
3779 reg_w(sd, 0x23, 0xff);
3780 break;
3781 case 10:
3782 reg_w(sd, 0xa4, 0x06);
3783 reg_w(sd, 0x23, 0x1f);
3784 break;
3785 case 5:
3786 reg_w(sd, 0xa4, 0x06);
3787 reg_w(sd, 0x23, 0x1b);
3788 break;
3789 }
594f5b8b
JFM		 3790 break;
3791 case SEN_OV7670: /* guesses, based on 7640 */
6a7eba24
JFM		 3792 PDEBUG(D_STREAM, "Setting framerate to %d fps",
3793 (sd->frame_rate == 0) ? 15 : sd->frame_rate);
594f5b8b 3794 reg_w(sd, 0xa4, 0x10);
6a7eba24
JFM		 3795 switch (sd->frame_rate) {
3796 case 30:
6a7eba24
JFM		 3797 reg_w(sd, 0x23, 0xff);
3798 break;
3799 case 20:
6a7eba24
JFM		 3800 reg_w(sd, 0x23, 0x1b);
3801 break;
594f5b8b
JFM		 3802 default:
3803/* case 15: */
6a7eba24
JFM		 3804 reg_w(sd, 0x23, 0xff);
3805 sd->clockdiv = 1;
3806 break;
3807 }
594f5b8b 3808 break;
6a7eba24 3809 }
6a7eba24
JFM		 3810}
3811
f8f20188 3812static void mode_init_ov_sensor_regs(struct sd *sd)
6a7eba24 3813{
594f5b8b 3814 struct gspca_dev *gspca_dev;
ebbb5c3e 3815 int qvga, xstart, xend, ystart, yend;
9d1593a8 3816 u8 v;
594f5b8b
JFM		 3817
3818 gspca_dev = &sd->gspca_dev;
87bae740 3819 qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
6a7eba24
JFM		 3820
3821 /******** Mode (VGA/QVGA) and sensor specific regs ********/
3822 switch (sd->sensor) {
635118d5
HG		 3823 case SEN_OV2610:
3824 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3825 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3826 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3827 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3828 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
3829 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
3830 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
f8f20188 3831 return;
ebbb5c3e 3832 case SEN_OV3610:
635118d5
HG		 3833 if (qvga) {
3834 xstart = (1040 - gspca_dev->width) / 2 + (0x1f << 4);
b46aaa02 3835 ystart = (776 - gspca_dev->height) / 2;
635118d5 3836 } else {
b46aaa02 3837 xstart = (2076 - gspca_dev->width) / 2 + (0x10 << 4);
635118d5
HG		 3838 ystart = (1544 - gspca_dev->height) / 2;
3839 }
3840 xend = xstart + gspca_dev->width;
3841 yend = ystart + gspca_dev->height;
3842 /* Writing to the COMH register resets the other windowing regs
3843 to their default values, so we must do this first. */
3844 i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0xf0);
3845 i2c_w_mask(sd, 0x32,
3846 (((xend >> 1) & 7) << 3) | ((xstart >> 1) & 7),
3847 0x3f);
3848 i2c_w_mask(sd, 0x03,
3849 (((yend >> 1) & 3) << 2) | ((ystart >> 1) & 3),
3850 0x0f);
3851 i2c_w(sd, 0x17, xstart >> 4);
3852 i2c_w(sd, 0x18, xend >> 4);
3853 i2c_w(sd, 0x19, ystart >> 3);
3854 i2c_w(sd, 0x1a, yend >> 3);
f8f20188 3855 return;
6a7eba24
JFM		 3856 case SEN_OV8610:
3857 /* For OV8610 qvga means qsvga */
3858 i2c_w_mask(sd, OV7610_REG_COM_C, qvga ? (1 << 5) : 0, 1 << 5);
ebbb5c3e
HG		 3859 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3860 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3861 i2c_w_mask(sd, 0x2d, 0x00, 0x40); /* from windrv 090403 */
3862 i2c_w_mask(sd, 0x28, 0x20, 0x20); /* progressive mode on */
6a7eba24
JFM		 3863 break;
3864 case SEN_OV7610:
3865 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
780e3121 3866 i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
ebbb5c3e
HG		 3867 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3868 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3869 break;
3870 case SEN_OV7620:
859cc470 3871 case SEN_OV7620AE:
b282d873 3872 case SEN_OV76BE:
6a7eba24
JFM		 3873 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3874 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3875 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3876 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3877 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
b282d873 3878 i2c_w_mask(sd, 0x67, qvga ? 0xb0 : 0x90, 0xf0);
6a7eba24 3879 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e
HG		 3880 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3881 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3882 if (sd->sensor == SEN_OV76BE)
3883 i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
6a7eba24 3884 break;
6a7eba24 3885 case SEN_OV7640:
035d3a3d 3886 case SEN_OV7648:
6a7eba24
JFM		 3887 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3888 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
8d0082fa
HG		 3889 /* Setting this undocumented bit in qvga mode removes a very
3890 annoying vertical shaking of the image */
035d3a3d 3891 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
8d0082fa 3892 /* Unknown */
035d3a3d 3893 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
8d0082fa 3894 /* Allow higher automatic gain (to allow higher framerates) */
035d3a3d 3895 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3896 i2c_w_mask(sd, 0x12, 0x04, 0x04); /* AWB: 1 */
6a7eba24
JFM		 3897 break;
3898 case SEN_OV7670:
3899 /* set COM7_FMT_VGA or COM7_FMT_QVGA
3900 * do we need to set anything else?
3901 * HSTART etc are set in set_ov_sensor_window itself */
21867803 3902 i2c_w_mask(sd, OV7670_R12_COM7,
6a7eba24
JFM		 3903 qvga ? OV7670_COM7_FMT_QVGA : OV7670_COM7_FMT_VGA,
3904 OV7670_COM7_FMT_MASK);
ebbb5c3e 3905 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
21867803 3906 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_AWB,
ebbb5c3e
HG		 3907 OV7670_COM8_AWB);
3908 if (qvga) { /* QVGA from ov7670.c by
3909 * Jonathan Corbet */
3910 xstart = 164;
3911 xend = 28;
3912 ystart = 14;
3913 yend = 494;
3914 } else { /* VGA */
3915 xstart = 158;
3916 xend = 14;
3917 ystart = 10;
3918 yend = 490;
3919 }
3920 /* OV7670 hardware window registers are split across
3921 * multiple locations */
21867803
JFM		 3922 i2c_w(sd, OV7670_R17_HSTART, xstart >> 3);
3923 i2c_w(sd, OV7670_R18_HSTOP, xend >> 3);
3924 v = i2c_r(sd, OV7670_R32_HREF);
ebbb5c3e
HG		 3925 v = (v & 0xc0) | ((xend & 0x7) << 3) | (xstart & 0x07);
3926 msleep(10); /* need to sleep between read and write to
3927 * same reg! */
21867803 3928 i2c_w(sd, OV7670_R32_HREF, v);
ebbb5c3e 3929
21867803
JFM		 3930 i2c_w(sd, OV7670_R19_VSTART, ystart >> 2);
3931 i2c_w(sd, OV7670_R1A_VSTOP, yend >> 2);
3932 v = i2c_r(sd, OV7670_R03_VREF);
ebbb5c3e
HG		 3933 v = (v & 0xc0) | ((yend & 0x3) << 2) | (ystart & 0x03);
3934 msleep(10); /* need to sleep between read and write to
3935 * same reg! */
21867803 3936 i2c_w(sd, OV7670_R03_VREF, v);
6a7eba24
JFM		 3937 break;
3938 case SEN_OV6620:
ebbb5c3e
HG		 3939 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3940 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3941 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3942 break;
6a7eba24 3943 case SEN_OV6630:
7d971373 3944 case SEN_OV66308AF:
6a7eba24 3945 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3946 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3947 break;
3948 default:
f8f20188 3949 return;
6a7eba24
JFM		 3950 }
3951
6a7eba24 3952 /******** Clock programming ********/
ae49c404 3953 i2c_w(sd, 0x11, sd->clockdiv);
6a7eba24
JFM		 3954}
3955
42e142f6 3956/* this function works for bridge ov519 and sensors ov7660 and ov7670 only */
62833acd 3957static void sethvflip(struct gspca_dev *gspca_dev)
0cd6759d 3958{
62833acd
JFM		 3959 struct sd *sd = (struct sd *) gspca_dev;
3960
0cd6759d 3961 if (sd->gspca_dev.streaming)
5927abcb 3962 reg_w(sd, OV519_R51_RESET1, 0x0f); /* block stream */
21867803 3963 i2c_w_mask(sd, OV7670_R1E_MVFP,
62833acd
JFM		 3964 OV7670_MVFP_MIRROR * sd->ctrls[HFLIP].val
3965 | OV7670_MVFP_VFLIP * sd->ctrls[VFLIP].val,
594f5b8b 3966 OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP);
0cd6759d 3967 if (sd->gspca_dev.streaming)
5927abcb 3968 reg_w(sd, OV519_R51_RESET1, 0x00); /* restart stream */
0cd6759d
JFM		 3969}
3970
f8f20188 3971static void set_ov_sensor_window(struct sd *sd)
6a7eba24 3972{
594f5b8b 3973 struct gspca_dev *gspca_dev;
124cc9c0 3974 int qvga, crop;
6a7eba24 3975 int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;
6a7eba24 3976
635118d5 3977 /* mode setup is fully handled in mode_init_ov_sensor_regs for these */
42e142f6
JFM		 3978 switch (sd->sensor) {
3979 case SEN_OV2610:
3980 case SEN_OV3610:
3981 case SEN_OV7670:
f8f20188
JFM		 3982 mode_init_ov_sensor_regs(sd);
3983 return;
42e142f6
JFM		 3984 case SEN_OV7660:
3985 ov519_set_mode(sd);
3986 ov519_set_fr(sd);
3987 return;
f8f20188 3988 }
42e142f6 3989
594f5b8b 3990 gspca_dev = &sd->gspca_dev;
87bae740
JFM		 3991 qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
3992 crop = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 2;
594f5b8b 3993
6a7eba24
JFM		 3994 /* The different sensor ICs handle setting up of window differently.
3995 * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */
3996 switch (sd->sensor) {
3997 case SEN_OV8610:
3998 hwsbase = 0x1e;
3999 hwebase = 0x1e;
4000 vwsbase = 0x02;
4001 vwebase = 0x02;
4002 break;
4003 case SEN_OV7610:
4004 case SEN_OV76BE:
4005 hwsbase = 0x38;
4006 hwebase = 0x3a;
4007 vwsbase = vwebase = 0x05;
4008 break;
4009 case SEN_OV6620:
4010 case SEN_OV6630:
7d971373 4011 case SEN_OV66308AF:
6a7eba24
JFM		 4012 hwsbase = 0x38;
4013 hwebase = 0x3a;
4014 vwsbase = 0x05;
4015 vwebase = 0x06;
7d971373 4016 if (sd->sensor == SEN_OV66308AF && qvga)
49809d6a 4017 /* HDG: this fixes U and V getting swapped */
7d971373 4018 hwsbase++;
124cc9c0
HG		 4019 if (crop) {
4020 hwsbase += 8;
4021 hwebase += 8;
4022 vwsbase += 11;
4023 vwebase += 11;
4024 }
6a7eba24
JFM		 4025 break;
4026 case SEN_OV7620:
859cc470 4027 case SEN_OV7620AE:
6a7eba24
JFM		 4028 hwsbase = 0x2f; /* From 7620.SET (spec is wrong) */
4029 hwebase = 0x2f;
4030 vwsbase = vwebase = 0x05;
4031 break;
4032 case SEN_OV7640:
035d3a3d 4033 case SEN_OV7648:
6a7eba24
JFM		 4034 hwsbase = 0x1a;
4035 hwebase = 0x1a;
4036 vwsbase = vwebase = 0x03;
4037 break;
6a7eba24 4038 default:
f8f20188 4039 return;
6a7eba24
JFM		 4040 }
4041
4042 switch (sd->sensor) {
4043 case SEN_OV6620:
4044 case SEN_OV6630:
7d971373 4045 case SEN_OV66308AF:
594f5b8b 4046 if (qvga) { /* QCIF */
6a7eba24
JFM		 4047 hwscale = 0;
4048 vwscale = 0;
4049 } else { /* CIF */
4050 hwscale = 1;
4051 vwscale = 1; /* The datasheet says 0;
4052 * it's wrong */
4053 }
4054 break;
4055 case SEN_OV8610:
594f5b8b 4056 if (qvga) { /* QSVGA */
6a7eba24
JFM		 4057 hwscale = 1;
4058 vwscale = 1;
4059 } else { /* SVGA */
4060 hwscale = 2;
4061 vwscale = 2;
4062 }
4063 break;
4064 default: /* SEN_OV7xx0 */
594f5b8b 4065 if (qvga) { /* QVGA */
6a7eba24
JFM		 4066 hwscale = 1;
4067 vwscale = 0;
4068 } else { /* VGA */
4069 hwscale = 2;
4070 vwscale = 1;
4071 }
4072 }
4073
f8f20188 4074 mode_init_ov_sensor_regs(sd);
6a7eba24 4075
ebbb5c3e 4076 i2c_w(sd, 0x17, hwsbase);
a511ba94 4077 i2c_w(sd, 0x18, hwebase + (sd->sensor_width >> hwscale));
ebbb5c3e 4078 i2c_w(sd, 0x19, vwsbase);
a511ba94 4079 i2c_w(sd, 0x1a, vwebase + (sd->sensor_height >> vwscale));
6a7eba24
JFM		 4080}
4081
6a7eba24 4082/* -- start the camera -- */
72ab97ce 4083static int sd_start(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 4084{
4085 struct sd *sd = (struct sd *) gspca_dev;
6a7eba24 4086
a511ba94
HG		 4087 /* Default for most bridges, allow bridge_mode_init_regs to override */
4088 sd->sensor_width = sd->gspca_dev.width;
4089 sd->sensor_height = sd->gspca_dev.height;
4090
49809d6a 4091 switch (sd->bridge) {
1876bb92
HG		 4092 case BRIDGE_OV511:
4093 case BRIDGE_OV511PLUS:
f8f20188 4094 ov511_mode_init_regs(sd);
1876bb92 4095 break;
49809d6a
HG		 4096 case BRIDGE_OV518:
4097 case BRIDGE_OV518PLUS:
f8f20188 4098 ov518_mode_init_regs(sd);
49809d6a
HG		 4099 break;
4100 case BRIDGE_OV519:
f8f20188 4101 ov519_mode_init_regs(sd);
49809d6a 4102 break;
b46aaa02 4103 /* case BRIDGE_OVFX2: nothing to do */
a511ba94 4104 case BRIDGE_W9968CF:
f8f20188 4105 w9968cf_mode_init_regs(sd);
a511ba94 4106 break;
49809d6a 4107 }
49809d6a 4108
f8f20188 4109 set_ov_sensor_window(sd);
6a7eba24 4110
e2817029
JFM		 4111 if (!(sd->gspca_dev.ctrl_dis & (1 << CONTRAST)))
4112 setcontrast(gspca_dev);
4113 if (!(sd->gspca_dev.ctrl_dis & (1 << BRIGHTNESS)))
4114 setbrightness(gspca_dev);
4115 if (!(sd->gspca_dev.ctrl_dis & (1 << COLORS)))
4116 setcolors(gspca_dev);
4117 if (!(sd->gspca_dev.ctrl_dis & ((1 << HFLIP) | (1 << VFLIP))))
4118 sethvflip(gspca_dev);
4119 if (!(sd->gspca_dev.ctrl_dis & (1 << AUTOBRIGHT)))
4120 setautobright(gspca_dev);
4121 if (!(sd->gspca_dev.ctrl_dis & (1 << FREQ)))
4122 setfreq_i(sd);
49809d6a 4123
417a4d26
HG		 4124 /* Force clear snapshot state in case the snapshot button was
4125 pressed while we weren't streaming */
4126 sd->snapshot_needs_reset = 1;
4127 sd_reset_snapshot(gspca_dev);
417a4d26 4128
d6b6d7ae
HG		 4129 sd->first_frame = 3;
4130
f8f20188 4131 ov51x_restart(sd);
6a7eba24 4132 ov51x_led_control(sd, 1);
f8f20188 4133 return gspca_dev->usb_err;
6a7eba24
JFM		 4134}
4135
4136static void sd_stopN(struct gspca_dev *gspca_dev)
4137{
ac40b1fa
JFM		 4138 struct sd *sd = (struct sd *) gspca_dev;
4139
4140 ov51x_stop(sd);
4141 ov51x_led_control(sd, 0);
6a7eba24
JFM		 4142}
4143
79b35902
HG		 4144static void sd_stop0(struct gspca_dev *gspca_dev)
4145{
4146 struct sd *sd = (struct sd *) gspca_dev;
4147
d65174c0
JFM		 4148 if (!sd->gspca_dev.present)
4149 return;
79b35902
HG		 4150 if (sd->bridge == BRIDGE_W9968CF)
4151 w9968cf_stop0(sd);
614d0691 4152
14653e64 4153#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
614d0691
HG		 4154 /* If the last button state is pressed, release it now! */
4155 if (sd->snapshot_pressed) {
4156 input_report_key(gspca_dev->input_dev, KEY_CAMERA, 0);
4157 input_sync(gspca_dev->input_dev);
4158 sd->snapshot_pressed = 0;
4159 }
4160#endif
b4e96ea3
JFM		 4161 if (sd->bridge == BRIDGE_OV519)
4162 reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
79b35902
HG		 4163}
4164
92e232ac
HG		 4165static void ov51x_handle_button(struct gspca_dev *gspca_dev, u8 state)
4166{
4167 struct sd *sd = (struct sd *) gspca_dev;
4168
4169 if (sd->snapshot_pressed != state) {
2856643e 4170#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
92e232ac
HG		 4171 input_report_key(gspca_dev->input_dev, KEY_CAMERA, state);
4172 input_sync(gspca_dev->input_dev);
4173#endif
4174 if (state)
4175 sd->snapshot_needs_reset = 1;
4176
4177 sd->snapshot_pressed = state;
4178 } else {
88e8d20a
HG		 4179 /* On the ov511 / ov519 we need to reset the button state
4180 multiple times, as resetting does not work as long as the
4181 button stays pressed */
4182 switch (sd->bridge) {
4183 case BRIDGE_OV511:
4184 case BRIDGE_OV511PLUS:
4185 case BRIDGE_OV519:
4186 if (state)
4187 sd->snapshot_needs_reset = 1;
4188 break;
4189 }
92e232ac
HG		 4190 }
4191}
4192
1876bb92 4193static void ov511_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b
JFM		 4194 u8 *in, /* isoc packet */
4195 int len) /* iso packet length */
1876bb92
HG		 4196{
4197 struct sd *sd = (struct sd *) gspca_dev;
4198
4199 /* SOF/EOF packets have 1st to 8th bytes zeroed and the 9th
4200 * byte non-zero. The EOF packet has image width/height in the
4201 * 10th and 11th bytes. The 9th byte is given as follows:
4202 *
4203 * bit 7: EOF
4204 * 6: compression enabled
4205 * 5: 422/420/400 modes
4206 * 4: 422/420/400 modes
4207 * 3: 1
4208 * 2: snapshot button on
4209 * 1: snapshot frame
4210 * 0: even/odd field
4211 */
4212 if (!(in[0] | in[1] | in[2] | in[3] | in[4] | in[5] | in[6] | in[7]) &&
4213 (in[8] & 0x08)) {
88e8d20a 4214 ov51x_handle_button(gspca_dev, (in[8] >> 2) & 1);
1876bb92
HG		 4215 if (in[8] & 0x80) {
4216 /* Frame end */
4217 if ((in[9] + 1) * 8 != gspca_dev->width ||
4218 (in[10] + 1) * 8 != gspca_dev->height) {
4219 PDEBUG(D_ERR, "Invalid frame size, got: %dx%d,"
4220 " requested: %dx%d\n",
4221 (in[9] + 1) * 8, (in[10] + 1) * 8,
4222 gspca_dev->width, gspca_dev->height);
4223 gspca_dev->last_packet_type = DISCARD_PACKET;
4224 return;
4225 }
4226 /* Add 11 byte footer to frame, might be usefull */
76dd272b 4227 gspca_frame_add(gspca_dev, LAST_PACKET, in, 11);
1876bb92
HG		 4228 return;
4229 } else {
4230 /* Frame start */
76dd272b 4231 gspca_frame_add(gspca_dev, FIRST_PACKET, in, 0);
1876bb92
HG		 4232 sd->packet_nr = 0;
4233 }
4234 }
4235
4236 /* Ignore the packet number */
4237 len--;
4238
4239 /* intermediate packet */
76dd272b 4240 gspca_frame_add(gspca_dev, INTER_PACKET, in, len);
1876bb92
HG		 4241}
4242
49809d6a 4243static void ov518_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4244 u8 *data, /* isoc packet */
49809d6a
HG		 4245 int len) /* iso packet length */
4246{
92918a53 4247 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 4248
4249 /* A false positive here is likely, until OVT gives me
4250 * the definitive SOF/EOF format */
4251 if ((!(data[0] | data[1] | data[2] | data[3] | data[5])) && data[6]) {
92e232ac 4252 ov51x_handle_button(gspca_dev, (data[6] >> 1) & 1);
76dd272b
JFM		 4253 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
4254 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
92918a53
HG		 4255 sd->packet_nr = 0;
4256 }
4257
4258 if (gspca_dev->last_packet_type == DISCARD_PACKET)
4259 return;
4260
4261 /* Does this device use packet numbers ? */
4262 if (len & 7) {
4263 len--;
4264 if (sd->packet_nr == data[len])
4265 sd->packet_nr++;
4266 /* The last few packets of the frame (which are all 0's
4267 except that they may contain part of the footer), are
4268 numbered 0 */
4269 else if (sd->packet_nr == 0 || data[len]) {
4270 PDEBUG(D_ERR, "Invalid packet nr: %d (expect: %d)",
4271 (int)data[len], (int)sd->packet_nr);
4272 gspca_dev->last_packet_type = DISCARD_PACKET;
4273 return;
4274 }
49809d6a
HG		 4275 }
4276
4277 /* intermediate packet */
76dd272b 4278 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
49809d6a
HG		 4279}
4280
4281static void ov519_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4282 u8 *data, /* isoc packet */
6a7eba24
JFM		 4283 int len) /* iso packet length */
4284{
4285 /* Header of ov519 is 16 bytes:
4286 * Byte Value Description
4287 * 0 0xff magic
4288 * 1 0xff magic
4289 * 2 0xff magic
4290 * 3 0xXX 0x50 = SOF, 0x51 = EOF
4291 * 9 0xXX 0x01 initial frame without data,
4292 * 0x00 standard frame with image
4293 * 14 Lo in EOF: length of image data / 8
4294 * 15 Hi
4295 */
4296
4297 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff) {
4298 switch (data[3]) {
4299 case 0x50: /* start of frame */
417a4d26
HG		 4300 /* Don't check the button state here, as the state
4301 usually (always ?) changes at EOF and checking it
4302 here leads to unnecessary snapshot state resets. */
6a7eba24
JFM		 4303#define HDRSZ 16
4304 data += HDRSZ;
4305 len -= HDRSZ;
4306#undef HDRSZ
4307 if (data[0] == 0xff || data[1] == 0xd8)
76dd272b 4308 gspca_frame_add(gspca_dev, FIRST_PACKET,
6a7eba24
JFM		 4309 data, len);
4310 else
4311 gspca_dev->last_packet_type = DISCARD_PACKET;
4312 return;
4313 case 0x51: /* end of frame */
92e232ac 4314 ov51x_handle_button(gspca_dev, data[11] & 1);
6a7eba24
JFM		 4315 if (data[9] != 0)
4316 gspca_dev->last_packet_type = DISCARD_PACKET;
76dd272b
JFM		 4317 gspca_frame_add(gspca_dev, LAST_PACKET,
4318 NULL, 0);
6a7eba24
JFM		 4319 return;
4320 }
4321 }
4322
4323 /* intermediate packet */
76dd272b 4324 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
6a7eba24
JFM		 4325}
4326
b46aaa02 4327static void ovfx2_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4328 u8 *data, /* isoc packet */
b46aaa02
HG		 4329 int len) /* iso packet length */
4330{
d6b6d7ae 4331 struct sd *sd = (struct sd *) gspca_dev;
d6b6d7ae
HG		 4332
4333 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
4334
b46aaa02
HG		 4335 /* A short read signals EOF */
4336 if (len < OVFX2_BULK_SIZE) {
d6b6d7ae
HG		 4337 /* If the frame is short, and it is one of the first ones
4338 the sensor and bridge are still syncing, so drop it. */
4339 if (sd->first_frame) {
4340 sd->first_frame--;
b192ca98
JFM		 4341 if (gspca_dev->image_len <
4342 sd->gspca_dev.width * sd->gspca_dev.height)
d6b6d7ae
HG		 4343 gspca_dev->last_packet_type = DISCARD_PACKET;
4344 }
4345 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
76dd272b 4346 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
b46aaa02 4347 }
b46aaa02
HG		 4348}
4349
49809d6a 4350static void sd_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4351 u8 *data, /* isoc packet */
49809d6a
HG		 4352 int len) /* iso packet length */
4353{
4354 struct sd *sd = (struct sd *) gspca_dev;
4355
4356 switch (sd->bridge) {
4357 case BRIDGE_OV511:
4358 case BRIDGE_OV511PLUS:
76dd272b 4359 ov511_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4360 break;
4361 case BRIDGE_OV518:
4362 case BRIDGE_OV518PLUS:
76dd272b 4363 ov518_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4364 break;
4365 case BRIDGE_OV519:
76dd272b 4366 ov519_pkt_scan(gspca_dev, data, len);
49809d6a 4367 break;
b46aaa02 4368 case BRIDGE_OVFX2:
76dd272b 4369 ovfx2_pkt_scan(gspca_dev, data, len);
b46aaa02 4370 break;
a511ba94 4371 case BRIDGE_W9968CF:
76dd272b 4372 w9968cf_pkt_scan(gspca_dev, data, len);
a511ba94 4373 break;
49809d6a
HG		 4374 }
4375}
4376
6a7eba24
JFM		 4377/* -- management routines -- */
4378
4379static void setbrightness(struct gspca_dev *gspca_dev)
4380{
4381 struct sd *sd = (struct sd *) gspca_dev;
4382 int val;
42e142f6
JFM		 4383 static const struct ov_i2c_regvals brit_7660[][7] = {
4384 {{0x0f, 0x6a}, {0x24, 0x40}, {0x25, 0x2b}, {0x26, 0x90},
4385 {0x27, 0xe0}, {0x28, 0xe0}, {0x2c, 0xe0}},
4386 {{0x0f, 0x6a}, {0x24, 0x50}, {0x25, 0x40}, {0x26, 0xa1},
4387 {0x27, 0xc0}, {0x28, 0xc0}, {0x2c, 0xc0}},
4388 {{0x0f, 0x6a}, {0x24, 0x68}, {0x25, 0x58}, {0x26, 0xc2},
4389 {0x27, 0xa0}, {0x28, 0xa0}, {0x2c, 0xa0}},
4390 {{0x0f, 0x6a}, {0x24, 0x70}, {0x25, 0x68}, {0x26, 0xd3},
4391 {0x27, 0x80}, {0x28, 0x80}, {0x2c, 0x80}},
4392 {{0x0f, 0x6a}, {0x24, 0x80}, {0x25, 0x70}, {0x26, 0xd3},
4393 {0x27, 0x20}, {0x28, 0x20}, {0x2c, 0x20}},
4394 {{0x0f, 0x6a}, {0x24, 0x88}, {0x25, 0x78}, {0x26, 0xd3},
4395 {0x27, 0x40}, {0x28, 0x40}, {0x2c, 0x40}},
4396 {{0x0f, 0x6a}, {0x24, 0x90}, {0x25, 0x80}, {0x26, 0xd4},
4397 {0x27, 0x60}, {0x28, 0x60}, {0x2c, 0x60}}
4398 };
6a7eba24 4399
62833acd 4400 val = sd->ctrls[BRIGHTNESS].val;
6a7eba24
JFM		 4401 switch (sd->sensor) {
4402 case SEN_OV8610:
4403 case SEN_OV7610:
4404 case SEN_OV76BE:
4405 case SEN_OV6620:
4406 case SEN_OV6630:
7d971373 4407 case SEN_OV66308AF:
6a7eba24 4408 case SEN_OV7640:
035d3a3d 4409 case SEN_OV7648:
6a7eba24
JFM		 4410 i2c_w(sd, OV7610_REG_BRT, val);
4411 break;
4412 case SEN_OV7620:
859cc470 4413 case SEN_OV7620AE:
6a7eba24 4414 /* 7620 doesn't like manual changes when in auto mode */
62833acd 4415 if (!sd->ctrls[AUTOBRIGHT].val)
6a7eba24
JFM		 4416 i2c_w(sd, OV7610_REG_BRT, val);
4417 break;
42e142f6
JFM		 4418 case SEN_OV7660:
4419 write_i2c_regvals(sd, brit_7660[val],
4420 ARRAY_SIZE(brit_7660[0]));
4421 break;
6a7eba24 4422 case SEN_OV7670:
594f5b8b 4423/*win trace
21867803
JFM		 4424 * i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_AEC); */
4425 i2c_w(sd, OV7670_R55_BRIGHT, ov7670_abs_to_sm(val));
6a7eba24
JFM		 4426 break;
4427 }
6a7eba24
JFM		 4428}
4429
4430static void setcontrast(struct gspca_dev *gspca_dev)
4431{
4432 struct sd *sd = (struct sd *) gspca_dev;
4433 int val;
42e142f6
JFM		 4434 static const struct ov_i2c_regvals contrast_7660[][31] = {
4435 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0xa0},
4436 {0x70, 0x58}, {0x71, 0x38}, {0x72, 0x30}, {0x73, 0x30},
4437 {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x24}, {0x77, 0x24},
4438 {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x34},
4439 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x65},
4440 {0x80, 0x70}, {0x81, 0x77}, {0x82, 0x7d}, {0x83, 0x83},
4441 {0x84, 0x88}, {0x85, 0x8d}, {0x86, 0x96}, {0x87, 0x9f},
4442 {0x88, 0xb0}, {0x89, 0xc4}, {0x8a, 0xd9}},
4443 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0x94},
4444 {0x70, 0x58}, {0x71, 0x40}, {0x72, 0x30}, {0x73, 0x30},
4445 {0x74, 0x30}, {0x75, 0x30}, {0x76, 0x2c}, {0x77, 0x24},
4446 {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x31},
4447 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x62},
4448 {0x80, 0x6d}, {0x81, 0x75}, {0x82, 0x7b}, {0x83, 0x81},
4449 {0x84, 0x87}, {0x85, 0x8d}, {0x86, 0x98}, {0x87, 0xa1},
4450 {0x88, 0xb2}, {0x89, 0xc6}, {0x8a, 0xdb}},
4451 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x84},
4452 {0x70, 0x58}, {0x71, 0x48}, {0x72, 0x40}, {0x73, 0x40},
4453 {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x28}, {0x77, 0x24},
4454 {0x78, 0x26}, {0x79, 0x28}, {0x7a, 0x28}, {0x7b, 0x34},
4455 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x5d},
4456 {0x80, 0x68}, {0x81, 0x71}, {0x82, 0x79}, {0x83, 0x81},
4457 {0x84, 0x86}, {0x85, 0x8b}, {0x86, 0x95}, {0x87, 0x9e},
4458 {0x88, 0xb1}, {0x89, 0xc5}, {0x8a, 0xd9}},
4459 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x70},
4460 {0x70, 0x58}, {0x71, 0x58}, {0x72, 0x48}, {0x73, 0x48},
4461 {0x74, 0x38}, {0x75, 0x40}, {0x76, 0x34}, {0x77, 0x34},
4462 {0x78, 0x2e}, {0x79, 0x28}, {0x7a, 0x24}, {0x7b, 0x22},
4463 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x58},
4464 {0x80, 0x63}, {0x81, 0x6e}, {0x82, 0x77}, {0x83, 0x80},
4465 {0x84, 0x87}, {0x85, 0x8f}, {0x86, 0x9c}, {0x87, 0xa9},
4466 {0x88, 0xc0}, {0x89, 0xd4}, {0x8a, 0xe6}},
4467 {{0x6c, 0xa0}, {0x6d, 0xf0}, {0x6e, 0x90}, {0x6f, 0x80},
4468 {0x70, 0x70}, {0x71, 0x80}, {0x72, 0x60}, {0x73, 0x60},
4469 {0x74, 0x58}, {0x75, 0x60}, {0x76, 0x4c}, {0x77, 0x38},
4470 {0x78, 0x38}, {0x79, 0x2a}, {0x7a, 0x20}, {0x7b, 0x0e},
4471 {0x7c, 0x0a}, {0x7d, 0x14}, {0x7e, 0x26}, {0x7f, 0x46},
4472 {0x80, 0x54}, {0x81, 0x64}, {0x82, 0x70}, {0x83, 0x7c},
4473 {0x84, 0x87}, {0x85, 0x93}, {0x86, 0xa6}, {0x87, 0xb4},
4474 {0x88, 0xd0}, {0x89, 0xe5}, {0x8a, 0xf5}},
4475 {{0x6c, 0x60}, {0x6d, 0x80}, {0x6e, 0x60}, {0x6f, 0x80},
4476 {0x70, 0x80}, {0x71, 0x80}, {0x72, 0x88}, {0x73, 0x30},
4477 {0x74, 0x70}, {0x75, 0x68}, {0x76, 0x64}, {0x77, 0x50},
4478 {0x78, 0x3c}, {0x79, 0x22}, {0x7a, 0x10}, {0x7b, 0x08},
4479 {0x7c, 0x06}, {0x7d, 0x0e}, {0x7e, 0x1a}, {0x7f, 0x3a},
4480 {0x80, 0x4a}, {0x81, 0x5a}, {0x82, 0x6b}, {0x83, 0x7b},
4481 {0x84, 0x89}, {0x85, 0x96}, {0x86, 0xaf}, {0x87, 0xc3},
4482 {0x88, 0xe1}, {0x89, 0xf2}, {0x8a, 0xfa}},
4483 {{0x6c, 0x20}, {0x6d, 0x40}, {0x6e, 0x20}, {0x6f, 0x60},
4484 {0x70, 0x88}, {0x71, 0xc8}, {0x72, 0xc0}, {0x73, 0xb8},
4485 {0x74, 0xa8}, {0x75, 0xb8}, {0x76, 0x80}, {0x77, 0x5c},
4486 {0x78, 0x26}, {0x79, 0x10}, {0x7a, 0x08}, {0x7b, 0x04},
4487 {0x7c, 0x02}, {0x7d, 0x06}, {0x7e, 0x0a}, {0x7f, 0x22},
4488 {0x80, 0x33}, {0x81, 0x4c}, {0x82, 0x64}, {0x83, 0x7b},
4489 {0x84, 0x90}, {0x85, 0xa7}, {0x86, 0xc7}, {0x87, 0xde},
4490 {0x88, 0xf1}, {0x89, 0xf9}, {0x8a, 0xfd}},
4491 };
6a7eba24 4492
62833acd 4493 val = sd->ctrls[CONTRAST].val;
6a7eba24
JFM		 4494 switch (sd->sensor) {
4495 case SEN_OV7610:
4496 case SEN_OV6620:
4497 i2c_w(sd, OV7610_REG_CNT, val);
4498 break;
4499 case SEN_OV6630:
7d971373 4500 case SEN_OV66308AF:
6a7eba24 4501 i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f);
49809d6a 4502 break;
6a7eba24 4503 case SEN_OV8610: {
9d1593a8 4504 static const u8 ctab[] = {
6a7eba24
JFM		 4505 0x03, 0x09, 0x0b, 0x0f, 0x53, 0x6f, 0x35, 0x7f
4506 };
4507
4508 /* Use Y gamma control instead. Bit 0 enables it. */
4509 i2c_w(sd, 0x64, ctab[val >> 5]);
4510 break;
4511 }
859cc470
HG		 4512 case SEN_OV7620:
4513 case SEN_OV7620AE: {
9d1593a8 4514 static const u8 ctab[] = {
6a7eba24
JFM		 4515 0x01, 0x05, 0x09, 0x11, 0x15, 0x35, 0x37, 0x57,
4516 0x5b, 0xa5, 0xa7, 0xc7, 0xc9, 0xcf, 0xef, 0xff
4517 };
4518
4519 /* Use Y gamma control instead. Bit 0 enables it. */
4520 i2c_w(sd, 0x64, ctab[val >> 4]);
4521 break;
4522 }
42e142f6
JFM		 4523 case SEN_OV7660:
4524 write_i2c_regvals(sd, contrast_7660[val],
4525 ARRAY_SIZE(contrast_7660[0]));
4526 break;
6a7eba24
JFM		 4527 case SEN_OV7670:
4528 /* check that this isn't just the same as ov7610 */
21867803 4529 i2c_w(sd, OV7670_R56_CONTRAS, val >> 1);
6a7eba24
JFM		 4530 break;
4531 }
6a7eba24
JFM		 4532}
4533
4534static void setcolors(struct gspca_dev *gspca_dev)
4535{
4536 struct sd *sd = (struct sd *) gspca_dev;
4537 int val;
42e142f6
JFM		 4538 static const struct ov_i2c_regvals colors_7660[][6] = {
4539 {{0x4f, 0x28}, {0x50, 0x2a}, {0x51, 0x02}, {0x52, 0x0a},
4540 {0x53, 0x19}, {0x54, 0x23}},
4541 {{0x4f, 0x47}, {0x50, 0x4a}, {0x51, 0x03}, {0x52, 0x11},
4542 {0x53, 0x2c}, {0x54, 0x3e}},
4543 {{0x4f, 0x66}, {0x50, 0x6b}, {0x51, 0x05}, {0x52, 0x19},
4544 {0x53, 0x40}, {0x54, 0x59}},
4545 {{0x4f, 0x84}, {0x50, 0x8b}, {0x51, 0x06}, {0x52, 0x20},
4546 {0x53, 0x53}, {0x54, 0x73}},
4547 {{0x4f, 0xa3}, {0x50, 0xab}, {0x51, 0x08}, {0x52, 0x28},
4548 {0x53, 0x66}, {0x54, 0x8e}},
4549 };
6a7eba24 4550
62833acd 4551 val = sd->ctrls[COLORS].val;
6a7eba24
JFM		 4552 switch (sd->sensor) {
4553 case SEN_OV8610:
4554 case SEN_OV7610:
4555 case SEN_OV76BE:
4556 case SEN_OV6620:
4557 case SEN_OV6630:
7d971373 4558 case SEN_OV66308AF:
6a7eba24
JFM		 4559 i2c_w(sd, OV7610_REG_SAT, val);
4560 break;
4561 case SEN_OV7620:
859cc470 4562 case SEN_OV7620AE:
6a7eba24
JFM		 4563 /* Use UV gamma control instead. Bits 0 & 7 are reserved. */
4564/* rc = ov_i2c_write(sd->dev, 0x62, (val >> 9) & 0x7e);
4565 if (rc < 0)
4566 goto out; */
4567 i2c_w(sd, OV7610_REG_SAT, val);
4568 break;
4569 case SEN_OV7640:
035d3a3d 4570 case SEN_OV7648:
6a7eba24
JFM		 4571 i2c_w(sd, OV7610_REG_SAT, val & 0xf0);
4572 break;
42e142f6
JFM		 4573 case SEN_OV7660:
4574 write_i2c_regvals(sd, colors_7660[val],
4575 ARRAY_SIZE(colors_7660[0]));
4576 break;
6a7eba24
JFM		 4577 case SEN_OV7670:
4578 /* supported later once I work out how to do it
4579 * transparently fail now! */
4580 /* set REG_COM13 values for UV sat auto mode */
4581 break;
4582 }
6a7eba24
JFM		 4583}
4584
62833acd 4585static void setautobright(struct gspca_dev *gspca_dev)
02ab18b0 4586{
62833acd
JFM		 4587 struct sd *sd = (struct sd *) gspca_dev;
4588
62833acd 4589 i2c_w_mask(sd, 0x2d, sd->ctrls[AUTOBRIGHT].val ? 0x10 : 0x00, 0x10);
02ab18b0
HG		 4590}
4591
62833acd 4592static void setfreq_i(struct sd *sd)
02ab18b0 4593{
42e142f6
JFM		 4594 if (sd->sensor == SEN_OV7660
4595 || sd->sensor == SEN_OV7670) {
62833acd 4596 switch (sd->ctrls[FREQ].val) {
02ab18b0 4597 case 0: /* Banding filter disabled */
21867803 4598 i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_BFILT);
02ab18b0
HG		 4599 break;
4600 case 1: /* 50 hz */
21867803 4601 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
02ab18b0 4602 OV7670_COM8_BFILT);
21867803 4603 i2c_w_mask(sd, OV7670_R3B_COM11, 0x08, 0x18);
02ab18b0
HG		 4604 break;
4605 case 2: /* 60 hz */
21867803 4606 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
02ab18b0 4607 OV7670_COM8_BFILT);
21867803 4608 i2c_w_mask(sd, OV7670_R3B_COM11, 0x00, 0x18);
02ab18b0 4609 break;
21867803
JFM		 4610 case 3: /* Auto hz - ov7670 only */
4611 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
02ab18b0 4612 OV7670_COM8_BFILT);
21867803 4613 i2c_w_mask(sd, OV7670_R3B_COM11, OV7670_COM11_HZAUTO,
02ab18b0
HG		 4614 0x18);
4615 break;
4616 }
4617 } else {
62833acd 4618 switch (sd->ctrls[FREQ].val) {
02ab18b0
HG		 4619 case 0: /* Banding filter disabled */
4620 i2c_w_mask(sd, 0x2d, 0x00, 0x04);
4621 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4622 break;
4623 case 1: /* 50 hz (filter on and framerate adj) */
4624 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4625 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4626 /* 20 fps -> 16.667 fps */
4627 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4628 sd->sensor == SEN_OV6630 ||
4629 sd->sensor == SEN_OV66308AF)
02ab18b0
HG		 4630 i2c_w(sd, 0x2b, 0x5e);
4631 else
4632 i2c_w(sd, 0x2b, 0xac);
4633 break;
4634 case 2: /* 60 hz (filter on, ...) */
4635 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4636 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4637 sd->sensor == SEN_OV6630 ||
4638 sd->sensor == SEN_OV66308AF) {
02ab18b0
HG		 4639 /* 20 fps -> 15 fps */
4640 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4641 i2c_w(sd, 0x2b, 0xa8);
4642 } else {
4643 /* no framerate adj. */
4644 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4645 }
4646 break;
4647 }
4648 }
4649}
62833acd 4650static void setfreq(struct gspca_dev *gspca_dev)
02ab18b0
HG		 4651{
4652 struct sd *sd = (struct sd *) gspca_dev;
4653
62833acd 4654 setfreq_i(sd);
02ab18b0 4655
62833acd
JFM		 4656 /* Ugly but necessary */
4657 if (sd->bridge == BRIDGE_W9968CF)
4658 w9968cf_set_crop_window(sd);
02ab18b0
HG		 4659}
4660
4661static int sd_querymenu(struct gspca_dev *gspca_dev,
4662 struct v4l2_querymenu *menu)
4663{
4664 struct sd *sd = (struct sd *) gspca_dev;
4665
4666 switch (menu->id) {
4667 case V4L2_CID_POWER_LINE_FREQUENCY:
4668 switch (menu->index) {
4669 case 0: /* V4L2_CID_POWER_LINE_FREQUENCY_DISABLED */
4670 strcpy((char *) menu->name, "NoFliker");
4671 return 0;
4672 case 1: /* V4L2_CID_POWER_LINE_FREQUENCY_50HZ */
4673 strcpy((char *) menu->name, "50 Hz");
4674 return 0;
4675 case 2: /* V4L2_CID_POWER_LINE_FREQUENCY_60HZ */
4676 strcpy((char *) menu->name, "60 Hz");
4677 return 0;
4678 case 3:
4679 if (sd->sensor != SEN_OV7670)
4680 return -EINVAL;
4681
4682 strcpy((char *) menu->name, "Automatic");
4683 return 0;
4684 }
4685 break;
4686 }
4687 return -EINVAL;
4688}
4689
79b35902
HG		 4690static int sd_get_jcomp(struct gspca_dev *gspca_dev,
4691 struct v4l2_jpegcompression *jcomp)
4692{
4693 struct sd *sd = (struct sd *) gspca_dev;
4694
4695 if (sd->bridge != BRIDGE_W9968CF)
4696 return -EINVAL;
4697
4698 memset(jcomp, 0, sizeof *jcomp);
4699 jcomp->quality = sd->quality;
4700 jcomp->jpeg_markers = V4L2_JPEG_MARKER_DHT | V4L2_JPEG_MARKER_DQT |
4701 V4L2_JPEG_MARKER_DRI;
4702 return 0;
4703}
4704
4705static int sd_set_jcomp(struct gspca_dev *gspca_dev,
4706 struct v4l2_jpegcompression *jcomp)
4707{
4708 struct sd *sd = (struct sd *) gspca_dev;
4709
4710 if (sd->bridge != BRIDGE_W9968CF)
4711 return -EINVAL;
4712
4713 if (gspca_dev->streaming)
4714 return -EBUSY;
4715
4716 if (jcomp->quality < QUALITY_MIN)
4717 sd->quality = QUALITY_MIN;
4718 else if (jcomp->quality > QUALITY_MAX)
4719 sd->quality = QUALITY_MAX;
4720 else
4721 sd->quality = jcomp->quality;
4722
4723 /* Return resulting jcomp params to app */
4724 sd_get_jcomp(gspca_dev, jcomp);
4725
4726 return 0;
4727}
4728
6a7eba24 4729/* sub-driver description */
a5ae2062 4730static const struct sd_desc sd_desc = {
6a7eba24
JFM		 4731 .name = MODULE_NAME,
4732 .ctrls = sd_ctrls,
4733 .nctrls = ARRAY_SIZE(sd_ctrls),
4734 .config = sd_config,
012d6b02 4735 .init = sd_init,
6a7eba24
JFM		 4736 .start = sd_start,
4737 .stopN = sd_stopN,
79b35902 4738 .stop0 = sd_stop0,
6a7eba24 4739 .pkt_scan = sd_pkt_scan,
417a4d26 4740 .dq_callback = sd_reset_snapshot,
02ab18b0 4741 .querymenu = sd_querymenu,
79b35902
HG		 4742 .get_jcomp = sd_get_jcomp,
4743 .set_jcomp = sd_set_jcomp,
2856643e 4744#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
417a4d26
HG		 4745 .other_input = 1,
4746#endif
6a7eba24
JFM		 4747};
4748
4749/* -- module initialisation -- */
95c967c1 4750static const struct usb_device_id device_table[] = {
a511ba94 4751 {USB_DEVICE(0x041e, 0x4003), .driver_info = BRIDGE_W9968CF },
49809d6a
HG		 4752 {USB_DEVICE(0x041e, 0x4052), .driver_info = BRIDGE_OV519 },
4753 {USB_DEVICE(0x041e, 0x405f), .driver_info = BRIDGE_OV519 },
4754 {USB_DEVICE(0x041e, 0x4060), .driver_info = BRIDGE_OV519 },
4755 {USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
9e4d8258 4756 {USB_DEVICE(0x041e, 0x4064),
87bae740 4757 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
518c8df7 4758 {USB_DEVICE(0x041e, 0x4067), .driver_info = BRIDGE_OV519 },
9e4d8258 4759 {USB_DEVICE(0x041e, 0x4068),
87bae740 4760 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
49809d6a
HG		 4761 {USB_DEVICE(0x045e, 0x028c), .driver_info = BRIDGE_OV519 },
4762 {USB_DEVICE(0x054c, 0x0154), .driver_info = BRIDGE_OV519 },
98184f78 4763 {USB_DEVICE(0x054c, 0x0155),
87bae740 4764 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
1876bb92 4765 {USB_DEVICE(0x05a9, 0x0511), .driver_info = BRIDGE_OV511 },
49809d6a
HG		 4766 {USB_DEVICE(0x05a9, 0x0518), .driver_info = BRIDGE_OV518 },
4767 {USB_DEVICE(0x05a9, 0x0519), .driver_info = BRIDGE_OV519 },
4768 {USB_DEVICE(0x05a9, 0x0530), .driver_info = BRIDGE_OV519 },
b46aaa02 4769 {USB_DEVICE(0x05a9, 0x2800), .driver_info = BRIDGE_OVFX2 },
49809d6a
HG		 4770 {USB_DEVICE(0x05a9, 0x4519), .driver_info = BRIDGE_OV519 },
4771 {USB_DEVICE(0x05a9, 0x8519), .driver_info = BRIDGE_OV519 },
1876bb92 4772 {USB_DEVICE(0x05a9, 0xa511), .driver_info = BRIDGE_OV511PLUS },
49809d6a 4773 {USB_DEVICE(0x05a9, 0xa518), .driver_info = BRIDGE_OV518PLUS },
1876bb92 4774 {USB_DEVICE(0x0813, 0x0002), .driver_info = BRIDGE_OV511PLUS },
b46aaa02
HG		 4775 {USB_DEVICE(0x0b62, 0x0059), .driver_info = BRIDGE_OVFX2 },
4776 {USB_DEVICE(0x0e96, 0xc001), .driver_info = BRIDGE_OVFX2 },
a511ba94 4777 {USB_DEVICE(0x1046, 0x9967), .driver_info = BRIDGE_W9968CF },
87bae740 4778 {USB_DEVICE(0x8020, 0xef04), .driver_info = BRIDGE_OVFX2 },
6a7eba24
JFM		 4779 {}
4780};
ac40b1fa 4781
6a7eba24
JFM		 4782MODULE_DEVICE_TABLE(usb, device_table);
4783
4784/* -- device connect -- */
4785static int sd_probe(struct usb_interface *intf,
4786 const struct usb_device_id *id)
4787{
4788 return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
4789 THIS_MODULE);
4790}
4791
4792static struct usb_driver sd_driver = {
4793 .name = MODULE_NAME,
4794 .id_table = device_table,
4795 .probe = sd_probe,
4796 .disconnect = gspca_disconnect,
6a709749
JFM		 4797#ifdef CONFIG_PM
4798 .suspend = gspca_suspend,
4799 .resume = gspca_resume,
4800#endif
6a7eba24
JFM		 4801};
4802
4803/* -- module insert / remove -- */
4804static int __init sd_mod_init(void)
4805{
54826437 4806 return usb_register(&sd_driver);
6a7eba24
JFM		 4807}
4808static void __exit sd_mod_exit(void)
4809{
4810 usb_deregister(&sd_driver);
6a7eba24
JFM		 4811}
4812
4813module_init(sd_mod_init);
4814module_exit(sd_mod_exit);
4815
4816module_param(frame_rate, int, 0644);
4817MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)");
Linux kernel - Deliverables
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