byteorder: provide swabb.h generically in asm/byteorder.h
[deliverable/linux.git] / drivers / media / video / ivtv / ivtv-driver.h
CommitLineData
1a0adaf3
HV
1/*
2 ivtv driver internal defines and structures
3 Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
4 Copyright (C) 2004 Chris Kennedy <c@groovy.org>
5 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef IVTV_DRIVER_H
23#define IVTV_DRIVER_H
24
25/* Internal header for ivtv project:
26 * Driver for the cx23415/6 chip.
27 * Author: Kevin Thayer (nufan_wfk at yahoo.com)
28 * License: GPL
29 * http://www.ivtvdriver.org
30 *
31 * -----
32 * MPG600/MPG160 support by T.Adachi <tadachi@tadachi-net.com>
33 * and Takeru KOMORIYA<komoriya@paken.org>
34 *
35 * AVerMedia M179 GPIO info by Chris Pinkham <cpinkham@bc2va.org>
36 * using information provided by Jiun-Kuei Jung @ AVerMedia.
37 */
38
39#include <linux/version.h>
40#include <linux/module.h>
1a0adaf3
HV
41#include <linux/init.h>
42#include <linux/delay.h>
43#include <linux/sched.h>
44#include <linux/fs.h>
45#include <linux/pci.h>
46#include <linux/interrupt.h>
47#include <linux/spinlock.h>
48#include <linux/i2c.h>
49#include <linux/i2c-algo-bit.h>
50#include <linux/list.h>
51#include <linux/unistd.h>
1a0adaf3 52#include <linux/pagemap.h>
11763609 53#include <linux/scatterlist.h>
1a0adaf3
HV
54#include <linux/workqueue.h>
55#include <linux/mutex.h>
56#include <asm/uaccess.h>
57#include <asm/system.h>
58
59#include <linux/dvb/video.h>
60#include <linux/dvb/audio.h>
61#include <media/v4l2-common.h>
35ea11ff 62#include <media/v4l2-ioctl.h>
1a0adaf3
HV
63#include <media/tuner.h>
64#include <media/cx2341x.h>
65
51b39dfa 66#include <linux/ivtv.h>
1a0adaf3 67
33c0fcad 68/* Memory layout */
1a0adaf3 69#define IVTV_ENCODER_OFFSET 0x00000000
33c0fcad 70#define IVTV_ENCODER_SIZE 0x00800000 /* Total size is 0x01000000, but only first half is used */
1a0adaf3 71#define IVTV_DECODER_OFFSET 0x01000000
33c0fcad 72#define IVTV_DECODER_SIZE 0x00800000 /* Total size is 0x01000000, but only first half is used */
1a0adaf3
HV
73#define IVTV_REG_OFFSET 0x02000000
74#define IVTV_REG_SIZE 0x00010000
75
32db7754
HV
76/* Maximum ivtv driver instances. Some people have a huge number of
77 capture cards, so set this to a high value. */
78#define IVTV_MAX_CARDS 32
1a0adaf3 79
1a0adaf3
HV
80#define IVTV_ENC_STREAM_TYPE_MPG 0
81#define IVTV_ENC_STREAM_TYPE_YUV 1
82#define IVTV_ENC_STREAM_TYPE_VBI 2
83#define IVTV_ENC_STREAM_TYPE_PCM 3
84#define IVTV_ENC_STREAM_TYPE_RAD 4
85#define IVTV_DEC_STREAM_TYPE_MPG 5
86#define IVTV_DEC_STREAM_TYPE_VBI 6
87#define IVTV_DEC_STREAM_TYPE_VOUT 7
88#define IVTV_DEC_STREAM_TYPE_YUV 8
89#define IVTV_MAX_STREAMS 9
90
1a0adaf3
HV
91#define IVTV_DMA_SG_OSD_ENT (2883584/PAGE_SIZE) /* sg entities */
92
1a0adaf3
HV
93/* DMA Registers */
94#define IVTV_REG_DMAXFER (0x0000)
95#define IVTV_REG_DMASTATUS (0x0004)
96#define IVTV_REG_DECDMAADDR (0x0008)
97#define IVTV_REG_ENCDMAADDR (0x000c)
98#define IVTV_REG_DMACONTROL (0x0010)
99#define IVTV_REG_IRQSTATUS (0x0040)
100#define IVTV_REG_IRQMASK (0x0048)
101
102/* Setup Registers */
103#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
104#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
105#define IVTV_REG_DEC_SDRAM_REFRESH (0x08F8)
106#define IVTV_REG_DEC_SDRAM_PRECHARGE (0x08FC)
107#define IVTV_REG_VDM (0x2800)
108#define IVTV_REG_AO (0x2D00)
109#define IVTV_REG_BYTEFLUSH (0x2D24)
110#define IVTV_REG_SPU (0x9050)
111#define IVTV_REG_HW_BLOCKS (0x9054)
112#define IVTV_REG_VPU (0x9058)
113#define IVTV_REG_APU (0xA064)
114
1a0adaf3
HV
115/* i2c stuff */
116#define I2C_CLIENTS_MAX 16
117
118/* debugging */
33c0fcad 119extern int ivtv_debug;
1a0adaf3 120
1aa32c2f
HV
121#define IVTV_DBGFLG_WARN (1 << 0)
122#define IVTV_DBGFLG_INFO (1 << 1)
123#define IVTV_DBGFLG_MB (1 << 2)
124#define IVTV_DBGFLG_IOCTL (1 << 3)
125#define IVTV_DBGFLG_FILE (1 << 4)
126#define IVTV_DBGFLG_DMA (1 << 5)
127#define IVTV_DBGFLG_IRQ (1 << 6)
128#define IVTV_DBGFLG_DEC (1 << 7)
129#define IVTV_DBGFLG_YUV (1 << 8)
130#define IVTV_DBGFLG_I2C (1 << 9)
bd58df6d 131/* Flag to turn on high volume debugging */
1aa32c2f 132#define IVTV_DBGFLG_HIGHVOL (1 << 10)
1a0adaf3
HV
133
134/* NOTE: extra space before comma in 'itv->num , ## args' is required for
135 gcc-2.95, otherwise it won't compile. */
136#define IVTV_DEBUG(x, type, fmt, args...) \
137 do { \
138 if ((x) & ivtv_debug) \
139 printk(KERN_INFO "ivtv%d " type ": " fmt, itv->num , ## args); \
140 } while (0)
1aa32c2f
HV
141#define IVTV_DEBUG_WARN(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_WARN, "warn", fmt , ## args)
142#define IVTV_DEBUG_INFO(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_INFO, "info", fmt , ## args)
143#define IVTV_DEBUG_MB(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_MB, "mb", fmt , ## args)
144#define IVTV_DEBUG_DMA(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DMA, "dma", fmt , ## args)
1a0adaf3 145#define IVTV_DEBUG_IOCTL(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args)
1aa32c2f
HV
146#define IVTV_DEBUG_FILE(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_FILE, "file", fmt , ## args)
147#define IVTV_DEBUG_I2C(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_I2C, "i2c", fmt , ## args)
148#define IVTV_DEBUG_IRQ(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IRQ, "irq", fmt , ## args)
149#define IVTV_DEBUG_DEC(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DEC, "dec", fmt , ## args)
150#define IVTV_DEBUG_YUV(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_YUV, "yuv", fmt , ## args)
1a0adaf3 151
bd58df6d
HV
152#define IVTV_DEBUG_HIGH_VOL(x, type, fmt, args...) \
153 do { \
154 if (((x) & ivtv_debug) && (ivtv_debug & IVTV_DBGFLG_HIGHVOL)) \
155 printk(KERN_INFO "ivtv%d " type ": " fmt, itv->num , ## args); \
156 } while (0)
1aa32c2f
HV
157#define IVTV_DEBUG_HI_WARN(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_WARN, "warn", fmt , ## args)
158#define IVTV_DEBUG_HI_INFO(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_INFO, "info", fmt , ## args)
159#define IVTV_DEBUG_HI_MB(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_MB, "mb", fmt , ## args)
160#define IVTV_DEBUG_HI_DMA(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DMA, "dma", fmt , ## args)
bd58df6d 161#define IVTV_DEBUG_HI_IOCTL(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args)
1aa32c2f
HV
162#define IVTV_DEBUG_HI_FILE(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_FILE, "file", fmt , ## args)
163#define IVTV_DEBUG_HI_I2C(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_I2C, "i2c", fmt , ## args)
164#define IVTV_DEBUG_HI_IRQ(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IRQ, "irq", fmt , ## args)
165#define IVTV_DEBUG_HI_DEC(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DEC, "dec", fmt , ## args)
166#define IVTV_DEBUG_HI_YUV(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_YUV, "yuv", fmt , ## args)
bd58df6d 167
1a0adaf3
HV
168/* Standard kernel messages */
169#define IVTV_ERR(fmt, args...) printk(KERN_ERR "ivtv%d: " fmt, itv->num , ## args)
170#define IVTV_WARN(fmt, args...) printk(KERN_WARNING "ivtv%d: " fmt, itv->num , ## args)
171#define IVTV_INFO(fmt, args...) printk(KERN_INFO "ivtv%d: " fmt, itv->num , ## args)
1a0adaf3 172
1a0adaf3
HV
173/* output modes (cx23415 only) */
174#define OUT_NONE 0
175#define OUT_MPG 1
176#define OUT_YUV 2
177#define OUT_UDMA_YUV 3
178#define OUT_PASSTHROUGH 4
179
180#define IVTV_MAX_PGM_INDEX (400)
181
1a0adaf3 182struct ivtv_options {
a158f355
HV
183 int kilobytes[IVTV_MAX_STREAMS]; /* size in kilobytes of each stream */
184 int cardtype; /* force card type on load */
185 int tuner; /* set tuner on load */
186 int radio; /* enable/disable radio */
187 int newi2c; /* new I2C algorithm */
1a0adaf3
HV
188};
189
1a0adaf3
HV
190/* ivtv-specific mailbox template */
191struct ivtv_mailbox {
192 u32 flags;
193 u32 cmd;
194 u32 retval;
195 u32 timeout;
196 u32 data[CX2341X_MBOX_MAX_DATA];
197};
198
199struct ivtv_api_cache {
200 unsigned long last_jiffies; /* when last command was issued */
201 u32 data[CX2341X_MBOX_MAX_DATA]; /* last sent api data */
202};
203
204struct ivtv_mailbox_data {
205 volatile struct ivtv_mailbox __iomem *mbox;
206 /* Bits 0-2 are for the encoder mailboxes, 0-1 are for the decoder mailboxes.
207 If the bit is set, then the corresponding mailbox is in use by the driver. */
208 unsigned long busy;
209 u8 max_mbox;
210};
211
212/* per-buffer bit flags */
f4071b85 213#define IVTV_F_B_NEED_BUF_SWAP (1 << 0) /* this buffer should be byte swapped */
1a0adaf3
HV
214
215/* per-stream, s_flags */
216#define IVTV_F_S_DMA_PENDING 0 /* this stream has pending DMA */
217#define IVTV_F_S_DMA_HAS_VBI 1 /* the current DMA request also requests VBI data */
218#define IVTV_F_S_NEEDS_DATA 2 /* this decoding stream needs more data */
219
220#define IVTV_F_S_CLAIMED 3 /* this stream is claimed */
221#define IVTV_F_S_STREAMING 4 /* the fw is decoding/encoding this stream */
222#define IVTV_F_S_INTERNAL_USE 5 /* this stream is used internally (sliced VBI processing) */
223#define IVTV_F_S_PASSTHROUGH 6 /* this stream is in passthrough mode */
224#define IVTV_F_S_STREAMOFF 7 /* signal end of stream EOS */
225#define IVTV_F_S_APPL_IO 8 /* this stream is used read/written by an application */
226
dc02d50a
HV
227#define IVTV_F_S_PIO_PENDING 9 /* this stream has pending PIO */
228#define IVTV_F_S_PIO_HAS_VBI 1 /* the current PIO request also requests VBI data */
229
1a0adaf3 230/* per-ivtv, i_flags */
1e13f9e3
HV
231#define IVTV_F_I_DMA 0 /* DMA in progress */
232#define IVTV_F_I_UDMA 1 /* UDMA in progress */
233#define IVTV_F_I_UDMA_PENDING 2 /* UDMA pending */
a158f355
HV
234#define IVTV_F_I_SPEED_CHANGE 3 /* a speed change is in progress */
235#define IVTV_F_I_EOS 4 /* end of encoder stream reached */
236#define IVTV_F_I_RADIO_USER 5 /* the radio tuner is selected */
237#define IVTV_F_I_DIG_RST 6 /* reset digitizer */
1e13f9e3 238#define IVTV_F_I_DEC_YUV 7 /* YUV instead of MPG is being decoded */
1e13f9e3
HV
239#define IVTV_F_I_UPDATE_CC 9 /* CC should be updated */
240#define IVTV_F_I_UPDATE_WSS 10 /* WSS should be updated */
241#define IVTV_F_I_UPDATE_VPS 11 /* VPS should be updated */
242#define IVTV_F_I_DECODING_YUV 12 /* this stream is YUV frame decoding */
243#define IVTV_F_I_ENC_PAUSED 13 /* the encoder is paused */
1a0adaf3 244#define IVTV_F_I_VALID_DEC_TIMINGS 14 /* last_dec_timing is valid */
a158f355 245#define IVTV_F_I_HAVE_WORK 15 /* used in the interrupt handler: there is work to be done */
dc02d50a
HV
246#define IVTV_F_I_WORK_HANDLER_VBI 16 /* there is work to be done for VBI */
247#define IVTV_F_I_WORK_HANDLER_YUV 17 /* there is work to be done for YUV */
248#define IVTV_F_I_WORK_HANDLER_PIO 18 /* there is work to be done for PIO */
249#define IVTV_F_I_PIO 19 /* PIO in progress */
ac425144 250#define IVTV_F_I_DEC_PAUSED 20 /* the decoder is paused */
c976bc82
HV
251#define IVTV_F_I_INITED 21 /* set after first open */
252#define IVTV_F_I_FAILED 22 /* set if first open failed */
d526afe0 253#define IVTV_F_I_WORK_INITED 23 /* worker thread was initialized */
1a0adaf3
HV
254
255/* Event notifications */
1e13f9e3
HV
256#define IVTV_F_I_EV_DEC_STOPPED 28 /* decoder stopped event */
257#define IVTV_F_I_EV_VSYNC 29 /* VSYNC event */
258#define IVTV_F_I_EV_VSYNC_FIELD 30 /* VSYNC event field (0 = first, 1 = second field) */
259#define IVTV_F_I_EV_VSYNC_ENABLED 31 /* VSYNC event enabled */
1a0adaf3
HV
260
261/* Scatter-Gather array element, used in DMA transfers */
37093b1e 262struct ivtv_sg_element {
b0510f8d
AV
263 __le32 src;
264 __le32 dst;
265 __le32 size;
266};
267
268struct ivtv_sg_host_element {
1a0adaf3
HV
269 u32 src;
270 u32 dst;
271 u32 size;
272};
273
274struct ivtv_user_dma {
275 struct mutex lock;
276 int page_count;
277 struct page *map[IVTV_DMA_SG_OSD_ENT];
0989fd2c
HV
278 /* Needed when dealing with highmem userspace buffers */
279 struct page *bouncemap[IVTV_DMA_SG_OSD_ENT];
1a0adaf3
HV
280
281 /* Base Dev SG Array for cx23415/6 */
37093b1e 282 struct ivtv_sg_element SGarray[IVTV_DMA_SG_OSD_ENT];
1a0adaf3
HV
283 dma_addr_t SG_handle;
284 int SG_length;
285
286 /* SG List of Buffers */
287 struct scatterlist SGlist[IVTV_DMA_SG_OSD_ENT];
288};
289
290struct ivtv_dma_page_info {
291 unsigned long uaddr;
292 unsigned long first;
293 unsigned long last;
294 unsigned int offset;
295 unsigned int tail;
296 int page_count;
297};
298
299struct ivtv_buffer {
300 struct list_head list;
301 dma_addr_t dma_handle;
f4071b85
HV
302 unsigned short b_flags;
303 unsigned short dma_xfer_cnt;
1a0adaf3 304 char *buf;
1a0adaf3
HV
305 u32 bytesused;
306 u32 readpos;
307};
308
309struct ivtv_queue {
a158f355
HV
310 struct list_head list; /* the list of buffers in this queue */
311 u32 buffers; /* number of buffers in this queue */
312 u32 length; /* total number of bytes of available buffer space */
313 u32 bytesused; /* total number of bytes used in this queue */
1a0adaf3
HV
314};
315
a158f355 316struct ivtv; /* forward reference */
1a0adaf3
HV
317
318struct ivtv_stream {
319 /* These first four fields are always set, even if the stream
320 is not actually created. */
321 struct video_device *v4l2dev; /* NULL when stream not created */
322 struct ivtv *itv; /* for ease of use */
323 const char *name; /* name of the stream */
324 int type; /* stream type */
325
326 u32 id;
a158f355
HV
327 spinlock_t qlock; /* locks access to the queues */
328 unsigned long s_flags; /* status flags, see above */
329 int dma; /* can be PCI_DMA_TODEVICE, PCI_DMA_FROMDEVICE or PCI_DMA_NONE */
37093b1e
HV
330 u32 pending_offset;
331 u32 pending_backup;
332 u64 pending_pts;
333
1a0adaf3
HV
334 u32 dma_offset;
335 u32 dma_backup;
336 u64 dma_pts;
337
338 int subtype;
339 wait_queue_head_t waitq;
340 u32 dma_last_offset;
341
342 /* Buffer Stats */
343 u32 buffers;
344 u32 buf_size;
345 u32 buffers_stolen;
346
347 /* Buffer Queues */
348 struct ivtv_queue q_free; /* free buffers */
349 struct ivtv_queue q_full; /* full buffers */
350 struct ivtv_queue q_io; /* waiting for I/O */
351 struct ivtv_queue q_dma; /* waiting for DMA */
352 struct ivtv_queue q_predma; /* waiting for DMA */
353
f4071b85
HV
354 /* DMA xfer counter, buffers belonging to the same DMA
355 xfer will have the same dma_xfer_cnt. */
356 u16 dma_xfer_cnt;
357
1a0adaf3 358 /* Base Dev SG Array for cx23415/6 */
b0510f8d
AV
359 struct ivtv_sg_host_element *sg_pending;
360 struct ivtv_sg_host_element *sg_processing;
37093b1e
HV
361 struct ivtv_sg_element *sg_dma;
362 dma_addr_t sg_handle;
363 int sg_pending_size;
364 int sg_processing_size;
365 int sg_processed;
1a0adaf3
HV
366
367 /* SG List of Buffers */
368 struct scatterlist *SGlist;
369};
370
371struct ivtv_open_id {
a158f355
HV
372 u32 open_id; /* unique ID for this file descriptor */
373 int type; /* stream type */
374 int yuv_frames; /* 1: started OUT_UDMA_YUV output mode */
375 enum v4l2_priority prio; /* priority */
1a0adaf3
HV
376 struct ivtv *itv;
377};
378
1a0adaf3
HV
379struct yuv_frame_info
380{
381 u32 update;
33c0fcad
HV
382 s32 src_x;
383 s32 src_y;
384 u32 src_w;
385 u32 src_h;
386 s32 dst_x;
387 s32 dst_y;
388 u32 dst_w;
389 u32 dst_h;
390 s32 pan_x;
391 s32 pan_y;
1a0adaf3
HV
392 u32 vis_w;
393 u32 vis_h;
394 u32 interlaced_y;
395 u32 interlaced_uv;
33c0fcad 396 s32 tru_x;
1a0adaf3
HV
397 u32 tru_w;
398 u32 tru_h;
399 u32 offset_y;
33c0fcad 400 s32 lace_mode;
3b5c1c8e
IA
401 u32 sync_field;
402 u32 delay;
403 u32 interlaced;
1a0adaf3
HV
404};
405
406#define IVTV_YUV_MODE_INTERLACED 0x00
407#define IVTV_YUV_MODE_PROGRESSIVE 0x01
408#define IVTV_YUV_MODE_AUTO 0x02
409#define IVTV_YUV_MODE_MASK 0x03
410
411#define IVTV_YUV_SYNC_EVEN 0x00
412#define IVTV_YUV_SYNC_ODD 0x04
413#define IVTV_YUV_SYNC_MASK 0x04
414
a3e5f5e2
IA
415#define IVTV_YUV_BUFFERS 8
416
1a0adaf3
HV
417struct yuv_playback_info
418{
419 u32 reg_2834;
420 u32 reg_2838;
421 u32 reg_283c;
422 u32 reg_2840;
423 u32 reg_2844;
424 u32 reg_2848;
425 u32 reg_2854;
426 u32 reg_285c;
427 u32 reg_2864;
428
429 u32 reg_2870;
430 u32 reg_2874;
431 u32 reg_2890;
432 u32 reg_2898;
433 u32 reg_289c;
434
435 u32 reg_2918;
436 u32 reg_291c;
437 u32 reg_2920;
438 u32 reg_2924;
439 u32 reg_2928;
440 u32 reg_292c;
441 u32 reg_2930;
442
443 u32 reg_2934;
444
445 u32 reg_2938;
446 u32 reg_293c;
447 u32 reg_2940;
448 u32 reg_2944;
449 u32 reg_2948;
450 u32 reg_294c;
451 u32 reg_2950;
452 u32 reg_2954;
453 u32 reg_2958;
454 u32 reg_295c;
455 u32 reg_2960;
456 u32 reg_2964;
457 u32 reg_2968;
458 u32 reg_296c;
459
460 u32 reg_2970;
461
462 int v_filter_1;
463 int v_filter_2;
464 int h_filter;
465
88ab075a
IA
466 u8 track_osd; /* Should yuv output track the OSD size & position */
467
1a0adaf3
HV
468 u32 osd_x_offset;
469 u32 osd_y_offset;
470
471 u32 osd_x_pan;
472 u32 osd_y_pan;
473
474 u32 osd_vis_w;
475 u32 osd_vis_h;
476
77aded6b
IA
477 u32 osd_full_w;
478 u32 osd_full_h;
479
1a0adaf3
HV
480 int decode_height;
481
1a0adaf3
HV
482 int lace_mode;
483 int lace_threshold;
1a0adaf3
HV
484 int lace_sync_field;
485
486 atomic_t next_dma_frame;
487 atomic_t next_fill_frame;
488
489 u32 yuv_forced_update;
490 int update_frame;
bfd7beac 491
bfd7beac
IA
492 u8 fields_lapsed; /* Counter used when delaying a frame */
493
a3e5f5e2 494 struct yuv_frame_info new_frame_info[IVTV_YUV_BUFFERS];
1a0adaf3
HV
495 struct yuv_frame_info old_frame_info;
496 struct yuv_frame_info old_frame_info_args;
497
498 void *blanking_ptr;
499 dma_addr_t blanking_dmaptr;
c240ad00
IA
500
501 int stream_size;
a3e5f5e2
IA
502
503 u8 draw_frame; /* PVR350 buffer to draw into */
504 u8 max_frames_buffered; /* Maximum number of frames to buffer */
77aded6b
IA
505
506 struct v4l2_rect main_rect;
507 u32 v4l2_src_w;
508 u32 v4l2_src_h;
2bd7ac55
IA
509
510 u8 running; /* Have any frames been displayed */
1a0adaf3
HV
511};
512
513#define IVTV_VBI_FRAMES 32
514
515/* VBI data */
2f3a9893
HV
516struct vbi_cc {
517 u8 odd[2]; /* two-byte payload of odd field */
518 u8 even[2]; /* two-byte payload of even field */;
519};
520
521struct vbi_vps {
522 u8 data[5]; /* five-byte VPS payload */
523};
524
1a0adaf3 525struct vbi_info {
effa0b08
HV
526 /* VBI general data, does not change during streaming */
527
a158f355
HV
528 u32 raw_decoder_line_size; /* raw VBI line size from digitizer */
529 u8 raw_decoder_sav_odd_field; /* raw VBI Start Active Video digitizer code of odd field */
530 u8 raw_decoder_sav_even_field; /* raw VBI Start Active Video digitizer code of even field */
531 u32 sliced_decoder_line_size; /* sliced VBI line size from digitizer */
532 u8 sliced_decoder_sav_odd_field; /* sliced VBI Start Active Video digitizer code of odd field */
533 u8 sliced_decoder_sav_even_field; /* sliced VBI Start Active Video digitizer code of even field */
534
effa0b08
HV
535 u32 start[2]; /* start of first VBI line in the odd/even fields */
536 u32 count; /* number of VBI lines per field */
537 u32 raw_size; /* size of raw VBI line from the digitizer */
538 u32 sliced_size; /* size of sliced VBI line from the digitizer */
539
540 u32 dec_start; /* start in decoder memory of VBI re-insertion buffers */
541 u32 enc_start; /* start in encoder memory of VBI capture buffers */
542 u32 enc_size; /* size of VBI capture area */
543 int fpi; /* number of VBI frames per interrupt */
544
545 struct v4l2_format in; /* current VBI capture format */
546 struct v4l2_sliced_vbi_format *sliced_in; /* convenience pointer to sliced struct in vbi.in union */
547 int insert_mpeg; /* if non-zero, then embed VBI data in MPEG stream */
548
549 /* Raw VBI compatibility hack */
550
551 u32 frame; /* frame counter hack needed for backwards compatibility
552 of old VBI software */
553
554 /* Sliced VBI output data */
555
556 struct vbi_cc cc_payload[256]; /* sliced VBI CC payload array: it is an array to
2f3a9893 557 prevent dropping CC data if they couldn't be
effa0b08
HV
558 processed fast enough */
559 int cc_payload_idx; /* index in cc_payload */
560 u8 cc_missing_cnt; /* counts number of frames without CC for passthrough mode */
561 int wss_payload; /* sliced VBI WSS payload */
562 u8 wss_missing_cnt; /* counts number of frames without WSS for passthrough mode */
563 struct vbi_vps vps_payload; /* sliced VBI VPS payload */
564
565 /* Sliced VBI capture data */
566
567 struct v4l2_sliced_vbi_data sliced_data[36]; /* sliced VBI storage for VBI encoder stream */
568 struct v4l2_sliced_vbi_data sliced_dec_data[36];/* sliced VBI storage for VBI decoder stream */
569
570 /* VBI Embedding data */
1a0adaf3
HV
571
572 /* Buffer for VBI data inserted into MPEG stream.
573 The first byte is a dummy byte that's never used.
574 The next 16 bytes contain the MPEG header for the VBI data,
575 the remainder is the actual VBI data.
576 The max size accepted by the MPEG VBI reinsertion turns out
577 to be 1552 bytes, which happens to be 4 + (1 + 42) * (2 * 18) bytes,
578 where 4 is a four byte header, 42 is the max sliced VBI payload, 1 is
579 a single line header byte and 2 * 18 is the number of VBI lines per frame.
580
581 However, it seems that the data must be 1K aligned, so we have to
582 pad the data until the 1 or 2 K boundary.
583
584 This pointer array will allocate 2049 bytes to store each VBI frame. */
585 u8 *sliced_mpeg_data[IVTV_VBI_FRAMES];
586 u32 sliced_mpeg_size[IVTV_VBI_FRAMES];
effa0b08
HV
587 struct ivtv_buffer sliced_mpeg_buf; /* temporary buffer holding data from sliced_mpeg_data */
588 u32 inserted_frame; /* index in sliced_mpeg_size of next sliced data
589 to be inserted in the MPEG stream */
1a0adaf3
HV
590};
591
592/* forward declaration of struct defined in ivtv-cards.h */
593struct ivtv_card;
594
595/* Struct to hold info about ivtv cards */
596struct ivtv {
fd8b281a
HV
597 /* General fixed card data */
598 int num; /* board number, -1 during init! */
599 char name[8]; /* board name for printk and interrupts (e.g. 'ivtv0') */
600 struct pci_dev *dev; /* PCI device */
1a0adaf3 601 const struct ivtv_card *card; /* card information */
fd8b281a 602 const char *card_name; /* full name of the card */
d9009201 603 const struct ivtv_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */
fd8b281a
HV
604 u8 has_cx23415; /* 1 if it is a cx23415 based card, 0 for cx23416 */
605 u8 pvr150_workaround; /* 1 if the cx25840 needs to workaround a PVR150 bug */
606 u8 nof_inputs; /* number of video inputs */
607 u8 nof_audio_inputs; /* number of audio inputs */
608 u32 v4l2_cap; /* V4L2 capabilities of card */
609 u32 hw_flags; /* hardware description of the board */
fd8b281a
HV
610 v4l2_std_id tuner_std; /* the norm of the card's tuner (fixed) */
611 /* controlling video decoder function */
1a0adaf3 612 int (*video_dec_func)(struct ivtv *, unsigned int, void *);
fd8b281a
HV
613 u32 base_addr; /* PCI resource base address */
614 volatile void __iomem *enc_mem; /* pointer to mapped encoder memory */
615 volatile void __iomem *dec_mem; /* pointer to mapped decoder memory */
616 volatile void __iomem *reg_mem; /* pointer to mapped registers */
617 struct ivtv_options options; /* user options */
618
619
620 /* High-level state info */
621 unsigned long i_flags; /* global ivtv flags */
622 u8 is_50hz; /* 1 if the current capture standard is 50 Hz */
623 u8 is_60hz /* 1 if the current capture standard is 60 Hz */;
624 u8 is_out_50hz /* 1 if the current TV output standard is 50 Hz */;
625 u8 is_out_60hz /* 1 if the current TV output standard is 60 Hz */;
626 int output_mode; /* decoder output mode: NONE, MPG, YUV, UDMA YUV, passthrough */
627 u32 audio_input; /* current audio input */
628 u32 active_input; /* current video input */
629 u32 active_output; /* current video output */
630 v4l2_std_id std; /* current capture TV standard */
631 v4l2_std_id std_out; /* current TV output standard */
632 u8 audio_stereo_mode; /* decoder setting how to handle stereo MPEG audio */
633 u8 audio_bilingual_mode; /* decoder setting how to handle bilingual MPEG audio */
634 struct cx2341x_mpeg_params params; /* current encoder parameters */
635
636
637 /* Locking */
638 spinlock_t lock; /* lock access to this struct */
a158f355 639 struct mutex serialize_lock; /* mutex used to serialize open/close/start/stop/ioctl operations */
fd8b281a 640
fd8b281a
HV
641 /* Streams */
642 int stream_buf_size[IVTV_MAX_STREAMS]; /* stream buffer size */
643 struct ivtv_stream streams[IVTV_MAX_STREAMS]; /* stream data */
644 atomic_t capturing; /* count number of active capture streams */
645 atomic_t decoding; /* count number of active decoding streams */
646
647
648 /* Interrupts & DMA */
649 u32 irqmask; /* active interrupts */
650 u32 irq_rr_idx; /* round-robin stream index */
651 struct workqueue_struct *irq_work_queues; /* workqueue for PIO/YUV/VBI actions */
652 struct work_struct irq_work_queue; /* work entry */
653 spinlock_t dma_reg_lock; /* lock access to DMA engine registers */
654 int cur_dma_stream; /* index of current stream doing DMA (-1 if none) */
655 int cur_pio_stream; /* index of current stream doing PIO (-1 if none) */
656 u32 dma_data_req_offset; /* store offset in decoder memory of current DMA request */
657 u32 dma_data_req_size; /* store size of current DMA request */
658 int dma_retries; /* current DMA retry attempt */
659 struct ivtv_user_dma udma; /* user based DMA for OSD */
660 struct timer_list dma_timer; /* timer used to catch unfinished DMAs */
a158f355 661 u32 last_vsync_field; /* last seen vsync field */
fd8b281a
HV
662 wait_queue_head_t dma_waitq; /* wake up when the current DMA is finished */
663 wait_queue_head_t eos_waitq; /* wake up when EOS arrives */
664 wait_queue_head_t event_waitq; /* wake up when the next decoder event arrives */
665 wait_queue_head_t vsync_waitq; /* wake up when the next decoder vsync arrives */
666
667
668 /* Mailbox */
669 struct ivtv_mailbox_data enc_mbox; /* encoder mailboxes */
670 struct ivtv_mailbox_data dec_mbox; /* decoder mailboxes */
671 struct ivtv_api_cache api_cache[256]; /* cached API commands */
672
673
674 /* I2C */
675 struct i2c_adapter i2c_adap;
676 struct i2c_algo_bit_data i2c_algo;
677 struct i2c_client i2c_client;
678 struct i2c_client *i2c_clients[I2C_CLIENTS_MAX];/* pointers to all I2C clients */
679 int i2c_state; /* i2c bit state */
680 struct mutex i2c_bus_lock; /* lock i2c bus */
681
682
683 /* Program Index information */
684 u32 pgm_info_offset; /* start of pgm info in encoder memory */
685 u32 pgm_info_num; /* number of elements in the pgm cyclic buffer in encoder memory */
686 u32 pgm_info_write_idx; /* last index written by the card that was transferred to pgm_info[] */
687 u32 pgm_info_read_idx; /* last index in pgm_info read by the application */
688 struct v4l2_enc_idx_entry pgm_info[IVTV_MAX_PGM_INDEX]; /* filled from the pgm cyclic buffer on the card */
689
690
691 /* Miscellaneous */
692 u32 open_id; /* incremented each time an open occurs, is >= 1 */
693 struct v4l2_prio_state prio; /* priority state */
694 int search_pack_header; /* 1 if ivtv_copy_buf_to_user() is scanning for a pack header (0xba) */
695 int speed; /* current playback speed setting */
696 u8 speed_mute_audio; /* 1 if audio should be muted when fast forward */
697 u64 mpg_data_received; /* number of bytes received from the MPEG stream */
698 u64 vbi_data_inserted; /* number of VBI bytes inserted into the MPEG stream */
699 u32 last_dec_timing[3]; /* cache last retrieved pts/scr/frame values */
700 unsigned long dualwatch_jiffies;/* jiffies value of the previous dualwatch check */
701 u16 dualwatch_stereo_mode; /* current detected dualwatch stereo mode */
702
703
704 /* VBI state info */
705 struct vbi_info vbi; /* VBI-specific data */
706
707
708 /* YUV playback */
709 struct yuv_playback_info yuv_info; /* YUV playback data */
1a0adaf3 710
1a0adaf3
HV
711
712 /* OSD support */
713 unsigned long osd_video_pbase;
fd8b281a
HV
714 int osd_global_alpha_state; /* 1 = global alpha is on */
715 int osd_local_alpha_state; /* 1 = local alpha is on */
716 int osd_chroma_key_state; /* 1 = chroma-keying is on */
717 u8 osd_global_alpha; /* current global alpha */
718 u32 osd_chroma_key; /* current chroma key */
fd8b281a
HV
719 struct v4l2_rect osd_rect; /* current OSD position and size */
720 struct v4l2_rect main_rect; /* current Main window position and size */
7b3a0d49 721 struct osd_info *osd_info; /* ivtvfb private OSD info */
1a0adaf3
HV
722};
723
724/* Globals */
725extern struct ivtv *ivtv_cards[];
726extern int ivtv_cards_active;
727extern int ivtv_first_minor;
728extern spinlock_t ivtv_cards_lock;
729
730/*==============Prototypes==================*/
731
732/* Hardware/IRQ */
733void ivtv_set_irq_mask(struct ivtv *itv, u32 mask);
734void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask);
735
736/* try to set output mode, return current mode. */
737int ivtv_set_output_mode(struct ivtv *itv, int mode);
738
739/* return current output stream based on current mode */
740struct ivtv_stream *ivtv_get_output_stream(struct ivtv *itv);
741
742/* Return non-zero if a signal is pending */
201700d3 743int ivtv_msleep_timeout(unsigned int msecs, int intr);
1a0adaf3
HV
744
745/* Wait on queue, returns -EINTR if interrupted */
746int ivtv_waitq(wait_queue_head_t *waitq);
747
748/* Read Hauppauge eeprom */
749struct tveeprom; /* forward reference */
750void ivtv_read_eeprom(struct ivtv *itv, struct tveeprom *tv);
751
c976bc82
HV
752/* First-open initialization: load firmware, init cx25840, etc. */
753int ivtv_init_on_first_open(struct ivtv *itv);
754
a8b86435
HV
755/* Test if the current VBI mode is raw (1) or sliced (0) */
756static inline int ivtv_raw_vbi(const struct ivtv *itv)
757{
758 return itv->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE;
759}
760
1a0adaf3
HV
761/* This is a PCI post thing, where if the pci register is not read, then
762 the write doesn't always take effect right away. By reading back the
763 register any pending PCI writes will be performed (in order), and so
764 you can be sure that the writes are guaranteed to be done.
765
766 Rarely needed, only in some timing sensitive cases.
767 Apparently if this is not done some motherboards seem
768 to kill the firmware and get into the broken state until computer is
769 rebooted. */
770#define write_sync(val, reg) \
771 do { writel(val, reg); readl(reg); } while (0)
772
773#define read_reg(reg) readl(itv->reg_mem + (reg))
774#define write_reg(val, reg) writel(val, itv->reg_mem + (reg))
775#define write_reg_sync(val, reg) \
776 do { write_reg(val, reg); read_reg(reg); } while (0)
777
778#define read_enc(addr) readl(itv->enc_mem + (u32)(addr))
779#define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr))
780#define write_enc_sync(val, addr) \
781 do { write_enc(val, addr); read_enc(addr); } while (0)
782
783#define read_dec(addr) readl(itv->dec_mem + (u32)(addr))
784#define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr))
785#define write_dec_sync(val, addr) \
786 do { write_dec(val, addr); read_dec(addr); } while (0)
787
612570f2 788#endif
This page took 0.262455 seconds and 5 git commands to generate.