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1a0adaf3 HV |
1 | /* |
2 | ivtv driver internal defines and structures | |
3 | Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com> | |
4 | Copyright (C) 2004 Chris Kennedy <c@groovy.org> | |
5 | Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef IVTV_DRIVER_H | |
23 | #define IVTV_DRIVER_H | |
24 | ||
25 | /* Internal header for ivtv project: | |
26 | * Driver for the cx23415/6 chip. | |
27 | * Author: Kevin Thayer (nufan_wfk at yahoo.com) | |
28 | * License: GPL | |
29 | * http://www.ivtvdriver.org | |
30 | * | |
31 | * ----- | |
32 | * MPG600/MPG160 support by T.Adachi <tadachi@tadachi-net.com> | |
33 | * and Takeru KOMORIYA<komoriya@paken.org> | |
34 | * | |
35 | * AVerMedia M179 GPIO info by Chris Pinkham <cpinkham@bc2va.org> | |
36 | * using information provided by Jiun-Kuei Jung @ AVerMedia. | |
37 | */ | |
38 | ||
39 | #include <linux/version.h> | |
40 | #include <linux/module.h> | |
1a0adaf3 HV |
41 | #include <linux/init.h> |
42 | #include <linux/delay.h> | |
43 | #include <linux/sched.h> | |
44 | #include <linux/fs.h> | |
45 | #include <linux/pci.h> | |
46 | #include <linux/interrupt.h> | |
47 | #include <linux/spinlock.h> | |
48 | #include <linux/i2c.h> | |
49 | #include <linux/i2c-algo-bit.h> | |
50 | #include <linux/list.h> | |
51 | #include <linux/unistd.h> | |
52 | #include <linux/byteorder/swab.h> | |
53 | #include <linux/pagemap.h> | |
54 | #include <linux/workqueue.h> | |
55 | #include <linux/mutex.h> | |
56 | #include <asm/uaccess.h> | |
57 | #include <asm/system.h> | |
58 | ||
59 | #include <linux/dvb/video.h> | |
60 | #include <linux/dvb/audio.h> | |
61 | #include <media/v4l2-common.h> | |
62 | #include <media/tuner.h> | |
63 | #include <media/cx2341x.h> | |
64 | ||
1a0adaf3 HV |
65 | #include <media/ivtv.h> |
66 | ||
37297805 | 67 | |
1a0adaf3 HV |
68 | #define IVTV_ENCODER_OFFSET 0x00000000 |
69 | #define IVTV_ENCODER_SIZE 0x00800000 /* Last half isn't needed 0x01000000 */ | |
70 | ||
71 | #define IVTV_DECODER_OFFSET 0x01000000 | |
72 | #define IVTV_DECODER_SIZE 0x00800000 /* Last half isn't needed 0x01000000 */ | |
73 | ||
74 | #define IVTV_REG_OFFSET 0x02000000 | |
75 | #define IVTV_REG_SIZE 0x00010000 | |
76 | ||
77 | /* Buffers on hardware offsets */ | |
78 | #define IVTV_YUV_BUFFER_OFFSET 0x001a8600 /* First YUV Buffer */ | |
79 | #define IVTV_YUV_BUFFER_OFFSET_1 0x00240400 /* Second YUV Buffer */ | |
80 | #define IVTV_YUV_BUFFER_OFFSET_2 0x002d8200 /* Third YUV Buffer */ | |
81 | #define IVTV_YUV_BUFFER_OFFSET_3 0x00370000 /* Fourth YUV Buffer */ | |
82 | #define IVTV_YUV_BUFFER_UV_OFFSET 0x65400 /* Offset to UV Buffer */ | |
83 | ||
84 | /* Offset to filter table in firmware */ | |
85 | #define IVTV_YUV_HORIZONTAL_FILTER_OFFSET 0x025d8 | |
86 | #define IVTV_YUV_VERTICAL_FILTER_OFFSET 0x03358 | |
87 | ||
88 | extern const u32 yuv_offset[4]; | |
89 | ||
32db7754 HV |
90 | /* Maximum ivtv driver instances. Some people have a huge number of |
91 | capture cards, so set this to a high value. */ | |
92 | #define IVTV_MAX_CARDS 32 | |
1a0adaf3 HV |
93 | |
94 | /* Supported cards */ | |
95 | #define IVTV_CARD_PVR_250 0 /* WinTV PVR 250 */ | |
96 | #define IVTV_CARD_PVR_350 1 /* encoder, decoder, tv-out */ | |
97 | #define IVTV_CARD_PVR_150 2 /* WinTV PVR 150 and PVR 500 (really just two | |
98 | PVR150s on one PCI board) */ | |
99 | #define IVTV_CARD_M179 3 /* AVerMedia M179 (encoder only) */ | |
100 | #define IVTV_CARD_MPG600 4 /* Kuroutoshikou ITVC16-STVLP/YUAN MPG600, encoder only */ | |
101 | #define IVTV_CARD_MPG160 5 /* Kuroutoshikou ITVC15-STVLP/YUAN MPG160 | |
102 | cx23415 based, but does not have tv-out */ | |
103 | #define IVTV_CARD_PG600 6 /* YUAN PG600/DIAMONDMM PVR-550 based on the CX Falcon 2 */ | |
104 | #define IVTV_CARD_AVC2410 7 /* Adaptec AVC-2410 */ | |
105 | #define IVTV_CARD_AVC2010 8 /* Adaptec AVD-2010 (No Tuner) */ | |
106 | #define IVTV_CARD_TG5000TV 9 /* NAGASE TRANSGEAR 5000TV, encoder only */ | |
107 | #define IVTV_CARD_VA2000MAX_SNT6 10 /* VA2000MAX-STN6 */ | |
108 | #define IVTV_CARD_CX23416GYC 11 /* Kuroutoshikou CX23416GYC-STVLP (Yuan MPG600GR OEM) */ | |
109 | #define IVTV_CARD_GV_MVPRX 12 /* I/O Data GV-MVP/RX, RX2, RX2W */ | |
110 | #define IVTV_CARD_GV_MVPRX2E 13 /* I/O Data GV-MVP/RX2E */ | |
111 | #define IVTV_CARD_GOTVIEW_PCI_DVD 14 /* GotView PCI DVD */ | |
112 | #define IVTV_CARD_GOTVIEW_PCI_DVD2 15 /* GotView PCI DVD2 */ | |
113 | #define IVTV_CARD_YUAN_MPC622 16 /* Yuan MPC622 miniPCI */ | |
114 | #define IVTV_CARD_DCTMTVP1 17 /* DIGITAL COWBOY DCT-MTVP1 */ | |
37297805 HV |
115 | #define IVTV_CARD_PG600V2 18 /* Yuan PG600V2/GotView PCI DVD Lite */ |
116 | #define IVTV_CARD_CLUB3D 19 /* Club3D ZAP-TV1x01 */ | |
117 | #define IVTV_CARD_AVERTV_MCE116 20 /* AVerTV MCE 116 Plus */ | |
118 | #define IVTV_CARD_LAST 20 | |
1a0adaf3 HV |
119 | |
120 | /* Variants of existing cards but with the same PCI IDs. The driver | |
121 | detects these based on other device information. | |
122 | These cards must always come last. | |
123 | New cards must be inserted above, and the indices of the cards below | |
124 | must be adjusted accordingly. */ | |
125 | ||
126 | /* PVR-350 V1 (uses saa7114) */ | |
127 | #define IVTV_CARD_PVR_350_V1 (IVTV_CARD_LAST+1) | |
128 | /* 2 variants of Kuroutoshikou CX23416GYC-STVLP (Yuan MPG600GR OEM) */ | |
129 | #define IVTV_CARD_CX23416GYC_NOGR (IVTV_CARD_LAST+2) | |
130 | #define IVTV_CARD_CX23416GYC_NOGRYCS (IVTV_CARD_LAST+3) | |
131 | ||
132 | #define IVTV_ENC_STREAM_TYPE_MPG 0 | |
133 | #define IVTV_ENC_STREAM_TYPE_YUV 1 | |
134 | #define IVTV_ENC_STREAM_TYPE_VBI 2 | |
135 | #define IVTV_ENC_STREAM_TYPE_PCM 3 | |
136 | #define IVTV_ENC_STREAM_TYPE_RAD 4 | |
137 | #define IVTV_DEC_STREAM_TYPE_MPG 5 | |
138 | #define IVTV_DEC_STREAM_TYPE_VBI 6 | |
139 | #define IVTV_DEC_STREAM_TYPE_VOUT 7 | |
140 | #define IVTV_DEC_STREAM_TYPE_YUV 8 | |
141 | #define IVTV_MAX_STREAMS 9 | |
142 | ||
143 | #define IVTV_V4L2_DEC_MPG_OFFSET 16 /* offset from 0 to register decoder mpg v4l2 minors on */ | |
144 | #define IVTV_V4L2_ENC_PCM_OFFSET 24 /* offset from 0 to register pcm v4l2 minors on */ | |
145 | #define IVTV_V4L2_ENC_YUV_OFFSET 32 /* offset from 0 to register yuv v4l2 minors on */ | |
146 | #define IVTV_V4L2_DEC_YUV_OFFSET 48 /* offset from 0 to register decoder yuv v4l2 minors on */ | |
147 | #define IVTV_V4L2_DEC_VBI_OFFSET 8 /* offset from 0 to register decoder vbi input v4l2 minors on */ | |
148 | #define IVTV_V4L2_DEC_VOUT_OFFSET 16 /* offset from 0 to register vbi output v4l2 minors on */ | |
149 | ||
150 | #define IVTV_ENC_MEM_START 0x00000000 | |
151 | #define IVTV_DEC_MEM_START 0x01000000 | |
152 | ||
153 | /* system vendor and device IDs */ | |
154 | #define PCI_VENDOR_ID_ICOMP 0x4444 | |
155 | #define PCI_DEVICE_ID_IVTV15 0x0803 | |
156 | #define PCI_DEVICE_ID_IVTV16 0x0016 | |
157 | ||
158 | /* subsystem vendor ID */ | |
159 | #define IVTV_PCI_ID_HAUPPAUGE 0x0070 | |
160 | #define IVTV_PCI_ID_HAUPPAUGE_ALT1 0x0270 | |
161 | #define IVTV_PCI_ID_HAUPPAUGE_ALT2 0x4070 | |
162 | #define IVTV_PCI_ID_ADAPTEC 0x9005 | |
163 | #define IVTV_PCI_ID_AVERMEDIA 0x1461 | |
164 | #define IVTV_PCI_ID_YUAN1 0x12ab | |
165 | #define IVTV_PCI_ID_YUAN2 0xff01 | |
166 | #define IVTV_PCI_ID_YUAN3 0xffab | |
167 | #define IVTV_PCI_ID_YUAN4 0xfbab | |
168 | #define IVTV_PCI_ID_DIAMONDMM 0xff92 | |
169 | #define IVTV_PCI_ID_IODATA 0x10fc | |
170 | #define IVTV_PCI_ID_MELCO 0x1154 | |
171 | #define IVTV_PCI_ID_GOTVIEW1 0xffac | |
172 | #define IVTV_PCI_ID_GOTVIEW2 0xffad | |
173 | ||
174 | /* Decoder Buffer hardware size on Chip */ | |
175 | #define IVTV_DEC_MAX_BUF 0x00100000 /* max bytes in decoder buffer */ | |
176 | #define IVTV_DEC_MIN_BUF 0x00010000 /* min bytes in dec buffer */ | |
177 | ||
178 | /* ======================================================================== */ | |
179 | /* ========================== START USER SETTABLE DMA VARIABLES =========== */ | |
180 | /* ======================================================================== */ | |
181 | ||
182 | #define IVTV_DMA_SG_OSD_ENT (2883584/PAGE_SIZE) /* sg entities */ | |
183 | ||
184 | /* DMA Buffers, Default size in MB allocated */ | |
185 | #define IVTV_DEFAULT_ENC_MPG_BUFFERS 4 | |
186 | #define IVTV_DEFAULT_ENC_YUV_BUFFERS 2 | |
187 | #define IVTV_DEFAULT_ENC_VBI_BUFFERS 1 | |
313e91e8 HV |
188 | /* Exception: size in kB for this stream (MB is overkill) */ |
189 | #define IVTV_DEFAULT_ENC_PCM_BUFFERS 320 | |
1a0adaf3 HV |
190 | #define IVTV_DEFAULT_DEC_MPG_BUFFERS 1 |
191 | #define IVTV_DEFAULT_DEC_YUV_BUFFERS 1 | |
313e91e8 HV |
192 | /* Exception: size in kB for this stream (MB is way overkill) */ |
193 | #define IVTV_DEFAULT_DEC_VBI_BUFFERS 64 | |
1a0adaf3 HV |
194 | |
195 | /* ======================================================================== */ | |
196 | /* ========================== END USER SETTABLE DMA VARIABLES ============= */ | |
197 | /* ======================================================================== */ | |
198 | ||
199 | /* Decoder Status Register */ | |
200 | #define IVTV_DMA_ERR_LIST 0x00000010 | |
201 | #define IVTV_DMA_ERR_WRITE 0x00000008 | |
202 | #define IVTV_DMA_ERR_READ 0x00000004 | |
203 | #define IVTV_DMA_SUCCESS_WRITE 0x00000002 | |
204 | #define IVTV_DMA_SUCCESS_READ 0x00000001 | |
205 | #define IVTV_DMA_READ_ERR (IVTV_DMA_ERR_LIST | IVTV_DMA_ERR_READ) | |
206 | #define IVTV_DMA_WRITE_ERR (IVTV_DMA_ERR_LIST | IVTV_DMA_ERR_WRITE) | |
207 | #define IVTV_DMA_ERR (IVTV_DMA_ERR_LIST | IVTV_DMA_ERR_WRITE | IVTV_DMA_ERR_READ) | |
208 | ||
209 | /* DMA Registers */ | |
210 | #define IVTV_REG_DMAXFER (0x0000) | |
211 | #define IVTV_REG_DMASTATUS (0x0004) | |
212 | #define IVTV_REG_DECDMAADDR (0x0008) | |
213 | #define IVTV_REG_ENCDMAADDR (0x000c) | |
214 | #define IVTV_REG_DMACONTROL (0x0010) | |
215 | #define IVTV_REG_IRQSTATUS (0x0040) | |
216 | #define IVTV_REG_IRQMASK (0x0048) | |
217 | ||
218 | /* Setup Registers */ | |
219 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) | |
220 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) | |
221 | #define IVTV_REG_DEC_SDRAM_REFRESH (0x08F8) | |
222 | #define IVTV_REG_DEC_SDRAM_PRECHARGE (0x08FC) | |
223 | #define IVTV_REG_VDM (0x2800) | |
224 | #define IVTV_REG_AO (0x2D00) | |
225 | #define IVTV_REG_BYTEFLUSH (0x2D24) | |
226 | #define IVTV_REG_SPU (0x9050) | |
227 | #define IVTV_REG_HW_BLOCKS (0x9054) | |
228 | #define IVTV_REG_VPU (0x9058) | |
229 | #define IVTV_REG_APU (0xA064) | |
230 | ||
231 | #define IVTV_IRQ_ENC_START_CAP (0x1 << 31) | |
232 | #define IVTV_IRQ_ENC_EOS (0x1 << 30) | |
233 | #define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) | |
234 | #define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) | |
235 | #define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) | |
dc02d50a | 236 | #define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) |
1a0adaf3 HV |
237 | #define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) |
238 | #define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) | |
239 | #define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) | |
240 | #define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19) | |
241 | #define IVTV_IRQ_DMA_ERR (0x1 << 18) | |
242 | #define IVTV_IRQ_DMA_WRITE (0x1 << 17) | |
243 | #define IVTV_IRQ_DMA_READ (0x1 << 16) | |
244 | #define IVTV_IRQ_DEC_VSYNC (0x1 << 10) | |
245 | ||
246 | /* IRQ Masks */ | |
dc02d50a HV |
247 | #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ |
248 | IVTV_IRQ_DMA_READ|IVTV_IRQ_ENC_PIO_COMPLETE) | |
1a0adaf3 HV |
249 | |
250 | #define IVTV_IRQ_MASK_CAPTURE (IVTV_IRQ_ENC_START_CAP | IVTV_IRQ_ENC_EOS) | |
251 | #define IVTV_IRQ_MASK_DECODE (IVTV_IRQ_DEC_DATA_REQ|IVTV_IRQ_DEC_AUD_MODE_CHG) | |
252 | ||
253 | /* i2c stuff */ | |
254 | #define I2C_CLIENTS_MAX 16 | |
255 | ||
256 | /* debugging */ | |
257 | ||
1aa32c2f HV |
258 | #define IVTV_DBGFLG_WARN (1 << 0) |
259 | #define IVTV_DBGFLG_INFO (1 << 1) | |
260 | #define IVTV_DBGFLG_MB (1 << 2) | |
261 | #define IVTV_DBGFLG_IOCTL (1 << 3) | |
262 | #define IVTV_DBGFLG_FILE (1 << 4) | |
263 | #define IVTV_DBGFLG_DMA (1 << 5) | |
264 | #define IVTV_DBGFLG_IRQ (1 << 6) | |
265 | #define IVTV_DBGFLG_DEC (1 << 7) | |
266 | #define IVTV_DBGFLG_YUV (1 << 8) | |
267 | #define IVTV_DBGFLG_I2C (1 << 9) | |
bd58df6d | 268 | /* Flag to turn on high volume debugging */ |
1aa32c2f | 269 | #define IVTV_DBGFLG_HIGHVOL (1 << 10) |
1a0adaf3 HV |
270 | |
271 | /* NOTE: extra space before comma in 'itv->num , ## args' is required for | |
272 | gcc-2.95, otherwise it won't compile. */ | |
273 | #define IVTV_DEBUG(x, type, fmt, args...) \ | |
274 | do { \ | |
275 | if ((x) & ivtv_debug) \ | |
276 | printk(KERN_INFO "ivtv%d " type ": " fmt, itv->num , ## args); \ | |
277 | } while (0) | |
1aa32c2f HV |
278 | #define IVTV_DEBUG_WARN(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_WARN, "warn", fmt , ## args) |
279 | #define IVTV_DEBUG_INFO(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_INFO, "info", fmt , ## args) | |
280 | #define IVTV_DEBUG_MB(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_MB, "mb", fmt , ## args) | |
281 | #define IVTV_DEBUG_DMA(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DMA, "dma", fmt , ## args) | |
1a0adaf3 | 282 | #define IVTV_DEBUG_IOCTL(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args) |
1aa32c2f HV |
283 | #define IVTV_DEBUG_FILE(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_FILE, "file", fmt , ## args) |
284 | #define IVTV_DEBUG_I2C(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_I2C, "i2c", fmt , ## args) | |
285 | #define IVTV_DEBUG_IRQ(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IRQ, "irq", fmt , ## args) | |
286 | #define IVTV_DEBUG_DEC(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DEC, "dec", fmt , ## args) | |
287 | #define IVTV_DEBUG_YUV(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_YUV, "yuv", fmt , ## args) | |
1a0adaf3 | 288 | |
bd58df6d HV |
289 | #define IVTV_DEBUG_HIGH_VOL(x, type, fmt, args...) \ |
290 | do { \ | |
291 | if (((x) & ivtv_debug) && (ivtv_debug & IVTV_DBGFLG_HIGHVOL)) \ | |
292 | printk(KERN_INFO "ivtv%d " type ": " fmt, itv->num , ## args); \ | |
293 | } while (0) | |
1aa32c2f HV |
294 | #define IVTV_DEBUG_HI_WARN(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_WARN, "warn", fmt , ## args) |
295 | #define IVTV_DEBUG_HI_INFO(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_INFO, "info", fmt , ## args) | |
296 | #define IVTV_DEBUG_HI_MB(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_MB, "mb", fmt , ## args) | |
297 | #define IVTV_DEBUG_HI_DMA(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DMA, "dma", fmt , ## args) | |
bd58df6d | 298 | #define IVTV_DEBUG_HI_IOCTL(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args) |
1aa32c2f HV |
299 | #define IVTV_DEBUG_HI_FILE(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_FILE, "file", fmt , ## args) |
300 | #define IVTV_DEBUG_HI_I2C(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_I2C, "i2c", fmt , ## args) | |
301 | #define IVTV_DEBUG_HI_IRQ(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IRQ, "irq", fmt , ## args) | |
302 | #define IVTV_DEBUG_HI_DEC(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DEC, "dec", fmt , ## args) | |
303 | #define IVTV_DEBUG_HI_YUV(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_YUV, "yuv", fmt , ## args) | |
bd58df6d | 304 | |
1a0adaf3 HV |
305 | /* Standard kernel messages */ |
306 | #define IVTV_ERR(fmt, args...) printk(KERN_ERR "ivtv%d: " fmt, itv->num , ## args) | |
307 | #define IVTV_WARN(fmt, args...) printk(KERN_WARNING "ivtv%d: " fmt, itv->num , ## args) | |
308 | #define IVTV_INFO(fmt, args...) printk(KERN_INFO "ivtv%d: " fmt, itv->num , ## args) | |
1a0adaf3 HV |
309 | |
310 | /* Values for IVTV_API_DEC_PLAYBACK_SPEED mpeg_frame_type_mask parameter: */ | |
311 | #define MPEG_FRAME_TYPE_IFRAME 1 | |
312 | #define MPEG_FRAME_TYPE_IFRAME_PFRAME 3 | |
313 | #define MPEG_FRAME_TYPE_ALL 7 | |
314 | ||
315 | /* output modes (cx23415 only) */ | |
316 | #define OUT_NONE 0 | |
317 | #define OUT_MPG 1 | |
318 | #define OUT_YUV 2 | |
319 | #define OUT_UDMA_YUV 3 | |
320 | #define OUT_PASSTHROUGH 4 | |
321 | ||
322 | #define IVTV_MAX_PGM_INDEX (400) | |
323 | ||
324 | extern int ivtv_debug; | |
325 | ||
326 | ||
327 | struct ivtv_options { | |
313e91e8 | 328 | int kilobytes[IVTV_MAX_STREAMS]; /* Size in kilobytes of each stream */ |
1a0adaf3 HV |
329 | int cardtype; /* force card type on load */ |
330 | int tuner; /* set tuner on load */ | |
331 | int radio; /* enable/disable radio */ | |
332 | int newi2c; /* New I2C algorithm */ | |
333 | }; | |
334 | ||
335 | #define IVTV_MBOX_DMA_START 6 | |
336 | #define IVTV_MBOX_DMA_END 8 | |
337 | #define IVTV_MBOX_DMA 9 | |
338 | #define IVTV_MBOX_FIELD_DISPLAYED 8 | |
339 | ||
340 | /* ivtv-specific mailbox template */ | |
341 | struct ivtv_mailbox { | |
342 | u32 flags; | |
343 | u32 cmd; | |
344 | u32 retval; | |
345 | u32 timeout; | |
346 | u32 data[CX2341X_MBOX_MAX_DATA]; | |
347 | }; | |
348 | ||
349 | struct ivtv_api_cache { | |
350 | unsigned long last_jiffies; /* when last command was issued */ | |
351 | u32 data[CX2341X_MBOX_MAX_DATA]; /* last sent api data */ | |
352 | }; | |
353 | ||
354 | struct ivtv_mailbox_data { | |
355 | volatile struct ivtv_mailbox __iomem *mbox; | |
356 | /* Bits 0-2 are for the encoder mailboxes, 0-1 are for the decoder mailboxes. | |
357 | If the bit is set, then the corresponding mailbox is in use by the driver. */ | |
358 | unsigned long busy; | |
359 | u8 max_mbox; | |
360 | }; | |
361 | ||
362 | /* per-buffer bit flags */ | |
f4071b85 | 363 | #define IVTV_F_B_NEED_BUF_SWAP (1 << 0) /* this buffer should be byte swapped */ |
1a0adaf3 HV |
364 | |
365 | /* per-stream, s_flags */ | |
366 | #define IVTV_F_S_DMA_PENDING 0 /* this stream has pending DMA */ | |
367 | #define IVTV_F_S_DMA_HAS_VBI 1 /* the current DMA request also requests VBI data */ | |
368 | #define IVTV_F_S_NEEDS_DATA 2 /* this decoding stream needs more data */ | |
369 | ||
370 | #define IVTV_F_S_CLAIMED 3 /* this stream is claimed */ | |
371 | #define IVTV_F_S_STREAMING 4 /* the fw is decoding/encoding this stream */ | |
372 | #define IVTV_F_S_INTERNAL_USE 5 /* this stream is used internally (sliced VBI processing) */ | |
373 | #define IVTV_F_S_PASSTHROUGH 6 /* this stream is in passthrough mode */ | |
374 | #define IVTV_F_S_STREAMOFF 7 /* signal end of stream EOS */ | |
375 | #define IVTV_F_S_APPL_IO 8 /* this stream is used read/written by an application */ | |
376 | ||
dc02d50a HV |
377 | #define IVTV_F_S_PIO_PENDING 9 /* this stream has pending PIO */ |
378 | #define IVTV_F_S_PIO_HAS_VBI 1 /* the current PIO request also requests VBI data */ | |
379 | ||
1a0adaf3 | 380 | /* per-ivtv, i_flags */ |
1e13f9e3 HV |
381 | #define IVTV_F_I_DMA 0 /* DMA in progress */ |
382 | #define IVTV_F_I_UDMA 1 /* UDMA in progress */ | |
383 | #define IVTV_F_I_UDMA_PENDING 2 /* UDMA pending */ | |
384 | #define IVTV_F_I_SPEED_CHANGE 3 /* A speed change is in progress */ | |
385 | #define IVTV_F_I_EOS 4 /* End of encoder stream reached */ | |
386 | #define IVTV_F_I_RADIO_USER 5 /* The radio tuner is selected */ | |
387 | #define IVTV_F_I_DIG_RST 6 /* Reset digitizer */ | |
388 | #define IVTV_F_I_DEC_YUV 7 /* YUV instead of MPG is being decoded */ | |
1e13f9e3 HV |
389 | #define IVTV_F_I_UPDATE_CC 9 /* CC should be updated */ |
390 | #define IVTV_F_I_UPDATE_WSS 10 /* WSS should be updated */ | |
391 | #define IVTV_F_I_UPDATE_VPS 11 /* VPS should be updated */ | |
392 | #define IVTV_F_I_DECODING_YUV 12 /* this stream is YUV frame decoding */ | |
393 | #define IVTV_F_I_ENC_PAUSED 13 /* the encoder is paused */ | |
1a0adaf3 | 394 | #define IVTV_F_I_VALID_DEC_TIMINGS 14 /* last_dec_timing is valid */ |
dc02d50a HV |
395 | #define IVTV_F_I_HAVE_WORK 15 /* Used in the interrupt handler: there is work to be done */ |
396 | #define IVTV_F_I_WORK_HANDLER_VBI 16 /* there is work to be done for VBI */ | |
397 | #define IVTV_F_I_WORK_HANDLER_YUV 17 /* there is work to be done for YUV */ | |
398 | #define IVTV_F_I_WORK_HANDLER_PIO 18 /* there is work to be done for PIO */ | |
399 | #define IVTV_F_I_PIO 19 /* PIO in progress */ | |
ac425144 | 400 | #define IVTV_F_I_DEC_PAUSED 20 /* the decoder is paused */ |
c976bc82 HV |
401 | #define IVTV_F_I_INITED 21 /* set after first open */ |
402 | #define IVTV_F_I_FAILED 22 /* set if first open failed */ | |
1a0adaf3 HV |
403 | |
404 | /* Event notifications */ | |
1e13f9e3 HV |
405 | #define IVTV_F_I_EV_DEC_STOPPED 28 /* decoder stopped event */ |
406 | #define IVTV_F_I_EV_VSYNC 29 /* VSYNC event */ | |
407 | #define IVTV_F_I_EV_VSYNC_FIELD 30 /* VSYNC event field (0 = first, 1 = second field) */ | |
408 | #define IVTV_F_I_EV_VSYNC_ENABLED 31 /* VSYNC event enabled */ | |
1a0adaf3 HV |
409 | |
410 | /* Scatter-Gather array element, used in DMA transfers */ | |
37093b1e | 411 | struct ivtv_sg_element { |
1a0adaf3 HV |
412 | u32 src; |
413 | u32 dst; | |
414 | u32 size; | |
415 | }; | |
416 | ||
417 | struct ivtv_user_dma { | |
418 | struct mutex lock; | |
419 | int page_count; | |
420 | struct page *map[IVTV_DMA_SG_OSD_ENT]; | |
0989fd2c HV |
421 | /* Needed when dealing with highmem userspace buffers */ |
422 | struct page *bouncemap[IVTV_DMA_SG_OSD_ENT]; | |
1a0adaf3 HV |
423 | |
424 | /* Base Dev SG Array for cx23415/6 */ | |
37093b1e | 425 | struct ivtv_sg_element SGarray[IVTV_DMA_SG_OSD_ENT]; |
1a0adaf3 HV |
426 | dma_addr_t SG_handle; |
427 | int SG_length; | |
428 | ||
429 | /* SG List of Buffers */ | |
430 | struct scatterlist SGlist[IVTV_DMA_SG_OSD_ENT]; | |
431 | }; | |
432 | ||
433 | struct ivtv_dma_page_info { | |
434 | unsigned long uaddr; | |
435 | unsigned long first; | |
436 | unsigned long last; | |
437 | unsigned int offset; | |
438 | unsigned int tail; | |
439 | int page_count; | |
440 | }; | |
441 | ||
442 | struct ivtv_buffer { | |
443 | struct list_head list; | |
444 | dma_addr_t dma_handle; | |
f4071b85 HV |
445 | unsigned short b_flags; |
446 | unsigned short dma_xfer_cnt; | |
1a0adaf3 HV |
447 | char *buf; |
448 | ||
449 | u32 bytesused; | |
450 | u32 readpos; | |
451 | }; | |
452 | ||
453 | struct ivtv_queue { | |
454 | struct list_head list; | |
455 | u32 buffers; | |
456 | u32 length; | |
457 | u32 bytesused; | |
458 | }; | |
459 | ||
460 | struct ivtv; /* forward reference */ | |
461 | ||
462 | struct ivtv_stream { | |
463 | /* These first four fields are always set, even if the stream | |
464 | is not actually created. */ | |
465 | struct video_device *v4l2dev; /* NULL when stream not created */ | |
466 | struct ivtv *itv; /* for ease of use */ | |
467 | const char *name; /* name of the stream */ | |
468 | int type; /* stream type */ | |
469 | ||
470 | u32 id; | |
471 | spinlock_t qlock; /* locks access to the queues */ | |
472 | unsigned long s_flags; /* status flags, see above */ | |
473 | int dma; /* can be PCI_DMA_TODEVICE, | |
474 | PCI_DMA_FROMDEVICE or | |
475 | PCI_DMA_NONE */ | |
37093b1e HV |
476 | u32 pending_offset; |
477 | u32 pending_backup; | |
478 | u64 pending_pts; | |
479 | ||
1a0adaf3 HV |
480 | u32 dma_offset; |
481 | u32 dma_backup; | |
482 | u64 dma_pts; | |
483 | ||
484 | int subtype; | |
485 | wait_queue_head_t waitq; | |
486 | u32 dma_last_offset; | |
487 | ||
488 | /* Buffer Stats */ | |
489 | u32 buffers; | |
490 | u32 buf_size; | |
491 | u32 buffers_stolen; | |
492 | ||
493 | /* Buffer Queues */ | |
494 | struct ivtv_queue q_free; /* free buffers */ | |
495 | struct ivtv_queue q_full; /* full buffers */ | |
496 | struct ivtv_queue q_io; /* waiting for I/O */ | |
497 | struct ivtv_queue q_dma; /* waiting for DMA */ | |
498 | struct ivtv_queue q_predma; /* waiting for DMA */ | |
499 | ||
f4071b85 HV |
500 | /* DMA xfer counter, buffers belonging to the same DMA |
501 | xfer will have the same dma_xfer_cnt. */ | |
502 | u16 dma_xfer_cnt; | |
503 | ||
1a0adaf3 | 504 | /* Base Dev SG Array for cx23415/6 */ |
37093b1e HV |
505 | struct ivtv_sg_element *sg_pending; |
506 | struct ivtv_sg_element *sg_processing; | |
507 | struct ivtv_sg_element *sg_dma; | |
508 | dma_addr_t sg_handle; | |
509 | int sg_pending_size; | |
510 | int sg_processing_size; | |
511 | int sg_processed; | |
1a0adaf3 HV |
512 | |
513 | /* SG List of Buffers */ | |
514 | struct scatterlist *SGlist; | |
515 | }; | |
516 | ||
517 | struct ivtv_open_id { | |
518 | u32 open_id; | |
519 | int type; | |
ad8ff0f1 | 520 | int yuv_frames; |
d46c17d7 | 521 | enum v4l2_priority prio; |
1a0adaf3 HV |
522 | struct ivtv *itv; |
523 | }; | |
524 | ||
525 | #define IVTV_YUV_UPDATE_HORIZONTAL 0x01 | |
526 | #define IVTV_YUV_UPDATE_VERTICAL 0x02 | |
527 | ||
528 | struct yuv_frame_info | |
529 | { | |
530 | u32 update; | |
531 | int src_x; | |
532 | int src_y; | |
533 | unsigned int src_w; | |
534 | unsigned int src_h; | |
535 | int dst_x; | |
536 | int dst_y; | |
537 | unsigned int dst_w; | |
538 | unsigned int dst_h; | |
539 | int pan_x; | |
540 | int pan_y; | |
541 | u32 vis_w; | |
542 | u32 vis_h; | |
543 | u32 interlaced_y; | |
544 | u32 interlaced_uv; | |
545 | int tru_x; | |
546 | u32 tru_w; | |
547 | u32 tru_h; | |
548 | u32 offset_y; | |
bfd7beac | 549 | int lace_mode; |
1a0adaf3 HV |
550 | }; |
551 | ||
552 | #define IVTV_YUV_MODE_INTERLACED 0x00 | |
553 | #define IVTV_YUV_MODE_PROGRESSIVE 0x01 | |
554 | #define IVTV_YUV_MODE_AUTO 0x02 | |
555 | #define IVTV_YUV_MODE_MASK 0x03 | |
556 | ||
557 | #define IVTV_YUV_SYNC_EVEN 0x00 | |
558 | #define IVTV_YUV_SYNC_ODD 0x04 | |
559 | #define IVTV_YUV_SYNC_MASK 0x04 | |
560 | ||
561 | struct yuv_playback_info | |
562 | { | |
563 | u32 reg_2834; | |
564 | u32 reg_2838; | |
565 | u32 reg_283c; | |
566 | u32 reg_2840; | |
567 | u32 reg_2844; | |
568 | u32 reg_2848; | |
569 | u32 reg_2854; | |
570 | u32 reg_285c; | |
571 | u32 reg_2864; | |
572 | ||
573 | u32 reg_2870; | |
574 | u32 reg_2874; | |
575 | u32 reg_2890; | |
576 | u32 reg_2898; | |
577 | u32 reg_289c; | |
578 | ||
579 | u32 reg_2918; | |
580 | u32 reg_291c; | |
581 | u32 reg_2920; | |
582 | u32 reg_2924; | |
583 | u32 reg_2928; | |
584 | u32 reg_292c; | |
585 | u32 reg_2930; | |
586 | ||
587 | u32 reg_2934; | |
588 | ||
589 | u32 reg_2938; | |
590 | u32 reg_293c; | |
591 | u32 reg_2940; | |
592 | u32 reg_2944; | |
593 | u32 reg_2948; | |
594 | u32 reg_294c; | |
595 | u32 reg_2950; | |
596 | u32 reg_2954; | |
597 | u32 reg_2958; | |
598 | u32 reg_295c; | |
599 | u32 reg_2960; | |
600 | u32 reg_2964; | |
601 | u32 reg_2968; | |
602 | u32 reg_296c; | |
603 | ||
604 | u32 reg_2970; | |
605 | ||
606 | int v_filter_1; | |
607 | int v_filter_2; | |
608 | int h_filter; | |
609 | ||
610 | u32 osd_x_offset; | |
611 | u32 osd_y_offset; | |
612 | ||
613 | u32 osd_x_pan; | |
614 | u32 osd_y_pan; | |
615 | ||
616 | u32 osd_vis_w; | |
617 | u32 osd_vis_h; | |
618 | ||
619 | int decode_height; | |
620 | ||
621 | int frame_interlaced; | |
1a0adaf3 HV |
622 | |
623 | int lace_mode; | |
624 | int lace_threshold; | |
1a0adaf3 HV |
625 | int lace_sync_field; |
626 | ||
627 | atomic_t next_dma_frame; | |
628 | atomic_t next_fill_frame; | |
629 | ||
630 | u32 yuv_forced_update; | |
631 | int update_frame; | |
bfd7beac IA |
632 | |
633 | int sync_field[4]; /* Field to sync on */ | |
634 | int field_delay[4]; /* Flag to extend duration of previous frame */ | |
635 | u8 fields_lapsed; /* Counter used when delaying a frame */ | |
636 | ||
1a0adaf3 HV |
637 | struct yuv_frame_info new_frame_info[4]; |
638 | struct yuv_frame_info old_frame_info; | |
639 | struct yuv_frame_info old_frame_info_args; | |
640 | ||
641 | void *blanking_ptr; | |
642 | dma_addr_t blanking_dmaptr; | |
643 | }; | |
644 | ||
645 | #define IVTV_VBI_FRAMES 32 | |
646 | ||
647 | /* VBI data */ | |
648 | struct vbi_info { | |
649 | u32 dec_start; | |
650 | u32 enc_start, enc_size; | |
651 | int fpi; | |
652 | u32 frame; | |
1a0adaf3 HV |
653 | u8 cc_data_odd[256]; |
654 | u8 cc_data_even[256]; | |
655 | int cc_pos; | |
656 | u8 cc_no_update; | |
657 | u8 vps[5]; | |
658 | u8 vps_found; | |
659 | int wss; | |
660 | u8 wss_found; | |
661 | u8 wss_no_update; | |
662 | u32 raw_decoder_line_size; | |
663 | u8 raw_decoder_sav_odd_field; | |
664 | u8 raw_decoder_sav_even_field; | |
665 | u32 sliced_decoder_line_size; | |
666 | u8 sliced_decoder_sav_odd_field; | |
667 | u8 sliced_decoder_sav_even_field; | |
668 | struct v4l2_format in; | |
669 | /* convenience pointer to sliced struct in vbi_in union */ | |
670 | struct v4l2_sliced_vbi_format *sliced_in; | |
1a0adaf3 HV |
671 | int insert_mpeg; |
672 | ||
673 | /* Buffer for the maximum of 2 * 18 * packet_size sliced VBI lines. | |
674 | One for /dev/vbi0 and one for /dev/vbi8 */ | |
675 | struct v4l2_sliced_vbi_data sliced_data[36]; | |
676 | struct v4l2_sliced_vbi_data sliced_dec_data[36]; | |
677 | ||
678 | /* Buffer for VBI data inserted into MPEG stream. | |
679 | The first byte is a dummy byte that's never used. | |
680 | The next 16 bytes contain the MPEG header for the VBI data, | |
681 | the remainder is the actual VBI data. | |
682 | The max size accepted by the MPEG VBI reinsertion turns out | |
683 | to be 1552 bytes, which happens to be 4 + (1 + 42) * (2 * 18) bytes, | |
684 | where 4 is a four byte header, 42 is the max sliced VBI payload, 1 is | |
685 | a single line header byte and 2 * 18 is the number of VBI lines per frame. | |
686 | ||
687 | However, it seems that the data must be 1K aligned, so we have to | |
688 | pad the data until the 1 or 2 K boundary. | |
689 | ||
690 | This pointer array will allocate 2049 bytes to store each VBI frame. */ | |
691 | u8 *sliced_mpeg_data[IVTV_VBI_FRAMES]; | |
692 | u32 sliced_mpeg_size[IVTV_VBI_FRAMES]; | |
693 | struct ivtv_buffer sliced_mpeg_buf; | |
694 | u32 inserted_frame; | |
695 | ||
1a0adaf3 HV |
696 | u32 start[2], count; |
697 | u32 raw_size; | |
698 | u32 sliced_size; | |
699 | }; | |
700 | ||
701 | /* forward declaration of struct defined in ivtv-cards.h */ | |
702 | struct ivtv_card; | |
703 | ||
704 | /* Struct to hold info about ivtv cards */ | |
705 | struct ivtv { | |
706 | int num; /* board number, -1 during init! */ | |
707 | char name[8]; /* board name for printk and interrupts (e.g. 'ivtv0') */ | |
708 | struct pci_dev *dev; /* PCI device */ | |
709 | const struct ivtv_card *card; /* card information */ | |
710 | const char *card_name; /* full name of the card */ | |
711 | u8 has_cx23415; /* 1 if it is a cx23415 based card, 0 for cx23416 */ | |
712 | u8 is_50hz; | |
713 | u8 is_60hz; | |
714 | u8 is_out_50hz; | |
715 | u8 is_out_60hz; | |
716 | u8 pvr150_workaround; /* 1 if the cx25840 needs to workaround a PVR150 bug */ | |
717 | u8 nof_inputs; /* number of video inputs */ | |
718 | u8 nof_audio_inputs; /* number of audio inputs */ | |
719 | u32 v4l2_cap; /* V4L2 capabilities of card */ | |
720 | u32 hw_flags; /* Hardware description of the board */ | |
37297805 | 721 | int tunerid; /* Userspace tuner ID for experimental Xceive tuner support */ |
1a0adaf3 HV |
722 | |
723 | /* controlling Video decoder function */ | |
724 | int (*video_dec_func)(struct ivtv *, unsigned int, void *); | |
725 | ||
726 | struct ivtv_options options; /* User options */ | |
727 | int stream_buf_size[IVTV_MAX_STREAMS]; /* Stream buffer size */ | |
728 | struct ivtv_stream streams[IVTV_MAX_STREAMS]; /* Stream data */ | |
729 | int speed; | |
730 | u8 speed_mute_audio; | |
731 | unsigned long i_flags; /* global ivtv flags */ | |
732 | atomic_t capturing; /* count number of active capture streams */ | |
733 | atomic_t decoding; /* count number of active decoding streams */ | |
734 | u32 irq_rr_idx; /* Round-robin stream index */ | |
735 | int cur_dma_stream; /* index of stream doing DMA */ | |
dc02d50a | 736 | int cur_pio_stream; /* index of stream doing PIO */ |
1a0adaf3 HV |
737 | u32 dma_data_req_offset; |
738 | u32 dma_data_req_size; | |
37093b1e | 739 | int dma_retries; |
1a0adaf3 HV |
740 | int output_mode; /* NONE, MPG, YUV, UDMA YUV, passthrough */ |
741 | spinlock_t lock; /* lock access to this struct */ | |
742 | int search_pack_header; | |
743 | ||
744 | spinlock_t dma_reg_lock; /* lock access to DMA engine registers */ | |
f8859691 | 745 | struct mutex serialize_lock; /* lock used to serialize starting streams */ |
1a0adaf3 HV |
746 | |
747 | /* User based DMA for OSD */ | |
748 | struct ivtv_user_dma udma; | |
749 | ||
750 | int open_id; /* incremented each time an open occurs, used as unique ID. | |
751 | starts at 1, so 0 can be used as uninitialized value | |
752 | in the stream->id. */ | |
753 | ||
754 | u32 base_addr; | |
755 | u32 irqmask; | |
1e13f9e3 | 756 | |
d46c17d7 | 757 | struct v4l2_prio_state prio; |
1e13f9e3 HV |
758 | struct workqueue_struct *irq_work_queues; |
759 | struct work_struct irq_work_queue; | |
1a0adaf3 HV |
760 | struct timer_list dma_timer; /* Timer used to catch unfinished DMAs */ |
761 | ||
762 | struct vbi_info vbi; | |
763 | ||
764 | struct ivtv_mailbox_data enc_mbox; | |
765 | struct ivtv_mailbox_data dec_mbox; | |
766 | struct ivtv_api_cache api_cache[256]; /* Cached API Commands */ | |
767 | ||
768 | u8 card_rev; | |
769 | volatile void __iomem *enc_mem, *dec_mem, *reg_mem; | |
770 | ||
771 | u32 pgm_info_offset; | |
772 | u32 pgm_info_num; | |
773 | u32 pgm_info_write_idx; | |
774 | u32 pgm_info_read_idx; | |
775 | struct v4l2_enc_idx_entry pgm_info[IVTV_MAX_PGM_INDEX]; | |
776 | ||
777 | u64 mpg_data_received; | |
778 | u64 vbi_data_inserted; | |
779 | ||
780 | wait_queue_head_t cap_w; | |
781 | /* when the next decoder event arrives this queue is woken up */ | |
782 | wait_queue_head_t event_waitq; | |
783 | /* when the next decoder vsync arrives this queue is woken up */ | |
784 | wait_queue_head_t vsync_waitq; | |
785 | /* when the current DMA is finished this queue is woken up */ | |
786 | wait_queue_head_t dma_waitq; | |
787 | ||
788 | /* OSD support */ | |
789 | unsigned long osd_video_pbase; | |
790 | int osd_global_alpha_state; /* 0=off : 1=on */ | |
791 | int osd_local_alpha_state; /* 0=off : 1=on */ | |
792 | int osd_color_key_state; /* 0=off : 1=on */ | |
793 | u8 osd_global_alpha; /* Current global alpha */ | |
794 | u32 osd_color_key; /* Current color key */ | |
795 | u32 osd_pixelformat; /* Current pixel format */ | |
796 | struct v4l2_rect osd_rect; /* Current OSD position and size */ | |
797 | struct v4l2_rect main_rect; /* Current Main window position and size */ | |
798 | ||
799 | u32 last_dec_timing[3]; /* Store last retrieved pts/scr/frame values */ | |
800 | ||
801 | /* i2c */ | |
802 | struct i2c_adapter i2c_adap; | |
803 | struct i2c_algo_bit_data i2c_algo; | |
804 | struct i2c_client i2c_client; | |
805 | struct mutex i2c_bus_lock; | |
806 | int i2c_state; | |
807 | struct i2c_client *i2c_clients[I2C_CLIENTS_MAX]; | |
808 | ||
809 | /* v4l2 and User settings */ | |
810 | ||
811 | /* codec settings */ | |
812 | struct cx2341x_mpeg_params params; | |
813 | u32 audio_input; | |
814 | u32 active_input; | |
815 | u32 active_output; | |
816 | v4l2_std_id std; | |
817 | v4l2_std_id std_out; | |
818 | v4l2_std_id tuner_std; /* The norm of the tuner (fixed) */ | |
819 | u8 audio_stereo_mode; | |
820 | u8 audio_bilingual_mode; | |
821 | ||
822 | /* dualwatch */ | |
823 | unsigned long dualwatch_jiffies; | |
824 | u16 dualwatch_stereo_mode; | |
825 | ||
826 | /* Digitizer type */ | |
827 | int digitizer; /* 0x00EF = saa7114 0x00FO = saa7115 0x0106 = mic */ | |
828 | ||
829 | u32 lastVsyncFrame; | |
830 | ||
831 | struct yuv_playback_info yuv_info; | |
832 | struct osd_info *osd_info; | |
833 | }; | |
834 | ||
835 | /* Globals */ | |
836 | extern struct ivtv *ivtv_cards[]; | |
837 | extern int ivtv_cards_active; | |
838 | extern int ivtv_first_minor; | |
839 | extern spinlock_t ivtv_cards_lock; | |
840 | ||
841 | /*==============Prototypes==================*/ | |
842 | ||
843 | /* Hardware/IRQ */ | |
844 | void ivtv_set_irq_mask(struct ivtv *itv, u32 mask); | |
845 | void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask); | |
846 | ||
847 | /* try to set output mode, return current mode. */ | |
848 | int ivtv_set_output_mode(struct ivtv *itv, int mode); | |
849 | ||
850 | /* return current output stream based on current mode */ | |
851 | struct ivtv_stream *ivtv_get_output_stream(struct ivtv *itv); | |
852 | ||
853 | /* Return non-zero if a signal is pending */ | |
201700d3 | 854 | int ivtv_msleep_timeout(unsigned int msecs, int intr); |
1a0adaf3 HV |
855 | |
856 | /* Wait on queue, returns -EINTR if interrupted */ | |
857 | int ivtv_waitq(wait_queue_head_t *waitq); | |
858 | ||
859 | /* Read Hauppauge eeprom */ | |
860 | struct tveeprom; /* forward reference */ | |
861 | void ivtv_read_eeprom(struct ivtv *itv, struct tveeprom *tv); | |
862 | ||
c976bc82 HV |
863 | /* First-open initialization: load firmware, init cx25840, etc. */ |
864 | int ivtv_init_on_first_open(struct ivtv *itv); | |
865 | ||
1a0adaf3 HV |
866 | /* This is a PCI post thing, where if the pci register is not read, then |
867 | the write doesn't always take effect right away. By reading back the | |
868 | register any pending PCI writes will be performed (in order), and so | |
869 | you can be sure that the writes are guaranteed to be done. | |
870 | ||
871 | Rarely needed, only in some timing sensitive cases. | |
872 | Apparently if this is not done some motherboards seem | |
873 | to kill the firmware and get into the broken state until computer is | |
874 | rebooted. */ | |
875 | #define write_sync(val, reg) \ | |
876 | do { writel(val, reg); readl(reg); } while (0) | |
877 | ||
878 | #define read_reg(reg) readl(itv->reg_mem + (reg)) | |
879 | #define write_reg(val, reg) writel(val, itv->reg_mem + (reg)) | |
880 | #define write_reg_sync(val, reg) \ | |
881 | do { write_reg(val, reg); read_reg(reg); } while (0) | |
882 | ||
883 | #define read_enc(addr) readl(itv->enc_mem + (u32)(addr)) | |
884 | #define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr)) | |
885 | #define write_enc_sync(val, addr) \ | |
886 | do { write_enc(val, addr); read_enc(addr); } while (0) | |
887 | ||
888 | #define read_dec(addr) readl(itv->dec_mem + (u32)(addr)) | |
889 | #define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr)) | |
890 | #define write_dec_sync(val, addr) \ | |
891 | do { write_dec(val, addr); read_dec(addr); } while (0) | |
892 | ||
893 | #endif /* IVTV_DRIVER_H */ |