Commit | Line | Data |
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1a0adaf3 HV |
1 | /* |
2 | I2C functions | |
3 | Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com> | |
4 | Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl> | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | /* | |
22 | This file includes an i2c implementation that was reverse engineered | |
23 | from the Hauppauge windows driver. Older ivtv versions used i2c-algo-bit, | |
24 | which whilst fine under most circumstances, had trouble with the Zilog | |
25 | CPU on the PVR-150 which handles IR functions (occasional inability to | |
26 | communicate with the chip until it was reset) and also with the i2c | |
27 | bus being completely unreachable when multiple PVR cards were present. | |
28 | ||
29 | The implementation is very similar to i2c-algo-bit, but there are enough | |
30 | subtle differences that the two are hard to merge. The general strategy | |
31 | employed by i2c-algo-bit is to use udelay() to implement the timing | |
32 | when putting out bits on the scl/sda lines. The general strategy taken | |
33 | here is to poll the lines for state changes (see ivtv_waitscl and | |
34 | ivtv_waitsda). In addition there are small delays at various locations | |
35 | which poll the SCL line 5 times (ivtv_scldelay). I would guess that | |
36 | since this is memory mapped I/O that the length of those delays is tied | |
37 | to the PCI bus clock. There is some extra code to do with recovery | |
38 | and retries. Since it is not known what causes the actual i2c problems | |
39 | in the first place, the only goal if one was to attempt to use | |
40 | i2c-algo-bit would be to try to make it follow the same code path. | |
41 | This would be a lot of work, and I'm also not convinced that it would | |
42 | provide a generic benefit to i2c-algo-bit. Therefore consider this | |
43 | an engineering solution -- not pretty, but it works. | |
44 | ||
45 | Some more general comments about what we are doing: | |
46 | ||
47 | The i2c bus is a 2 wire serial bus, with clock (SCL) and data (SDA) | |
48 | lines. To communicate on the bus (as a master, we don't act as a slave), | |
49 | we first initiate a start condition (ivtv_start). We then write the | |
50 | address of the device that we want to communicate with, along with a flag | |
51 | that indicates whether this is a read or a write. The slave then issues | |
52 | an ACK signal (ivtv_ack), which tells us that it is ready for reading / | |
53 | writing. We then proceed with reading or writing (ivtv_read/ivtv_write), | |
54 | and finally issue a stop condition (ivtv_stop) to make the bus available | |
55 | to other masters. | |
56 | ||
57 | There is an additional form of transaction where a write may be | |
58 | immediately followed by a read. In this case, there is no intervening | |
59 | stop condition. (Only the msp3400 chip uses this method of data transfer). | |
60 | */ | |
61 | ||
62 | #include "ivtv-driver.h" | |
63 | #include "ivtv-cards.h" | |
64 | #include "ivtv-gpio.h" | |
83df8e7b | 65 | #include "ivtv-i2c.h" |
1a0adaf3 | 66 | |
1a0adaf3 HV |
67 | /* i2c implementation for cx23415/6 chip, ivtv project. |
68 | * Author: Kevin Thayer (nufan_wfk at yahoo.com) | |
69 | */ | |
70 | /* i2c stuff */ | |
71 | #define IVTV_REG_I2C_SETSCL_OFFSET 0x7000 | |
72 | #define IVTV_REG_I2C_SETSDA_OFFSET 0x7004 | |
73 | #define IVTV_REG_I2C_GETSCL_OFFSET 0x7008 | |
74 | #define IVTV_REG_I2C_GETSDA_OFFSET 0x700c | |
75 | ||
1a0adaf3 | 76 | #define IVTV_CS53L32A_I2C_ADDR 0x11 |
e2a1774d | 77 | #define IVTV_M52790_I2C_ADDR 0x48 |
1a0adaf3 HV |
78 | #define IVTV_CX25840_I2C_ADDR 0x44 |
79 | #define IVTV_SAA7115_I2C_ADDR 0x21 | |
80 | #define IVTV_SAA7127_I2C_ADDR 0x44 | |
81 | #define IVTV_SAA717x_I2C_ADDR 0x21 | |
82 | #define IVTV_MSP3400_I2C_ADDR 0x40 | |
83 | #define IVTV_HAUPPAUGE_I2C_ADDR 0x50 | |
84 | #define IVTV_WM8739_I2C_ADDR 0x1a | |
85 | #define IVTV_WM8775_I2C_ADDR 0x1b | |
86 | #define IVTV_TEA5767_I2C_ADDR 0x60 | |
87 | #define IVTV_UPD64031A_I2C_ADDR 0x12 | |
88 | #define IVTV_UPD64083_I2C_ADDR 0x5c | |
d9009201 HV |
89 | #define IVTV_VP27SMPX_I2C_ADDR 0x5b |
90 | #define IVTV_M52790_I2C_ADDR 0x48 | |
1a0adaf3 | 91 | |
d9009201 HV |
92 | /* This array should match the IVTV_HW_ defines */ |
93 | static const u8 hw_addrs[] = { | |
94 | IVTV_CX25840_I2C_ADDR, | |
95 | IVTV_SAA7115_I2C_ADDR, | |
96 | IVTV_SAA7127_I2C_ADDR, | |
97 | IVTV_MSP3400_I2C_ADDR, | |
98 | 0, | |
99 | IVTV_WM8775_I2C_ADDR, | |
100 | IVTV_CS53L32A_I2C_ADDR, | |
101 | 0, | |
102 | IVTV_SAA7115_I2C_ADDR, | |
103 | IVTV_UPD64031A_I2C_ADDR, | |
104 | IVTV_UPD64083_I2C_ADDR, | |
105 | IVTV_SAA717x_I2C_ADDR, | |
106 | IVTV_WM8739_I2C_ADDR, | |
107 | IVTV_VP27SMPX_I2C_ADDR, | |
108 | IVTV_M52790_I2C_ADDR, | |
109 | 0 /* IVTV_HW_GPIO dummy driver ID */ | |
110 | }; | |
111 | ||
67ec09fd HV |
112 | /* This array should match the IVTV_HW_ defines */ |
113 | static const char *hw_modules[] = { | |
114 | "cx25840", | |
115 | "saa7115", | |
116 | "saa7127", | |
117 | "msp3400", | |
118 | "tuner", | |
119 | "wm8775", | |
120 | "cs53l32a", | |
121 | NULL, | |
122 | "saa7115", | |
123 | "upd64031a", | |
124 | "upd64083", | |
125 | "saa717x", | |
126 | "wm8739", | |
127 | "vp27smpx", | |
128 | "m52790", | |
129 | NULL | |
130 | }; | |
131 | ||
1a0adaf3 | 132 | /* This array should match the IVTV_HW_ defines */ |
af294867 | 133 | static const char * const hw_devicenames[] = { |
d9009201 | 134 | "cx25840", |
1a0adaf3 | 135 | "saa7115", |
5daed074 | 136 | "saa7127_auto", /* saa7127 or saa7129 */ |
1a0adaf3 HV |
137 | "msp3400", |
138 | "tuner", | |
139 | "wm8775", | |
140 | "cs53l32a", | |
141 | "tveeprom", | |
af294867 | 142 | "saa7114", |
1a0adaf3 HV |
143 | "upd64031a", |
144 | "upd64083", | |
145 | "saa717x", | |
146 | "wm8739", | |
ac247433 | 147 | "vp27smpx", |
e2a1774d | 148 | "m52790", |
1a0adaf3 HV |
149 | "gpio", |
150 | }; | |
151 | ||
d9009201 | 152 | int ivtv_i2c_register(struct ivtv *itv, unsigned idx) |
1a0adaf3 | 153 | { |
67ec09fd HV |
154 | struct v4l2_subdev *sd; |
155 | struct i2c_adapter *adap = &itv->i2c_adap; | |
156 | const char *mod = hw_modules[idx]; | |
157 | const char *type = hw_devicenames[idx]; | |
158 | u32 hw = 1 << idx; | |
1a0adaf3 | 159 | |
67ec09fd | 160 | if (idx >= ARRAY_SIZE(hw_addrs)) |
d9009201 | 161 | return -1; |
67ec09fd HV |
162 | if (hw == IVTV_HW_TUNER) { |
163 | /* special tuner handling */ | |
53dacb15 | 164 | sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, |
e6574f2f | 165 | adap, mod, type, |
53dacb15 | 166 | 0, itv->card_i2c->radio); |
67ec09fd HV |
167 | if (sd) |
168 | sd->grp_id = 1 << idx; | |
53dacb15 | 169 | sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, |
e6574f2f | 170 | adap, mod, type, |
53dacb15 | 171 | 0, itv->card_i2c->demod); |
67ec09fd HV |
172 | if (sd) |
173 | sd->grp_id = 1 << idx; | |
53dacb15 | 174 | sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, |
e6574f2f | 175 | adap, mod, type, |
53dacb15 | 176 | 0, itv->card_i2c->tv); |
67ec09fd HV |
177 | if (sd) |
178 | sd->grp_id = 1 << idx; | |
179 | return sd ? 0 : -1; | |
1a0adaf3 | 180 | } |
67ec09fd HV |
181 | if (!hw_addrs[idx]) |
182 | return -1; | |
183 | if (hw == IVTV_HW_UPD64031A || hw == IVTV_HW_UPD6408X) { | |
53dacb15 HV |
184 | sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, |
185 | adap, mod, type, 0, I2C_ADDRS(hw_addrs[idx])); | |
67ec09fd | 186 | } else { |
e6574f2f | 187 | sd = v4l2_i2c_new_subdev(&itv->v4l2_dev, |
53dacb15 | 188 | adap, mod, type, hw_addrs[idx], NULL); |
d9009201 | 189 | } |
67ec09fd HV |
190 | if (sd) |
191 | sd->grp_id = 1 << idx; | |
192 | return sd ? 0 : -1; | |
1a0adaf3 HV |
193 | } |
194 | ||
67ec09fd | 195 | struct v4l2_subdev *ivtv_find_hw(struct ivtv *itv, u32 hw) |
1a0adaf3 | 196 | { |
67ec09fd HV |
197 | struct v4l2_subdev *result = NULL; |
198 | struct v4l2_subdev *sd; | |
1a0adaf3 | 199 | |
8ac05ae3 HV |
200 | spin_lock(&itv->v4l2_dev.lock); |
201 | v4l2_device_for_each_subdev(sd, &itv->v4l2_dev) { | |
67ec09fd HV |
202 | if (sd->grp_id == hw) { |
203 | result = sd; | |
1a0adaf3 HV |
204 | break; |
205 | } | |
206 | } | |
8ac05ae3 | 207 | spin_unlock(&itv->v4l2_dev.lock); |
67ec09fd | 208 | return result; |
1a0adaf3 HV |
209 | } |
210 | ||
211 | /* Set the serial clock line to the desired state */ | |
212 | static void ivtv_setscl(struct ivtv *itv, int state) | |
213 | { | |
214 | /* write them out */ | |
215 | /* write bits are inverted */ | |
216 | write_reg(~state, IVTV_REG_I2C_SETSCL_OFFSET); | |
217 | } | |
218 | ||
219 | /* Set the serial data line to the desired state */ | |
220 | static void ivtv_setsda(struct ivtv *itv, int state) | |
221 | { | |
222 | /* write them out */ | |
223 | /* write bits are inverted */ | |
224 | write_reg(~state & 1, IVTV_REG_I2C_SETSDA_OFFSET); | |
225 | } | |
226 | ||
227 | /* Read the serial clock line */ | |
228 | static int ivtv_getscl(struct ivtv *itv) | |
229 | { | |
230 | return read_reg(IVTV_REG_I2C_GETSCL_OFFSET) & 1; | |
231 | } | |
232 | ||
233 | /* Read the serial data line */ | |
234 | static int ivtv_getsda(struct ivtv *itv) | |
235 | { | |
236 | return read_reg(IVTV_REG_I2C_GETSDA_OFFSET) & 1; | |
237 | } | |
238 | ||
239 | /* Implement a short delay by polling the serial clock line */ | |
240 | static void ivtv_scldelay(struct ivtv *itv) | |
241 | { | |
242 | int i; | |
243 | ||
244 | for (i = 0; i < 5; ++i) | |
245 | ivtv_getscl(itv); | |
246 | } | |
247 | ||
248 | /* Wait for the serial clock line to become set to a specific value */ | |
249 | static int ivtv_waitscl(struct ivtv *itv, int val) | |
250 | { | |
251 | int i; | |
252 | ||
253 | ivtv_scldelay(itv); | |
254 | for (i = 0; i < 1000; ++i) { | |
255 | if (ivtv_getscl(itv) == val) | |
256 | return 1; | |
257 | } | |
258 | return 0; | |
259 | } | |
260 | ||
261 | /* Wait for the serial data line to become set to a specific value */ | |
262 | static int ivtv_waitsda(struct ivtv *itv, int val) | |
263 | { | |
264 | int i; | |
265 | ||
266 | ivtv_scldelay(itv); | |
267 | for (i = 0; i < 1000; ++i) { | |
268 | if (ivtv_getsda(itv) == val) | |
269 | return 1; | |
270 | } | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /* Wait for the slave to issue an ACK */ | |
275 | static int ivtv_ack(struct ivtv *itv) | |
276 | { | |
277 | int ret = 0; | |
278 | ||
279 | if (ivtv_getscl(itv) == 1) { | |
11d28766 | 280 | IVTV_DEBUG_HI_I2C("SCL was high starting an ack\n"); |
1a0adaf3 HV |
281 | ivtv_setscl(itv, 0); |
282 | if (!ivtv_waitscl(itv, 0)) { | |
283 | IVTV_DEBUG_I2C("Could not set SCL low starting an ack\n"); | |
284 | return -EREMOTEIO; | |
285 | } | |
286 | } | |
287 | ivtv_setsda(itv, 1); | |
288 | ivtv_scldelay(itv); | |
289 | ivtv_setscl(itv, 1); | |
290 | if (!ivtv_waitsda(itv, 0)) { | |
291 | IVTV_DEBUG_I2C("Slave did not ack\n"); | |
292 | ret = -EREMOTEIO; | |
293 | } | |
294 | ivtv_setscl(itv, 0); | |
295 | if (!ivtv_waitscl(itv, 0)) { | |
296 | IVTV_DEBUG_I2C("Failed to set SCL low after ACK\n"); | |
297 | ret = -EREMOTEIO; | |
298 | } | |
299 | return ret; | |
300 | } | |
301 | ||
302 | /* Write a single byte to the i2c bus and wait for the slave to ACK */ | |
303 | static int ivtv_sendbyte(struct ivtv *itv, unsigned char byte) | |
304 | { | |
305 | int i, bit; | |
306 | ||
11d28766 | 307 | IVTV_DEBUG_HI_I2C("write %x\n",byte); |
1a0adaf3 HV |
308 | for (i = 0; i < 8; ++i, byte<<=1) { |
309 | ivtv_setscl(itv, 0); | |
310 | if (!ivtv_waitscl(itv, 0)) { | |
311 | IVTV_DEBUG_I2C("Error setting SCL low\n"); | |
312 | return -EREMOTEIO; | |
313 | } | |
314 | bit = (byte>>7)&1; | |
315 | ivtv_setsda(itv, bit); | |
316 | if (!ivtv_waitsda(itv, bit)) { | |
317 | IVTV_DEBUG_I2C("Error setting SDA\n"); | |
318 | return -EREMOTEIO; | |
319 | } | |
320 | ivtv_setscl(itv, 1); | |
321 | if (!ivtv_waitscl(itv, 1)) { | |
322 | IVTV_DEBUG_I2C("Slave not ready for bit\n"); | |
323 | return -EREMOTEIO; | |
324 | } | |
325 | } | |
326 | ivtv_setscl(itv, 0); | |
327 | if (!ivtv_waitscl(itv, 0)) { | |
328 | IVTV_DEBUG_I2C("Error setting SCL low\n"); | |
329 | return -EREMOTEIO; | |
330 | } | |
331 | return ivtv_ack(itv); | |
332 | } | |
333 | ||
334 | /* Read a byte from the i2c bus and send a NACK if applicable (i.e. for the | |
335 | final byte) */ | |
336 | static int ivtv_readbyte(struct ivtv *itv, unsigned char *byte, int nack) | |
337 | { | |
338 | int i; | |
339 | ||
340 | *byte = 0; | |
341 | ||
342 | ivtv_setsda(itv, 1); | |
343 | ivtv_scldelay(itv); | |
344 | for (i = 0; i < 8; ++i) { | |
345 | ivtv_setscl(itv, 0); | |
346 | ivtv_scldelay(itv); | |
347 | ivtv_setscl(itv, 1); | |
348 | if (!ivtv_waitscl(itv, 1)) { | |
349 | IVTV_DEBUG_I2C("Error setting SCL high\n"); | |
350 | return -EREMOTEIO; | |
351 | } | |
352 | *byte = ((*byte)<<1)|ivtv_getsda(itv); | |
353 | } | |
354 | ivtv_setscl(itv, 0); | |
355 | ivtv_scldelay(itv); | |
356 | ivtv_setsda(itv, nack); | |
357 | ivtv_scldelay(itv); | |
358 | ivtv_setscl(itv, 1); | |
359 | ivtv_scldelay(itv); | |
360 | ivtv_setscl(itv, 0); | |
361 | ivtv_scldelay(itv); | |
11d28766 | 362 | IVTV_DEBUG_HI_I2C("read %x\n",*byte); |
1a0adaf3 HV |
363 | return 0; |
364 | } | |
365 | ||
366 | /* Issue a start condition on the i2c bus to alert slaves to prepare for | |
367 | an address write */ | |
368 | static int ivtv_start(struct ivtv *itv) | |
369 | { | |
370 | int sda; | |
371 | ||
372 | sda = ivtv_getsda(itv); | |
373 | if (sda != 1) { | |
11d28766 | 374 | IVTV_DEBUG_HI_I2C("SDA was low at start\n"); |
1a0adaf3 HV |
375 | ivtv_setsda(itv, 1); |
376 | if (!ivtv_waitsda(itv, 1)) { | |
377 | IVTV_DEBUG_I2C("SDA stuck low\n"); | |
378 | return -EREMOTEIO; | |
379 | } | |
380 | } | |
381 | if (ivtv_getscl(itv) != 1) { | |
382 | ivtv_setscl(itv, 1); | |
383 | if (!ivtv_waitscl(itv, 1)) { | |
384 | IVTV_DEBUG_I2C("SCL stuck low at start\n"); | |
385 | return -EREMOTEIO; | |
386 | } | |
387 | } | |
388 | ivtv_setsda(itv, 0); | |
389 | ivtv_scldelay(itv); | |
390 | return 0; | |
391 | } | |
392 | ||
393 | /* Issue a stop condition on the i2c bus to release it */ | |
394 | static int ivtv_stop(struct ivtv *itv) | |
395 | { | |
396 | int i; | |
397 | ||
398 | if (ivtv_getscl(itv) != 0) { | |
11d28766 | 399 | IVTV_DEBUG_HI_I2C("SCL not low when stopping\n"); |
1a0adaf3 HV |
400 | ivtv_setscl(itv, 0); |
401 | if (!ivtv_waitscl(itv, 0)) { | |
402 | IVTV_DEBUG_I2C("SCL could not be set low\n"); | |
403 | } | |
404 | } | |
405 | ivtv_setsda(itv, 0); | |
406 | ivtv_scldelay(itv); | |
407 | ivtv_setscl(itv, 1); | |
408 | if (!ivtv_waitscl(itv, 1)) { | |
409 | IVTV_DEBUG_I2C("SCL could not be set high\n"); | |
410 | return -EREMOTEIO; | |
411 | } | |
412 | ivtv_scldelay(itv); | |
413 | ivtv_setsda(itv, 1); | |
414 | if (!ivtv_waitsda(itv, 1)) { | |
415 | IVTV_DEBUG_I2C("resetting I2C\n"); | |
416 | for (i = 0; i < 16; ++i) { | |
417 | ivtv_setscl(itv, 0); | |
418 | ivtv_scldelay(itv); | |
419 | ivtv_setscl(itv, 1); | |
420 | ivtv_scldelay(itv); | |
421 | ivtv_setsda(itv, 1); | |
422 | } | |
423 | ivtv_waitsda(itv, 1); | |
424 | return -EREMOTEIO; | |
425 | } | |
426 | return 0; | |
427 | } | |
428 | ||
429 | /* Write a message to the given i2c slave. do_stop may be 0 to prevent | |
430 | issuing the i2c stop condition (when following with a read) */ | |
431 | static int ivtv_write(struct ivtv *itv, unsigned char addr, unsigned char *data, u32 len, int do_stop) | |
432 | { | |
433 | int retry, ret = -EREMOTEIO; | |
434 | u32 i; | |
435 | ||
436 | for (retry = 0; ret != 0 && retry < 8; ++retry) { | |
437 | ret = ivtv_start(itv); | |
438 | ||
439 | if (ret == 0) { | |
440 | ret = ivtv_sendbyte(itv, addr<<1); | |
441 | for (i = 0; ret == 0 && i < len; ++i) | |
442 | ret = ivtv_sendbyte(itv, data[i]); | |
443 | } | |
444 | if (ret != 0 || do_stop) { | |
445 | ivtv_stop(itv); | |
446 | } | |
447 | } | |
448 | if (ret) | |
449 | IVTV_DEBUG_I2C("i2c write to %x failed\n", addr); | |
450 | return ret; | |
451 | } | |
452 | ||
453 | /* Read data from the given i2c slave. A stop condition is always issued. */ | |
454 | static int ivtv_read(struct ivtv *itv, unsigned char addr, unsigned char *data, u32 len) | |
455 | { | |
456 | int retry, ret = -EREMOTEIO; | |
457 | u32 i; | |
458 | ||
459 | for (retry = 0; ret != 0 && retry < 8; ++retry) { | |
460 | ret = ivtv_start(itv); | |
461 | if (ret == 0) | |
462 | ret = ivtv_sendbyte(itv, (addr << 1) | 1); | |
463 | for (i = 0; ret == 0 && i < len; ++i) { | |
464 | ret = ivtv_readbyte(itv, &data[i], i == len - 1); | |
465 | } | |
466 | ivtv_stop(itv); | |
467 | } | |
468 | if (ret) | |
469 | IVTV_DEBUG_I2C("i2c read from %x failed\n", addr); | |
470 | return ret; | |
471 | } | |
472 | ||
473 | /* Kernel i2c transfer implementation. Takes a number of messages to be read | |
474 | or written. If a read follows a write, this will occur without an | |
475 | intervening stop condition */ | |
476 | static int ivtv_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) | |
477 | { | |
8ac05ae3 HV |
478 | struct v4l2_device *v4l2_dev = i2c_get_adapdata(i2c_adap); |
479 | struct ivtv *itv = to_ivtv(v4l2_dev); | |
1a0adaf3 HV |
480 | int retval; |
481 | int i; | |
482 | ||
483 | mutex_lock(&itv->i2c_bus_lock); | |
484 | for (i = retval = 0; retval == 0 && i < num; i++) { | |
485 | if (msgs[i].flags & I2C_M_RD) | |
486 | retval = ivtv_read(itv, msgs[i].addr, msgs[i].buf, msgs[i].len); | |
487 | else { | |
488 | /* if followed by a read, don't stop */ | |
489 | int stop = !(i + 1 < num && msgs[i + 1].flags == I2C_M_RD); | |
490 | ||
491 | retval = ivtv_write(itv, msgs[i].addr, msgs[i].buf, msgs[i].len, stop); | |
492 | } | |
493 | } | |
494 | mutex_unlock(&itv->i2c_bus_lock); | |
495 | return retval ? retval : num; | |
496 | } | |
497 | ||
498 | /* Kernel i2c capabilities */ | |
499 | static u32 ivtv_functionality(struct i2c_adapter *adap) | |
500 | { | |
501 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
502 | } | |
503 | ||
504 | static struct i2c_algorithm ivtv_algo = { | |
505 | .master_xfer = ivtv_xfer, | |
506 | .functionality = ivtv_functionality, | |
507 | }; | |
508 | ||
509 | /* template for our-bit banger */ | |
510 | static struct i2c_adapter ivtv_i2c_adap_hw_template = { | |
511 | .name = "ivtv i2c driver", | |
1a0adaf3 HV |
512 | .algo = &ivtv_algo, |
513 | .algo_data = NULL, /* filled from template */ | |
1a0adaf3 | 514 | .owner = THIS_MODULE, |
1a0adaf3 HV |
515 | }; |
516 | ||
517 | static void ivtv_setscl_old(void *data, int state) | |
518 | { | |
519 | struct ivtv *itv = (struct ivtv *)data; | |
520 | ||
521 | if (state) | |
522 | itv->i2c_state |= 0x01; | |
523 | else | |
524 | itv->i2c_state &= ~0x01; | |
525 | ||
526 | /* write them out */ | |
527 | /* write bits are inverted */ | |
528 | write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSCL_OFFSET); | |
529 | } | |
530 | ||
531 | static void ivtv_setsda_old(void *data, int state) | |
532 | { | |
533 | struct ivtv *itv = (struct ivtv *)data; | |
534 | ||
535 | if (state) | |
536 | itv->i2c_state |= 0x01; | |
537 | else | |
538 | itv->i2c_state &= ~0x01; | |
539 | ||
540 | /* write them out */ | |
541 | /* write bits are inverted */ | |
542 | write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSDA_OFFSET); | |
543 | } | |
544 | ||
545 | static int ivtv_getscl_old(void *data) | |
546 | { | |
547 | struct ivtv *itv = (struct ivtv *)data; | |
548 | ||
549 | return read_reg(IVTV_REG_I2C_GETSCL_OFFSET) & 1; | |
550 | } | |
551 | ||
552 | static int ivtv_getsda_old(void *data) | |
553 | { | |
554 | struct ivtv *itv = (struct ivtv *)data; | |
555 | ||
556 | return read_reg(IVTV_REG_I2C_GETSDA_OFFSET) & 1; | |
557 | } | |
558 | ||
559 | /* template for i2c-bit-algo */ | |
560 | static struct i2c_adapter ivtv_i2c_adap_template = { | |
561 | .name = "ivtv i2c driver", | |
1a0adaf3 HV |
562 | .algo = NULL, /* set by i2c-algo-bit */ |
563 | .algo_data = NULL, /* filled from template */ | |
1a0adaf3 | 564 | .owner = THIS_MODULE, |
1a0adaf3 HV |
565 | }; |
566 | ||
aeb292d1 JD |
567 | static const struct i2c_algo_bit_data ivtv_i2c_algo_template = { |
568 | .setsda = ivtv_setsda_old, | |
569 | .setscl = ivtv_setscl_old, | |
570 | .getsda = ivtv_getsda_old, | |
571 | .getscl = ivtv_getscl_old, | |
89dab357 | 572 | .udelay = 10, |
aeb292d1 | 573 | .timeout = 200, |
1a0adaf3 HV |
574 | }; |
575 | ||
576 | static struct i2c_client ivtv_i2c_client_template = { | |
a415783b | 577 | .name = "ivtv internal", |
1a0adaf3 HV |
578 | }; |
579 | ||
c668f32d | 580 | /* init + register i2c adapter + instantiate IR receiver */ |
056827a4 | 581 | int init_ivtv_i2c(struct ivtv *itv) |
1a0adaf3 | 582 | { |
c668f32d JD |
583 | int retval; |
584 | ||
1a0adaf3 HV |
585 | IVTV_DEBUG_I2C("i2c init\n"); |
586 | ||
d9009201 HV |
587 | /* Sanity checks for the I2C hardware arrays. They must be the |
588 | * same size and GPIO must be the last entry. | |
589 | */ | |
67ec09fd HV |
590 | if (ARRAY_SIZE(hw_devicenames) != ARRAY_SIZE(hw_addrs) || |
591 | ARRAY_SIZE(hw_devicenames) != ARRAY_SIZE(hw_modules) || | |
592 | IVTV_HW_GPIO != (1 << (ARRAY_SIZE(hw_addrs) - 1))) { | |
d9009201 HV |
593 | IVTV_ERR("Mismatched I2C hardware arrays\n"); |
594 | return -ENODEV; | |
595 | } | |
1a0adaf3 HV |
596 | if (itv->options.newi2c > 0) { |
597 | memcpy(&itv->i2c_adap, &ivtv_i2c_adap_hw_template, | |
598 | sizeof(struct i2c_adapter)); | |
599 | } else { | |
600 | memcpy(&itv->i2c_adap, &ivtv_i2c_adap_template, | |
601 | sizeof(struct i2c_adapter)); | |
602 | memcpy(&itv->i2c_algo, &ivtv_i2c_algo_template, | |
603 | sizeof(struct i2c_algo_bit_data)); | |
1a0adaf3 | 604 | } |
0e614cd1 HV |
605 | itv->i2c_algo.data = itv; |
606 | itv->i2c_adap.algo_data = &itv->i2c_algo; | |
1a0adaf3 HV |
607 | |
608 | sprintf(itv->i2c_adap.name + strlen(itv->i2c_adap.name), " #%d", | |
67ec09fd | 609 | itv->instance); |
8ac05ae3 | 610 | i2c_set_adapdata(&itv->i2c_adap, &itv->v4l2_dev); |
1a0adaf3 HV |
611 | |
612 | memcpy(&itv->i2c_client, &ivtv_i2c_client_template, | |
613 | sizeof(struct i2c_client)); | |
614 | itv->i2c_client.adapter = &itv->i2c_adap; | |
8ac05ae3 | 615 | itv->i2c_adap.dev.parent = &itv->pdev->dev; |
1a0adaf3 HV |
616 | |
617 | IVTV_DEBUG_I2C("setting scl and sda to 1\n"); | |
618 | ivtv_setscl(itv, 1); | |
619 | ivtv_setsda(itv, 1); | |
620 | ||
621 | if (itv->options.newi2c > 0) | |
c668f32d | 622 | retval = i2c_add_adapter(&itv->i2c_adap); |
1a0adaf3 | 623 | else |
c668f32d JD |
624 | retval = i2c_bit_add_bus(&itv->i2c_adap); |
625 | ||
626 | /* Instantiate the IR receiver device, if present */ | |
627 | if (retval == 0) { | |
628 | struct i2c_board_info info; | |
629 | /* The external IR receiver is at i2c address 0x34 (0x35 for | |
630 | reads). Future Hauppauge cards will have an internal | |
631 | receiver at 0x30 (0x31 for reads). In theory, both can be | |
632 | fitted, and Hauppauge suggest an external overrides an | |
633 | internal. | |
634 | ||
635 | That's why we probe 0x1a (~0x34) first. CB | |
636 | */ | |
637 | const unsigned short addr_list[] = { | |
20b0ead5 JD |
638 | 0x1a, /* Hauppauge IR external */ |
639 | 0x18, /* Hauppauge IR internal */ | |
640 | 0x71, /* Hauppauge IR (PVR150) */ | |
641 | 0x64, /* Pixelview IR */ | |
642 | 0x30, /* KNC ONE IR */ | |
643 | 0x6b, /* Adaptec IR */ | |
c668f32d JD |
644 | I2C_CLIENT_END |
645 | }; | |
646 | ||
647 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
648 | strlcpy(info.type, "ir_video", I2C_NAME_SIZE); | |
649 | i2c_new_probed_device(&itv->i2c_adap, &info, addr_list); | |
650 | } | |
651 | ||
652 | return retval; | |
1a0adaf3 HV |
653 | } |
654 | ||
bb374b7b | 655 | void exit_ivtv_i2c(struct ivtv *itv) |
1a0adaf3 HV |
656 | { |
657 | IVTV_DEBUG_I2C("i2c exit\n"); | |
658 | ||
659 | i2c_del_adapter(&itv->i2c_adap); | |
660 | } |