Commit | Line | Data |
---|---|---|
77110abb | 1 | /* |
c8cf078e | 2 | * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina |
77110abb RJ |
3 | * |
4 | * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/videodev2.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/i2c.h> | |
13 | #include <linux/log2.h> | |
14 | #include <linux/gpio.h> | |
15 | #include <linux/delay.h> | |
16 | ||
0c0b446d GL |
17 | #include <media/soc_camera.h> |
18 | #include <media/soc_mediabus.h> | |
77110abb | 19 | #include <media/v4l2-common.h> |
af8425c5 | 20 | #include <media/v4l2-ctrls.h> |
77110abb | 21 | #include <media/v4l2-chip-ident.h> |
77110abb RJ |
22 | |
23 | /* | |
c8cf078e PW |
24 | * MT9M111, MT9M112 and MT9M131: |
25 | * i2c address is 0x48 or 0x5d (depending on SADDR pin) | |
77110abb RJ |
26 | * The platform has to define i2c_board_info and call i2c_register_board_info() |
27 | */ | |
28 | ||
c8cf078e PW |
29 | /* |
30 | * Sensor core register addresses (0x000..0x0ff) | |
31 | */ | |
77110abb RJ |
32 | #define MT9M111_CHIP_VERSION 0x000 |
33 | #define MT9M111_ROW_START 0x001 | |
34 | #define MT9M111_COLUMN_START 0x002 | |
35 | #define MT9M111_WINDOW_HEIGHT 0x003 | |
36 | #define MT9M111_WINDOW_WIDTH 0x004 | |
37 | #define MT9M111_HORIZONTAL_BLANKING_B 0x005 | |
38 | #define MT9M111_VERTICAL_BLANKING_B 0x006 | |
39 | #define MT9M111_HORIZONTAL_BLANKING_A 0x007 | |
40 | #define MT9M111_VERTICAL_BLANKING_A 0x008 | |
41 | #define MT9M111_SHUTTER_WIDTH 0x009 | |
42 | #define MT9M111_ROW_SPEED 0x00a | |
43 | #define MT9M111_EXTRA_DELAY 0x00b | |
44 | #define MT9M111_SHUTTER_DELAY 0x00c | |
45 | #define MT9M111_RESET 0x00d | |
46 | #define MT9M111_READ_MODE_B 0x020 | |
47 | #define MT9M111_READ_MODE_A 0x021 | |
48 | #define MT9M111_FLASH_CONTROL 0x023 | |
49 | #define MT9M111_GREEN1_GAIN 0x02b | |
50 | #define MT9M111_BLUE_GAIN 0x02c | |
51 | #define MT9M111_RED_GAIN 0x02d | |
52 | #define MT9M111_GREEN2_GAIN 0x02e | |
53 | #define MT9M111_GLOBAL_GAIN 0x02f | |
54 | #define MT9M111_CONTEXT_CONTROL 0x0c8 | |
55 | #define MT9M111_PAGE_MAP 0x0f0 | |
56 | #define MT9M111_BYTE_WISE_ADDR 0x0f1 | |
57 | ||
58 | #define MT9M111_RESET_SYNC_CHANGES (1 << 15) | |
59 | #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9) | |
60 | #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8) | |
61 | #define MT9M111_RESET_RESET_SOC (1 << 5) | |
62 | #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4) | |
63 | #define MT9M111_RESET_CHIP_ENABLE (1 << 3) | |
64 | #define MT9M111_RESET_ANALOG_STANDBY (1 << 2) | |
65 | #define MT9M111_RESET_RESTART_FRAME (1 << 1) | |
66 | #define MT9M111_RESET_RESET_MODE (1 << 0) | |
67 | ||
7c58e7d0 MG |
68 | #define MT9M111_RM_FULL_POWER_RD (0 << 10) |
69 | #define MT9M111_RM_LOW_POWER_RD (1 << 10) | |
70 | #define MT9M111_RM_COL_SKIP_4X (1 << 5) | |
71 | #define MT9M111_RM_ROW_SKIP_4X (1 << 4) | |
72 | #define MT9M111_RM_COL_SKIP_2X (1 << 3) | |
73 | #define MT9M111_RM_ROW_SKIP_2X (1 << 2) | |
77110abb RJ |
74 | #define MT9M111_RMB_MIRROR_COLS (1 << 1) |
75 | #define MT9M111_RMB_MIRROR_ROWS (1 << 0) | |
76 | #define MT9M111_CTXT_CTRL_RESTART (1 << 15) | |
77 | #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12) | |
78 | #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10) | |
79 | #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9) | |
80 | #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8) | |
81 | #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7) | |
82 | #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3) | |
83 | #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2) | |
84 | #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1) | |
85 | #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0) | |
c8cf078e | 86 | |
77110abb | 87 | /* |
c8cf078e | 88 | * Colorpipe register addresses (0x100..0x1ff) |
77110abb RJ |
89 | */ |
90 | #define MT9M111_OPER_MODE_CTRL 0x106 | |
91 | #define MT9M111_OUTPUT_FORMAT_CTRL 0x108 | |
92 | #define MT9M111_REDUCER_XZOOM_B 0x1a0 | |
93 | #define MT9M111_REDUCER_XSIZE_B 0x1a1 | |
94 | #define MT9M111_REDUCER_YZOOM_B 0x1a3 | |
95 | #define MT9M111_REDUCER_YSIZE_B 0x1a4 | |
96 | #define MT9M111_REDUCER_XZOOM_A 0x1a6 | |
97 | #define MT9M111_REDUCER_XSIZE_A 0x1a7 | |
98 | #define MT9M111_REDUCER_YZOOM_A 0x1a9 | |
99 | #define MT9M111_REDUCER_YSIZE_A 0x1aa | |
100 | ||
101 | #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a | |
102 | #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b | |
103 | ||
104 | #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14) | |
39bf372f | 105 | #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1) |
7c58e7d0 MG |
106 | #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9) |
107 | #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8) | |
77110abb RJ |
108 | #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14) |
109 | #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10) | |
110 | #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9) | |
111 | #define MT9M111_OUTFMT_RGB (1 << 8) | |
ec73365b MG |
112 | #define MT9M111_OUTFMT_RGB565 (0 << 6) |
113 | #define MT9M111_OUTFMT_RGB555 (1 << 6) | |
114 | #define MT9M111_OUTFMT_RGB444x (2 << 6) | |
115 | #define MT9M111_OUTFMT_RGBx444 (3 << 6) | |
116 | #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4) | |
117 | #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4) | |
118 | #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4) | |
119 | #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4) | |
77110abb RJ |
120 | #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3) |
121 | #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2) | |
7c58e7d0 MG |
122 | #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1) |
123 | #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0) | |
c8cf078e | 124 | |
77110abb | 125 | /* |
c8cf078e | 126 | * Camera control register addresses (0x200..0x2ff not implemented) |
77110abb RJ |
127 | */ |
128 | ||
9538e1c2 GL |
129 | #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg) |
130 | #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) | |
131 | #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) | |
132 | #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) | |
7c58e7d0 MG |
133 | #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ |
134 | (val), (mask)) | |
77110abb RJ |
135 | |
136 | #define MT9M111_MIN_DARK_ROWS 8 | |
669470a8 | 137 | #define MT9M111_MIN_DARK_COLS 26 |
77110abb RJ |
138 | #define MT9M111_MAX_HEIGHT 1024 |
139 | #define MT9M111_MAX_WIDTH 1280 | |
140 | ||
760697be GL |
141 | /* MT9M111 has only one fixed colorspace per pixelcode */ |
142 | struct mt9m111_datafmt { | |
143 | enum v4l2_mbus_pixelcode code; | |
144 | enum v4l2_colorspace colorspace; | |
145 | }; | |
146 | ||
147 | /* Find a data format by a pixel code in an array */ | |
148 | static const struct mt9m111_datafmt *mt9m111_find_datafmt( | |
149 | enum v4l2_mbus_pixelcode code, const struct mt9m111_datafmt *fmt, | |
150 | int n) | |
151 | { | |
152 | int i; | |
153 | for (i = 0; i < n; i++) | |
154 | if (fmt[i].code == code) | |
155 | return fmt + i; | |
156 | ||
157 | return NULL; | |
158 | } | |
159 | ||
160 | static const struct mt9m111_datafmt mt9m111_colour_fmts[] = { | |
ace6e979 GL |
161 | {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG}, |
162 | {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG}, | |
163 | {V4L2_MBUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG}, | |
164 | {V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG}, | |
760697be | 165 | {V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, |
7c58e7d0 | 166 | {V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB}, |
760697be | 167 | {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB}, |
7c58e7d0 MG |
168 | {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB}, |
169 | {V4L2_MBUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB}, | |
170 | {V4L2_MBUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB}, | |
760697be GL |
171 | {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB}, |
172 | {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, | |
77110abb RJ |
173 | }; |
174 | ||
175 | enum mt9m111_context { | |
176 | HIGHPOWER = 0, | |
177 | LOWPOWER, | |
178 | }; | |
179 | ||
180 | struct mt9m111 { | |
979ea1dd | 181 | struct v4l2_subdev subdev; |
af8425c5 HV |
182 | struct v4l2_ctrl_handler hdl; |
183 | struct v4l2_ctrl *gain; | |
c8cf078e PW |
184 | int model; /* V4L2_IDENT_MT9M111 or V4L2_IDENT_MT9M112 code |
185 | * from v4l2-chip-ident.h */ | |
77110abb | 186 | enum mt9m111_context context; |
09e231b3 | 187 | struct v4l2_rect rect; |
14c5ea9b GL |
188 | struct mutex power_lock; /* lock to protect power_count */ |
189 | int power_count; | |
760697be | 190 | const struct mt9m111_datafmt *fmt; |
096b703f | 191 | int lastpage; /* PageMap cache value */ |
77110abb RJ |
192 | unsigned char datawidth; |
193 | unsigned int powered:1; | |
77110abb RJ |
194 | }; |
195 | ||
979ea1dd GL |
196 | static struct mt9m111 *to_mt9m111(const struct i2c_client *client) |
197 | { | |
198 | return container_of(i2c_get_clientdata(client), struct mt9m111, subdev); | |
199 | } | |
200 | ||
77110abb RJ |
201 | static int reg_page_map_set(struct i2c_client *client, const u16 reg) |
202 | { | |
203 | int ret; | |
204 | u16 page; | |
096b703f | 205 | struct mt9m111 *mt9m111 = to_mt9m111(client); |
77110abb RJ |
206 | |
207 | page = (reg >> 8); | |
096b703f | 208 | if (page == mt9m111->lastpage) |
77110abb RJ |
209 | return 0; |
210 | if (page > 2) | |
211 | return -EINVAL; | |
212 | ||
213 | ret = i2c_smbus_write_word_data(client, MT9M111_PAGE_MAP, swab16(page)); | |
506c629a | 214 | if (!ret) |
096b703f | 215 | mt9m111->lastpage = page; |
77110abb RJ |
216 | return ret; |
217 | } | |
218 | ||
9538e1c2 | 219 | static int mt9m111_reg_read(struct i2c_client *client, const u16 reg) |
77110abb | 220 | { |
77110abb RJ |
221 | int ret; |
222 | ||
223 | ret = reg_page_map_set(client, reg); | |
224 | if (!ret) | |
6a6c8786 | 225 | ret = swab16(i2c_smbus_read_word_data(client, reg & 0xff)); |
77110abb | 226 | |
9538e1c2 | 227 | dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret); |
77110abb RJ |
228 | return ret; |
229 | } | |
230 | ||
9538e1c2 | 231 | static int mt9m111_reg_write(struct i2c_client *client, const u16 reg, |
77110abb RJ |
232 | const u16 data) |
233 | { | |
77110abb RJ |
234 | int ret; |
235 | ||
236 | ret = reg_page_map_set(client, reg); | |
506c629a | 237 | if (!ret) |
40e2e092 | 238 | ret = i2c_smbus_write_word_data(client, reg & 0xff, |
77110abb | 239 | swab16(data)); |
9538e1c2 | 240 | dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret); |
77110abb RJ |
241 | return ret; |
242 | } | |
243 | ||
9538e1c2 | 244 | static int mt9m111_reg_set(struct i2c_client *client, const u16 reg, |
77110abb RJ |
245 | const u16 data) |
246 | { | |
247 | int ret; | |
248 | ||
9538e1c2 | 249 | ret = mt9m111_reg_read(client, reg); |
77110abb | 250 | if (ret >= 0) |
9538e1c2 | 251 | ret = mt9m111_reg_write(client, reg, ret | data); |
77110abb RJ |
252 | return ret; |
253 | } | |
254 | ||
9538e1c2 | 255 | static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg, |
77110abb RJ |
256 | const u16 data) |
257 | { | |
258 | int ret; | |
259 | ||
9538e1c2 | 260 | ret = mt9m111_reg_read(client, reg); |
9c56cbf9 MG |
261 | if (ret >= 0) |
262 | ret = mt9m111_reg_write(client, reg, ret & ~data); | |
263 | return ret; | |
77110abb RJ |
264 | } |
265 | ||
7c58e7d0 MG |
266 | static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg, |
267 | const u16 data, const u16 mask) | |
268 | { | |
269 | int ret; | |
270 | ||
271 | ret = mt9m111_reg_read(client, reg); | |
272 | if (ret >= 0) | |
273 | ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data); | |
274 | return ret; | |
275 | } | |
276 | ||
2768cbbb | 277 | static int mt9m111_set_context(struct mt9m111 *mt9m111, |
77110abb RJ |
278 | enum mt9m111_context ctxt) |
279 | { | |
2768cbbb | 280 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
281 | int valB = MT9M111_CTXT_CTRL_RESTART | MT9M111_CTXT_CTRL_DEFECTCOR_B |
282 | | MT9M111_CTXT_CTRL_RESIZE_B | MT9M111_CTXT_CTRL_CTRL2_B | |
283 | | MT9M111_CTXT_CTRL_GAMMA_B | MT9M111_CTXT_CTRL_READ_MODE_B | |
284 | | MT9M111_CTXT_CTRL_VBLANK_SEL_B | |
285 | | MT9M111_CTXT_CTRL_HBLANK_SEL_B; | |
286 | int valA = MT9M111_CTXT_CTRL_RESTART; | |
287 | ||
288 | if (ctxt == HIGHPOWER) | |
289 | return reg_write(CONTEXT_CONTROL, valB); | |
290 | else | |
291 | return reg_write(CONTEXT_CONTROL, valA); | |
292 | } | |
293 | ||
2768cbbb | 294 | static int mt9m111_setup_rect(struct mt9m111 *mt9m111, |
09e231b3 | 295 | struct v4l2_rect *rect) |
77110abb | 296 | { |
2768cbbb | 297 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
506c629a | 298 | int ret, is_raw_format; |
09e231b3 GL |
299 | int width = rect->width; |
300 | int height = rect->height; | |
77110abb | 301 | |
760697be GL |
302 | if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 || |
303 | mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) | |
77110abb RJ |
304 | is_raw_format = 1; |
305 | else | |
306 | is_raw_format = 0; | |
307 | ||
09e231b3 | 308 | ret = reg_write(COLUMN_START, rect->left); |
506c629a | 309 | if (!ret) |
09e231b3 | 310 | ret = reg_write(ROW_START, rect->top); |
77110abb RJ |
311 | |
312 | if (is_raw_format) { | |
506c629a | 313 | if (!ret) |
77110abb | 314 | ret = reg_write(WINDOW_WIDTH, width); |
506c629a | 315 | if (!ret) |
77110abb RJ |
316 | ret = reg_write(WINDOW_HEIGHT, height); |
317 | } else { | |
506c629a | 318 | if (!ret) |
77110abb | 319 | ret = reg_write(REDUCER_XZOOM_B, MT9M111_MAX_WIDTH); |
506c629a | 320 | if (!ret) |
77110abb | 321 | ret = reg_write(REDUCER_YZOOM_B, MT9M111_MAX_HEIGHT); |
506c629a | 322 | if (!ret) |
77110abb | 323 | ret = reg_write(REDUCER_XSIZE_B, width); |
506c629a | 324 | if (!ret) |
77110abb | 325 | ret = reg_write(REDUCER_YSIZE_B, height); |
506c629a | 326 | if (!ret) |
77110abb | 327 | ret = reg_write(REDUCER_XZOOM_A, MT9M111_MAX_WIDTH); |
506c629a | 328 | if (!ret) |
77110abb | 329 | ret = reg_write(REDUCER_YZOOM_A, MT9M111_MAX_HEIGHT); |
506c629a | 330 | if (!ret) |
77110abb | 331 | ret = reg_write(REDUCER_XSIZE_A, width); |
506c629a | 332 | if (!ret) |
77110abb RJ |
333 | ret = reg_write(REDUCER_YSIZE_A, height); |
334 | } | |
335 | ||
336 | return ret; | |
337 | } | |
338 | ||
2768cbbb | 339 | static int mt9m111_enable(struct mt9m111 *mt9m111) |
77110abb | 340 | { |
2768cbbb | 341 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
342 | int ret; |
343 | ||
344 | ret = reg_set(RESET, MT9M111_RESET_CHIP_ENABLE); | |
506c629a | 345 | if (!ret) |
77110abb RJ |
346 | mt9m111->powered = 1; |
347 | return ret; | |
348 | } | |
349 | ||
2768cbbb | 350 | static int mt9m111_reset(struct mt9m111 *mt9m111) |
77110abb | 351 | { |
2768cbbb | 352 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
353 | int ret; |
354 | ||
355 | ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); | |
506c629a | 356 | if (!ret) |
77110abb | 357 | ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); |
506c629a | 358 | if (!ret) |
77110abb RJ |
359 | ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE |
360 | | MT9M111_RESET_RESET_SOC); | |
afb13683 | 361 | |
77110abb RJ |
362 | return ret; |
363 | } | |
364 | ||
2768cbbb | 365 | static int mt9m111_make_rect(struct mt9m111 *mt9m111, |
6a6c8786 GL |
366 | struct v4l2_rect *rect) |
367 | { | |
760697be GL |
368 | if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 || |
369 | mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) { | |
6a6c8786 GL |
370 | /* Bayer format - even size lengths */ |
371 | rect->width = ALIGN(rect->width, 2); | |
372 | rect->height = ALIGN(rect->height, 2); | |
373 | /* Let the user play with the starting pixel */ | |
374 | } | |
375 | ||
376 | /* FIXME: the datasheet doesn't specify minimum sizes */ | |
377 | soc_camera_limit_side(&rect->left, &rect->width, | |
378 | MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH); | |
379 | ||
380 | soc_camera_limit_side(&rect->top, &rect->height, | |
381 | MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT); | |
382 | ||
2768cbbb | 383 | return mt9m111_setup_rect(mt9m111, rect); |
6a6c8786 GL |
384 | } |
385 | ||
08590b96 | 386 | static int mt9m111_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) |
09e231b3 | 387 | { |
6a6c8786 | 388 | struct v4l2_rect rect = a->c; |
c4ce6d14 | 389 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2768cbbb | 390 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
09e231b3 GL |
391 | int ret; |
392 | ||
85f8be68 | 393 | dev_dbg(&client->dev, "%s left=%d, top=%d, width=%d, height=%d\n", |
6a6c8786 | 394 | __func__, rect.left, rect.top, rect.width, rect.height); |
09e231b3 | 395 | |
6b6d33c7 MG |
396 | if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
397 | return -EINVAL; | |
398 | ||
2768cbbb | 399 | ret = mt9m111_make_rect(mt9m111, &rect); |
09e231b3 | 400 | if (!ret) |
6a6c8786 | 401 | mt9m111->rect = rect; |
09e231b3 GL |
402 | return ret; |
403 | } | |
404 | ||
6a6c8786 GL |
405 | static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) |
406 | { | |
2768cbbb | 407 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
6a6c8786 GL |
408 | |
409 | a->c = mt9m111->rect; | |
410 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) | |
416 | { | |
6b6d33c7 MG |
417 | if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
418 | return -EINVAL; | |
419 | ||
6a6c8786 GL |
420 | a->bounds.left = MT9M111_MIN_DARK_COLS; |
421 | a->bounds.top = MT9M111_MIN_DARK_ROWS; | |
422 | a->bounds.width = MT9M111_MAX_WIDTH; | |
423 | a->bounds.height = MT9M111_MAX_HEIGHT; | |
424 | a->defrect = a->bounds; | |
6a6c8786 GL |
425 | a->pixelaspect.numerator = 1; |
426 | a->pixelaspect.denominator = 1; | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
760697be GL |
431 | static int mt9m111_g_fmt(struct v4l2_subdev *sd, |
432 | struct v4l2_mbus_framefmt *mf) | |
6a6c8786 | 433 | { |
2768cbbb | 434 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
6a6c8786 | 435 | |
760697be GL |
436 | mf->width = mt9m111->rect.width; |
437 | mf->height = mt9m111->rect.height; | |
438 | mf->code = mt9m111->fmt->code; | |
01f5a394 | 439 | mf->colorspace = mt9m111->fmt->colorspace; |
760697be | 440 | mf->field = V4L2_FIELD_NONE; |
6a6c8786 GL |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
2768cbbb | 445 | static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111, |
760697be | 446 | enum v4l2_mbus_pixelcode code) |
77110abb | 447 | { |
7c58e7d0 MG |
448 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
449 | u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | | |
450 | MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB | | |
451 | MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 | | |
452 | MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 | | |
453 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | | |
454 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
506c629a | 455 | int ret; |
77110abb | 456 | |
760697be GL |
457 | switch (code) { |
458 | case V4L2_MBUS_FMT_SBGGR8_1X8: | |
7c58e7d0 MG |
459 | data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | |
460 | MT9M111_OUTFMT_RGB; | |
77110abb | 461 | break; |
760697be | 462 | case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE: |
7c58e7d0 | 463 | data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB; |
77110abb | 464 | break; |
760697be | 465 | case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE: |
7c58e7d0 MG |
466 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 | |
467 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; | |
468 | break; | |
469 | case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE: | |
470 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555; | |
77110abb | 471 | break; |
760697be | 472 | case V4L2_MBUS_FMT_RGB565_2X8_LE: |
7c58e7d0 MG |
473 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | |
474 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; | |
475 | break; | |
476 | case V4L2_MBUS_FMT_RGB565_2X8_BE: | |
477 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565; | |
478 | break; | |
479 | case V4L2_MBUS_FMT_BGR565_2X8_BE: | |
480 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | | |
481 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
482 | break; | |
483 | case V4L2_MBUS_FMT_BGR565_2X8_LE: | |
484 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | | |
485 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | | |
486 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
77110abb | 487 | break; |
ace6e979 | 488 | case V4L2_MBUS_FMT_UYVY8_2X8: |
7c58e7d0 | 489 | data_outfmt2 = 0; |
88f4b899 | 490 | break; |
ace6e979 | 491 | case V4L2_MBUS_FMT_VYUY8_2X8: |
7c58e7d0 | 492 | data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; |
88f4b899 | 493 | break; |
ace6e979 | 494 | case V4L2_MBUS_FMT_YUYV8_2X8: |
7c58e7d0 | 495 | data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; |
88f4b899 | 496 | break; |
ace6e979 | 497 | case V4L2_MBUS_FMT_YVYU8_2X8: |
7c58e7d0 MG |
498 | data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | |
499 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
77110abb RJ |
500 | break; |
501 | default: | |
7c58e7d0 MG |
502 | dev_err(&client->dev, "Pixel format not handled: %x\n", code); |
503 | return -EINVAL; | |
77110abb RJ |
504 | } |
505 | ||
7c58e7d0 MG |
506 | ret = reg_mask(OUTPUT_FORMAT_CTRL2_A, data_outfmt2, |
507 | mask_outfmt2); | |
508 | if (!ret) | |
509 | ret = reg_mask(OUTPUT_FORMAT_CTRL2_B, data_outfmt2, | |
510 | mask_outfmt2); | |
511 | ||
77110abb RJ |
512 | return ret; |
513 | } | |
514 | ||
760697be GL |
515 | static int mt9m111_s_fmt(struct v4l2_subdev *sd, |
516 | struct v4l2_mbus_framefmt *mf) | |
77110abb | 517 | { |
c4ce6d14 | 518 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
760697be | 519 | const struct mt9m111_datafmt *fmt; |
2768cbbb | 520 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
09e231b3 GL |
521 | struct v4l2_rect rect = { |
522 | .left = mt9m111->rect.left, | |
523 | .top = mt9m111->rect.top, | |
760697be GL |
524 | .width = mf->width, |
525 | .height = mf->height, | |
09e231b3 | 526 | }; |
506c629a | 527 | int ret; |
77110abb | 528 | |
760697be GL |
529 | fmt = mt9m111_find_datafmt(mf->code, mt9m111_colour_fmts, |
530 | ARRAY_SIZE(mt9m111_colour_fmts)); | |
531 | if (!fmt) | |
532 | return -EINVAL; | |
533 | ||
96c75399 | 534 | dev_dbg(&client->dev, |
760697be GL |
535 | "%s code=%x left=%d, top=%d, width=%d, height=%d\n", __func__, |
536 | mf->code, rect.left, rect.top, rect.width, rect.height); | |
77110abb | 537 | |
2768cbbb | 538 | ret = mt9m111_make_rect(mt9m111, &rect); |
09e231b3 | 539 | if (!ret) |
2768cbbb | 540 | ret = mt9m111_set_pixfmt(mt9m111, mf->code); |
760697be GL |
541 | if (!ret) { |
542 | mt9m111->rect = rect; | |
543 | mt9m111->fmt = fmt; | |
544 | mf->colorspace = fmt->colorspace; | |
545 | } | |
546 | ||
506c629a | 547 | return ret; |
77110abb RJ |
548 | } |
549 | ||
760697be GL |
550 | static int mt9m111_try_fmt(struct v4l2_subdev *sd, |
551 | struct v4l2_mbus_framefmt *mf) | |
77110abb | 552 | { |
2768cbbb | 553 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
760697be GL |
554 | const struct mt9m111_datafmt *fmt; |
555 | bool bayer = mf->code == V4L2_MBUS_FMT_SBGGR8_1X8 || | |
556 | mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE; | |
557 | ||
558 | fmt = mt9m111_find_datafmt(mf->code, mt9m111_colour_fmts, | |
559 | ARRAY_SIZE(mt9m111_colour_fmts)); | |
560 | if (!fmt) { | |
561 | fmt = mt9m111->fmt; | |
562 | mf->code = fmt->code; | |
563 | } | |
6a6c8786 GL |
564 | |
565 | /* | |
566 | * With Bayer format enforce even side lengths, but let the user play | |
567 | * with the starting pixel | |
568 | */ | |
64f5905e | 569 | |
760697be GL |
570 | if (mf->height > MT9M111_MAX_HEIGHT) |
571 | mf->height = MT9M111_MAX_HEIGHT; | |
572 | else if (mf->height < 2) | |
573 | mf->height = 2; | |
6a6c8786 | 574 | else if (bayer) |
760697be | 575 | mf->height = ALIGN(mf->height, 2); |
6a6c8786 | 576 | |
760697be GL |
577 | if (mf->width > MT9M111_MAX_WIDTH) |
578 | mf->width = MT9M111_MAX_WIDTH; | |
579 | else if (mf->width < 2) | |
580 | mf->width = 2; | |
6a6c8786 | 581 | else if (bayer) |
760697be GL |
582 | mf->width = ALIGN(mf->width, 2); |
583 | ||
584 | mf->colorspace = fmt->colorspace; | |
77110abb RJ |
585 | |
586 | return 0; | |
587 | } | |
588 | ||
979ea1dd GL |
589 | static int mt9m111_g_chip_ident(struct v4l2_subdev *sd, |
590 | struct v4l2_dbg_chip_ident *id) | |
77110abb | 591 | { |
c4ce6d14 | 592 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2768cbbb | 593 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
77110abb | 594 | |
aecde8b5 | 595 | if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR) |
77110abb RJ |
596 | return -EINVAL; |
597 | ||
40e2e092 | 598 | if (id->match.addr != client->addr) |
77110abb RJ |
599 | return -ENODEV; |
600 | ||
601 | id->ident = mt9m111->model; | |
602 | id->revision = 0; | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
979ea1dd GL |
608 | static int mt9m111_g_register(struct v4l2_subdev *sd, |
609 | struct v4l2_dbg_register *reg) | |
77110abb | 610 | { |
c4ce6d14 | 611 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
77110abb | 612 | int val; |
77110abb | 613 | |
aecde8b5 | 614 | if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff) |
77110abb | 615 | return -EINVAL; |
9538e1c2 | 616 | if (reg->match.addr != client->addr) |
77110abb RJ |
617 | return -ENODEV; |
618 | ||
9538e1c2 | 619 | val = mt9m111_reg_read(client, reg->reg); |
aecde8b5 | 620 | reg->size = 2; |
77110abb RJ |
621 | reg->val = (u64)val; |
622 | ||
623 | if (reg->val > 0xffff) | |
624 | return -EIO; | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
979ea1dd GL |
629 | static int mt9m111_s_register(struct v4l2_subdev *sd, |
630 | struct v4l2_dbg_register *reg) | |
77110abb | 631 | { |
c4ce6d14 | 632 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
77110abb | 633 | |
aecde8b5 | 634 | if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff) |
77110abb RJ |
635 | return -EINVAL; |
636 | ||
9538e1c2 | 637 | if (reg->match.addr != client->addr) |
77110abb RJ |
638 | return -ENODEV; |
639 | ||
9538e1c2 | 640 | if (mt9m111_reg_write(client, reg->reg, reg->val) < 0) |
77110abb RJ |
641 | return -EIO; |
642 | ||
643 | return 0; | |
644 | } | |
645 | #endif | |
646 | ||
2768cbbb | 647 | static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask) |
77110abb | 648 | { |
2768cbbb | 649 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
650 | int ret; |
651 | ||
652 | if (mt9m111->context == HIGHPOWER) { | |
653 | if (flip) | |
654 | ret = reg_set(READ_MODE_B, mask); | |
655 | else | |
656 | ret = reg_clear(READ_MODE_B, mask); | |
657 | } else { | |
658 | if (flip) | |
659 | ret = reg_set(READ_MODE_A, mask); | |
660 | else | |
661 | ret = reg_clear(READ_MODE_A, mask); | |
662 | } | |
663 | ||
664 | return ret; | |
665 | } | |
666 | ||
2768cbbb | 667 | static int mt9m111_get_global_gain(struct mt9m111 *mt9m111) |
77110abb | 668 | { |
2768cbbb | 669 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
0f28b793 | 670 | int data; |
77110abb RJ |
671 | |
672 | data = reg_read(GLOBAL_GAIN); | |
673 | if (data >= 0) | |
0f28b793 | 674 | return (data & 0x2f) * (1 << ((data >> 10) & 1)) * |
675 | (1 << ((data >> 9) & 1)); | |
676 | return data; | |
77110abb | 677 | } |
0f28b793 | 678 | |
2768cbbb | 679 | static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain) |
77110abb | 680 | { |
2768cbbb | 681 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
682 | u16 val; |
683 | ||
684 | if (gain > 63 * 2 * 2) | |
685 | return -EINVAL; | |
686 | ||
77110abb RJ |
687 | if ((gain >= 64 * 2) && (gain < 63 * 2 * 2)) |
688 | val = (1 << 10) | (1 << 9) | (gain / 4); | |
689 | else if ((gain >= 64) && (gain < 64 * 2)) | |
506c629a | 690 | val = (1 << 9) | (gain / 2); |
77110abb RJ |
691 | else |
692 | val = gain; | |
693 | ||
694 | return reg_write(GLOBAL_GAIN, val); | |
695 | } | |
696 | ||
2768cbbb | 697 | static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int on) |
77110abb | 698 | { |
2768cbbb | 699 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
700 | |
701 | if (on) | |
af8425c5 HV |
702 | return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); |
703 | return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); | |
77110abb | 704 | } |
39bf372f | 705 | |
2768cbbb | 706 | static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on) |
39bf372f | 707 | { |
2768cbbb | 708 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
39bf372f RJ |
709 | |
710 | if (on) | |
af8425c5 HV |
711 | return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); |
712 | return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); | |
39bf372f RJ |
713 | } |
714 | ||
af8425c5 | 715 | static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl) |
77110abb | 716 | { |
af8425c5 HV |
717 | struct mt9m111 *mt9m111 = container_of(ctrl->handler, |
718 | struct mt9m111, hdl); | |
77110abb RJ |
719 | |
720 | switch (ctrl->id) { | |
721 | case V4L2_CID_VFLIP: | |
af8425c5 | 722 | return mt9m111_set_flip(mt9m111, ctrl->val, |
77110abb | 723 | MT9M111_RMB_MIRROR_ROWS); |
77110abb | 724 | case V4L2_CID_HFLIP: |
af8425c5 | 725 | return mt9m111_set_flip(mt9m111, ctrl->val, |
77110abb | 726 | MT9M111_RMB_MIRROR_COLS); |
77110abb | 727 | case V4L2_CID_GAIN: |
af8425c5 | 728 | return mt9m111_set_global_gain(mt9m111, ctrl->val); |
77110abb | 729 | case V4L2_CID_EXPOSURE_AUTO: |
af8425c5 | 730 | return mt9m111_set_autoexposure(mt9m111, ctrl->val); |
39bf372f | 731 | case V4L2_CID_AUTO_WHITE_BALANCE: |
af8425c5 | 732 | return mt9m111_set_autowhitebalance(mt9m111, ctrl->val); |
77110abb RJ |
733 | } |
734 | ||
af8425c5 | 735 | return -EINVAL; |
77110abb RJ |
736 | } |
737 | ||
14c5ea9b | 738 | static int mt9m111_suspend(struct mt9m111 *mt9m111) |
96c75399 | 739 | { |
af8425c5 | 740 | v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111)); |
96c75399 GL |
741 | |
742 | return 0; | |
743 | } | |
744 | ||
2768cbbb | 745 | static void mt9m111_restore_state(struct mt9m111 *mt9m111) |
77110abb | 746 | { |
2768cbbb GL |
747 | mt9m111_set_context(mt9m111, mt9m111->context); |
748 | mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code); | |
749 | mt9m111_setup_rect(mt9m111, &mt9m111->rect); | |
af8425c5 | 750 | v4l2_ctrl_handler_setup(&mt9m111->hdl); |
77110abb RJ |
751 | } |
752 | ||
14c5ea9b | 753 | static int mt9m111_resume(struct mt9m111 *mt9m111) |
77110abb | 754 | { |
77110abb RJ |
755 | int ret = 0; |
756 | ||
757 | if (mt9m111->powered) { | |
2768cbbb | 758 | ret = mt9m111_enable(mt9m111); |
506c629a | 759 | if (!ret) |
2768cbbb | 760 | ret = mt9m111_reset(mt9m111); |
506c629a | 761 | if (!ret) |
2768cbbb | 762 | mt9m111_restore_state(mt9m111); |
77110abb RJ |
763 | } |
764 | return ret; | |
765 | } | |
766 | ||
2768cbbb | 767 | static int mt9m111_init(struct mt9m111 *mt9m111) |
77110abb | 768 | { |
2768cbbb | 769 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
770 | int ret; |
771 | ||
772 | mt9m111->context = HIGHPOWER; | |
2768cbbb | 773 | ret = mt9m111_enable(mt9m111); |
506c629a | 774 | if (!ret) |
2768cbbb | 775 | ret = mt9m111_reset(mt9m111); |
506c629a | 776 | if (!ret) |
2768cbbb | 777 | ret = mt9m111_set_context(mt9m111, mt9m111->context); |
506c629a | 778 | if (ret) |
c8cf078e | 779 | dev_err(&client->dev, "mt9m111 init failed: %d\n", ret); |
506c629a | 780 | return ret; |
77110abb RJ |
781 | } |
782 | ||
77110abb RJ |
783 | /* |
784 | * Interface active, can use i2c. If it fails, it can indeed mean, that | |
785 | * this wasn't our capture interface, so, we wait for the right one | |
786 | */ | |
14178aa5 | 787 | static int mt9m111_video_probe(struct i2c_client *client) |
77110abb | 788 | { |
979ea1dd | 789 | struct mt9m111 *mt9m111 = to_mt9m111(client); |
77110abb RJ |
790 | s32 data; |
791 | int ret; | |
792 | ||
77110abb RJ |
793 | data = reg_read(CHIP_VERSION); |
794 | ||
795 | switch (data) { | |
c8cf078e | 796 | case 0x143a: /* MT9M111 or MT9M131 */ |
77110abb | 797 | mt9m111->model = V4L2_IDENT_MT9M111; |
c8cf078e PW |
798 | dev_info(&client->dev, |
799 | "Detected a MT9M111/MT9M131 chip ID %x\n", data); | |
d7f83a51 MR |
800 | break; |
801 | case 0x148c: /* MT9M112 */ | |
802 | mt9m111->model = V4L2_IDENT_MT9M112; | |
c8cf078e | 803 | dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data); |
77110abb RJ |
804 | break; |
805 | default: | |
85f8be68 | 806 | dev_err(&client->dev, |
c8cf078e PW |
807 | "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n", |
808 | data); | |
af8425c5 | 809 | return -ENODEV; |
77110abb RJ |
810 | } |
811 | ||
2768cbbb | 812 | ret = mt9m111_init(mt9m111); |
af8425c5 HV |
813 | if (ret) |
814 | return ret; | |
815 | return v4l2_ctrl_handler_setup(&mt9m111->hdl); | |
77110abb RJ |
816 | } |
817 | ||
14c5ea9b GL |
818 | static int mt9m111_s_power(struct v4l2_subdev *sd, int on) |
819 | { | |
820 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); | |
821 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
822 | int ret = 0; | |
823 | ||
824 | mutex_lock(&mt9m111->power_lock); | |
825 | ||
826 | /* | |
827 | * If the power count is modified from 0 to != 0 or from != 0 to 0, | |
828 | * update the power state. | |
829 | */ | |
830 | if (mt9m111->power_count == !on) { | |
831 | if (on) { | |
832 | ret = mt9m111_resume(mt9m111); | |
833 | if (ret) { | |
834 | dev_err(&client->dev, | |
835 | "Failed to resume the sensor: %d\n", ret); | |
836 | goto out; | |
837 | } | |
838 | } else { | |
839 | mt9m111_suspend(mt9m111); | |
840 | } | |
841 | } | |
842 | ||
843 | /* Update the power count. */ | |
844 | mt9m111->power_count += on ? 1 : -1; | |
845 | WARN_ON(mt9m111->power_count < 0); | |
846 | ||
847 | out: | |
848 | mutex_unlock(&mt9m111->power_lock); | |
849 | return ret; | |
850 | } | |
851 | ||
af8425c5 HV |
852 | static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = { |
853 | .s_ctrl = mt9m111_s_ctrl, | |
854 | }; | |
855 | ||
979ea1dd | 856 | static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = { |
979ea1dd | 857 | .g_chip_ident = mt9m111_g_chip_ident, |
14c5ea9b | 858 | .s_power = mt9m111_s_power, |
979ea1dd GL |
859 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
860 | .g_register = mt9m111_g_register, | |
861 | .s_register = mt9m111_s_register, | |
862 | #endif | |
863 | }; | |
864 | ||
3805f201 | 865 | static int mt9m111_enum_fmt(struct v4l2_subdev *sd, unsigned int index, |
760697be GL |
866 | enum v4l2_mbus_pixelcode *code) |
867 | { | |
3805f201 | 868 | if (index >= ARRAY_SIZE(mt9m111_colour_fmts)) |
760697be GL |
869 | return -EINVAL; |
870 | ||
871 | *code = mt9m111_colour_fmts[index].code; | |
872 | return 0; | |
873 | } | |
874 | ||
0c0b446d GL |
875 | static int mt9m111_g_mbus_config(struct v4l2_subdev *sd, |
876 | struct v4l2_mbus_config *cfg) | |
877 | { | |
878 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
14178aa5 | 879 | struct soc_camera_link *icl = soc_camera_i2c_to_link(client); |
0c0b446d GL |
880 | |
881 | cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
882 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
883 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
884 | cfg->type = V4L2_MBUS_PARALLEL; | |
885 | cfg->flags = soc_camera_apply_board_flags(icl, cfg); | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
979ea1dd | 890 | static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = { |
760697be GL |
891 | .s_mbus_fmt = mt9m111_s_fmt, |
892 | .g_mbus_fmt = mt9m111_g_fmt, | |
893 | .try_mbus_fmt = mt9m111_try_fmt, | |
08590b96 | 894 | .s_crop = mt9m111_s_crop, |
6a6c8786 GL |
895 | .g_crop = mt9m111_g_crop, |
896 | .cropcap = mt9m111_cropcap, | |
760697be | 897 | .enum_mbus_fmt = mt9m111_enum_fmt, |
0c0b446d | 898 | .g_mbus_config = mt9m111_g_mbus_config, |
979ea1dd GL |
899 | }; |
900 | ||
901 | static struct v4l2_subdev_ops mt9m111_subdev_ops = { | |
902 | .core = &mt9m111_subdev_core_ops, | |
903 | .video = &mt9m111_subdev_video_ops, | |
904 | }; | |
905 | ||
77110abb RJ |
906 | static int mt9m111_probe(struct i2c_client *client, |
907 | const struct i2c_device_id *did) | |
908 | { | |
909 | struct mt9m111 *mt9m111; | |
77110abb | 910 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
14178aa5 | 911 | struct soc_camera_link *icl = soc_camera_i2c_to_link(client); |
77110abb RJ |
912 | int ret; |
913 | ||
914 | if (!icl) { | |
c8cf078e | 915 | dev_err(&client->dev, "mt9m111: driver needs platform data\n"); |
77110abb RJ |
916 | return -EINVAL; |
917 | } | |
918 | ||
919 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { | |
920 | dev_warn(&adapter->dev, | |
921 | "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); | |
922 | return -EIO; | |
923 | } | |
924 | ||
925 | mt9m111 = kzalloc(sizeof(struct mt9m111), GFP_KERNEL); | |
926 | if (!mt9m111) | |
927 | return -ENOMEM; | |
928 | ||
979ea1dd | 929 | v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops); |
af8425c5 HV |
930 | v4l2_ctrl_handler_init(&mt9m111->hdl, 5); |
931 | v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
932 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
933 | v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
934 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
935 | v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
936 | V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); | |
937 | mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
938 | V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32); | |
939 | v4l2_ctrl_new_std_menu(&mt9m111->hdl, | |
940 | &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0, | |
941 | V4L2_EXPOSURE_AUTO); | |
942 | mt9m111->subdev.ctrl_handler = &mt9m111->hdl; | |
943 | if (mt9m111->hdl.error) { | |
944 | int err = mt9m111->hdl.error; | |
77110abb | 945 | |
af8425c5 HV |
946 | kfree(mt9m111); |
947 | return err; | |
948 | } | |
77110abb | 949 | |
af8425c5 | 950 | /* Second stage probe - when a capture adapter is there */ |
6a6c8786 GL |
951 | mt9m111->rect.left = MT9M111_MIN_DARK_COLS; |
952 | mt9m111->rect.top = MT9M111_MIN_DARK_ROWS; | |
953 | mt9m111->rect.width = MT9M111_MAX_WIDTH; | |
954 | mt9m111->rect.height = MT9M111_MAX_HEIGHT; | |
760697be | 955 | mt9m111->fmt = &mt9m111_colour_fmts[0]; |
14178aa5 | 956 | mt9m111->lastpage = -1; |
6a6c8786 | 957 | |
14178aa5 | 958 | ret = mt9m111_video_probe(client); |
40e2e092 | 959 | if (ret) { |
af8425c5 | 960 | v4l2_ctrl_handler_free(&mt9m111->hdl); |
40e2e092 GL |
961 | kfree(mt9m111); |
962 | } | |
77110abb | 963 | |
77110abb RJ |
964 | return ret; |
965 | } | |
966 | ||
967 | static int mt9m111_remove(struct i2c_client *client) | |
968 | { | |
979ea1dd | 969 | struct mt9m111 *mt9m111 = to_mt9m111(client); |
40e2e092 | 970 | |
af8425c5 HV |
971 | v4l2_device_unregister_subdev(&mt9m111->subdev); |
972 | v4l2_ctrl_handler_free(&mt9m111->hdl); | |
77110abb RJ |
973 | kfree(mt9m111); |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | static const struct i2c_device_id mt9m111_id[] = { | |
979 | { "mt9m111", 0 }, | |
980 | { } | |
981 | }; | |
982 | MODULE_DEVICE_TABLE(i2c, mt9m111_id); | |
983 | ||
984 | static struct i2c_driver mt9m111_i2c_driver = { | |
985 | .driver = { | |
986 | .name = "mt9m111", | |
987 | }, | |
988 | .probe = mt9m111_probe, | |
989 | .remove = mt9m111_remove, | |
990 | .id_table = mt9m111_id, | |
991 | }; | |
992 | ||
993 | static int __init mt9m111_mod_init(void) | |
994 | { | |
995 | return i2c_add_driver(&mt9m111_i2c_driver); | |
996 | } | |
997 | ||
998 | static void __exit mt9m111_mod_exit(void) | |
999 | { | |
1000 | i2c_del_driver(&mt9m111_i2c_driver); | |
1001 | } | |
1002 | ||
1003 | module_init(mt9m111_mod_init); | |
1004 | module_exit(mt9m111_mod_exit); | |
1005 | ||
c8cf078e | 1006 | MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver"); |
77110abb RJ |
1007 | MODULE_AUTHOR("Robert Jarzmik"); |
1008 | MODULE_LICENSE("GPL"); |