[media] mt9m111: power down most circuits when suspended
[deliverable/linux.git] / drivers / media / video / mt9m111.c
CommitLineData
77110abb 1/*
c8cf078e 2 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
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3 *
4 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/videodev2.h>
11#include <linux/slab.h>
12#include <linux/i2c.h>
13#include <linux/log2.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
95d20109 16#include <linux/v4l2-mediabus.h>
7a707b89 17#include <linux/module.h>
77110abb 18
0c0b446d 19#include <media/soc_camera.h>
77110abb 20#include <media/v4l2-common.h>
af8425c5 21#include <media/v4l2-ctrls.h>
77110abb 22#include <media/v4l2-chip-ident.h>
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23
24/*
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25 * MT9M111, MT9M112 and MT9M131:
26 * i2c address is 0x48 or 0x5d (depending on SADDR pin)
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27 * The platform has to define i2c_board_info and call i2c_register_board_info()
28 */
29
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30/*
31 * Sensor core register addresses (0x000..0x0ff)
32 */
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33#define MT9M111_CHIP_VERSION 0x000
34#define MT9M111_ROW_START 0x001
35#define MT9M111_COLUMN_START 0x002
36#define MT9M111_WINDOW_HEIGHT 0x003
37#define MT9M111_WINDOW_WIDTH 0x004
38#define MT9M111_HORIZONTAL_BLANKING_B 0x005
39#define MT9M111_VERTICAL_BLANKING_B 0x006
40#define MT9M111_HORIZONTAL_BLANKING_A 0x007
41#define MT9M111_VERTICAL_BLANKING_A 0x008
42#define MT9M111_SHUTTER_WIDTH 0x009
43#define MT9M111_ROW_SPEED 0x00a
44#define MT9M111_EXTRA_DELAY 0x00b
45#define MT9M111_SHUTTER_DELAY 0x00c
46#define MT9M111_RESET 0x00d
47#define MT9M111_READ_MODE_B 0x020
48#define MT9M111_READ_MODE_A 0x021
49#define MT9M111_FLASH_CONTROL 0x023
50#define MT9M111_GREEN1_GAIN 0x02b
51#define MT9M111_BLUE_GAIN 0x02c
52#define MT9M111_RED_GAIN 0x02d
53#define MT9M111_GREEN2_GAIN 0x02e
54#define MT9M111_GLOBAL_GAIN 0x02f
55#define MT9M111_CONTEXT_CONTROL 0x0c8
56#define MT9M111_PAGE_MAP 0x0f0
57#define MT9M111_BYTE_WISE_ADDR 0x0f1
58
59#define MT9M111_RESET_SYNC_CHANGES (1 << 15)
60#define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
61#define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
62#define MT9M111_RESET_RESET_SOC (1 << 5)
63#define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
64#define MT9M111_RESET_CHIP_ENABLE (1 << 3)
65#define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
66#define MT9M111_RESET_RESTART_FRAME (1 << 1)
67#define MT9M111_RESET_RESET_MODE (1 << 0)
68
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69#define MT9M111_RM_FULL_POWER_RD (0 << 10)
70#define MT9M111_RM_LOW_POWER_RD (1 << 10)
71#define MT9M111_RM_COL_SKIP_4X (1 << 5)
72#define MT9M111_RM_ROW_SKIP_4X (1 << 4)
73#define MT9M111_RM_COL_SKIP_2X (1 << 3)
74#define MT9M111_RM_ROW_SKIP_2X (1 << 2)
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75#define MT9M111_RMB_MIRROR_COLS (1 << 1)
76#define MT9M111_RMB_MIRROR_ROWS (1 << 0)
77#define MT9M111_CTXT_CTRL_RESTART (1 << 15)
78#define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
79#define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
80#define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
81#define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
82#define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
83#define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
84#define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
85#define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
86#define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
c8cf078e 87
77110abb 88/*
c8cf078e 89 * Colorpipe register addresses (0x100..0x1ff)
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90 */
91#define MT9M111_OPER_MODE_CTRL 0x106
92#define MT9M111_OUTPUT_FORMAT_CTRL 0x108
93#define MT9M111_REDUCER_XZOOM_B 0x1a0
94#define MT9M111_REDUCER_XSIZE_B 0x1a1
95#define MT9M111_REDUCER_YZOOM_B 0x1a3
96#define MT9M111_REDUCER_YSIZE_B 0x1a4
97#define MT9M111_REDUCER_XZOOM_A 0x1a6
98#define MT9M111_REDUCER_XSIZE_A 0x1a7
99#define MT9M111_REDUCER_YZOOM_A 0x1a9
100#define MT9M111_REDUCER_YSIZE_A 0x1aa
101
102#define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
103#define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
104
105#define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
39bf372f 106#define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
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107#define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
108#define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
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109#define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
110#define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
111#define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
112#define MT9M111_OUTFMT_RGB (1 << 8)
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113#define MT9M111_OUTFMT_RGB565 (0 << 6)
114#define MT9M111_OUTFMT_RGB555 (1 << 6)
115#define MT9M111_OUTFMT_RGB444x (2 << 6)
116#define MT9M111_OUTFMT_RGBx444 (3 << 6)
117#define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
118#define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
119#define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
120#define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
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121#define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
122#define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
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123#define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
124#define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
c8cf078e 125
77110abb 126/*
c8cf078e 127 * Camera control register addresses (0x200..0x2ff not implemented)
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128 */
129
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130#define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
131#define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
132#define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
133#define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
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134#define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
135 (val), (mask))
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136
137#define MT9M111_MIN_DARK_ROWS 8
669470a8 138#define MT9M111_MIN_DARK_COLS 26
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139#define MT9M111_MAX_HEIGHT 1024
140#define MT9M111_MAX_WIDTH 1280
141
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142struct mt9m111_context {
143 u16 read_mode;
144 u16 blanking_h;
145 u16 blanking_v;
146 u16 reducer_xzoom;
147 u16 reducer_yzoom;
148 u16 reducer_xsize;
149 u16 reducer_ysize;
150 u16 output_fmt_ctrl2;
151 u16 control;
152};
153
154static struct mt9m111_context context_a = {
155 .read_mode = MT9M111_READ_MODE_A,
156 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
157 .blanking_v = MT9M111_VERTICAL_BLANKING_A,
158 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
159 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
160 .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
161 .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
162 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
163 .control = MT9M111_CTXT_CTRL_RESTART,
164};
165
166static struct mt9m111_context context_b = {
167 .read_mode = MT9M111_READ_MODE_B,
168 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
169 .blanking_v = MT9M111_VERTICAL_BLANKING_B,
170 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
171 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
172 .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
173 .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
174 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
175 .control = MT9M111_CTXT_CTRL_RESTART |
176 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
177 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
178 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
179 MT9M111_CTXT_CTRL_HBLANK_SEL_B,
180};
181
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182/* MT9M111 has only one fixed colorspace per pixelcode */
183struct mt9m111_datafmt {
184 enum v4l2_mbus_pixelcode code;
185 enum v4l2_colorspace colorspace;
186};
187
188/* Find a data format by a pixel code in an array */
189static const struct mt9m111_datafmt *mt9m111_find_datafmt(
190 enum v4l2_mbus_pixelcode code, const struct mt9m111_datafmt *fmt,
191 int n)
192{
193 int i;
194 for (i = 0; i < n; i++)
195 if (fmt[i].code == code)
196 return fmt + i;
197
198 return NULL;
199}
200
201static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
ace6e979
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202 {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
203 {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
204 {V4L2_MBUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG},
205 {V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG},
760697be 206 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
7c58e7d0 207 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
760697be 208 {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
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209 {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
210 {V4L2_MBUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
211 {V4L2_MBUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
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212 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
213 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
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214};
215
77110abb 216struct mt9m111 {
979ea1dd 217 struct v4l2_subdev subdev;
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218 struct v4l2_ctrl_handler hdl;
219 struct v4l2_ctrl *gain;
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220 int model; /* V4L2_IDENT_MT9M111 or V4L2_IDENT_MT9M112 code
221 * from v4l2-chip-ident.h */
47921932 222 struct mt9m111_context *ctx;
09e231b3 223 struct v4l2_rect rect;
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224 struct mutex power_lock; /* lock to protect power_count */
225 int power_count;
760697be 226 const struct mt9m111_datafmt *fmt;
096b703f 227 int lastpage; /* PageMap cache value */
77110abb 228 unsigned char datawidth;
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229};
230
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231static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
232{
233 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
234}
235
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236static int reg_page_map_set(struct i2c_client *client, const u16 reg)
237{
238 int ret;
239 u16 page;
096b703f 240 struct mt9m111 *mt9m111 = to_mt9m111(client);
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241
242 page = (reg >> 8);
096b703f 243 if (page == mt9m111->lastpage)
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244 return 0;
245 if (page > 2)
246 return -EINVAL;
247
3f877045 248 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
506c629a 249 if (!ret)
096b703f 250 mt9m111->lastpage = page;
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251 return ret;
252}
253
9538e1c2 254static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
77110abb 255{
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256 int ret;
257
258 ret = reg_page_map_set(client, reg);
259 if (!ret)
3f877045 260 ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
77110abb 261
9538e1c2 262 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
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263 return ret;
264}
265
9538e1c2 266static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
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267 const u16 data)
268{
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269 int ret;
270
271 ret = reg_page_map_set(client, reg);
506c629a 272 if (!ret)
3f877045 273 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
9538e1c2 274 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
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275 return ret;
276}
277
9538e1c2 278static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
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279 const u16 data)
280{
281 int ret;
282
9538e1c2 283 ret = mt9m111_reg_read(client, reg);
77110abb 284 if (ret >= 0)
9538e1c2 285 ret = mt9m111_reg_write(client, reg, ret | data);
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286 return ret;
287}
288
9538e1c2 289static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
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290 const u16 data)
291{
292 int ret;
293
9538e1c2 294 ret = mt9m111_reg_read(client, reg);
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295 if (ret >= 0)
296 ret = mt9m111_reg_write(client, reg, ret & ~data);
297 return ret;
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298}
299
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300static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
301 const u16 data, const u16 mask)
302{
303 int ret;
304
305 ret = mt9m111_reg_read(client, reg);
306 if (ret >= 0)
307 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
308 return ret;
309}
310
2768cbbb 311static int mt9m111_set_context(struct mt9m111 *mt9m111,
47921932 312 struct mt9m111_context *ctx)
77110abb 313{
2768cbbb 314 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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GL
315 return reg_write(CONTEXT_CONTROL, ctx->control);
316}
317
318static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
319 struct v4l2_rect *rect, struct mt9m111_context *ctx)
320{
321 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
322 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, MT9M111_MAX_WIDTH);
323 if (!ret)
324 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, MT9M111_MAX_HEIGHT);
325 if (!ret)
326 ret = mt9m111_reg_write(client, ctx->reducer_xsize, rect->width);
327 if (!ret)
328 ret = mt9m111_reg_write(client, ctx->reducer_ysize, rect->height);
329 return ret;
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330}
331
2768cbbb 332static int mt9m111_setup_rect(struct mt9m111 *mt9m111,
09e231b3 333 struct v4l2_rect *rect)
77110abb 334{
2768cbbb 335 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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GL
336 int ret;
337 bool is_raw_format = mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
338 mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE;
77110abb 339
09e231b3 340 ret = reg_write(COLUMN_START, rect->left);
506c629a 341 if (!ret)
09e231b3 342 ret = reg_write(ROW_START, rect->top);
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343
344 if (is_raw_format) {
506c629a 345 if (!ret)
47921932 346 ret = reg_write(WINDOW_WIDTH, rect->width);
506c629a 347 if (!ret)
47921932 348 ret = reg_write(WINDOW_HEIGHT, rect->height);
77110abb 349 } else {
506c629a 350 if (!ret)
47921932 351 ret = mt9m111_setup_rect_ctx(mt9m111, rect, &context_b);
506c629a 352 if (!ret)
47921932 353 ret = mt9m111_setup_rect_ctx(mt9m111, rect, &context_a);
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354 }
355
356 return ret;
357}
358
2768cbbb 359static int mt9m111_enable(struct mt9m111 *mt9m111)
77110abb 360{
2768cbbb 361 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
a650bf1e 362 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
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363}
364
2768cbbb 365static int mt9m111_reset(struct mt9m111 *mt9m111)
77110abb 366{
2768cbbb 367 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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368 int ret;
369
370 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
506c629a 371 if (!ret)
77110abb 372 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
506c629a 373 if (!ret)
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374 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
375 | MT9M111_RESET_RESET_SOC);
afb13683 376
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377 return ret;
378}
379
2768cbbb 380static int mt9m111_make_rect(struct mt9m111 *mt9m111,
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GL
381 struct v4l2_rect *rect)
382{
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383 if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
384 mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
6a6c8786
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385 /* Bayer format - even size lengths */
386 rect->width = ALIGN(rect->width, 2);
387 rect->height = ALIGN(rect->height, 2);
388 /* Let the user play with the starting pixel */
389 }
390
391 /* FIXME: the datasheet doesn't specify minimum sizes */
392 soc_camera_limit_side(&rect->left, &rect->width,
393 MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH);
394
395 soc_camera_limit_side(&rect->top, &rect->height,
396 MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT);
397
2768cbbb 398 return mt9m111_setup_rect(mt9m111, rect);
6a6c8786
GL
399}
400
08590b96 401static int mt9m111_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
09e231b3 402{
6a6c8786 403 struct v4l2_rect rect = a->c;
c4ce6d14 404 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 405 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
09e231b3
GL
406 int ret;
407
85f8be68 408 dev_dbg(&client->dev, "%s left=%d, top=%d, width=%d, height=%d\n",
6a6c8786 409 __func__, rect.left, rect.top, rect.width, rect.height);
09e231b3 410
6b6d33c7
MG
411 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
412 return -EINVAL;
413
2768cbbb 414 ret = mt9m111_make_rect(mt9m111, &rect);
09e231b3 415 if (!ret)
6a6c8786 416 mt9m111->rect = rect;
09e231b3
GL
417 return ret;
418}
419
6a6c8786
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420static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
421{
2768cbbb 422 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
6a6c8786
GL
423
424 a->c = mt9m111->rect;
425 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
426
427 return 0;
428}
429
430static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
431{
6b6d33c7
MG
432 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
433 return -EINVAL;
434
6a6c8786
GL
435 a->bounds.left = MT9M111_MIN_DARK_COLS;
436 a->bounds.top = MT9M111_MIN_DARK_ROWS;
437 a->bounds.width = MT9M111_MAX_WIDTH;
438 a->bounds.height = MT9M111_MAX_HEIGHT;
439 a->defrect = a->bounds;
6a6c8786
GL
440 a->pixelaspect.numerator = 1;
441 a->pixelaspect.denominator = 1;
442
443 return 0;
444}
445
760697be
GL
446static int mt9m111_g_fmt(struct v4l2_subdev *sd,
447 struct v4l2_mbus_framefmt *mf)
6a6c8786 448{
2768cbbb 449 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
6a6c8786 450
760697be
GL
451 mf->width = mt9m111->rect.width;
452 mf->height = mt9m111->rect.height;
453 mf->code = mt9m111->fmt->code;
01f5a394 454 mf->colorspace = mt9m111->fmt->colorspace;
760697be 455 mf->field = V4L2_FIELD_NONE;
6a6c8786
GL
456
457 return 0;
458}
459
2768cbbb 460static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
760697be 461 enum v4l2_mbus_pixelcode code)
77110abb 462{
7c58e7d0
MG
463 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
464 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
465 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
466 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
467 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
468 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
469 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
506c629a 470 int ret;
77110abb 471
760697be
GL
472 switch (code) {
473 case V4L2_MBUS_FMT_SBGGR8_1X8:
7c58e7d0
MG
474 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
475 MT9M111_OUTFMT_RGB;
77110abb 476 break;
760697be 477 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
7c58e7d0 478 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
77110abb 479 break;
760697be 480 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
7c58e7d0
MG
481 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
482 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
483 break;
484 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
485 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
77110abb 486 break;
760697be 487 case V4L2_MBUS_FMT_RGB565_2X8_LE:
7c58e7d0
MG
488 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
489 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
490 break;
491 case V4L2_MBUS_FMT_RGB565_2X8_BE:
492 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
493 break;
494 case V4L2_MBUS_FMT_BGR565_2X8_BE:
495 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
496 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
497 break;
498 case V4L2_MBUS_FMT_BGR565_2X8_LE:
499 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
500 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
501 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb 502 break;
ace6e979 503 case V4L2_MBUS_FMT_UYVY8_2X8:
7c58e7d0 504 data_outfmt2 = 0;
88f4b899 505 break;
ace6e979 506 case V4L2_MBUS_FMT_VYUY8_2X8:
7c58e7d0 507 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
88f4b899 508 break;
ace6e979 509 case V4L2_MBUS_FMT_YUYV8_2X8:
7c58e7d0 510 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
88f4b899 511 break;
ace6e979 512 case V4L2_MBUS_FMT_YVYU8_2X8:
7c58e7d0
MG
513 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
514 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb
RJ
515 break;
516 default:
7c58e7d0
MG
517 dev_err(&client->dev, "Pixel format not handled: %x\n", code);
518 return -EINVAL;
77110abb
RJ
519 }
520
47921932
GL
521 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
522 data_outfmt2, mask_outfmt2);
7c58e7d0 523 if (!ret)
47921932
GL
524 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
525 data_outfmt2, mask_outfmt2);
7c58e7d0 526
77110abb
RJ
527 return ret;
528}
529
760697be
GL
530static int mt9m111_s_fmt(struct v4l2_subdev *sd,
531 struct v4l2_mbus_framefmt *mf)
77110abb 532{
c4ce6d14 533 struct i2c_client *client = v4l2_get_subdevdata(sd);
760697be 534 const struct mt9m111_datafmt *fmt;
2768cbbb 535 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
09e231b3
GL
536 struct v4l2_rect rect = {
537 .left = mt9m111->rect.left,
538 .top = mt9m111->rect.top,
760697be
GL
539 .width = mf->width,
540 .height = mf->height,
09e231b3 541 };
506c629a 542 int ret;
77110abb 543
760697be
GL
544 fmt = mt9m111_find_datafmt(mf->code, mt9m111_colour_fmts,
545 ARRAY_SIZE(mt9m111_colour_fmts));
546 if (!fmt)
547 return -EINVAL;
548
96c75399 549 dev_dbg(&client->dev,
760697be
GL
550 "%s code=%x left=%d, top=%d, width=%d, height=%d\n", __func__,
551 mf->code, rect.left, rect.top, rect.width, rect.height);
77110abb 552
2768cbbb 553 ret = mt9m111_make_rect(mt9m111, &rect);
09e231b3 554 if (!ret)
2768cbbb 555 ret = mt9m111_set_pixfmt(mt9m111, mf->code);
760697be
GL
556 if (!ret) {
557 mt9m111->rect = rect;
558 mt9m111->fmt = fmt;
559 mf->colorspace = fmt->colorspace;
560 }
561
506c629a 562 return ret;
77110abb
RJ
563}
564
760697be
GL
565static int mt9m111_try_fmt(struct v4l2_subdev *sd,
566 struct v4l2_mbus_framefmt *mf)
77110abb 567{
2768cbbb 568 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
760697be
GL
569 const struct mt9m111_datafmt *fmt;
570 bool bayer = mf->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
571 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE;
572
573 fmt = mt9m111_find_datafmt(mf->code, mt9m111_colour_fmts,
574 ARRAY_SIZE(mt9m111_colour_fmts));
575 if (!fmt) {
576 fmt = mt9m111->fmt;
577 mf->code = fmt->code;
578 }
6a6c8786
GL
579
580 /*
581 * With Bayer format enforce even side lengths, but let the user play
582 * with the starting pixel
583 */
64f5905e 584
760697be
GL
585 if (mf->height > MT9M111_MAX_HEIGHT)
586 mf->height = MT9M111_MAX_HEIGHT;
587 else if (mf->height < 2)
588 mf->height = 2;
6a6c8786 589 else if (bayer)
760697be 590 mf->height = ALIGN(mf->height, 2);
6a6c8786 591
760697be
GL
592 if (mf->width > MT9M111_MAX_WIDTH)
593 mf->width = MT9M111_MAX_WIDTH;
594 else if (mf->width < 2)
595 mf->width = 2;
6a6c8786 596 else if (bayer)
760697be
GL
597 mf->width = ALIGN(mf->width, 2);
598
599 mf->colorspace = fmt->colorspace;
77110abb
RJ
600
601 return 0;
602}
603
979ea1dd
GL
604static int mt9m111_g_chip_ident(struct v4l2_subdev *sd,
605 struct v4l2_dbg_chip_ident *id)
77110abb 606{
c4ce6d14 607 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 608 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
77110abb 609
aecde8b5 610 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
77110abb
RJ
611 return -EINVAL;
612
40e2e092 613 if (id->match.addr != client->addr)
77110abb
RJ
614 return -ENODEV;
615
616 id->ident = mt9m111->model;
617 id->revision = 0;
618
619 return 0;
620}
621
622#ifdef CONFIG_VIDEO_ADV_DEBUG
979ea1dd
GL
623static int mt9m111_g_register(struct v4l2_subdev *sd,
624 struct v4l2_dbg_register *reg)
77110abb 625{
c4ce6d14 626 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 627 int val;
77110abb 628
aecde8b5 629 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
77110abb 630 return -EINVAL;
9538e1c2 631 if (reg->match.addr != client->addr)
77110abb
RJ
632 return -ENODEV;
633
9538e1c2 634 val = mt9m111_reg_read(client, reg->reg);
aecde8b5 635 reg->size = 2;
77110abb
RJ
636 reg->val = (u64)val;
637
638 if (reg->val > 0xffff)
639 return -EIO;
640
641 return 0;
642}
643
979ea1dd
GL
644static int mt9m111_s_register(struct v4l2_subdev *sd,
645 struct v4l2_dbg_register *reg)
77110abb 646{
c4ce6d14 647 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 648
aecde8b5 649 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
77110abb
RJ
650 return -EINVAL;
651
9538e1c2 652 if (reg->match.addr != client->addr)
77110abb
RJ
653 return -ENODEV;
654
9538e1c2 655 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
77110abb
RJ
656 return -EIO;
657
658 return 0;
659}
660#endif
661
2768cbbb 662static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
77110abb 663{
2768cbbb 664 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
665 int ret;
666
47921932
GL
667 if (flip)
668 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
669 else
670 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
77110abb
RJ
671
672 return ret;
673}
674
2768cbbb 675static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
77110abb 676{
2768cbbb 677 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
0f28b793 678 int data;
77110abb
RJ
679
680 data = reg_read(GLOBAL_GAIN);
681 if (data >= 0)
0f28b793 682 return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
683 (1 << ((data >> 9) & 1));
684 return data;
77110abb 685}
0f28b793 686
2768cbbb 687static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
77110abb 688{
2768cbbb 689 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
690 u16 val;
691
692 if (gain > 63 * 2 * 2)
693 return -EINVAL;
694
77110abb
RJ
695 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
696 val = (1 << 10) | (1 << 9) | (gain / 4);
697 else if ((gain >= 64) && (gain < 64 * 2))
506c629a 698 val = (1 << 9) | (gain / 2);
77110abb
RJ
699 else
700 val = gain;
701
702 return reg_write(GLOBAL_GAIN, val);
703}
704
2768cbbb 705static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int on)
77110abb 706{
2768cbbb 707 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
708
709 if (on)
af8425c5
HV
710 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
711 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
77110abb 712}
39bf372f 713
2768cbbb 714static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
39bf372f 715{
2768cbbb 716 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
39bf372f
RJ
717
718 if (on)
af8425c5
HV
719 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
720 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
39bf372f
RJ
721}
722
af8425c5 723static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
77110abb 724{
af8425c5
HV
725 struct mt9m111 *mt9m111 = container_of(ctrl->handler,
726 struct mt9m111, hdl);
77110abb
RJ
727
728 switch (ctrl->id) {
729 case V4L2_CID_VFLIP:
af8425c5 730 return mt9m111_set_flip(mt9m111, ctrl->val,
77110abb 731 MT9M111_RMB_MIRROR_ROWS);
77110abb 732 case V4L2_CID_HFLIP:
af8425c5 733 return mt9m111_set_flip(mt9m111, ctrl->val,
77110abb 734 MT9M111_RMB_MIRROR_COLS);
77110abb 735 case V4L2_CID_GAIN:
af8425c5 736 return mt9m111_set_global_gain(mt9m111, ctrl->val);
77110abb 737 case V4L2_CID_EXPOSURE_AUTO:
af8425c5 738 return mt9m111_set_autoexposure(mt9m111, ctrl->val);
39bf372f 739 case V4L2_CID_AUTO_WHITE_BALANCE:
af8425c5 740 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
77110abb
RJ
741 }
742
af8425c5 743 return -EINVAL;
77110abb
RJ
744}
745
14c5ea9b 746static int mt9m111_suspend(struct mt9m111 *mt9m111)
96c75399 747{
a650bf1e
GL
748 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
749 int ret;
750
af8425c5 751 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
96c75399 752
a650bf1e
GL
753 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
754 if (!ret)
755 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
756 MT9M111_RESET_OUTPUT_DISABLE |
757 MT9M111_RESET_ANALOG_STANDBY);
758 if (!ret)
759 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
760
761 return ret;
96c75399
GL
762}
763
2768cbbb 764static void mt9m111_restore_state(struct mt9m111 *mt9m111)
77110abb 765{
47921932 766 mt9m111_set_context(mt9m111, mt9m111->ctx);
2768cbbb
GL
767 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
768 mt9m111_setup_rect(mt9m111, &mt9m111->rect);
af8425c5 769 v4l2_ctrl_handler_setup(&mt9m111->hdl);
77110abb
RJ
770}
771
14c5ea9b 772static int mt9m111_resume(struct mt9m111 *mt9m111)
77110abb 773{
a650bf1e
GL
774 int ret = mt9m111_enable(mt9m111);
775 if (!ret)
776 ret = mt9m111_reset(mt9m111);
777 if (!ret)
778 mt9m111_restore_state(mt9m111);
77110abb 779
77110abb
RJ
780 return ret;
781}
782
2768cbbb 783static int mt9m111_init(struct mt9m111 *mt9m111)
77110abb 784{
2768cbbb 785 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
786 int ret;
787
47921932
GL
788 /* Default HIGHPOWER context */
789 mt9m111->ctx = &context_b;
2768cbbb 790 ret = mt9m111_enable(mt9m111);
506c629a 791 if (!ret)
2768cbbb 792 ret = mt9m111_reset(mt9m111);
506c629a 793 if (!ret)
47921932 794 ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
506c629a 795 if (ret)
c8cf078e 796 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
506c629a 797 return ret;
77110abb
RJ
798}
799
77110abb
RJ
800/*
801 * Interface active, can use i2c. If it fails, it can indeed mean, that
802 * this wasn't our capture interface, so, we wait for the right one
803 */
14178aa5 804static int mt9m111_video_probe(struct i2c_client *client)
77110abb 805{
979ea1dd 806 struct mt9m111 *mt9m111 = to_mt9m111(client);
77110abb
RJ
807 s32 data;
808 int ret;
809
77110abb
RJ
810 data = reg_read(CHIP_VERSION);
811
812 switch (data) {
c8cf078e 813 case 0x143a: /* MT9M111 or MT9M131 */
77110abb 814 mt9m111->model = V4L2_IDENT_MT9M111;
c8cf078e
PW
815 dev_info(&client->dev,
816 "Detected a MT9M111/MT9M131 chip ID %x\n", data);
d7f83a51
MR
817 break;
818 case 0x148c: /* MT9M112 */
819 mt9m111->model = V4L2_IDENT_MT9M112;
c8cf078e 820 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
77110abb
RJ
821 break;
822 default:
85f8be68 823 dev_err(&client->dev,
c8cf078e
PW
824 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
825 data);
af8425c5 826 return -ENODEV;
77110abb
RJ
827 }
828
2768cbbb 829 ret = mt9m111_init(mt9m111);
af8425c5
HV
830 if (ret)
831 return ret;
832 return v4l2_ctrl_handler_setup(&mt9m111->hdl);
77110abb
RJ
833}
834
14c5ea9b
GL
835static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
836{
837 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
838 struct i2c_client *client = v4l2_get_subdevdata(sd);
839 int ret = 0;
840
841 mutex_lock(&mt9m111->power_lock);
842
843 /*
844 * If the power count is modified from 0 to != 0 or from != 0 to 0,
845 * update the power state.
846 */
847 if (mt9m111->power_count == !on) {
848 if (on) {
849 ret = mt9m111_resume(mt9m111);
850 if (ret) {
851 dev_err(&client->dev,
852 "Failed to resume the sensor: %d\n", ret);
853 goto out;
854 }
855 } else {
856 mt9m111_suspend(mt9m111);
857 }
858 }
859
860 /* Update the power count. */
861 mt9m111->power_count += on ? 1 : -1;
862 WARN_ON(mt9m111->power_count < 0);
863
864out:
865 mutex_unlock(&mt9m111->power_lock);
866 return ret;
867}
868
af8425c5
HV
869static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
870 .s_ctrl = mt9m111_s_ctrl,
871};
872
979ea1dd 873static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
979ea1dd 874 .g_chip_ident = mt9m111_g_chip_ident,
14c5ea9b 875 .s_power = mt9m111_s_power,
979ea1dd
GL
876#ifdef CONFIG_VIDEO_ADV_DEBUG
877 .g_register = mt9m111_g_register,
878 .s_register = mt9m111_s_register,
879#endif
880};
881
3805f201 882static int mt9m111_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
760697be
GL
883 enum v4l2_mbus_pixelcode *code)
884{
3805f201 885 if (index >= ARRAY_SIZE(mt9m111_colour_fmts))
760697be
GL
886 return -EINVAL;
887
888 *code = mt9m111_colour_fmts[index].code;
889 return 0;
890}
891
0c0b446d
GL
892static int mt9m111_g_mbus_config(struct v4l2_subdev *sd,
893 struct v4l2_mbus_config *cfg)
894{
895 struct i2c_client *client = v4l2_get_subdevdata(sd);
14178aa5 896 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
0c0b446d
GL
897
898 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
899 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
900 V4L2_MBUS_DATA_ACTIVE_HIGH;
901 cfg->type = V4L2_MBUS_PARALLEL;
902 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
903
904 return 0;
905}
906
979ea1dd 907static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
760697be
GL
908 .s_mbus_fmt = mt9m111_s_fmt,
909 .g_mbus_fmt = mt9m111_g_fmt,
910 .try_mbus_fmt = mt9m111_try_fmt,
08590b96 911 .s_crop = mt9m111_s_crop,
6a6c8786
GL
912 .g_crop = mt9m111_g_crop,
913 .cropcap = mt9m111_cropcap,
760697be 914 .enum_mbus_fmt = mt9m111_enum_fmt,
0c0b446d 915 .g_mbus_config = mt9m111_g_mbus_config,
979ea1dd
GL
916};
917
918static struct v4l2_subdev_ops mt9m111_subdev_ops = {
919 .core = &mt9m111_subdev_core_ops,
920 .video = &mt9m111_subdev_video_ops,
921};
922
77110abb
RJ
923static int mt9m111_probe(struct i2c_client *client,
924 const struct i2c_device_id *did)
925{
926 struct mt9m111 *mt9m111;
77110abb 927 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
14178aa5 928 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
77110abb
RJ
929 int ret;
930
931 if (!icl) {
c8cf078e 932 dev_err(&client->dev, "mt9m111: driver needs platform data\n");
77110abb
RJ
933 return -EINVAL;
934 }
935
936 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
937 dev_warn(&adapter->dev,
938 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
939 return -EIO;
940 }
941
942 mt9m111 = kzalloc(sizeof(struct mt9m111), GFP_KERNEL);
943 if (!mt9m111)
944 return -ENOMEM;
945
979ea1dd 946 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
af8425c5
HV
947 v4l2_ctrl_handler_init(&mt9m111->hdl, 5);
948 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
949 V4L2_CID_VFLIP, 0, 1, 1, 0);
950 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
951 V4L2_CID_HFLIP, 0, 1, 1, 0);
952 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
953 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
954 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
955 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
956 v4l2_ctrl_new_std_menu(&mt9m111->hdl,
957 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
958 V4L2_EXPOSURE_AUTO);
959 mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
960 if (mt9m111->hdl.error) {
961 int err = mt9m111->hdl.error;
77110abb 962
af8425c5
HV
963 kfree(mt9m111);
964 return err;
965 }
77110abb 966
af8425c5 967 /* Second stage probe - when a capture adapter is there */
6a6c8786
GL
968 mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
969 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
970 mt9m111->rect.width = MT9M111_MAX_WIDTH;
971 mt9m111->rect.height = MT9M111_MAX_HEIGHT;
760697be 972 mt9m111->fmt = &mt9m111_colour_fmts[0];
14178aa5 973 mt9m111->lastpage = -1;
6b806e30 974 mutex_init(&mt9m111->power_lock);
6a6c8786 975
14178aa5 976 ret = mt9m111_video_probe(client);
40e2e092 977 if (ret) {
af8425c5 978 v4l2_ctrl_handler_free(&mt9m111->hdl);
40e2e092
GL
979 kfree(mt9m111);
980 }
77110abb 981
77110abb
RJ
982 return ret;
983}
984
985static int mt9m111_remove(struct i2c_client *client)
986{
979ea1dd 987 struct mt9m111 *mt9m111 = to_mt9m111(client);
40e2e092 988
af8425c5
HV
989 v4l2_device_unregister_subdev(&mt9m111->subdev);
990 v4l2_ctrl_handler_free(&mt9m111->hdl);
77110abb
RJ
991 kfree(mt9m111);
992
993 return 0;
994}
995
996static const struct i2c_device_id mt9m111_id[] = {
997 { "mt9m111", 0 },
998 { }
999};
1000MODULE_DEVICE_TABLE(i2c, mt9m111_id);
1001
1002static struct i2c_driver mt9m111_i2c_driver = {
1003 .driver = {
1004 .name = "mt9m111",
1005 },
1006 .probe = mt9m111_probe,
1007 .remove = mt9m111_remove,
1008 .id_table = mt9m111_id,
1009};
1010
1011static int __init mt9m111_mod_init(void)
1012{
1013 return i2c_add_driver(&mt9m111_i2c_driver);
1014}
1015
1016static void __exit mt9m111_mod_exit(void)
1017{
1018 i2c_del_driver(&mt9m111_i2c_driver);
1019}
1020
1021module_init(mt9m111_mod_init);
1022module_exit(mt9m111_mod_exit);
1023
c8cf078e 1024MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
77110abb
RJ
1025MODULE_AUTHOR("Robert Jarzmik");
1026MODULE_LICENSE("GPL");
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