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Merge branches 'x86-cleanups-for-linus' and 'x86-cpufeature-for-linus' of git://git...
[deliverable/linux.git] / drivers / media / video / mt9t001.c
CommitLineData
0a54b86a
LP		 1/*
2 * Driver for MT9T001 CMOS Image Sensor from Aptina (Micron)
3 *
4 * Copyright (C) 2010-2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 *
6 * Based on the MT9M001 driver,
7 *
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/i2c.h>
86caf811 16#include <linux/module.h>
0a54b86a
LP		 17#include <linux/log2.h>
18#include <linux/slab.h>
19#include <linux/videodev2.h>
20#include <linux/v4l2-mediabus.h>
21
22#include <media/mt9t001.h>
23#include <media/v4l2-ctrls.h>
24#include <media/v4l2-device.h>
25#include <media/v4l2-subdev.h>
26
27#define MT9T001_PIXEL_ARRAY_HEIGHT 1568
28#define MT9T001_PIXEL_ARRAY_WIDTH 2112
29
30#define MT9T001_CHIP_VERSION 0x00
31#define MT9T001_CHIP_ID 0x1621
32#define MT9T001_ROW_START 0x01
33#define MT9T001_ROW_START_MIN 0
34#define MT9T001_ROW_START_DEF 20
35#define MT9T001_ROW_START_MAX 1534
36#define MT9T001_COLUMN_START 0x02
37#define MT9T001_COLUMN_START_MIN 0
38#define MT9T001_COLUMN_START_DEF 32
39#define MT9T001_COLUMN_START_MAX 2046
40#define MT9T001_WINDOW_HEIGHT 0x03
41#define MT9T001_WINDOW_HEIGHT_MIN 1
42#define MT9T001_WINDOW_HEIGHT_DEF 1535
43#define MT9T001_WINDOW_HEIGHT_MAX 1567
44#define MT9T001_WINDOW_WIDTH 0x04
45#define MT9T001_WINDOW_WIDTH_MIN 1
46#define MT9T001_WINDOW_WIDTH_DEF 2047
47#define MT9T001_WINDOW_WIDTH_MAX 2111
48#define MT9T001_HORIZONTAL_BLANKING 0x05
49#define MT9T001_HORIZONTAL_BLANKING_MIN 21
50#define MT9T001_HORIZONTAL_BLANKING_MAX 1023
51#define MT9T001_VERTICAL_BLANKING 0x06
52#define MT9T001_VERTICAL_BLANKING_MIN 3
53#define MT9T001_VERTICAL_BLANKING_MAX 1023
54#define MT9T001_OUTPUT_CONTROL 0x07
55#define MT9T001_OUTPUT_CONTROL_SYNC (1 << 0)
56#define MT9T001_OUTPUT_CONTROL_CHIP_ENABLE (1 << 1)
57#define MT9T001_OUTPUT_CONTROL_TEST_DATA (1 << 6)
58#define MT9T001_SHUTTER_WIDTH_HIGH 0x08
59#define MT9T001_SHUTTER_WIDTH_LOW 0x09
60#define MT9T001_SHUTTER_WIDTH_MIN 1
61#define MT9T001_SHUTTER_WIDTH_DEF 1561
62#define MT9T001_SHUTTER_WIDTH_MAX (1024 * 1024)
63#define MT9T001_PIXEL_CLOCK 0x0a
64#define MT9T001_PIXEL_CLOCK_INVERT (1 << 15)
65#define MT9T001_PIXEL_CLOCK_SHIFT_MASK (7 << 8)
66#define MT9T001_PIXEL_CLOCK_SHIFT_SHIFT 8
67#define MT9T001_PIXEL_CLOCK_DIVIDE_MASK (0x7f << 0)
68#define MT9T001_FRAME_RESTART 0x0b
69#define MT9T001_SHUTTER_DELAY 0x0c
70#define MT9T001_SHUTTER_DELAY_MAX 2047
71#define MT9T001_RESET 0x0d
72#define MT9T001_READ_MODE1 0x1e
73#define MT9T001_READ_MODE_SNAPSHOT (1 << 8)
74#define MT9T001_READ_MODE_STROBE_ENABLE (1 << 9)
75#define MT9T001_READ_MODE_STROBE_WIDTH (1 << 10)
76#define MT9T001_READ_MODE_STROBE_OVERRIDE (1 << 11)
77#define MT9T001_READ_MODE2 0x20
78#define MT9T001_READ_MODE_BAD_FRAMES (1 << 0)
79#define MT9T001_READ_MODE_LINE_VALID_CONTINUOUS (1 << 9)
80#define MT9T001_READ_MODE_LINE_VALID_FRAME (1 << 10)
81#define MT9T001_READ_MODE3 0x21
82#define MT9T001_READ_MODE_GLOBAL_RESET (1 << 0)
83#define MT9T001_READ_MODE_GHST_CTL (1 << 1)
84#define MT9T001_ROW_ADDRESS_MODE 0x22
85#define MT9T001_ROW_SKIP_MASK (7 << 0)
86#define MT9T001_ROW_BIN_MASK (3 << 3)
87#define MT9T001_ROW_BIN_SHIFT 3
88#define MT9T001_COLUMN_ADDRESS_MODE 0x23
89#define MT9T001_COLUMN_SKIP_MASK (7 << 0)
90#define MT9T001_COLUMN_BIN_MASK (3 << 3)
91#define MT9T001_COLUMN_BIN_SHIFT 3
92#define MT9T001_GREEN1_GAIN 0x2b
93#define MT9T001_BLUE_GAIN 0x2c
94#define MT9T001_RED_GAIN 0x2d
95#define MT9T001_GREEN2_GAIN 0x2e
96#define MT9T001_TEST_DATA 0x32
97#define MT9T001_GLOBAL_GAIN 0x35
98#define MT9T001_GLOBAL_GAIN_MIN 8
99#define MT9T001_GLOBAL_GAIN_MAX 1024
100#define MT9T001_BLACK_LEVEL 0x49
101#define MT9T001_ROW_BLACK_DEFAULT_OFFSET 0x4b
102#define MT9T001_BLC_DELTA_THRESHOLDS 0x5d
103#define MT9T001_CAL_THRESHOLDS 0x5f
104#define MT9T001_GREEN1_OFFSET 0x60
105#define MT9T001_GREEN2_OFFSET 0x61
106#define MT9T001_BLACK_LEVEL_CALIBRATION 0x62
107#define MT9T001_BLACK_LEVEL_OVERRIDE (1 << 0)
108#define MT9T001_BLACK_LEVEL_DISABLE_OFFSET (1 << 1)
109#define MT9T001_BLACK_LEVEL_RECALCULATE (1 << 12)
110#define MT9T001_BLACK_LEVEL_LOCK_RED_BLUE (1 << 13)
111#define MT9T001_BLACK_LEVEL_LOCK_GREEN (1 << 14)
112#define MT9T001_RED_OFFSET 0x63
113#define MT9T001_BLUE_OFFSET 0x64
114
115struct mt9t001 {
116 struct v4l2_subdev subdev;
117 struct media_pad pad;
118
119 struct v4l2_mbus_framefmt format;
120 struct v4l2_rect crop;
121
122 struct v4l2_ctrl_handler ctrls;
123 struct v4l2_ctrl *gains[4];
124
125 u16 output_control;
126 u16 black_level;
127};
128
129static inline struct mt9t001 *to_mt9t001(struct v4l2_subdev *sd)
130{
131 return container_of(sd, struct mt9t001, subdev);
132}
133
134static int mt9t001_read(struct i2c_client *client, u8 reg)
135{
c27e3050 136 return i2c_smbus_read_word_swapped(client, reg);
0a54b86a
LP		 137}
138
139static int mt9t001_write(struct i2c_client *client, u8 reg, u16 data)
140{
c27e3050 141 return i2c_smbus_write_word_swapped(client, reg, data);
0a54b86a
LP		 142}
143
144static int mt9t001_set_output_control(struct mt9t001 *mt9t001, u16 clear,
145 u16 set)
146{
147 struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
148 u16 value = (mt9t001->output_control & ~clear) | set;
149 int ret;
150
151 if (value == mt9t001->output_control)
152 return 0;
153
154 ret = mt9t001_write(client, MT9T001_OUTPUT_CONTROL, value);
155 if (ret < 0)
156 return ret;
157
158 mt9t001->output_control = value;
159 return 0;
160}
161
162/* -----------------------------------------------------------------------------
163 * V4L2 subdev video operations
164 */
165
166static struct v4l2_mbus_framefmt *
167__mt9t001_get_pad_format(struct mt9t001 *mt9t001, struct v4l2_subdev_fh *fh,
168 unsigned int pad, enum v4l2_subdev_format_whence which)
169{
170 switch (which) {
171 case V4L2_SUBDEV_FORMAT_TRY:
172 return v4l2_subdev_get_try_format(fh, pad);
173 case V4L2_SUBDEV_FORMAT_ACTIVE:
174 return &mt9t001->format;
175 default:
176 return NULL;
177 }
178}
179
180static struct v4l2_rect *
181__mt9t001_get_pad_crop(struct mt9t001 *mt9t001, struct v4l2_subdev_fh *fh,
182 unsigned int pad, enum v4l2_subdev_format_whence which)
183{
184 switch (which) {
185 case V4L2_SUBDEV_FORMAT_TRY:
186 return v4l2_subdev_get_try_crop(fh, pad);
187 case V4L2_SUBDEV_FORMAT_ACTIVE:
188 return &mt9t001->crop;
189 default:
190 return NULL;
191 }
192}
193
194static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable)
195{
196 const u16 mode = MT9T001_OUTPUT_CONTROL_CHIP_ENABLE;
197 struct i2c_client *client = v4l2_get_subdevdata(subdev);
198 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
199 struct v4l2_mbus_framefmt *format = &mt9t001->format;
200 struct v4l2_rect *crop = &mt9t001->crop;
201 unsigned int hratio;
202 unsigned int vratio;
203 int ret;
204
205 if (!enable)
206 return mt9t001_set_output_control(mt9t001, mode, 0);
207
208 /* Configure the window size and row/column bin */
209 hratio = DIV_ROUND_CLOSEST(crop->width, format->width);
210 vratio = DIV_ROUND_CLOSEST(crop->height, format->height);
211
212 ret = mt9t001_write(client, MT9T001_ROW_ADDRESS_MODE, hratio - 1);
213 if (ret < 0)
214 return ret;
215
216 ret = mt9t001_write(client, MT9T001_COLUMN_ADDRESS_MODE, vratio - 1);
217 if (ret < 0)
218 return ret;
219
220 ret = mt9t001_write(client, MT9T001_COLUMN_START, crop->left);
221 if (ret < 0)
222 return ret;
223
224 ret = mt9t001_write(client, MT9T001_ROW_START, crop->top);
225 if (ret < 0)
226 return ret;
227
228 ret = mt9t001_write(client, MT9T001_WINDOW_WIDTH, crop->width - 1);
229 if (ret < 0)
230 return ret;
231
232 ret = mt9t001_write(client, MT9T001_WINDOW_HEIGHT, crop->height - 1);
233 if (ret < 0)
234 return ret;
235
236 /* Switch to master "normal" mode */
237 return mt9t001_set_output_control(mt9t001, 0, mode);
238}
239
240static int mt9t001_enum_mbus_code(struct v4l2_subdev *subdev,
241 struct v4l2_subdev_fh *fh,
242 struct v4l2_subdev_mbus_code_enum *code)
243{
244 if (code->index > 0)
245 return -EINVAL;
246
247 code->code = V4L2_MBUS_FMT_SGRBG10_1X10;
248 return 0;
249}
250
251static int mt9t001_enum_frame_size(struct v4l2_subdev *subdev,
252 struct v4l2_subdev_fh *fh,
253 struct v4l2_subdev_frame_size_enum *fse)
254{
255 if (fse->index >= 8 || fse->code != V4L2_MBUS_FMT_SGRBG10_1X10)
256 return -EINVAL;
257
258 fse->min_width = (MT9T001_WINDOW_WIDTH_DEF + 1) / fse->index;
259 fse->max_width = fse->min_width;
260 fse->min_height = (MT9T001_WINDOW_HEIGHT_DEF + 1) / fse->index;
261 fse->max_height = fse->min_height;
262
263 return 0;
264}
265
266static int mt9t001_get_format(struct v4l2_subdev *subdev,
267 struct v4l2_subdev_fh *fh,
268 struct v4l2_subdev_format *format)
269{
270 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
271
272 format->format = *__mt9t001_get_pad_format(mt9t001, fh, format->pad,
273 format->which);
274 return 0;
275}
276
277static int mt9t001_set_format(struct v4l2_subdev *subdev,
278 struct v4l2_subdev_fh *fh,
279 struct v4l2_subdev_format *format)
280{
281 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
282 struct v4l2_mbus_framefmt *__format;
283 struct v4l2_rect *__crop;
284 unsigned int width;
285 unsigned int height;
286 unsigned int hratio;
287 unsigned int vratio;
288
289 __crop = __mt9t001_get_pad_crop(mt9t001, fh, format->pad,
290 format->which);
291
292 /* Clamp the width and height to avoid dividing by zero. */
293 width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
294 max(__crop->width / 8, MT9T001_WINDOW_HEIGHT_MIN + 1),
295 __crop->width);
296 height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
297 max(__crop->height / 8, MT9T001_WINDOW_HEIGHT_MIN + 1),
298 __crop->height);
299
300 hratio = DIV_ROUND_CLOSEST(__crop->width, width);
301 vratio = DIV_ROUND_CLOSEST(__crop->height, height);
302
303 __format = __mt9t001_get_pad_format(mt9t001, fh, format->pad,
304 format->which);
305 __format->width = __crop->width / hratio;
306 __format->height = __crop->height / vratio;
307
308 format->format = *__format;
309
310 return 0;
311}
312
313static int mt9t001_get_crop(struct v4l2_subdev *subdev,
314 struct v4l2_subdev_fh *fh,
315 struct v4l2_subdev_crop *crop)
316{
317 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
318
319 crop->rect = *__mt9t001_get_pad_crop(mt9t001, fh, crop->pad,
320 crop->which);
321 return 0;
322}
323
324static int mt9t001_set_crop(struct v4l2_subdev *subdev,
325 struct v4l2_subdev_fh *fh,
326 struct v4l2_subdev_crop *crop)
327{
328 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
329 struct v4l2_mbus_framefmt *__format;
330 struct v4l2_rect *__crop;
331 struct v4l2_rect rect;
332
333 /* Clamp the crop rectangle boundaries and align them to a multiple of 2
334 * pixels.
335 */
336 rect.left = clamp(ALIGN(crop->rect.left, 2),
337 MT9T001_COLUMN_START_MIN,
338 MT9T001_COLUMN_START_MAX);
339 rect.top = clamp(ALIGN(crop->rect.top, 2),
340 MT9T001_ROW_START_MIN,
341 MT9T001_ROW_START_MAX);
342 rect.width = clamp(ALIGN(crop->rect.width, 2),
343 MT9T001_WINDOW_WIDTH_MIN + 1,
344 MT9T001_WINDOW_WIDTH_MAX + 1);
345 rect.height = clamp(ALIGN(crop->rect.height, 2),
346 MT9T001_WINDOW_HEIGHT_MIN + 1,
347 MT9T001_WINDOW_HEIGHT_MAX + 1);
348
349 rect.width = min(rect.width, MT9T001_PIXEL_ARRAY_WIDTH - rect.left);
350 rect.height = min(rect.height, MT9T001_PIXEL_ARRAY_HEIGHT - rect.top);
351
352 __crop = __mt9t001_get_pad_crop(mt9t001, fh, crop->pad, crop->which);
353
354 if (rect.width != __crop->width || rect.height != __crop->height) {
355 /* Reset the output image size if the crop rectangle size has
356 * been modified.
357 */
358 __format = __mt9t001_get_pad_format(mt9t001, fh, crop->pad,
359 crop->which);
360 __format->width = rect.width;
361 __format->height = rect.height;
362 }
363
364 *__crop = rect;
365 crop->rect = rect;
366
367 return 0;
368}
369
370/* -----------------------------------------------------------------------------
371 * V4L2 subdev control operations
372 */
373
374#define V4L2_CID_TEST_PATTERN (V4L2_CID_USER_BASE | 0x1001)
375#define V4L2_CID_BLACK_LEVEL_AUTO (V4L2_CID_USER_BASE | 0x1002)
376#define V4L2_CID_BLACK_LEVEL_OFFSET (V4L2_CID_USER_BASE | 0x1003)
377#define V4L2_CID_BLACK_LEVEL_CALIBRATE (V4L2_CID_USER_BASE | 0x1004)
378
379#define V4L2_CID_GAIN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1001)
380#define V4L2_CID_GAIN_GREEN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1002)
381#define V4L2_CID_GAIN_GREEN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1003)
382#define V4L2_CID_GAIN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1004)
383
384static u16 mt9t001_gain_value(s32 *gain)
385{
386 /* Gain is controlled by 2 analog stages and a digital stage. Valid
387 * values for the 3 stages are
388 *
389 * Stage Min Max Step
390 * ------------------------------------------
391 * First analog stage x1 x2 1
392 * Second analog stage x1 x4 0.125
393 * Digital stage x1 x16 0.125
394 *
395 * To minimize noise, the gain stages should be used in the second
396 * analog stage, first analog stage, digital stage order. Gain from a
397 * previous stage should be pushed to its maximum value before the next
398 * stage is used.
399 */
400 if (*gain <= 32)
401 return *gain;
402
403 if (*gain <= 64) {
404 *gain &= ~1;
405 return (1 << 6) | (*gain >> 1);
406 }
407
408 *gain &= ~7;
409 return ((*gain - 64) << 5) | (1 << 6) | 32;
410}
411
412static int mt9t001_ctrl_freeze(struct mt9t001 *mt9t001, bool freeze)
413{
414 return mt9t001_set_output_control(mt9t001,
415 freeze ? 0 : MT9T001_OUTPUT_CONTROL_SYNC,
416 freeze ? MT9T001_OUTPUT_CONTROL_SYNC : 0);
417}
418
419static int mt9t001_s_ctrl(struct v4l2_ctrl *ctrl)
420{
421 static const u8 gains[4] = {
422 MT9T001_RED_GAIN, MT9T001_GREEN1_GAIN,
423 MT9T001_GREEN2_GAIN, MT9T001_BLUE_GAIN
424 };
425
426 struct mt9t001 *mt9t001 =
427 container_of(ctrl->handler, struct mt9t001, ctrls);
428 struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
429 unsigned int count;
430 unsigned int i;
431 u16 value;
432 int ret;
433
434 switch (ctrl->id) {
435 case V4L2_CID_GAIN_RED:
436 case V4L2_CID_GAIN_GREEN_RED:
437 case V4L2_CID_GAIN_GREEN_BLUE:
438 case V4L2_CID_GAIN_BLUE:
439
440 /* Disable control updates if more than one control has changed
441 * in the cluster.
442 */
443 for (i = 0, count = 0; i < 4; ++i) {
444 struct v4l2_ctrl *gain = mt9t001->gains[i];
445
446 if (gain->val != gain->cur.val)
447 count++;
448 }
449
450 if (count > 1) {
451 ret = mt9t001_ctrl_freeze(mt9t001, true);
452 if (ret < 0)
453 return ret;
454 }
455
456 /* Update the gain controls. */
457 for (i = 0; i < 4; ++i) {
458 struct v4l2_ctrl *gain = mt9t001->gains[i];
459
460 if (gain->val == gain->cur.val)
461 continue;
462
463 value = mt9t001_gain_value(&gain->val);
464 ret = mt9t001_write(client, gains[i], value);
465 if (ret < 0) {
466 mt9t001_ctrl_freeze(mt9t001, false);
467 return ret;
468 }
469 }
470
471 /* Enable control updates. */
472 if (count > 1) {
473 ret = mt9t001_ctrl_freeze(mt9t001, false);
474 if (ret < 0)
475 return ret;
476 }
477
478 break;
479
480 case V4L2_CID_EXPOSURE:
481 ret = mt9t001_write(client, MT9T001_SHUTTER_WIDTH_LOW,
482 ctrl->val & 0xffff);
483 if (ret < 0)
484 return ret;
485
486 return mt9t001_write(client, MT9T001_SHUTTER_WIDTH_HIGH,
487 ctrl->val >> 16);
488
489 case V4L2_CID_TEST_PATTERN:
490 ret = mt9t001_set_output_control(mt9t001,
491 ctrl->val ? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA,
492 ctrl->val ? MT9T001_OUTPUT_CONTROL_TEST_DATA : 0);
493 if (ret < 0)
494 return ret;
495
496 return mt9t001_write(client, MT9T001_TEST_DATA, ctrl->val << 2);
497
498 case V4L2_CID_BLACK_LEVEL_AUTO:
499 value = ctrl->val ? 0 : MT9T001_BLACK_LEVEL_OVERRIDE;
500 ret = mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
501 value);
502 if (ret < 0)
503 return ret;
504
505 mt9t001->black_level = value;
506 break;
507
508 case V4L2_CID_BLACK_LEVEL_OFFSET:
509 ret = mt9t001_write(client, MT9T001_GREEN1_OFFSET, ctrl->val);
510 if (ret < 0)
511 return ret;
512
513 ret = mt9t001_write(client, MT9T001_GREEN2_OFFSET, ctrl->val);
514 if (ret < 0)
515 return ret;
516
517 ret = mt9t001_write(client, MT9T001_RED_OFFSET, ctrl->val);
518 if (ret < 0)
519 return ret;
520
521 return mt9t001_write(client, MT9T001_BLUE_OFFSET, ctrl->val);
522
523 case V4L2_CID_BLACK_LEVEL_CALIBRATE:
524 return mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
525 MT9T001_BLACK_LEVEL_RECALCULATE |
526 mt9t001->black_level);
527 }
528
529 return 0;
530}
531
532static struct v4l2_ctrl_ops mt9t001_ctrl_ops = {
533 .s_ctrl = mt9t001_s_ctrl,
534};
535
536static const struct v4l2_ctrl_config mt9t001_ctrls[] = {
537 {
538 .ops = &mt9t001_ctrl_ops,
539 .id = V4L2_CID_TEST_PATTERN,
540 .type = V4L2_CTRL_TYPE_INTEGER,
541 .name = "Test pattern",
542 .min = 0,
543 .max = 1023,
544 .step = 1,
545 .def = 0,
546 .flags = 0,
547 }, {
548 .ops = &mt9t001_ctrl_ops,
549 .id = V4L2_CID_BLACK_LEVEL_AUTO,
550 .type = V4L2_CTRL_TYPE_BOOLEAN,
551 .name = "Black Level, Auto",
552 .min = 0,
553 .max = 1,
554 .step = 1,
555 .def = 1,
556 .flags = 0,
557 }, {
558 .ops = &mt9t001_ctrl_ops,
559 .id = V4L2_CID_BLACK_LEVEL_OFFSET,
560 .type = V4L2_CTRL_TYPE_INTEGER,
561 .name = "Black Level, Offset",
562 .min = -256,
563 .max = 255,
564 .step = 1,
565 .def = 32,
566 .flags = 0,
567 }, {
568 .ops = &mt9t001_ctrl_ops,
569 .id = V4L2_CID_BLACK_LEVEL_CALIBRATE,
570 .type = V4L2_CTRL_TYPE_BUTTON,
571 .name = "Black Level, Calibrate",
572 .min = 0,
573 .max = 0,
574 .step = 0,
575 .def = 0,
576 .flags = V4L2_CTRL_FLAG_WRITE_ONLY,
577 },
578};
579
580static const struct v4l2_ctrl_config mt9t001_gains[] = {
581 {
582 .ops = &mt9t001_ctrl_ops,
583 .id = V4L2_CID_GAIN_RED,
584 .type = V4L2_CTRL_TYPE_INTEGER,
585 .name = "Gain, Red",
586 .min = MT9T001_GLOBAL_GAIN_MIN,
587 .max = MT9T001_GLOBAL_GAIN_MAX,
588 .step = 1,
589 .def = MT9T001_GLOBAL_GAIN_MIN,
590 .flags = 0,
591 }, {
592 .ops = &mt9t001_ctrl_ops,
593 .id = V4L2_CID_GAIN_GREEN_RED,
594 .type = V4L2_CTRL_TYPE_INTEGER,
595 .name = "Gain, Green (R)",
596 .min = MT9T001_GLOBAL_GAIN_MIN,
597 .max = MT9T001_GLOBAL_GAIN_MAX,
598 .step = 1,
599 .def = MT9T001_GLOBAL_GAIN_MIN,
600 .flags = 0,
601 }, {
602 .ops = &mt9t001_ctrl_ops,
603 .id = V4L2_CID_GAIN_GREEN_BLUE,
604 .type = V4L2_CTRL_TYPE_INTEGER,
605 .name = "Gain, Green (B)",
606 .min = MT9T001_GLOBAL_GAIN_MIN,
607 .max = MT9T001_GLOBAL_GAIN_MAX,
608 .step = 1,
609 .def = MT9T001_GLOBAL_GAIN_MIN,
610 .flags = 0,
611 }, {
612 .ops = &mt9t001_ctrl_ops,
613 .id = V4L2_CID_GAIN_BLUE,
614 .type = V4L2_CTRL_TYPE_INTEGER,
615 .name = "Gain, Blue",
616 .min = MT9T001_GLOBAL_GAIN_MIN,
617 .max = MT9T001_GLOBAL_GAIN_MAX,
618 .step = 1,
619 .def = MT9T001_GLOBAL_GAIN_MIN,
620 .flags = 0,
621 },
622};
623
624/* -----------------------------------------------------------------------------
625 * V4L2 subdev internal operations
626 */
627
628static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
629{
630 struct v4l2_mbus_framefmt *format;
631 struct v4l2_rect *crop;
632
633 crop = v4l2_subdev_get_try_crop(fh, 0);
634 crop->left = MT9T001_COLUMN_START_DEF;
635 crop->top = MT9T001_ROW_START_DEF;
636 crop->width = MT9T001_WINDOW_WIDTH_DEF + 1;
637 crop->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
638
639 format = v4l2_subdev_get_try_format(fh, 0);
640 format->code = V4L2_MBUS_FMT_SGRBG10_1X10;
641 format->width = MT9T001_WINDOW_WIDTH_DEF + 1;
642 format->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
643 format->field = V4L2_FIELD_NONE;
644 format->colorspace = V4L2_COLORSPACE_SRGB;
645
646 return 0;
647}
648
649static struct v4l2_subdev_video_ops mt9t001_subdev_video_ops = {
650 .s_stream = mt9t001_s_stream,
651};
652
653static struct v4l2_subdev_pad_ops mt9t001_subdev_pad_ops = {
654 .enum_mbus_code = mt9t001_enum_mbus_code,
655 .enum_frame_size = mt9t001_enum_frame_size,
656 .get_fmt = mt9t001_get_format,
657 .set_fmt = mt9t001_set_format,
658 .get_crop = mt9t001_get_crop,
659 .set_crop = mt9t001_set_crop,
660};
661
662static struct v4l2_subdev_ops mt9t001_subdev_ops = {
663 .video = &mt9t001_subdev_video_ops,
664 .pad = &mt9t001_subdev_pad_ops,
665};
666
667static struct v4l2_subdev_internal_ops mt9t001_subdev_internal_ops = {
668 .open = mt9t001_open,
669};
670
671static int mt9t001_video_probe(struct i2c_client *client)
672{
673 struct mt9t001_platform_data *pdata = client->dev.platform_data;
674 s32 data;
675 int ret;
676
677 dev_info(&client->dev, "Probing MT9T001 at address 0x%02x\n",
678 client->addr);
679
680 /* Reset the chip and stop data read out */
681 ret = mt9t001_write(client, MT9T001_RESET, 1);
682 if (ret < 0)
683 return ret;
684
685 ret = mt9t001_write(client, MT9T001_RESET, 0);
686 if (ret < 0)
687 return ret;
688
689 ret = mt9t001_write(client, MT9T001_OUTPUT_CONTROL, 0);
690 if (ret < 0)
691 return ret;
692
693 /* Configure the pixel clock polarity */
694 if (pdata && pdata->clk_pol) {
695 ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK,
696 MT9T001_PIXEL_CLOCK_INVERT);
697 if (ret < 0)
698 return ret;
699 }
700
701 /* Read and check the sensor version */
702 data = mt9t001_read(client, MT9T001_CHIP_VERSION);
703 if (data != MT9T001_CHIP_ID) {
704 dev_err(&client->dev, "MT9T001 not detected, wrong version "
705 "0x%04x\n", data);
706 return -ENODEV;
707 }
708
709 dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n",
710 client->addr);
711
712 return ret;
713}
714
715static int mt9t001_probe(struct i2c_client *client,
716 const struct i2c_device_id *did)
717{
718 struct mt9t001 *mt9t001;
719 unsigned int i;
720 int ret;
721
722 if (!i2c_check_functionality(client->adapter,
723 I2C_FUNC_SMBUS_WORD_DATA)) {
724 dev_warn(&client->adapter->dev,
725 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
726 return -EIO;
727 }
728
729 ret = mt9t001_video_probe(client);
730 if (ret < 0)
731 return ret;
732
733 mt9t001 = kzalloc(sizeof(*mt9t001), GFP_KERNEL);
734 if (!mt9t001)
735 return -ENOMEM;
736
737 v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) +
738 ARRAY_SIZE(mt9t001_gains) + 2);
739
740 v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
741 V4L2_CID_EXPOSURE, MT9T001_SHUTTER_WIDTH_MIN,
742 MT9T001_SHUTTER_WIDTH_MAX, 1,
743 MT9T001_SHUTTER_WIDTH_DEF);
744 v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
745 V4L2_CID_BLACK_LEVEL, 1, 1, 1, 1);
746
747 for (i = 0; i < ARRAY_SIZE(mt9t001_ctrls); ++i)
748 v4l2_ctrl_new_custom(&mt9t001->ctrls, &mt9t001_ctrls[i], NULL);
749
750 for (i = 0; i < ARRAY_SIZE(mt9t001_gains); ++i)
751 mt9t001->gains[i] = v4l2_ctrl_new_custom(&mt9t001->ctrls,
752 &mt9t001_gains[i], NULL);
753
754 v4l2_ctrl_cluster(ARRAY_SIZE(mt9t001_gains), mt9t001->gains);
755
756 mt9t001->subdev.ctrl_handler = &mt9t001->ctrls;
757
758 if (mt9t001->ctrls.error) {
759 printk(KERN_INFO "%s: control initialization error %d\n",
760 __func__, mt9t001->ctrls.error);
761 ret = -EINVAL;
762 goto done;
763 }
764
765 mt9t001->crop.left = MT9T001_COLUMN_START_DEF;
766 mt9t001->crop.top = MT9T001_ROW_START_DEF;
767 mt9t001->crop.width = MT9T001_WINDOW_WIDTH_DEF + 1;
768 mt9t001->crop.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
769
770 mt9t001->format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
771 mt9t001->format.width = MT9T001_WINDOW_WIDTH_DEF + 1;
772 mt9t001->format.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
773 mt9t001->format.field = V4L2_FIELD_NONE;
774 mt9t001->format.colorspace = V4L2_COLORSPACE_SRGB;
775
776 v4l2_i2c_subdev_init(&mt9t001->subdev, client, &mt9t001_subdev_ops);
777 mt9t001->subdev.internal_ops = &mt9t001_subdev_internal_ops;
778 mt9t001->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
779
780 mt9t001->pad.flags = MEDIA_PAD_FL_SOURCE;
781 ret = media_entity_init(&mt9t001->subdev.entity, 1, &mt9t001->pad, 0);
782
783done:
784 if (ret < 0) {
785 v4l2_ctrl_handler_free(&mt9t001->ctrls);
786 media_entity_cleanup(&mt9t001->subdev.entity);
787 kfree(mt9t001);
788 }
789
790 return ret;
791}
792
793static int mt9t001_remove(struct i2c_client *client)
794{
795 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
796 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
797
798 v4l2_ctrl_handler_free(&mt9t001->ctrls);
799 v4l2_device_unregister_subdev(subdev);
800 media_entity_cleanup(&subdev->entity);
801 kfree(mt9t001);
802 return 0;
803}
804
805static const struct i2c_device_id mt9t001_id[] = {
806 { "mt9t001", 0 },
807 { }
808};
809MODULE_DEVICE_TABLE(i2c, mt9t001_id);
810
811static struct i2c_driver mt9t001_driver = {
812 .driver = {
813 .name = "mt9t001",
814 },
815 .probe = mt9t001_probe,
816 .remove = mt9t001_remove,
817 .id_table = mt9t001_id,
818};
819
c6e8d86f 820module_i2c_driver(mt9t001_driver);
0a54b86a
LP		 821
822MODULE_DESCRIPTION("Aptina (Micron) MT9T001 Camera driver");
823MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
824MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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