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2066930d BS |
1 | /* |
2 | * V4L2 Driver for i.MX27/i.MX25 camera host | |
3 | * | |
4 | * Copyright (C) 2008, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography | |
c6a41e32 | 6 | * Copyright (C) 2012, Javier Martin, Vista Silicon S.L. |
2066930d BS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/fs.h> | |
750a6dff | 22 | #include <linux/gcd.h> |
2066930d BS |
23 | #include <linux/interrupt.h> |
24 | #include <linux/kernel.h> | |
67e86524 | 25 | #include <linux/math64.h> |
2066930d BS |
26 | #include <linux/mm.h> |
27 | #include <linux/moduleparam.h> | |
28 | #include <linux/time.h> | |
2066930d BS |
29 | #include <linux/device.h> |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/mutex.h> | |
32 | #include <linux/clk.h> | |
33 | ||
34 | #include <media/v4l2-common.h> | |
35 | #include <media/v4l2-dev.h> | |
c6a41e32 JM |
36 | #include <media/videobuf2-core.h> |
37 | #include <media/videobuf2-dma-contig.h> | |
2066930d BS |
38 | #include <media/soc_camera.h> |
39 | #include <media/soc_mediabus.h> | |
40 | ||
41 | #include <linux/videodev2.h> | |
42 | ||
43 | #include <mach/mx2_cam.h> | |
2066930d BS |
44 | #include <mach/hardware.h> |
45 | ||
46 | #include <asm/dma.h> | |
47 | ||
48 | #define MX2_CAM_DRV_NAME "mx2-camera" | |
64dc3c1a | 49 | #define MX2_CAM_VERSION "0.0.6" |
2066930d BS |
50 | #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" |
51 | ||
52 | /* reset values */ | |
53 | #define CSICR1_RESET_VAL 0x40000800 | |
54 | #define CSICR2_RESET_VAL 0x0 | |
55 | #define CSICR3_RESET_VAL 0x0 | |
56 | ||
57 | /* csi control reg 1 */ | |
58 | #define CSICR1_SWAP16_EN (1 << 31) | |
59 | #define CSICR1_EXT_VSYNC (1 << 30) | |
60 | #define CSICR1_EOF_INTEN (1 << 29) | |
61 | #define CSICR1_PRP_IF_EN (1 << 28) | |
62 | #define CSICR1_CCIR_MODE (1 << 27) | |
63 | #define CSICR1_COF_INTEN (1 << 26) | |
64 | #define CSICR1_SF_OR_INTEN (1 << 25) | |
65 | #define CSICR1_RF_OR_INTEN (1 << 24) | |
66 | #define CSICR1_STATFF_LEVEL (3 << 22) | |
67 | #define CSICR1_STATFF_INTEN (1 << 21) | |
68 | #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ | |
69 | #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ | |
70 | #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ | |
71 | #define CSICR1_RXFF_INTEN (1 << 18) | |
72 | #define CSICR1_SOF_POL (1 << 17) | |
73 | #define CSICR1_SOF_INTEN (1 << 16) | |
74 | #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) | |
75 | #define CSICR1_HSYNC_POL (1 << 11) | |
76 | #define CSICR1_CCIR_EN (1 << 10) | |
77 | #define CSICR1_MCLKEN (1 << 9) | |
78 | #define CSICR1_FCC (1 << 8) | |
79 | #define CSICR1_PACK_DIR (1 << 7) | |
80 | #define CSICR1_CLR_STATFIFO (1 << 6) | |
81 | #define CSICR1_CLR_RXFIFO (1 << 5) | |
82 | #define CSICR1_GCLK_MODE (1 << 4) | |
83 | #define CSICR1_INV_DATA (1 << 3) | |
84 | #define CSICR1_INV_PCLK (1 << 2) | |
85 | #define CSICR1_REDGE (1 << 1) | |
86 | ||
87 | #define SHIFT_STATFF_LEVEL 22 | |
88 | #define SHIFT_RXFF_LEVEL 19 | |
89 | #define SHIFT_MCLKDIV 12 | |
90 | ||
91 | /* control reg 3 */ | |
92 | #define CSICR3_FRMCNT (0xFFFF << 16) | |
93 | #define CSICR3_FRMCNT_RST (1 << 15) | |
94 | #define CSICR3_DMA_REFLASH_RFF (1 << 14) | |
95 | #define CSICR3_DMA_REFLASH_SFF (1 << 13) | |
96 | #define CSICR3_DMA_REQ_EN_RFF (1 << 12) | |
97 | #define CSICR3_DMA_REQ_EN_SFF (1 << 11) | |
98 | #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ | |
99 | #define CSICR3_CSI_SUP (1 << 3) | |
100 | #define CSICR3_ZERO_PACK_EN (1 << 2) | |
101 | #define CSICR3_ECC_INT_EN (1 << 1) | |
102 | #define CSICR3_ECC_AUTO_EN (1 << 0) | |
103 | ||
104 | #define SHIFT_FRMCNT 16 | |
105 | ||
106 | /* csi status reg */ | |
107 | #define CSISR_SFF_OR_INT (1 << 25) | |
108 | #define CSISR_RFF_OR_INT (1 << 24) | |
109 | #define CSISR_STATFF_INT (1 << 21) | |
110 | #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ | |
111 | #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ | |
112 | #define CSISR_RXFF_INT (1 << 18) | |
113 | #define CSISR_EOF_INT (1 << 17) | |
114 | #define CSISR_SOF_INT (1 << 16) | |
115 | #define CSISR_F2_INT (1 << 15) | |
116 | #define CSISR_F1_INT (1 << 14) | |
117 | #define CSISR_COF_INT (1 << 13) | |
118 | #define CSISR_ECC_INT (1 << 1) | |
119 | #define CSISR_DRDY (1 << 0) | |
120 | ||
121 | #define CSICR1 0x00 | |
122 | #define CSICR2 0x04 | |
123 | #define CSISR (cpu_is_mx27() ? 0x08 : 0x18) | |
124 | #define CSISTATFIFO 0x0c | |
125 | #define CSIRFIFO 0x10 | |
126 | #define CSIRXCNT 0x14 | |
127 | #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) | |
128 | #define CSIDMASA_STATFIFO 0x20 | |
129 | #define CSIDMATA_STATFIFO 0x24 | |
130 | #define CSIDMASA_FB1 0x28 | |
131 | #define CSIDMASA_FB2 0x2c | |
132 | #define CSIFBUF_PARA 0x30 | |
133 | #define CSIIMAG_PARA 0x34 | |
134 | ||
135 | /* EMMA PrP */ | |
136 | #define PRP_CNTL 0x00 | |
137 | #define PRP_INTR_CNTL 0x04 | |
138 | #define PRP_INTRSTATUS 0x08 | |
139 | #define PRP_SOURCE_Y_PTR 0x0c | |
140 | #define PRP_SOURCE_CB_PTR 0x10 | |
141 | #define PRP_SOURCE_CR_PTR 0x14 | |
142 | #define PRP_DEST_RGB1_PTR 0x18 | |
143 | #define PRP_DEST_RGB2_PTR 0x1c | |
144 | #define PRP_DEST_Y_PTR 0x20 | |
145 | #define PRP_DEST_CB_PTR 0x24 | |
146 | #define PRP_DEST_CR_PTR 0x28 | |
147 | #define PRP_SRC_FRAME_SIZE 0x2c | |
148 | #define PRP_DEST_CH1_LINE_STRIDE 0x30 | |
149 | #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 | |
150 | #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 | |
151 | #define PRP_CH1_OUT_IMAGE_SIZE 0x3c | |
152 | #define PRP_CH2_OUT_IMAGE_SIZE 0x40 | |
153 | #define PRP_SRC_LINE_STRIDE 0x44 | |
154 | #define PRP_CSC_COEF_012 0x48 | |
155 | #define PRP_CSC_COEF_345 0x4c | |
156 | #define PRP_CSC_COEF_678 0x50 | |
157 | #define PRP_CH1_RZ_HORI_COEF1 0x54 | |
158 | #define PRP_CH1_RZ_HORI_COEF2 0x58 | |
159 | #define PRP_CH1_RZ_HORI_VALID 0x5c | |
160 | #define PRP_CH1_RZ_VERT_COEF1 0x60 | |
161 | #define PRP_CH1_RZ_VERT_COEF2 0x64 | |
162 | #define PRP_CH1_RZ_VERT_VALID 0x68 | |
163 | #define PRP_CH2_RZ_HORI_COEF1 0x6c | |
164 | #define PRP_CH2_RZ_HORI_COEF2 0x70 | |
165 | #define PRP_CH2_RZ_HORI_VALID 0x74 | |
166 | #define PRP_CH2_RZ_VERT_COEF1 0x78 | |
167 | #define PRP_CH2_RZ_VERT_COEF2 0x7c | |
168 | #define PRP_CH2_RZ_VERT_VALID 0x80 | |
169 | ||
170 | #define PRP_CNTL_CH1EN (1 << 0) | |
171 | #define PRP_CNTL_CH2EN (1 << 1) | |
172 | #define PRP_CNTL_CSIEN (1 << 2) | |
173 | #define PRP_CNTL_DATA_IN_YUV420 (0 << 3) | |
174 | #define PRP_CNTL_DATA_IN_YUV422 (1 << 3) | |
175 | #define PRP_CNTL_DATA_IN_RGB16 (2 << 3) | |
176 | #define PRP_CNTL_DATA_IN_RGB32 (3 << 3) | |
177 | #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) | |
178 | #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) | |
179 | #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) | |
180 | #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) | |
181 | #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) | |
182 | #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) | |
183 | #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) | |
184 | #define PRP_CNTL_CH1_LEN (1 << 9) | |
185 | #define PRP_CNTL_CH2_LEN (1 << 10) | |
186 | #define PRP_CNTL_SKIP_FRAME (1 << 11) | |
187 | #define PRP_CNTL_SWRST (1 << 12) | |
188 | #define PRP_CNTL_CLKEN (1 << 13) | |
189 | #define PRP_CNTL_WEN (1 << 14) | |
190 | #define PRP_CNTL_CH1BYP (1 << 15) | |
191 | #define PRP_CNTL_IN_TSKIP(x) ((x) << 16) | |
192 | #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) | |
193 | #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) | |
194 | #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) | |
195 | #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) | |
196 | #define PRP_CNTL_CH2B1EN (1 << 29) | |
197 | #define PRP_CNTL_CH2B2EN (1 << 30) | |
198 | #define PRP_CNTL_CH2FEN (1 << 31) | |
199 | ||
200 | /* IRQ Enable and status register */ | |
201 | #define PRP_INTR_RDERR (1 << 0) | |
202 | #define PRP_INTR_CH1WERR (1 << 1) | |
203 | #define PRP_INTR_CH2WERR (1 << 2) | |
204 | #define PRP_INTR_CH1FC (1 << 3) | |
205 | #define PRP_INTR_CH2FC (1 << 5) | |
206 | #define PRP_INTR_LBOVF (1 << 7) | |
207 | #define PRP_INTR_CH2OVF (1 << 8) | |
208 | ||
750a6dff JM |
209 | /* Resizing registers */ |
210 | #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24) | |
211 | #define PRP_RZ_VALID_BILINEAR (1 << 31) | |
212 | ||
2066930d BS |
213 | #define MAX_VIDEO_MEM 16 |
214 | ||
750a6dff JM |
215 | #define RESIZE_NUM_MIN 1 |
216 | #define RESIZE_NUM_MAX 20 | |
217 | #define BC_COEF 3 | |
218 | #define SZ_COEF (1 << BC_COEF) | |
219 | ||
220 | #define RESIZE_DIR_H 0 | |
221 | #define RESIZE_DIR_V 1 | |
222 | ||
223 | #define RESIZE_ALGO_BILINEAR 0 | |
224 | #define RESIZE_ALGO_AVERAGING 1 | |
225 | ||
f410991d JM |
226 | struct mx2_prp_cfg { |
227 | int channel; | |
228 | u32 in_fmt; | |
229 | u32 out_fmt; | |
230 | u32 src_pixel; | |
231 | u32 ch1_pixel; | |
232 | u32 irq_flags; | |
233 | }; | |
234 | ||
750a6dff JM |
235 | /* prp resizing parameters */ |
236 | struct emma_prp_resize { | |
237 | int algo; /* type of algorithm used */ | |
238 | int len; /* number of coefficients */ | |
239 | unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */ | |
240 | }; | |
241 | ||
f410991d JM |
242 | /* prp configuration for a client-host fmt pair */ |
243 | struct mx2_fmt_cfg { | |
244 | enum v4l2_mbus_pixelcode in_fmt; | |
245 | u32 out_fmt; | |
246 | struct mx2_prp_cfg cfg; | |
247 | }; | |
248 | ||
c6a41e32 JM |
249 | enum mx2_buffer_state { |
250 | MX2_STATE_QUEUED, | |
251 | MX2_STATE_ACTIVE, | |
252 | MX2_STATE_DONE, | |
253 | }; | |
254 | ||
560fab62 JM |
255 | struct mx2_buf_internal { |
256 | struct list_head queue; | |
257 | int bufnum; | |
258 | bool discard; | |
259 | }; | |
260 | ||
c6a41e32 JM |
261 | /* buffer for one video frame */ |
262 | struct mx2_buffer { | |
263 | /* common v4l buffer stuff -- must be first */ | |
264 | struct vb2_buffer vb; | |
c6a41e32 | 265 | enum mx2_buffer_state state; |
560fab62 | 266 | struct mx2_buf_internal internal; |
c6a41e32 JM |
267 | }; |
268 | ||
2066930d BS |
269 | struct mx2_camera_dev { |
270 | struct device *dev; | |
271 | struct soc_camera_host soc_host; | |
272 | struct soc_camera_device *icd; | |
273 | struct clk *clk_csi, *clk_emma; | |
274 | ||
275 | unsigned int irq_csi, irq_emma; | |
276 | void __iomem *base_csi, *base_emma; | |
277 | unsigned long base_dma; | |
278 | ||
279 | struct mx2_camera_platform_data *pdata; | |
280 | struct resource *res_csi, *res_emma; | |
281 | unsigned long platform_flags; | |
282 | ||
283 | struct list_head capture; | |
284 | struct list_head active_bufs; | |
cdc9d6f1 | 285 | struct list_head discard; |
2066930d BS |
286 | |
287 | spinlock_t lock; | |
288 | ||
289 | int dma; | |
290 | struct mx2_buffer *active; | |
291 | struct mx2_buffer *fb1_active; | |
292 | struct mx2_buffer *fb2_active; | |
293 | ||
2066930d BS |
294 | u32 csicr1; |
295 | ||
560fab62 | 296 | struct mx2_buf_internal buf_discard[2]; |
79d3c2c2 | 297 | void *discard_buffer; |
2066930d BS |
298 | dma_addr_t discard_buffer_dma; |
299 | size_t discard_size; | |
f410991d | 300 | struct mx2_fmt_cfg *emma_prp; |
750a6dff JM |
301 | struct emma_prp_resize resizing[2]; |
302 | unsigned int s_width, s_height; | |
ccd1a499 | 303 | u32 frame_count; |
c6a41e32 | 304 | struct vb2_alloc_ctx *alloc_ctx; |
2066930d BS |
305 | }; |
306 | ||
560fab62 JM |
307 | static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf) |
308 | { | |
309 | return container_of(int_buf, struct mx2_buffer, internal); | |
310 | } | |
311 | ||
f410991d JM |
312 | static struct mx2_fmt_cfg mx27_emma_prp_table[] = { |
313 | /* | |
314 | * This is a generic configuration which is valid for most | |
315 | * prp input-output format combinations. | |
316 | * We set the incomming and outgoing pixelformat to a | |
317 | * 16 Bit wide format and adjust the bytesperline | |
318 | * accordingly. With this configuration the inputdata | |
319 | * will not be changed by the emma and could be any type | |
320 | * of 16 Bit Pixelformat. | |
321 | */ | |
322 | { | |
323 | .in_fmt = 0, | |
324 | .out_fmt = 0, | |
325 | .cfg = { | |
326 | .channel = 1, | |
327 | .in_fmt = PRP_CNTL_DATA_IN_RGB16, | |
328 | .out_fmt = PRP_CNTL_CH1_OUT_RGB16, | |
329 | .src_pixel = 0x2ca00565, /* RGB565 */ | |
330 | .ch1_pixel = 0x2ca00565, /* RGB565 */ | |
331 | .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR | | |
332 | PRP_INTR_CH1FC | PRP_INTR_LBOVF, | |
333 | } | |
334 | }, | |
335 | { | |
336 | .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8, | |
337 | .out_fmt = V4L2_PIX_FMT_YUV420, | |
338 | .cfg = { | |
339 | .channel = 2, | |
340 | .in_fmt = PRP_CNTL_DATA_IN_YUV422, | |
341 | .out_fmt = PRP_CNTL_CH2_OUT_YUV420, | |
342 | .src_pixel = 0x22000888, /* YUV422 (YUYV) */ | |
343 | .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR | | |
344 | PRP_INTR_CH2FC | PRP_INTR_LBOVF | | |
345 | PRP_INTR_CH2OVF, | |
346 | } | |
347 | }, | |
348 | }; | |
349 | ||
350 | static struct mx2_fmt_cfg *mx27_emma_prp_get_format( | |
351 | enum v4l2_mbus_pixelcode in_fmt, | |
352 | u32 out_fmt) | |
353 | { | |
354 | int i; | |
355 | ||
356 | for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++) | |
357 | if ((mx27_emma_prp_table[i].in_fmt == in_fmt) && | |
358 | (mx27_emma_prp_table[i].out_fmt == out_fmt)) { | |
359 | return &mx27_emma_prp_table[i]; | |
360 | } | |
361 | /* If no match return the most generic configuration */ | |
362 | return &mx27_emma_prp_table[0]; | |
363 | }; | |
364 | ||
cdc9d6f1 JM |
365 | static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev, |
366 | unsigned long phys, int bufnum) | |
367 | { | |
368 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
369 | ||
370 | if (prp->cfg.channel == 1) { | |
371 | writel(phys, pcdev->base_emma + | |
372 | PRP_DEST_RGB1_PTR + 4 * bufnum); | |
373 | } else { | |
374 | writel(phys, pcdev->base_emma + | |
375 | PRP_DEST_Y_PTR - 0x14 * bufnum); | |
376 | if (prp->out_fmt == V4L2_PIX_FMT_YUV420) { | |
377 | u32 imgsize = pcdev->icd->user_height * | |
378 | pcdev->icd->user_width; | |
379 | ||
380 | writel(phys + imgsize, pcdev->base_emma + | |
381 | PRP_DEST_CB_PTR - 0x14 * bufnum); | |
382 | writel(phys + ((5 * imgsize) / 4), pcdev->base_emma + | |
383 | PRP_DEST_CR_PTR - 0x14 * bufnum); | |
384 | } | |
385 | } | |
386 | } | |
387 | ||
2066930d BS |
388 | static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) |
389 | { | |
390 | unsigned long flags; | |
391 | ||
392 | clk_disable(pcdev->clk_csi); | |
393 | writel(0, pcdev->base_csi + CSICR1); | |
2c9ba37d | 394 | if (cpu_is_mx27()) { |
2066930d BS |
395 | writel(0, pcdev->base_emma + PRP_CNTL); |
396 | } else if (cpu_is_mx25()) { | |
397 | spin_lock_irqsave(&pcdev->lock, flags); | |
398 | pcdev->fb1_active = NULL; | |
399 | pcdev->fb2_active = NULL; | |
400 | writel(0, pcdev->base_csi + CSIDMASA_FB1); | |
401 | writel(0, pcdev->base_csi + CSIDMASA_FB2); | |
402 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
403 | } | |
404 | } | |
405 | ||
406 | /* | |
407 | * The following two functions absolutely depend on the fact, that | |
408 | * there can be only one camera on mx2 camera sensor interface | |
409 | */ | |
410 | static int mx2_camera_add_device(struct soc_camera_device *icd) | |
411 | { | |
7dfff953 | 412 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
2066930d BS |
413 | struct mx2_camera_dev *pcdev = ici->priv; |
414 | int ret; | |
415 | u32 csicr1; | |
416 | ||
417 | if (pcdev->icd) | |
418 | return -EBUSY; | |
419 | ||
420 | ret = clk_enable(pcdev->clk_csi); | |
421 | if (ret < 0) | |
422 | return ret; | |
423 | ||
424 | csicr1 = CSICR1_MCLKEN; | |
425 | ||
2c9ba37d | 426 | if (cpu_is_mx27()) { |
2066930d BS |
427 | csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | |
428 | CSICR1_RXFF_LEVEL(0); | |
429 | } else if (cpu_is_mx27()) | |
430 | csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); | |
431 | ||
432 | pcdev->csicr1 = csicr1; | |
433 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
434 | ||
435 | pcdev->icd = icd; | |
cdc9d6f1 | 436 | pcdev->frame_count = 0; |
2066930d | 437 | |
7dfff953 | 438 | dev_info(icd->parent, "Camera driver attached to camera %d\n", |
2066930d BS |
439 | icd->devnum); |
440 | ||
441 | return 0; | |
442 | } | |
443 | ||
444 | static void mx2_camera_remove_device(struct soc_camera_device *icd) | |
445 | { | |
7dfff953 | 446 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
2066930d BS |
447 | struct mx2_camera_dev *pcdev = ici->priv; |
448 | ||
449 | BUG_ON(icd != pcdev->icd); | |
450 | ||
7dfff953 | 451 | dev_info(icd->parent, "Camera driver detached from camera %d\n", |
2066930d BS |
452 | icd->devnum); |
453 | ||
454 | mx2_camera_deactivate(pcdev); | |
455 | ||
2066930d BS |
456 | pcdev->icd = NULL; |
457 | } | |
458 | ||
2066930d BS |
459 | static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, |
460 | int state) | |
461 | { | |
c6a41e32 | 462 | struct vb2_buffer *vb; |
2066930d BS |
463 | struct mx2_buffer *buf; |
464 | struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : | |
465 | &pcdev->fb2_active; | |
466 | u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; | |
467 | unsigned long flags; | |
468 | ||
469 | spin_lock_irqsave(&pcdev->lock, flags); | |
470 | ||
5384a12b BS |
471 | if (*fb_active == NULL) |
472 | goto out; | |
473 | ||
2066930d | 474 | vb = &(*fb_active)->vb; |
c6a41e32 JM |
475 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
476 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d | 477 | |
c6a41e32 JM |
478 | do_gettimeofday(&vb->v4l2_buf.timestamp); |
479 | vb->v4l2_buf.sequence++; | |
480 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
2066930d BS |
481 | |
482 | if (list_empty(&pcdev->capture)) { | |
483 | buf = NULL; | |
484 | writel(0, pcdev->base_csi + fb_reg); | |
485 | } else { | |
a654ba16 | 486 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
560fab62 | 487 | internal.queue); |
2066930d | 488 | vb = &buf->vb; |
560fab62 | 489 | list_del(&buf->internal.queue); |
c6a41e32 JM |
490 | buf->state = MX2_STATE_ACTIVE; |
491 | writel(vb2_dma_contig_plane_dma_addr(vb, 0), | |
492 | pcdev->base_csi + fb_reg); | |
2066930d BS |
493 | } |
494 | ||
495 | *fb_active = buf; | |
496 | ||
5384a12b | 497 | out: |
2066930d BS |
498 | spin_unlock_irqrestore(&pcdev->lock, flags); |
499 | } | |
500 | ||
501 | static irqreturn_t mx25_camera_irq(int irq_csi, void *data) | |
502 | { | |
503 | struct mx2_camera_dev *pcdev = data; | |
504 | u32 status = readl(pcdev->base_csi + CSISR); | |
505 | ||
506 | if (status & CSISR_DMA_TSF_FB1_INT) | |
c6a41e32 | 507 | mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE); |
2066930d | 508 | else if (status & CSISR_DMA_TSF_FB2_INT) |
c6a41e32 | 509 | mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE); |
2066930d BS |
510 | |
511 | /* FIXME: handle CSISR_RFF_OR_INT */ | |
512 | ||
513 | writel(status, pcdev->base_csi + CSISR); | |
514 | ||
515 | return IRQ_HANDLED; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Videobuf operations | |
520 | */ | |
c6a41e32 JM |
521 | static int mx2_videobuf_setup(struct vb2_queue *vq, |
522 | const struct v4l2_format *fmt, | |
523 | unsigned int *count, unsigned int *num_planes, | |
524 | unsigned int sizes[], void *alloc_ctxs[]) | |
2066930d | 525 | { |
c6a41e32 JM |
526 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); |
527 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
528 | struct mx2_camera_dev *pcdev = ici->priv; | |
2066930d | 529 | |
c6a41e32 JM |
530 | dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]); |
531 | ||
532 | /* TODO: support for VIDIOC_CREATE_BUFS not ready */ | |
533 | if (fmt != NULL) | |
534 | return -ENOTTY; | |
2066930d | 535 | |
c6a41e32 JM |
536 | alloc_ctxs[0] = pcdev->alloc_ctx; |
537 | ||
2b61d46e | 538 | sizes[0] = icd->sizeimage; |
2066930d BS |
539 | |
540 | if (0 == *count) | |
541 | *count = 32; | |
c6a41e32 JM |
542 | if (!*num_planes && |
543 | sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024) | |
544 | *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0]; | |
2066930d | 545 | |
c6a41e32 | 546 | *num_planes = 1; |
2066930d | 547 | |
c6a41e32 | 548 | return 0; |
2066930d BS |
549 | } |
550 | ||
c6a41e32 | 551 | static int mx2_videobuf_prepare(struct vb2_buffer *vb) |
2066930d | 552 | { |
c6a41e32 | 553 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
2066930d BS |
554 | int ret = 0; |
555 | ||
c6a41e32 JM |
556 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
557 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d | 558 | |
2066930d BS |
559 | #ifdef DEBUG |
560 | /* | |
561 | * This can be useful if you want to see if we actually fill | |
562 | * the buffer with something | |
563 | */ | |
c6a41e32 JM |
564 | memset((void *)vb2_plane_vaddr(vb, 0), |
565 | 0xaa, vb2_get_plane_payload(vb, 0)); | |
2066930d BS |
566 | #endif |
567 | ||
2b61d46e | 568 | vb2_set_plane_payload(vb, 0, icd->sizeimage); |
c6a41e32 JM |
569 | if (vb2_plane_vaddr(vb, 0) && |
570 | vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) { | |
2066930d BS |
571 | ret = -EINVAL; |
572 | goto out; | |
573 | } | |
574 | ||
2066930d BS |
575 | return 0; |
576 | ||
2066930d BS |
577 | out: |
578 | return ret; | |
579 | } | |
580 | ||
c6a41e32 | 581 | static void mx2_videobuf_queue(struct vb2_buffer *vb) |
2066930d | 582 | { |
c6a41e32 | 583 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
2066930d | 584 | struct soc_camera_host *ici = |
7dfff953 | 585 | to_soc_camera_host(icd->parent); |
2066930d BS |
586 | struct mx2_camera_dev *pcdev = ici->priv; |
587 | struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); | |
588 | unsigned long flags; | |
589 | ||
c6a41e32 JM |
590 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
591 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d BS |
592 | |
593 | spin_lock_irqsave(&pcdev->lock, flags); | |
594 | ||
c6a41e32 | 595 | buf->state = MX2_STATE_QUEUED; |
560fab62 | 596 | list_add_tail(&buf->internal.queue, &pcdev->capture); |
2066930d | 597 | |
2c9ba37d | 598 | if (cpu_is_mx25()) { |
2066930d BS |
599 | u32 csicr3, dma_inten = 0; |
600 | ||
601 | if (pcdev->fb1_active == NULL) { | |
c6a41e32 | 602 | writel(vb2_dma_contig_plane_dma_addr(vb, 0), |
2066930d BS |
603 | pcdev->base_csi + CSIDMASA_FB1); |
604 | pcdev->fb1_active = buf; | |
605 | dma_inten = CSICR1_FB1_DMA_INTEN; | |
606 | } else if (pcdev->fb2_active == NULL) { | |
c6a41e32 | 607 | writel(vb2_dma_contig_plane_dma_addr(vb, 0), |
2066930d BS |
608 | pcdev->base_csi + CSIDMASA_FB2); |
609 | pcdev->fb2_active = buf; | |
610 | dma_inten = CSICR1_FB2_DMA_INTEN; | |
611 | } | |
612 | ||
613 | if (dma_inten) { | |
560fab62 | 614 | list_del(&buf->internal.queue); |
c6a41e32 | 615 | buf->state = MX2_STATE_ACTIVE; |
2066930d BS |
616 | |
617 | csicr3 = readl(pcdev->base_csi + CSICR3); | |
618 | ||
619 | /* Reflash DMA */ | |
620 | writel(csicr3 | CSICR3_DMA_REFLASH_RFF, | |
621 | pcdev->base_csi + CSICR3); | |
622 | ||
623 | /* clear & enable interrupts */ | |
624 | writel(dma_inten, pcdev->base_csi + CSISR); | |
625 | pcdev->csicr1 |= dma_inten; | |
626 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
627 | ||
628 | /* enable DMA */ | |
629 | csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); | |
630 | writel(csicr3, pcdev->base_csi + CSICR3); | |
631 | } | |
632 | } | |
633 | ||
2066930d BS |
634 | spin_unlock_irqrestore(&pcdev->lock, flags); |
635 | } | |
636 | ||
c6a41e32 | 637 | static void mx2_videobuf_release(struct vb2_buffer *vb) |
2066930d | 638 | { |
c6a41e32 | 639 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 640 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
2066930d BS |
641 | struct mx2_camera_dev *pcdev = ici->priv; |
642 | struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); | |
643 | unsigned long flags; | |
644 | ||
645 | #ifdef DEBUG | |
c6a41e32 JM |
646 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, |
647 | vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); | |
2066930d | 648 | |
c6a41e32 JM |
649 | switch (buf->state) { |
650 | case MX2_STATE_ACTIVE: | |
7dfff953 | 651 | dev_info(icd->parent, "%s (active)\n", __func__); |
2066930d | 652 | break; |
c6a41e32 | 653 | case MX2_STATE_QUEUED: |
7dfff953 | 654 | dev_info(icd->parent, "%s (queued)\n", __func__); |
2066930d | 655 | break; |
2066930d | 656 | default: |
7dfff953 | 657 | dev_info(icd->parent, "%s (unknown) %d\n", __func__, |
c6a41e32 | 658 | buf->state); |
2066930d BS |
659 | break; |
660 | } | |
661 | #endif | |
662 | ||
663 | /* | |
664 | * Terminate only queued but inactive buffers. Active buffers are | |
665 | * released when they become inactive after videobuf_waiton(). | |
666 | * | |
7c6b7319 BS |
667 | * FIXME: implement forced termination of active buffers for mx27 and |
668 | * mx27 eMMA, so that the user won't get stuck in an uninterruptible | |
669 | * state. This requires a specific handling for each of the these DMA | |
670 | * types. | |
2066930d | 671 | */ |
c6a41e32 | 672 | |
2066930d | 673 | spin_lock_irqsave(&pcdev->lock, flags); |
c6a41e32 | 674 | if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) { |
7c6b7319 BS |
675 | if (pcdev->fb1_active == buf) { |
676 | pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN; | |
677 | writel(0, pcdev->base_csi + CSIDMASA_FB1); | |
678 | pcdev->fb1_active = NULL; | |
679 | } else if (pcdev->fb2_active == buf) { | |
680 | pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN; | |
681 | writel(0, pcdev->base_csi + CSIDMASA_FB2); | |
682 | pcdev->fb2_active = NULL; | |
683 | } | |
684 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
2066930d BS |
685 | } |
686 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
2066930d BS |
687 | } |
688 | ||
cdc9d6f1 JM |
689 | static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, |
690 | int bytesperline) | |
691 | { | |
692 | struct soc_camera_host *ici = | |
693 | to_soc_camera_host(icd->parent); | |
694 | struct mx2_camera_dev *pcdev = ici->priv; | |
695 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
696 | ||
750a6dff | 697 | writel((pcdev->s_width << 16) | pcdev->s_height, |
cdc9d6f1 JM |
698 | pcdev->base_emma + PRP_SRC_FRAME_SIZE); |
699 | writel(prp->cfg.src_pixel, | |
700 | pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); | |
701 | if (prp->cfg.channel == 1) { | |
702 | writel((icd->user_width << 16) | icd->user_height, | |
703 | pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); | |
704 | writel(bytesperline, | |
705 | pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); | |
706 | writel(prp->cfg.ch1_pixel, | |
707 | pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); | |
708 | } else { /* channel 2 */ | |
709 | writel((icd->user_width << 16) | icd->user_height, | |
710 | pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE); | |
711 | } | |
712 | ||
713 | /* Enable interrupts */ | |
714 | writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL); | |
715 | } | |
716 | ||
750a6dff JM |
717 | static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev) |
718 | { | |
719 | int dir; | |
720 | ||
721 | for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) { | |
722 | unsigned char *s = pcdev->resizing[dir].s; | |
723 | int len = pcdev->resizing[dir].len; | |
724 | unsigned int coeff[2] = {0, 0}; | |
725 | unsigned int valid = 0; | |
726 | int i; | |
727 | ||
728 | if (len == 0) | |
729 | continue; | |
730 | ||
731 | for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) { | |
732 | int j; | |
733 | ||
734 | j = i > 9 ? 1 : 0; | |
735 | coeff[j] = (coeff[j] << BC_COEF) | | |
736 | (s[i] & (SZ_COEF - 1)); | |
737 | ||
738 | if (i == 5 || i == 15) | |
739 | coeff[j] <<= 1; | |
740 | ||
741 | valid = (valid << 1) | (s[i] >> BC_COEF); | |
742 | } | |
743 | ||
744 | valid |= PRP_RZ_VALID_TBL_LEN(len); | |
745 | ||
746 | if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR) | |
747 | valid |= PRP_RZ_VALID_BILINEAR; | |
748 | ||
749 | if (pcdev->emma_prp->cfg.channel == 1) { | |
750 | if (dir == RESIZE_DIR_H) { | |
751 | writel(coeff[0], pcdev->base_emma + | |
752 | PRP_CH1_RZ_HORI_COEF1); | |
753 | writel(coeff[1], pcdev->base_emma + | |
754 | PRP_CH1_RZ_HORI_COEF2); | |
755 | writel(valid, pcdev->base_emma + | |
756 | PRP_CH1_RZ_HORI_VALID); | |
757 | } else { | |
758 | writel(coeff[0], pcdev->base_emma + | |
759 | PRP_CH1_RZ_VERT_COEF1); | |
760 | writel(coeff[1], pcdev->base_emma + | |
761 | PRP_CH1_RZ_VERT_COEF2); | |
762 | writel(valid, pcdev->base_emma + | |
763 | PRP_CH1_RZ_VERT_VALID); | |
764 | } | |
765 | } else { | |
766 | if (dir == RESIZE_DIR_H) { | |
767 | writel(coeff[0], pcdev->base_emma + | |
768 | PRP_CH2_RZ_HORI_COEF1); | |
769 | writel(coeff[1], pcdev->base_emma + | |
770 | PRP_CH2_RZ_HORI_COEF2); | |
771 | writel(valid, pcdev->base_emma + | |
772 | PRP_CH2_RZ_HORI_VALID); | |
773 | } else { | |
774 | writel(coeff[0], pcdev->base_emma + | |
775 | PRP_CH2_RZ_VERT_COEF1); | |
776 | writel(coeff[1], pcdev->base_emma + | |
777 | PRP_CH2_RZ_VERT_COEF2); | |
778 | writel(valid, pcdev->base_emma + | |
779 | PRP_CH2_RZ_VERT_VALID); | |
780 | } | |
781 | } | |
782 | } | |
783 | } | |
784 | ||
fb51cbdd JM |
785 | static int mx2_start_streaming(struct vb2_queue *q, unsigned int count) |
786 | { | |
787 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
788 | struct soc_camera_host *ici = | |
789 | to_soc_camera_host(icd->parent); | |
790 | struct mx2_camera_dev *pcdev = ici->priv; | |
791 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
cdc9d6f1 JM |
792 | struct vb2_buffer *vb; |
793 | struct mx2_buffer *buf; | |
794 | unsigned long phys; | |
795 | int bytesperline; | |
fb51cbdd JM |
796 | |
797 | if (cpu_is_mx27()) { | |
798 | unsigned long flags; | |
799 | if (count < 2) | |
800 | return -EINVAL; | |
801 | ||
802 | spin_lock_irqsave(&pcdev->lock, flags); | |
cdc9d6f1 | 803 | |
a654ba16 | 804 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
560fab62 JM |
805 | internal.queue); |
806 | buf->internal.bufnum = 0; | |
cdc9d6f1 JM |
807 | vb = &buf->vb; |
808 | buf->state = MX2_STATE_ACTIVE; | |
809 | ||
810 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); | |
560fab62 | 811 | mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum); |
cdc9d6f1 JM |
812 | list_move_tail(pcdev->capture.next, &pcdev->active_bufs); |
813 | ||
a654ba16 | 814 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
560fab62 JM |
815 | internal.queue); |
816 | buf->internal.bufnum = 1; | |
cdc9d6f1 JM |
817 | vb = &buf->vb; |
818 | buf->state = MX2_STATE_ACTIVE; | |
819 | ||
820 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); | |
560fab62 | 821 | mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum); |
cdc9d6f1 JM |
822 | list_move_tail(pcdev->capture.next, &pcdev->active_bufs); |
823 | ||
824 | bytesperline = soc_mbus_bytes_per_line(icd->user_width, | |
825 | icd->current_fmt->host_fmt); | |
826 | if (bytesperline < 0) | |
827 | return bytesperline; | |
828 | ||
829 | /* | |
830 | * I didn't manage to properly enable/disable the prp | |
831 | * on a per frame basis during running transfers, | |
832 | * thus we allocate a buffer here and use it to | |
833 | * discard frames when no buffer is available. | |
834 | * Feel free to work on this ;) | |
835 | */ | |
836 | pcdev->discard_size = icd->user_height * bytesperline; | |
837 | pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, | |
838 | pcdev->discard_size, &pcdev->discard_buffer_dma, | |
839 | GFP_KERNEL); | |
840 | if (!pcdev->discard_buffer) | |
841 | return -ENOMEM; | |
842 | ||
843 | pcdev->buf_discard[0].discard = true; | |
844 | list_add_tail(&pcdev->buf_discard[0].queue, | |
845 | &pcdev->discard); | |
846 | ||
847 | pcdev->buf_discard[1].discard = true; | |
848 | list_add_tail(&pcdev->buf_discard[1].queue, | |
849 | &pcdev->discard); | |
850 | ||
750a6dff JM |
851 | mx2_prp_resize_commit(pcdev); |
852 | ||
cdc9d6f1 JM |
853 | mx27_camera_emma_buf_init(icd, bytesperline); |
854 | ||
fb51cbdd JM |
855 | if (prp->cfg.channel == 1) { |
856 | writel(PRP_CNTL_CH1EN | | |
857 | PRP_CNTL_CSIEN | | |
858 | prp->cfg.in_fmt | | |
859 | prp->cfg.out_fmt | | |
860 | PRP_CNTL_CH1_LEN | | |
861 | PRP_CNTL_CH1BYP | | |
862 | PRP_CNTL_CH1_TSKIP(0) | | |
863 | PRP_CNTL_IN_TSKIP(0), | |
864 | pcdev->base_emma + PRP_CNTL); | |
865 | } else { | |
866 | writel(PRP_CNTL_CH2EN | | |
867 | PRP_CNTL_CSIEN | | |
868 | prp->cfg.in_fmt | | |
869 | prp->cfg.out_fmt | | |
870 | PRP_CNTL_CH2_LEN | | |
871 | PRP_CNTL_CH2_TSKIP(0) | | |
872 | PRP_CNTL_IN_TSKIP(0), | |
873 | pcdev->base_emma + PRP_CNTL); | |
874 | } | |
875 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
876 | } | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | static int mx2_stop_streaming(struct vb2_queue *q) | |
882 | { | |
883 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
884 | struct soc_camera_host *ici = | |
885 | to_soc_camera_host(icd->parent); | |
886 | struct mx2_camera_dev *pcdev = ici->priv; | |
887 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; | |
888 | unsigned long flags; | |
cdc9d6f1 | 889 | void *b; |
fb51cbdd JM |
890 | u32 cntl; |
891 | ||
fb51cbdd | 892 | if (cpu_is_mx27()) { |
cdc9d6f1 JM |
893 | spin_lock_irqsave(&pcdev->lock, flags); |
894 | ||
fb51cbdd JM |
895 | cntl = readl(pcdev->base_emma + PRP_CNTL); |
896 | if (prp->cfg.channel == 1) { | |
897 | writel(cntl & ~PRP_CNTL_CH1EN, | |
898 | pcdev->base_emma + PRP_CNTL); | |
899 | } else { | |
900 | writel(cntl & ~PRP_CNTL_CH2EN, | |
901 | pcdev->base_emma + PRP_CNTL); | |
902 | } | |
cdc9d6f1 JM |
903 | INIT_LIST_HEAD(&pcdev->capture); |
904 | INIT_LIST_HEAD(&pcdev->active_bufs); | |
905 | INIT_LIST_HEAD(&pcdev->discard); | |
906 | ||
907 | b = pcdev->discard_buffer; | |
908 | pcdev->discard_buffer = NULL; | |
909 | ||
910 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
911 | ||
912 | dma_free_coherent(ici->v4l2_dev.dev, | |
913 | pcdev->discard_size, b, pcdev->discard_buffer_dma); | |
fb51cbdd | 914 | } |
fb51cbdd JM |
915 | |
916 | return 0; | |
917 | } | |
918 | ||
c6a41e32 | 919 | static struct vb2_ops mx2_videobuf_ops = { |
fb51cbdd JM |
920 | .queue_setup = mx2_videobuf_setup, |
921 | .buf_prepare = mx2_videobuf_prepare, | |
922 | .buf_queue = mx2_videobuf_queue, | |
923 | .buf_cleanup = mx2_videobuf_release, | |
924 | .start_streaming = mx2_start_streaming, | |
925 | .stop_streaming = mx2_stop_streaming, | |
2066930d BS |
926 | }; |
927 | ||
c6a41e32 | 928 | static int mx2_camera_init_videobuf(struct vb2_queue *q, |
2066930d BS |
929 | struct soc_camera_device *icd) |
930 | { | |
c6a41e32 JM |
931 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
932 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
933 | q->drv_priv = icd; | |
934 | q->ops = &mx2_videobuf_ops; | |
935 | q->mem_ops = &vb2_dma_contig_memops; | |
936 | q->buf_struct_size = sizeof(struct mx2_buffer); | |
937 | ||
938 | return vb2_queue_init(q); | |
2066930d BS |
939 | } |
940 | ||
db592a24 GL |
941 | #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \ |
942 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | \ | |
943 | V4L2_MBUS_VSYNC_ACTIVE_LOW | \ | |
944 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | \ | |
945 | V4L2_MBUS_HSYNC_ACTIVE_LOW | \ | |
946 | V4L2_MBUS_PCLK_SAMPLE_RISING | \ | |
947 | V4L2_MBUS_PCLK_SAMPLE_FALLING | \ | |
948 | V4L2_MBUS_DATA_ACTIVE_HIGH | \ | |
949 | V4L2_MBUS_DATA_ACTIVE_LOW) | |
2066930d BS |
950 | |
951 | static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) | |
952 | { | |
953 | u32 cntl; | |
954 | int count = 0; | |
955 | ||
956 | cntl = readl(pcdev->base_emma + PRP_CNTL); | |
957 | writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); | |
958 | while (count++ < 100) { | |
959 | if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) | |
960 | return 0; | |
961 | barrier(); | |
962 | udelay(1); | |
963 | } | |
964 | ||
965 | return -ETIMEDOUT; | |
966 | } | |
967 | ||
8843d119 | 968 | static int mx2_camera_set_bus_param(struct soc_camera_device *icd) |
2066930d | 969 | { |
db592a24 GL |
970 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
971 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
2066930d | 972 | struct mx2_camera_dev *pcdev = ici->priv; |
db592a24 GL |
973 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
974 | unsigned long common_flags; | |
975 | int ret; | |
2066930d BS |
976 | int bytesperline; |
977 | u32 csicr1 = pcdev->csicr1; | |
978 | ||
db592a24 GL |
979 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
980 | if (!ret) { | |
981 | common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS); | |
982 | if (!common_flags) { | |
983 | dev_warn(icd->parent, | |
984 | "Flags incompatible: camera 0x%x, host 0x%x\n", | |
985 | cfg.flags, MX2_BUS_FLAGS); | |
986 | return -EINVAL; | |
987 | } | |
988 | } else if (ret != -ENOIOCTLCMD) { | |
989 | return ret; | |
990 | } else { | |
991 | common_flags = MX2_BUS_FLAGS; | |
992 | } | |
2066930d | 993 | |
db592a24 GL |
994 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
995 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
2066930d | 996 | if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) |
db592a24 | 997 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
2066930d | 998 | else |
db592a24 | 999 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
2066930d BS |
1000 | } |
1001 | ||
db592a24 GL |
1002 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1003 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
2066930d | 1004 | if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) |
db592a24 | 1005 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
2066930d | 1006 | else |
db592a24 | 1007 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
2066930d BS |
1008 | } |
1009 | ||
db592a24 GL |
1010 | cfg.flags = common_flags; |
1011 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1012 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1013 | dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", | |
1014 | common_flags, ret); | |
2066930d | 1015 | return ret; |
db592a24 | 1016 | } |
2066930d | 1017 | |
db592a24 | 1018 | if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) |
d86097e1 | 1019 | csicr1 |= CSICR1_REDGE; |
db592a24 | 1020 | if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) |
2066930d | 1021 | csicr1 |= CSICR1_SOF_POL; |
db592a24 | 1022 | if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) |
2066930d | 1023 | csicr1 |= CSICR1_HSYNC_POL; |
70c276a6 GL |
1024 | if (pcdev->platform_flags & MX2_CAMERA_SWAP16) |
1025 | csicr1 |= CSICR1_SWAP16_EN; | |
2066930d BS |
1026 | if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) |
1027 | csicr1 |= CSICR1_EXT_VSYNC; | |
1028 | if (pcdev->platform_flags & MX2_CAMERA_CCIR) | |
1029 | csicr1 |= CSICR1_CCIR_EN; | |
1030 | if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) | |
1031 | csicr1 |= CSICR1_CCIR_MODE; | |
1032 | if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) | |
1033 | csicr1 |= CSICR1_GCLK_MODE; | |
1034 | if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) | |
1035 | csicr1 |= CSICR1_INV_DATA; | |
70c276a6 GL |
1036 | if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) |
1037 | csicr1 |= CSICR1_PACK_DIR; | |
2066930d BS |
1038 | |
1039 | pcdev->csicr1 = csicr1; | |
1040 | ||
1041 | bytesperline = soc_mbus_bytes_per_line(icd->user_width, | |
1042 | icd->current_fmt->host_fmt); | |
1043 | if (bytesperline < 0) | |
1044 | return bytesperline; | |
1045 | ||
2c9ba37d | 1046 | if (cpu_is_mx27()) { |
2066930d BS |
1047 | ret = mx27_camera_emma_prp_reset(pcdev); |
1048 | if (ret) | |
1049 | return ret; | |
2066930d BS |
1050 | } else if (cpu_is_mx25()) { |
1051 | writel((bytesperline * icd->user_height) >> 2, | |
1052 | pcdev->base_csi + CSIRXCNT); | |
1053 | writel((bytesperline << 16) | icd->user_height, | |
1054 | pcdev->base_csi + CSIIMAG_PARA); | |
1055 | } | |
1056 | ||
1057 | writel(pcdev->csicr1, pcdev->base_csi + CSICR1); | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static int mx2_camera_set_crop(struct soc_camera_device *icd, | |
1063 | struct v4l2_crop *a) | |
1064 | { | |
1065 | struct v4l2_rect *rect = &a->c; | |
1066 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | |
1067 | struct v4l2_mbus_framefmt mf; | |
1068 | int ret; | |
1069 | ||
1070 | soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); | |
1071 | soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); | |
1072 | ||
1073 | ret = v4l2_subdev_call(sd, video, s_crop, a); | |
1074 | if (ret < 0) | |
1075 | return ret; | |
1076 | ||
1077 | /* The capture device might have changed its output */ | |
1078 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); | |
1079 | if (ret < 0) | |
1080 | return ret; | |
1081 | ||
7dfff953 | 1082 | dev_dbg(icd->parent, "Sensor cropped %dx%d\n", |
2066930d BS |
1083 | mf.width, mf.height); |
1084 | ||
1085 | icd->user_width = mf.width; | |
1086 | icd->user_height = mf.height; | |
1087 | ||
1088 | return ret; | |
1089 | } | |
1090 | ||
f410991d JM |
1091 | static int mx2_camera_get_formats(struct soc_camera_device *icd, |
1092 | unsigned int idx, | |
1093 | struct soc_camera_format_xlate *xlate) | |
1094 | { | |
1095 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); | |
1096 | const struct soc_mbus_pixelfmt *fmt; | |
1097 | struct device *dev = icd->parent; | |
1098 | enum v4l2_mbus_pixelcode code; | |
1099 | int ret, formats = 0; | |
1100 | ||
1101 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); | |
1102 | if (ret < 0) | |
1103 | /* no more formats */ | |
1104 | return 0; | |
1105 | ||
1106 | fmt = soc_mbus_get_fmtdesc(code); | |
1107 | if (!fmt) { | |
1108 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code); | |
1109 | return 0; | |
1110 | } | |
1111 | ||
70c276a6 | 1112 | if (code == V4L2_MBUS_FMT_YUYV8_2X8) { |
f410991d JM |
1113 | formats++; |
1114 | if (xlate) { | |
1115 | /* | |
1116 | * CH2 can output YUV420 which is a standard format in | |
1117 | * soc_mediabus.c | |
1118 | */ | |
1119 | xlate->host_fmt = | |
1120 | soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8); | |
1121 | xlate->code = code; | |
1122 | dev_dbg(dev, "Providing host format %s for sensor code %d\n", | |
1123 | xlate->host_fmt->name, code); | |
1124 | xlate++; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | /* Generic pass-trough */ | |
1129 | formats++; | |
1130 | if (xlate) { | |
1131 | xlate->host_fmt = fmt; | |
1132 | xlate->code = code; | |
1133 | xlate++; | |
1134 | } | |
1135 | return formats; | |
1136 | } | |
1137 | ||
750a6dff JM |
1138 | static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev, |
1139 | struct v4l2_mbus_framefmt *mf_in, | |
1140 | struct v4l2_pix_format *pix_out, bool apply) | |
1141 | { | |
1142 | int num, den; | |
1143 | unsigned long m; | |
1144 | int i, dir; | |
1145 | ||
1146 | for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) { | |
1147 | struct emma_prp_resize tmprsz; | |
1148 | unsigned char *s = tmprsz.s; | |
1149 | int len = 0; | |
1150 | int in, out; | |
1151 | ||
1152 | if (dir == RESIZE_DIR_H) { | |
1153 | in = mf_in->width; | |
1154 | out = pix_out->width; | |
1155 | } else { | |
1156 | in = mf_in->height; | |
1157 | out = pix_out->height; | |
1158 | } | |
1159 | ||
1160 | if (in < out) | |
1161 | return -EINVAL; | |
1162 | else if (in == out) | |
1163 | continue; | |
1164 | ||
1165 | /* Calculate ratio */ | |
1166 | m = gcd(in, out); | |
1167 | num = in / m; | |
1168 | den = out / m; | |
1169 | if (num > RESIZE_NUM_MAX) | |
1170 | return -EINVAL; | |
1171 | ||
1172 | if ((num >= 2 * den) && (den == 1) && | |
1173 | (num < 9) && (!(num & 0x01))) { | |
1174 | int sum = 0; | |
1175 | int j; | |
1176 | ||
1177 | /* Average scaling for >= 2:1 ratios */ | |
1178 | /* Support can be added for num >=9 and odd values */ | |
1179 | ||
1180 | tmprsz.algo = RESIZE_ALGO_AVERAGING; | |
1181 | len = num; | |
1182 | ||
1183 | for (i = 0; i < (len / 2); i++) | |
1184 | s[i] = 8; | |
1185 | ||
1186 | do { | |
1187 | for (i = 0; i < (len / 2); i++) { | |
1188 | s[i] = s[i] >> 1; | |
1189 | sum = 0; | |
1190 | for (j = 0; j < (len / 2); j++) | |
1191 | sum += s[j]; | |
1192 | if (sum == 4) | |
1193 | break; | |
1194 | } | |
1195 | } while (sum != 4); | |
1196 | ||
1197 | for (i = (len / 2); i < len; i++) | |
1198 | s[i] = s[len - i - 1]; | |
1199 | ||
1200 | s[len - 1] |= SZ_COEF; | |
1201 | } else { | |
1202 | /* bilinear scaling for < 2:1 ratios */ | |
1203 | int v; /* overflow counter */ | |
1204 | int coeff, nxt; /* table output */ | |
1205 | int in_pos_inc = 2 * den; | |
1206 | int out_pos = num; | |
1207 | int out_pos_inc = 2 * num; | |
1208 | int init_carry = num - den; | |
1209 | int carry = init_carry; | |
1210 | ||
1211 | tmprsz.algo = RESIZE_ALGO_BILINEAR; | |
1212 | v = den + in_pos_inc; | |
1213 | do { | |
1214 | coeff = v - out_pos; | |
1215 | out_pos += out_pos_inc; | |
1216 | carry += out_pos_inc; | |
1217 | for (nxt = 0; v < out_pos; nxt++) { | |
1218 | v += in_pos_inc; | |
1219 | carry -= in_pos_inc; | |
1220 | } | |
1221 | ||
1222 | if (len > RESIZE_NUM_MAX) | |
1223 | return -EINVAL; | |
1224 | ||
1225 | coeff = ((coeff << BC_COEF) + | |
1226 | (in_pos_inc >> 1)) / in_pos_inc; | |
1227 | ||
1228 | if (coeff >= (SZ_COEF - 1)) | |
1229 | coeff--; | |
1230 | ||
1231 | coeff |= SZ_COEF; | |
1232 | s[len] = (unsigned char)coeff; | |
1233 | len++; | |
1234 | ||
1235 | for (i = 1; i < nxt; i++) { | |
1236 | if (len >= RESIZE_NUM_MAX) | |
1237 | return -EINVAL; | |
1238 | s[len] = 0; | |
1239 | len++; | |
1240 | } | |
1241 | } while (carry != init_carry); | |
1242 | } | |
1243 | tmprsz.len = len; | |
1244 | if (dir == RESIZE_DIR_H) | |
1245 | mf_in->width = pix_out->width; | |
1246 | else | |
1247 | mf_in->height = pix_out->height; | |
1248 | ||
1249 | if (apply) | |
1250 | memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz)); | |
1251 | } | |
1252 | return 0; | |
1253 | } | |
1254 | ||
2066930d BS |
1255 | static int mx2_camera_set_fmt(struct soc_camera_device *icd, |
1256 | struct v4l2_format *f) | |
1257 | { | |
f410991d JM |
1258 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
1259 | struct mx2_camera_dev *pcdev = ici->priv; | |
2066930d BS |
1260 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
1261 | const struct soc_camera_format_xlate *xlate; | |
1262 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1263 | struct v4l2_mbus_framefmt mf; | |
1264 | int ret; | |
1265 | ||
750a6dff JM |
1266 | dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n", |
1267 | __func__, pix->width, pix->height); | |
1268 | ||
2066930d BS |
1269 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1270 | if (!xlate) { | |
7dfff953 | 1271 | dev_warn(icd->parent, "Format %x not found\n", |
2066930d BS |
1272 | pix->pixelformat); |
1273 | return -EINVAL; | |
1274 | } | |
1275 | ||
2066930d BS |
1276 | mf.width = pix->width; |
1277 | mf.height = pix->height; | |
1278 | mf.field = pix->field; | |
1279 | mf.colorspace = pix->colorspace; | |
1280 | mf.code = xlate->code; | |
1281 | ||
1282 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
1283 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
1284 | return ret; | |
1285 | ||
750a6dff JM |
1286 | /* Store width and height returned by the sensor for resizing */ |
1287 | pcdev->s_width = mf.width; | |
1288 | pcdev->s_height = mf.height; | |
1289 | dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n", | |
1290 | __func__, pcdev->s_width, pcdev->s_height); | |
1291 | ||
1292 | pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, | |
1293 | xlate->host_fmt->fourcc); | |
1294 | ||
1295 | memset(pcdev->resizing, 0, sizeof(pcdev->resizing)); | |
1296 | if ((mf.width != pix->width || mf.height != pix->height) && | |
1297 | pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) { | |
1298 | if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0) | |
1299 | dev_dbg(icd->parent, "%s: can't resize\n", __func__); | |
1300 | } | |
1301 | ||
2066930d BS |
1302 | if (mf.code != xlate->code) |
1303 | return -EINVAL; | |
1304 | ||
1305 | pix->width = mf.width; | |
1306 | pix->height = mf.height; | |
1307 | pix->field = mf.field; | |
1308 | pix->colorspace = mf.colorspace; | |
1309 | icd->current_fmt = xlate; | |
1310 | ||
750a6dff JM |
1311 | dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n", |
1312 | __func__, pix->width, pix->height); | |
f410991d | 1313 | |
2066930d BS |
1314 | return 0; |
1315 | } | |
1316 | ||
1317 | static int mx2_camera_try_fmt(struct soc_camera_device *icd, | |
1318 | struct v4l2_format *f) | |
1319 | { | |
2066930d BS |
1320 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
1321 | const struct soc_camera_format_xlate *xlate; | |
1322 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1323 | struct v4l2_mbus_framefmt mf; | |
1324 | __u32 pixfmt = pix->pixelformat; | |
750a6dff JM |
1325 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
1326 | struct mx2_camera_dev *pcdev = ici->priv; | |
2066930d BS |
1327 | unsigned int width_limit; |
1328 | int ret; | |
1329 | ||
750a6dff JM |
1330 | dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n", |
1331 | __func__, pix->width, pix->height); | |
1332 | ||
2066930d BS |
1333 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1334 | if (pixfmt && !xlate) { | |
7dfff953 | 1335 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
2066930d BS |
1336 | return -EINVAL; |
1337 | } | |
1338 | ||
1339 | /* FIXME: implement MX27 limits */ | |
1340 | ||
2066930d BS |
1341 | /* limit to MX25 hardware capabilities */ |
1342 | if (cpu_is_mx25()) { | |
1343 | if (xlate->host_fmt->bits_per_sample <= 8) | |
1344 | width_limit = 0xffff * 4; | |
1345 | else | |
1346 | width_limit = 0xffff * 2; | |
1347 | /* CSIIMAG_PARA limit */ | |
1348 | if (pix->width > width_limit) | |
1349 | pix->width = width_limit; | |
1350 | if (pix->height > 0xffff) | |
1351 | pix->height = 0xffff; | |
1352 | ||
1353 | pix->bytesperline = soc_mbus_bytes_per_line(pix->width, | |
1354 | xlate->host_fmt); | |
1355 | if (pix->bytesperline < 0) | |
1356 | return pix->bytesperline; | |
b0a461ff LP |
1357 | pix->sizeimage = soc_mbus_image_size(xlate->host_fmt, |
1358 | pix->bytesperline, pix->height); | |
28281a71 GL |
1359 | /* Check against the CSIRXCNT limit */ |
1360 | if (pix->sizeimage > 4 * 0x3ffff) { | |
1361 | /* Adjust geometry, preserve aspect ratio */ | |
67e86524 GL |
1362 | unsigned int new_height = int_sqrt(div_u64(0x3ffffULL * |
1363 | 4 * pix->height, pix->bytesperline)); | |
28281a71 GL |
1364 | pix->width = new_height * pix->width / pix->height; |
1365 | pix->height = new_height; | |
1366 | pix->bytesperline = soc_mbus_bytes_per_line(pix->width, | |
1367 | xlate->host_fmt); | |
1368 | BUG_ON(pix->bytesperline < 0); | |
b0a461ff LP |
1369 | pix->sizeimage = soc_mbus_image_size(xlate->host_fmt, |
1370 | pix->bytesperline, pix->height); | |
2066930d BS |
1371 | } |
1372 | } | |
1373 | ||
1374 | /* limit to sensor capabilities */ | |
1375 | mf.width = pix->width; | |
1376 | mf.height = pix->height; | |
1377 | mf.field = pix->field; | |
1378 | mf.colorspace = pix->colorspace; | |
1379 | mf.code = xlate->code; | |
1380 | ||
1381 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); | |
1382 | if (ret < 0) | |
1383 | return ret; | |
1384 | ||
750a6dff JM |
1385 | dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n", |
1386 | __func__, pcdev->s_width, pcdev->s_height); | |
1387 | ||
1388 | /* If the sensor does not support image size try PrP resizing */ | |
1389 | pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, | |
1390 | xlate->host_fmt->fourcc); | |
1391 | ||
1392 | memset(pcdev->resizing, 0, sizeof(pcdev->resizing)); | |
1393 | if ((mf.width != pix->width || mf.height != pix->height) && | |
1394 | pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) { | |
1395 | if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0) | |
1396 | dev_dbg(icd->parent, "%s: can't resize\n", __func__); | |
1397 | } | |
1398 | ||
2066930d BS |
1399 | if (mf.field == V4L2_FIELD_ANY) |
1400 | mf.field = V4L2_FIELD_NONE; | |
f410991d JM |
1401 | /* |
1402 | * Driver supports interlaced images provided they have | |
1403 | * both fields so that they can be processed as if they | |
1404 | * were progressive. | |
1405 | */ | |
1406 | if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) { | |
7dfff953 | 1407 | dev_err(icd->parent, "Field type %d unsupported.\n", |
2066930d BS |
1408 | mf.field); |
1409 | return -EINVAL; | |
1410 | } | |
1411 | ||
1412 | pix->width = mf.width; | |
1413 | pix->height = mf.height; | |
1414 | pix->field = mf.field; | |
1415 | pix->colorspace = mf.colorspace; | |
1416 | ||
750a6dff JM |
1417 | dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n", |
1418 | __func__, pix->width, pix->height); | |
1419 | ||
2066930d BS |
1420 | return 0; |
1421 | } | |
1422 | ||
1423 | static int mx2_camera_querycap(struct soc_camera_host *ici, | |
1424 | struct v4l2_capability *cap) | |
1425 | { | |
1426 | /* cap->name is set by the friendly caller:-> */ | |
1427 | strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); | |
2066930d BS |
1428 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
2066930d BS |
1433 | static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) |
1434 | { | |
6b101926 | 1435 | struct soc_camera_device *icd = file->private_data; |
2066930d | 1436 | |
c6a41e32 | 1437 | return vb2_poll(&icd->vb2_vidq, file, pt); |
2066930d BS |
1438 | } |
1439 | ||
1440 | static struct soc_camera_host_ops mx2_soc_camera_host_ops = { | |
1441 | .owner = THIS_MODULE, | |
1442 | .add = mx2_camera_add_device, | |
1443 | .remove = mx2_camera_remove_device, | |
1444 | .set_fmt = mx2_camera_set_fmt, | |
1445 | .set_crop = mx2_camera_set_crop, | |
f410991d | 1446 | .get_formats = mx2_camera_get_formats, |
2066930d | 1447 | .try_fmt = mx2_camera_try_fmt, |
c6a41e32 | 1448 | .init_videobuf2 = mx2_camera_init_videobuf, |
2066930d BS |
1449 | .poll = mx2_camera_poll, |
1450 | .querycap = mx2_camera_querycap, | |
1451 | .set_bus_param = mx2_camera_set_bus_param, | |
1452 | }; | |
1453 | ||
1454 | static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, | |
d84279e6 | 1455 | int bufnum, bool err) |
2066930d | 1456 | { |
8886a881 | 1457 | #ifdef DEBUG |
f410991d | 1458 | struct mx2_fmt_cfg *prp = pcdev->emma_prp; |
8886a881 | 1459 | #endif |
560fab62 | 1460 | struct mx2_buf_internal *ibuf; |
2066930d | 1461 | struct mx2_buffer *buf; |
c6a41e32 | 1462 | struct vb2_buffer *vb; |
2066930d BS |
1463 | unsigned long phys; |
1464 | ||
560fab62 JM |
1465 | ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal, |
1466 | queue); | |
2066930d | 1467 | |
560fab62 | 1468 | BUG_ON(ibuf->bufnum != bufnum); |
2066930d | 1469 | |
560fab62 | 1470 | if (ibuf->discard) { |
cdc9d6f1 JM |
1471 | /* |
1472 | * Discard buffer must not be returned to user space. | |
1473 | * Just return it to the discard queue. | |
1474 | */ | |
1475 | list_move_tail(pcdev->active_bufs.next, &pcdev->discard); | |
1476 | } else { | |
560fab62 JM |
1477 | buf = mx2_ibuf_to_buf(ibuf); |
1478 | ||
2066930d BS |
1479 | vb = &buf->vb; |
1480 | #ifdef DEBUG | |
c6a41e32 | 1481 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); |
f410991d JM |
1482 | if (prp->cfg.channel == 1) { |
1483 | if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + | |
1484 | 4 * bufnum) != phys) { | |
8886a881 JM |
1485 | dev_err(pcdev->dev, "%lx != %x\n", phys, |
1486 | readl(pcdev->base_emma + | |
1487 | PRP_DEST_RGB1_PTR + 4 * bufnum)); | |
f410991d JM |
1488 | } |
1489 | } else { | |
1490 | if (readl(pcdev->base_emma + PRP_DEST_Y_PTR - | |
1491 | 0x14 * bufnum) != phys) { | |
8886a881 JM |
1492 | dev_err(pcdev->dev, "%lx != %x\n", phys, |
1493 | readl(pcdev->base_emma + | |
1494 | PRP_DEST_Y_PTR - 0x14 * bufnum)); | |
f410991d | 1495 | } |
2066930d BS |
1496 | } |
1497 | #endif | |
c6a41e32 JM |
1498 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb, |
1499 | vb2_plane_vaddr(vb, 0), | |
1500 | vb2_get_plane_payload(vb, 0)); | |
2066930d | 1501 | |
560fab62 | 1502 | list_del_init(&buf->internal.queue); |
c6a41e32 | 1503 | do_gettimeofday(&vb->v4l2_buf.timestamp); |
c6a41e32 | 1504 | vb->v4l2_buf.sequence = pcdev->frame_count; |
d84279e6 JM |
1505 | if (err) |
1506 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); | |
1507 | else | |
1508 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
2066930d BS |
1509 | } |
1510 | ||
fb51cbdd JM |
1511 | pcdev->frame_count++; |
1512 | ||
2066930d | 1513 | if (list_empty(&pcdev->capture)) { |
cdc9d6f1 JM |
1514 | if (list_empty(&pcdev->discard)) { |
1515 | dev_warn(pcdev->dev, "%s: trying to access empty discard list\n", | |
1516 | __func__); | |
1517 | return; | |
f410991d | 1518 | } |
cdc9d6f1 | 1519 | |
560fab62 JM |
1520 | ibuf = list_first_entry(&pcdev->discard, |
1521 | struct mx2_buf_internal, queue); | |
1522 | ibuf->bufnum = bufnum; | |
cdc9d6f1 JM |
1523 | |
1524 | list_move_tail(pcdev->discard.next, &pcdev->active_bufs); | |
1525 | mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum); | |
2066930d BS |
1526 | return; |
1527 | } | |
1528 | ||
560fab62 JM |
1529 | buf = list_first_entry(&pcdev->capture, struct mx2_buffer, |
1530 | internal.queue); | |
2066930d | 1531 | |
560fab62 | 1532 | buf->internal.bufnum = bufnum; |
2066930d BS |
1533 | |
1534 | list_move_tail(pcdev->capture.next, &pcdev->active_bufs); | |
1535 | ||
1536 | vb = &buf->vb; | |
c6a41e32 | 1537 | buf->state = MX2_STATE_ACTIVE; |
2066930d | 1538 | |
c6a41e32 | 1539 | phys = vb2_dma_contig_plane_dma_addr(vb, 0); |
cdc9d6f1 | 1540 | mx27_update_emma_buf(pcdev, phys, bufnum); |
2066930d BS |
1541 | } |
1542 | ||
1543 | static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) | |
1544 | { | |
1545 | struct mx2_camera_dev *pcdev = data; | |
1546 | unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); | |
560fab62 | 1547 | struct mx2_buf_internal *ibuf; |
cdc9d6f1 | 1548 | |
8636ead8 | 1549 | spin_lock(&pcdev->lock); |
cdc9d6f1 JM |
1550 | |
1551 | if (list_empty(&pcdev->active_bufs)) { | |
1552 | dev_warn(pcdev->dev, "%s: called while active list is empty\n", | |
1553 | __func__); | |
665ad8af JM |
1554 | |
1555 | if (!status) { | |
1556 | spin_unlock(&pcdev->lock); | |
1557 | return IRQ_NONE; | |
1558 | } | |
cdc9d6f1 | 1559 | } |
2066930d BS |
1560 | |
1561 | if (status & (1 << 7)) { /* overflow */ | |
d84279e6 | 1562 | u32 cntl = readl(pcdev->base_emma + PRP_CNTL); |
f410991d JM |
1563 | writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN), |
1564 | pcdev->base_emma + PRP_CNTL); | |
2066930d | 1565 | writel(cntl, pcdev->base_emma + PRP_CNTL); |
d84279e6 | 1566 | |
560fab62 JM |
1567 | ibuf = list_first_entry(&pcdev->active_bufs, |
1568 | struct mx2_buf_internal, queue); | |
d84279e6 | 1569 | mx27_camera_frame_done_emma(pcdev, |
560fab62 | 1570 | ibuf->bufnum, true); |
d84279e6 JM |
1571 | |
1572 | status &= ~(1 << 7); | |
1573 | } else if (((status & (3 << 5)) == (3 << 5)) || | |
cdc9d6f1 | 1574 | ((status & (3 << 3)) == (3 << 3))) { |
2066930d BS |
1575 | /* |
1576 | * Both buffers have triggered, process the one we're expecting | |
1577 | * to first | |
1578 | */ | |
560fab62 JM |
1579 | ibuf = list_first_entry(&pcdev->active_bufs, |
1580 | struct mx2_buf_internal, queue); | |
1581 | mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false); | |
1582 | status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */ | |
d84279e6 JM |
1583 | } else if ((status & (1 << 6)) || (status & (1 << 4))) { |
1584 | mx27_camera_frame_done_emma(pcdev, 0, false); | |
1585 | } else if ((status & (1 << 5)) || (status & (1 << 3))) { | |
1586 | mx27_camera_frame_done_emma(pcdev, 1, false); | |
2066930d | 1587 | } |
2066930d | 1588 | |
8636ead8 | 1589 | spin_unlock(&pcdev->lock); |
2066930d BS |
1590 | writel(status, pcdev->base_emma + PRP_INTRSTATUS); |
1591 | ||
1592 | return IRQ_HANDLED; | |
1593 | } | |
1594 | ||
1595 | static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) | |
1596 | { | |
1597 | struct resource *res_emma = pcdev->res_emma; | |
1598 | int err = 0; | |
1599 | ||
1600 | if (!request_mem_region(res_emma->start, resource_size(res_emma), | |
1601 | MX2_CAM_DRV_NAME)) { | |
1602 | err = -EBUSY; | |
1603 | goto out; | |
1604 | } | |
1605 | ||
1606 | pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); | |
1607 | if (!pcdev->base_emma) { | |
1608 | err = -ENOMEM; | |
1609 | goto exit_release; | |
1610 | } | |
1611 | ||
1612 | err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, | |
1613 | MX2_CAM_DRV_NAME, pcdev); | |
1614 | if (err) { | |
1615 | dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); | |
1616 | goto exit_iounmap; | |
1617 | } | |
1618 | ||
1619 | pcdev->clk_emma = clk_get(NULL, "emma"); | |
1620 | if (IS_ERR(pcdev->clk_emma)) { | |
1621 | err = PTR_ERR(pcdev->clk_emma); | |
1622 | goto exit_free_irq; | |
1623 | } | |
1624 | ||
1625 | clk_enable(pcdev->clk_emma); | |
1626 | ||
1627 | err = mx27_camera_emma_prp_reset(pcdev); | |
1628 | if (err) | |
1629 | goto exit_clk_emma_put; | |
1630 | ||
1631 | return err; | |
1632 | ||
1633 | exit_clk_emma_put: | |
1634 | clk_disable(pcdev->clk_emma); | |
1635 | clk_put(pcdev->clk_emma); | |
1636 | exit_free_irq: | |
1637 | free_irq(pcdev->irq_emma, pcdev); | |
1638 | exit_iounmap: | |
1639 | iounmap(pcdev->base_emma); | |
1640 | exit_release: | |
1641 | release_mem_region(res_emma->start, resource_size(res_emma)); | |
1642 | out: | |
1643 | return err; | |
1644 | } | |
1645 | ||
1646 | static int __devinit mx2_camera_probe(struct platform_device *pdev) | |
1647 | { | |
1648 | struct mx2_camera_dev *pcdev; | |
1649 | struct resource *res_csi, *res_emma; | |
1650 | void __iomem *base_csi; | |
1651 | int irq_csi, irq_emma; | |
2066930d BS |
1652 | int err = 0; |
1653 | ||
1654 | dev_dbg(&pdev->dev, "initialising\n"); | |
1655 | ||
1656 | res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1657 | irq_csi = platform_get_irq(pdev, 0); | |
1658 | if (res_csi == NULL || irq_csi < 0) { | |
1659 | dev_err(&pdev->dev, "Missing platform resources data\n"); | |
1660 | err = -ENODEV; | |
1661 | goto exit; | |
1662 | } | |
1663 | ||
1664 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
1665 | if (!pcdev) { | |
1666 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); | |
1667 | err = -ENOMEM; | |
1668 | goto exit; | |
1669 | } | |
1670 | ||
1671 | pcdev->clk_csi = clk_get(&pdev->dev, NULL); | |
1672 | if (IS_ERR(pcdev->clk_csi)) { | |
d867be1c | 1673 | dev_err(&pdev->dev, "Could not get csi clock\n"); |
2066930d BS |
1674 | err = PTR_ERR(pcdev->clk_csi); |
1675 | goto exit_kfree; | |
1676 | } | |
1677 | ||
2066930d BS |
1678 | pcdev->res_csi = res_csi; |
1679 | pcdev->pdata = pdev->dev.platform_data; | |
1680 | if (pcdev->pdata) { | |
1681 | long rate; | |
1682 | ||
1683 | pcdev->platform_flags = pcdev->pdata->flags; | |
1684 | ||
1685 | rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); | |
1686 | if (rate <= 0) { | |
1687 | err = -ENODEV; | |
1688 | goto exit_dma_free; | |
1689 | } | |
1690 | err = clk_set_rate(pcdev->clk_csi, rate); | |
1691 | if (err < 0) | |
1692 | goto exit_dma_free; | |
1693 | } | |
1694 | ||
1695 | INIT_LIST_HEAD(&pcdev->capture); | |
1696 | INIT_LIST_HEAD(&pcdev->active_bufs); | |
cdc9d6f1 | 1697 | INIT_LIST_HEAD(&pcdev->discard); |
2066930d BS |
1698 | spin_lock_init(&pcdev->lock); |
1699 | ||
1700 | /* | |
1701 | * Request the regions. | |
1702 | */ | |
1703 | if (!request_mem_region(res_csi->start, resource_size(res_csi), | |
1704 | MX2_CAM_DRV_NAME)) { | |
1705 | err = -EBUSY; | |
1706 | goto exit_dma_free; | |
1707 | } | |
1708 | ||
1709 | base_csi = ioremap(res_csi->start, resource_size(res_csi)); | |
1710 | if (!base_csi) { | |
1711 | err = -ENOMEM; | |
1712 | goto exit_release; | |
1713 | } | |
1714 | pcdev->irq_csi = irq_csi; | |
1715 | pcdev->base_csi = base_csi; | |
1716 | pcdev->base_dma = res_csi->start; | |
1717 | pcdev->dev = &pdev->dev; | |
1718 | ||
2c9ba37d SH |
1719 | if (cpu_is_mx25()) { |
1720 | err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0, | |
1721 | MX2_CAM_DRV_NAME, pcdev); | |
1722 | if (err) { | |
1723 | dev_err(pcdev->dev, "Camera interrupt register failed \n"); | |
1724 | goto exit_iounmap; | |
1725 | } | |
2066930d BS |
1726 | } |
1727 | ||
1728 | if (cpu_is_mx27()) { | |
1729 | /* EMMA support */ | |
1730 | res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1731 | irq_emma = platform_get_irq(pdev, 1); | |
1732 | ||
2c9ba37d SH |
1733 | if (!res_emma || !irq_emma) { |
1734 | dev_err(&pdev->dev, "no EMMA resources\n"); | |
1735 | goto exit_free_irq; | |
2066930d | 1736 | } |
2c9ba37d SH |
1737 | |
1738 | pcdev->res_emma = res_emma; | |
1739 | pcdev->irq_emma = irq_emma; | |
1740 | if (mx27_camera_emma_init(pcdev)) | |
1741 | goto exit_free_irq; | |
2066930d BS |
1742 | } |
1743 | ||
1744 | pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, | |
1745 | pcdev->soc_host.ops = &mx2_soc_camera_host_ops, | |
1746 | pcdev->soc_host.priv = pcdev; | |
1747 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; | |
1748 | pcdev->soc_host.nr = pdev->id; | |
914f05c8 LP |
1749 | if (cpu_is_mx25()) |
1750 | pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE; | |
c6a41e32 JM |
1751 | |
1752 | pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); | |
1753 | if (IS_ERR(pcdev->alloc_ctx)) { | |
1754 | err = PTR_ERR(pcdev->alloc_ctx); | |
1755 | goto eallocctx; | |
1756 | } | |
2066930d BS |
1757 | err = soc_camera_host_register(&pcdev->soc_host); |
1758 | if (err) | |
1759 | goto exit_free_emma; | |
1760 | ||
45f4d4e8 MG |
1761 | dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n", |
1762 | clk_get_rate(pcdev->clk_csi)); | |
1763 | ||
2066930d BS |
1764 | return 0; |
1765 | ||
1766 | exit_free_emma: | |
c6a41e32 JM |
1767 | vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); |
1768 | eallocctx: | |
2c9ba37d | 1769 | if (cpu_is_mx27()) { |
2066930d BS |
1770 | free_irq(pcdev->irq_emma, pcdev); |
1771 | clk_disable(pcdev->clk_emma); | |
1772 | clk_put(pcdev->clk_emma); | |
1773 | iounmap(pcdev->base_emma); | |
2c9ba37d | 1774 | release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma)); |
2066930d BS |
1775 | } |
1776 | exit_free_irq: | |
2c9ba37d SH |
1777 | if (cpu_is_mx25()) |
1778 | free_irq(pcdev->irq_csi, pcdev); | |
2066930d BS |
1779 | exit_iounmap: |
1780 | iounmap(base_csi); | |
1781 | exit_release: | |
1782 | release_mem_region(res_csi->start, resource_size(res_csi)); | |
1783 | exit_dma_free: | |
2066930d | 1784 | clk_put(pcdev->clk_csi); |
2066930d BS |
1785 | exit_kfree: |
1786 | kfree(pcdev); | |
1787 | exit: | |
1788 | return err; | |
1789 | } | |
1790 | ||
1791 | static int __devexit mx2_camera_remove(struct platform_device *pdev) | |
1792 | { | |
1793 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); | |
1794 | struct mx2_camera_dev *pcdev = container_of(soc_host, | |
1795 | struct mx2_camera_dev, soc_host); | |
1796 | struct resource *res; | |
1797 | ||
1798 | clk_put(pcdev->clk_csi); | |
2c9ba37d SH |
1799 | if (cpu_is_mx25()) |
1800 | free_irq(pcdev->irq_csi, pcdev); | |
2066930d | 1801 | if (cpu_is_mx27()) |
2066930d BS |
1802 | free_irq(pcdev->irq_emma, pcdev); |
1803 | ||
1804 | soc_camera_host_unregister(&pcdev->soc_host); | |
1805 | ||
c6a41e32 JM |
1806 | vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); |
1807 | ||
2066930d BS |
1808 | iounmap(pcdev->base_csi); |
1809 | ||
2c9ba37d | 1810 | if (cpu_is_mx27()) { |
2066930d BS |
1811 | clk_disable(pcdev->clk_emma); |
1812 | clk_put(pcdev->clk_emma); | |
1813 | iounmap(pcdev->base_emma); | |
1814 | res = pcdev->res_emma; | |
1815 | release_mem_region(res->start, resource_size(res)); | |
1816 | } | |
1817 | ||
1818 | res = pcdev->res_csi; | |
1819 | release_mem_region(res->start, resource_size(res)); | |
1820 | ||
1821 | kfree(pcdev); | |
1822 | ||
1823 | dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); | |
1824 | ||
1825 | return 0; | |
1826 | } | |
1827 | ||
1828 | static struct platform_driver mx2_camera_driver = { | |
1829 | .driver = { | |
1830 | .name = MX2_CAM_DRV_NAME, | |
1831 | }, | |
1832 | .remove = __devexit_p(mx2_camera_remove), | |
1833 | }; | |
1834 | ||
1835 | ||
1836 | static int __init mx2_camera_init(void) | |
1837 | { | |
1838 | return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); | |
1839 | } | |
1840 | ||
1841 | static void __exit mx2_camera_exit(void) | |
1842 | { | |
1843 | return platform_driver_unregister(&mx2_camera_driver); | |
1844 | } | |
1845 | ||
1846 | module_init(mx2_camera_init); | |
1847 | module_exit(mx2_camera_exit); | |
1848 | ||
1849 | MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); | |
1850 | MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); | |
1851 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1852 | MODULE_VERSION(MX2_CAM_VERSION); |