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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[deliverable/linux.git] / drivers / media / video / mx2_camera.c
CommitLineData
2066930d
BS		 1/*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/slab.h>
18#include <linux/dma-mapping.h>
19#include <linux/errno.h>
20#include <linux/fs.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/mm.h>
24#include <linux/moduleparam.h>
25#include <linux/time.h>
2066930d
BS		 26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/mutex.h>
29#include <linux/clk.h>
30
31#include <media/v4l2-common.h>
32#include <media/v4l2-dev.h>
6b101926 33#include <media/videobuf-core.h>
2066930d
BS		 34#include <media/videobuf-dma-contig.h>
35#include <media/soc_camera.h>
36#include <media/soc_mediabus.h>
37
38#include <linux/videodev2.h>
39
40#include <mach/mx2_cam.h>
41#ifdef CONFIG_MACH_MX27
42#include <mach/dma-mx1-mx2.h>
43#endif
44#include <mach/hardware.h>
45
46#include <asm/dma.h>
47
48#define MX2_CAM_DRV_NAME "mx2-camera"
64dc3c1a 49#define MX2_CAM_VERSION "0.0.6"
2066930d
BS		 50#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51
52/* reset values */
53#define CSICR1_RESET_VAL 0x40000800
54#define CSICR2_RESET_VAL 0x0
55#define CSICR3_RESET_VAL 0x0
56
57/* csi control reg 1 */
58#define CSICR1_SWAP16_EN (1 << 31)
59#define CSICR1_EXT_VSYNC (1 << 30)
60#define CSICR1_EOF_INTEN (1 << 29)
61#define CSICR1_PRP_IF_EN (1 << 28)
62#define CSICR1_CCIR_MODE (1 << 27)
63#define CSICR1_COF_INTEN (1 << 26)
64#define CSICR1_SF_OR_INTEN (1 << 25)
65#define CSICR1_RF_OR_INTEN (1 << 24)
66#define CSICR1_STATFF_LEVEL (3 << 22)
67#define CSICR1_STATFF_INTEN (1 << 21)
68#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
69#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
70#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
71#define CSICR1_RXFF_INTEN (1 << 18)
72#define CSICR1_SOF_POL (1 << 17)
73#define CSICR1_SOF_INTEN (1 << 16)
74#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
75#define CSICR1_HSYNC_POL (1 << 11)
76#define CSICR1_CCIR_EN (1 << 10)
77#define CSICR1_MCLKEN (1 << 9)
78#define CSICR1_FCC (1 << 8)
79#define CSICR1_PACK_DIR (1 << 7)
80#define CSICR1_CLR_STATFIFO (1 << 6)
81#define CSICR1_CLR_RXFIFO (1 << 5)
82#define CSICR1_GCLK_MODE (1 << 4)
83#define CSICR1_INV_DATA (1 << 3)
84#define CSICR1_INV_PCLK (1 << 2)
85#define CSICR1_REDGE (1 << 1)
86
87#define SHIFT_STATFF_LEVEL 22
88#define SHIFT_RXFF_LEVEL 19
89#define SHIFT_MCLKDIV 12
90
91/* control reg 3 */
92#define CSICR3_FRMCNT (0xFFFF << 16)
93#define CSICR3_FRMCNT_RST (1 << 15)
94#define CSICR3_DMA_REFLASH_RFF (1 << 14)
95#define CSICR3_DMA_REFLASH_SFF (1 << 13)
96#define CSICR3_DMA_REQ_EN_RFF (1 << 12)
97#define CSICR3_DMA_REQ_EN_SFF (1 << 11)
98#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
99#define CSICR3_CSI_SUP (1 << 3)
100#define CSICR3_ZERO_PACK_EN (1 << 2)
101#define CSICR3_ECC_INT_EN (1 << 1)
102#define CSICR3_ECC_AUTO_EN (1 << 0)
103
104#define SHIFT_FRMCNT 16
105
106/* csi status reg */
107#define CSISR_SFF_OR_INT (1 << 25)
108#define CSISR_RFF_OR_INT (1 << 24)
109#define CSISR_STATFF_INT (1 << 21)
110#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
111#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
112#define CSISR_RXFF_INT (1 << 18)
113#define CSISR_EOF_INT (1 << 17)
114#define CSISR_SOF_INT (1 << 16)
115#define CSISR_F2_INT (1 << 15)
116#define CSISR_F1_INT (1 << 14)
117#define CSISR_COF_INT (1 << 13)
118#define CSISR_ECC_INT (1 << 1)
119#define CSISR_DRDY (1 << 0)
120
121#define CSICR1 0x00
122#define CSICR2 0x04
123#define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
124#define CSISTATFIFO 0x0c
125#define CSIRFIFO 0x10
126#define CSIRXCNT 0x14
127#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
128#define CSIDMASA_STATFIFO 0x20
129#define CSIDMATA_STATFIFO 0x24
130#define CSIDMASA_FB1 0x28
131#define CSIDMASA_FB2 0x2c
132#define CSIFBUF_PARA 0x30
133#define CSIIMAG_PARA 0x34
134
135/* EMMA PrP */
136#define PRP_CNTL 0x00
137#define PRP_INTR_CNTL 0x04
138#define PRP_INTRSTATUS 0x08
139#define PRP_SOURCE_Y_PTR 0x0c
140#define PRP_SOURCE_CB_PTR 0x10
141#define PRP_SOURCE_CR_PTR 0x14
142#define PRP_DEST_RGB1_PTR 0x18
143#define PRP_DEST_RGB2_PTR 0x1c
144#define PRP_DEST_Y_PTR 0x20
145#define PRP_DEST_CB_PTR 0x24
146#define PRP_DEST_CR_PTR 0x28
147#define PRP_SRC_FRAME_SIZE 0x2c
148#define PRP_DEST_CH1_LINE_STRIDE 0x30
149#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
150#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
151#define PRP_CH1_OUT_IMAGE_SIZE 0x3c
152#define PRP_CH2_OUT_IMAGE_SIZE 0x40
153#define PRP_SRC_LINE_STRIDE 0x44
154#define PRP_CSC_COEF_012 0x48
155#define PRP_CSC_COEF_345 0x4c
156#define PRP_CSC_COEF_678 0x50
157#define PRP_CH1_RZ_HORI_COEF1 0x54
158#define PRP_CH1_RZ_HORI_COEF2 0x58
159#define PRP_CH1_RZ_HORI_VALID 0x5c
160#define PRP_CH1_RZ_VERT_COEF1 0x60
161#define PRP_CH1_RZ_VERT_COEF2 0x64
162#define PRP_CH1_RZ_VERT_VALID 0x68
163#define PRP_CH2_RZ_HORI_COEF1 0x6c
164#define PRP_CH2_RZ_HORI_COEF2 0x70
165#define PRP_CH2_RZ_HORI_VALID 0x74
166#define PRP_CH2_RZ_VERT_COEF1 0x78
167#define PRP_CH2_RZ_VERT_COEF2 0x7c
168#define PRP_CH2_RZ_VERT_VALID 0x80
169
170#define PRP_CNTL_CH1EN (1 << 0)
171#define PRP_CNTL_CH2EN (1 << 1)
172#define PRP_CNTL_CSIEN (1 << 2)
173#define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
174#define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
175#define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
176#define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
177#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
178#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
179#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
180#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
181#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
182#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
183#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
184#define PRP_CNTL_CH1_LEN (1 << 9)
185#define PRP_CNTL_CH2_LEN (1 << 10)
186#define PRP_CNTL_SKIP_FRAME (1 << 11)
187#define PRP_CNTL_SWRST (1 << 12)
188#define PRP_CNTL_CLKEN (1 << 13)
189#define PRP_CNTL_WEN (1 << 14)
190#define PRP_CNTL_CH1BYP (1 << 15)
191#define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
192#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
193#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
194#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
195#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
196#define PRP_CNTL_CH2B1EN (1 << 29)
197#define PRP_CNTL_CH2B2EN (1 << 30)
198#define PRP_CNTL_CH2FEN (1 << 31)
199
200/* IRQ Enable and status register */
201#define PRP_INTR_RDERR (1 << 0)
202#define PRP_INTR_CH1WERR (1 << 1)
203#define PRP_INTR_CH2WERR (1 << 2)
204#define PRP_INTR_CH1FC (1 << 3)
205#define PRP_INTR_CH2FC (1 << 5)
206#define PRP_INTR_LBOVF (1 << 7)
207#define PRP_INTR_CH2OVF (1 << 8)
208
209#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma)
210
211#define MAX_VIDEO_MEM 16
212
f410991d
JM		 213struct mx2_prp_cfg {
214 int channel;
215 u32 in_fmt;
216 u32 out_fmt;
217 u32 src_pixel;
218 u32 ch1_pixel;
219 u32 irq_flags;
220};
221
222/* prp configuration for a client-host fmt pair */
223struct mx2_fmt_cfg {
224 enum v4l2_mbus_pixelcode in_fmt;
225 u32 out_fmt;
226 struct mx2_prp_cfg cfg;
227};
228
2066930d
BS		 229struct mx2_camera_dev {
230 struct device *dev;
231 struct soc_camera_host soc_host;
232 struct soc_camera_device *icd;
233 struct clk *clk_csi, *clk_emma;
234
235 unsigned int irq_csi, irq_emma;
236 void __iomem *base_csi, *base_emma;
237 unsigned long base_dma;
238
239 struct mx2_camera_platform_data *pdata;
240 struct resource *res_csi, *res_emma;
241 unsigned long platform_flags;
242
243 struct list_head capture;
244 struct list_head active_bufs;
245
246 spinlock_t lock;
247
248 int dma;
249 struct mx2_buffer *active;
250 struct mx2_buffer *fb1_active;
251 struct mx2_buffer *fb2_active;
252
253 int use_emma;
254
255 u32 csicr1;
256
79d3c2c2 257 void *discard_buffer;
2066930d
BS		 258 dma_addr_t discard_buffer_dma;
259 size_t discard_size;
f410991d 260 struct mx2_fmt_cfg *emma_prp;
ccd1a499 261 u32 frame_count;
2066930d
BS		 262};
263
264/* buffer for one video frame */
265struct mx2_buffer {
266 /* common v4l buffer stuff -- must be first */
267 struct videobuf_buffer vb;
268
269 enum v4l2_mbus_pixelcode code;
270
271 int bufnum;
272};
273
f410991d
JM		 274static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
275 /*
276 * This is a generic configuration which is valid for most
277 * prp input-output format combinations.
278 * We set the incomming and outgoing pixelformat to a
279 * 16 Bit wide format and adjust the bytesperline
280 * accordingly. With this configuration the inputdata
281 * will not be changed by the emma and could be any type
282 * of 16 Bit Pixelformat.
283 */
284 {
285 .in_fmt = 0,
286 .out_fmt = 0,
287 .cfg = {
288 .channel = 1,
289 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
290 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
291 .src_pixel = 0x2ca00565, /* RGB565 */
292 .ch1_pixel = 0x2ca00565, /* RGB565 */
293 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
294 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
295 }
296 },
297 {
298 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
299 .out_fmt = V4L2_PIX_FMT_YUV420,
300 .cfg = {
301 .channel = 2,
302 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
303 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
304 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
305 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
306 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
307 PRP_INTR_CH2OVF,
308 }
309 },
310};
311
312static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
313 enum v4l2_mbus_pixelcode in_fmt,
314 u32 out_fmt)
315{
316 int i;
317
318 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
319 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
320 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
321 return &mx27_emma_prp_table[i];
322 }
323 /* If no match return the most generic configuration */
324 return &mx27_emma_prp_table[0];
325};
326
2066930d
BS		 327static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
328{
329 unsigned long flags;
330
331 clk_disable(pcdev->clk_csi);
332 writel(0, pcdev->base_csi + CSICR1);
333 if (mx27_camera_emma(pcdev)) {
334 writel(0, pcdev->base_emma + PRP_CNTL);
335 } else if (cpu_is_mx25()) {
336 spin_lock_irqsave(&pcdev->lock, flags);
337 pcdev->fb1_active = NULL;
338 pcdev->fb2_active = NULL;
339 writel(0, pcdev->base_csi + CSIDMASA_FB1);
340 writel(0, pcdev->base_csi + CSIDMASA_FB2);
341 spin_unlock_irqrestore(&pcdev->lock, flags);
342 }
343}
344
345/*
346 * The following two functions absolutely depend on the fact, that
347 * there can be only one camera on mx2 camera sensor interface
348 */
349static int mx2_camera_add_device(struct soc_camera_device *icd)
350{
7dfff953 351 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 352 struct mx2_camera_dev *pcdev = ici->priv;
353 int ret;
354 u32 csicr1;
355
356 if (pcdev->icd)
357 return -EBUSY;
358
359 ret = clk_enable(pcdev->clk_csi);
360 if (ret < 0)
361 return ret;
362
363 csicr1 = CSICR1_MCLKEN;
364
365 if (mx27_camera_emma(pcdev)) {
366 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
367 CSICR1_RXFF_LEVEL(0);
368 } else if (cpu_is_mx27())
369 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
370
371 pcdev->csicr1 = csicr1;
372 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
373
374 pcdev->icd = icd;
ccd1a499 375 pcdev->frame_count = 0;
2066930d 376
7dfff953 377 dev_info(icd->parent, "Camera driver attached to camera %d\n",
2066930d
BS		 378 icd->devnum);
379
380 return 0;
381}
382
383static void mx2_camera_remove_device(struct soc_camera_device *icd)
384{
7dfff953 385 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 386 struct mx2_camera_dev *pcdev = ici->priv;
387
388 BUG_ON(icd != pcdev->icd);
389
7dfff953 390 dev_info(icd->parent, "Camera driver detached from camera %d\n",
2066930d
BS		 391 icd->devnum);
392
393 mx2_camera_deactivate(pcdev);
394
395 if (pcdev->discard_buffer) {
396 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
397 pcdev->discard_buffer,
398 pcdev->discard_buffer_dma);
399 pcdev->discard_buffer = NULL;
400 }
401
402 pcdev->icd = NULL;
403}
404
405#ifdef CONFIG_MACH_MX27
406static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
407{
408 u32 tmp;
409
410 imx_dma_enable(pcdev->dma);
411
412 tmp = readl(pcdev->base_csi + CSICR1);
413 tmp |= CSICR1_RF_OR_INTEN;
414 writel(tmp, pcdev->base_csi + CSICR1);
415}
416
417static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
418{
419 struct mx2_camera_dev *pcdev = data;
420 u32 status = readl(pcdev->base_csi + CSISR);
421
422 if (status & CSISR_SOF_INT && pcdev->active) {
423 u32 tmp;
424
425 tmp = readl(pcdev->base_csi + CSICR1);
426 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
427 mx27_camera_dma_enable(pcdev);
428 }
429
430 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
431
432 return IRQ_HANDLED;
433}
434#else
435static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
436{
437 return IRQ_NONE;
438}
439#endif /* CONFIG_MACH_MX27 */
440
441static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
442 int state)
443{
444 struct videobuf_buffer *vb;
445 struct mx2_buffer *buf;
446 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
447 &pcdev->fb2_active;
448 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
449 unsigned long flags;
450
451 spin_lock_irqsave(&pcdev->lock, flags);
452
5384a12b
BS		 453 if (*fb_active == NULL)
454 goto out;
455
2066930d
BS		 456 vb = &(*fb_active)->vb;
457 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
458 vb, vb->baddr, vb->bsize);
459
460 vb->state = state;
461 do_gettimeofday(&vb->ts);
462 vb->field_count++;
463
464 wake_up(&vb->done);
465
466 if (list_empty(&pcdev->capture)) {
467 buf = NULL;
468 writel(0, pcdev->base_csi + fb_reg);
469 } else {
470 buf = list_entry(pcdev->capture.next, struct mx2_buffer,
471 vb.queue);
472 vb = &buf->vb;
473 list_del(&vb->queue);
474 vb->state = VIDEOBUF_ACTIVE;
475 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
476 }
477
478 *fb_active = buf;
479
5384a12b 480out:
2066930d
BS		 481 spin_unlock_irqrestore(&pcdev->lock, flags);
482}
483
484static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
485{
486 struct mx2_camera_dev *pcdev = data;
487 u32 status = readl(pcdev->base_csi + CSISR);
488
489 if (status & CSISR_DMA_TSF_FB1_INT)
490 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
491 else if (status & CSISR_DMA_TSF_FB2_INT)
492 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
493
494 /* FIXME: handle CSISR_RFF_OR_INT */
495
496 writel(status, pcdev->base_csi + CSISR);
497
498 return IRQ_HANDLED;
499}
500
501/*
502 * Videobuf operations
503 */
504static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
505 unsigned int *size)
506{
507 struct soc_camera_device *icd = vq->priv_data;
508 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
509 icd->current_fmt->host_fmt);
510
7dfff953 511 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size);
2066930d
BS		 512
513 if (bytes_per_line < 0)
514 return bytes_per_line;
515
516 *size = bytes_per_line * icd->user_height;
517
518 if (0 == *count)
519 *count = 32;
520 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
521 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
522
523 return 0;
524}
525
526static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
527{
528 struct soc_camera_device *icd = vq->priv_data;
529 struct videobuf_buffer *vb = &buf->vb;
530
7dfff953 531 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 532 vb, vb->baddr, vb->bsize);
533
534 /*
535 * This waits until this buffer is out of danger, i.e., until it is no
88bfd0bd 536 * longer in state VIDEOBUF_QUEUED or VIDEOBUF_ACTIVE
2066930d 537 */
0e0809a5 538 videobuf_waiton(vq, vb, 0, 0);
2066930d
BS		 539
540 videobuf_dma_contig_free(vq, vb);
7dfff953 541 dev_dbg(icd->parent, "%s freed\n", __func__);
2066930d
BS		 542
543 vb->state = VIDEOBUF_NEEDS_INIT;
544}
545
546static int mx2_videobuf_prepare(struct videobuf_queue *vq,
547 struct videobuf_buffer *vb, enum v4l2_field field)
548{
549 struct soc_camera_device *icd = vq->priv_data;
550 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
551 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
552 icd->current_fmt->host_fmt);
553 int ret = 0;
554
7dfff953 555 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 556 vb, vb->baddr, vb->bsize);
557
558 if (bytes_per_line < 0)
559 return bytes_per_line;
560
561#ifdef DEBUG
562 /*
563 * This can be useful if you want to see if we actually fill
564 * the buffer with something
565 */
566 memset((void *)vb->baddr, 0xaa, vb->bsize);
567#endif
568
569 if (buf->code != icd->current_fmt->code ||
570 vb->width != icd->user_width ||
571 vb->height != icd->user_height ||
572 vb->field != field) {
573 buf->code = icd->current_fmt->code;
574 vb->width = icd->user_width;
575 vb->height = icd->user_height;
576 vb->field = field;
577 vb->state = VIDEOBUF_NEEDS_INIT;
578 }
579
580 vb->size = bytes_per_line * vb->height;
581 if (vb->baddr && vb->bsize < vb->size) {
582 ret = -EINVAL;
583 goto out;
584 }
585
586 if (vb->state == VIDEOBUF_NEEDS_INIT) {
587 ret = videobuf_iolock(vq, vb, NULL);
588 if (ret)
589 goto fail;
590
591 vb->state = VIDEOBUF_PREPARED;
592 }
593
594 return 0;
595
596fail:
597 free_buffer(vq, buf);
598out:
599 return ret;
600}
601
602static void mx2_videobuf_queue(struct videobuf_queue *vq,
603 struct videobuf_buffer *vb)
604{
605 struct soc_camera_device *icd = vq->priv_data;
606 struct soc_camera_host *ici =
7dfff953 607 to_soc_camera_host(icd->parent);
2066930d
BS		 608 struct mx2_camera_dev *pcdev = ici->priv;
609 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
610 unsigned long flags;
611
7dfff953 612 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 613 vb, vb->baddr, vb->bsize);
614
615 spin_lock_irqsave(&pcdev->lock, flags);
616
617 vb->state = VIDEOBUF_QUEUED;
618 list_add_tail(&vb->queue, &pcdev->capture);
619
620 if (mx27_camera_emma(pcdev)) {
621 goto out;
622#ifdef CONFIG_MACH_MX27
623 } else if (cpu_is_mx27()) {
624 int ret;
625
626 if (pcdev->active == NULL) {
627 ret = imx_dma_setup_single(pcdev->dma,
628 videobuf_to_dma_contig(vb), vb->size,
629 (u32)pcdev->base_dma + 0x10,
630 DMA_MODE_READ);
631 if (ret) {
632 vb->state = VIDEOBUF_ERROR;
633 wake_up(&vb->done);
634 goto out;
635 }
636
637 vb->state = VIDEOBUF_ACTIVE;
638 pcdev->active = buf;
639 }
640#endif
641 } else { /* cpu_is_mx25() */
642 u32 csicr3, dma_inten = 0;
643
644 if (pcdev->fb1_active == NULL) {
645 writel(videobuf_to_dma_contig(vb),
646 pcdev->base_csi + CSIDMASA_FB1);
647 pcdev->fb1_active = buf;
648 dma_inten = CSICR1_FB1_DMA_INTEN;
649 } else if (pcdev->fb2_active == NULL) {
650 writel(videobuf_to_dma_contig(vb),
651 pcdev->base_csi + CSIDMASA_FB2);
652 pcdev->fb2_active = buf;
653 dma_inten = CSICR1_FB2_DMA_INTEN;
654 }
655
656 if (dma_inten) {
657 list_del(&vb->queue);
658 vb->state = VIDEOBUF_ACTIVE;
659
660 csicr3 = readl(pcdev->base_csi + CSICR3);
661
662 /* Reflash DMA */
663 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
664 pcdev->base_csi + CSICR3);
665
666 /* clear & enable interrupts */
667 writel(dma_inten, pcdev->base_csi + CSISR);
668 pcdev->csicr1 |= dma_inten;
669 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
670
671 /* enable DMA */
672 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
673 writel(csicr3, pcdev->base_csi + CSICR3);
674 }
675 }
676
677out:
678 spin_unlock_irqrestore(&pcdev->lock, flags);
679}
680
681static void mx2_videobuf_release(struct videobuf_queue *vq,
682 struct videobuf_buffer *vb)
683{
684 struct soc_camera_device *icd = vq->priv_data;
7dfff953 685 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 686 struct mx2_camera_dev *pcdev = ici->priv;
687 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
688 unsigned long flags;
689
690#ifdef DEBUG
7dfff953 691 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 692 vb, vb->baddr, vb->bsize);
693
694 switch (vb->state) {
695 case VIDEOBUF_ACTIVE:
7dfff953 696 dev_info(icd->parent, "%s (active)\n", __func__);
2066930d
BS		 697 break;
698 case VIDEOBUF_QUEUED:
7dfff953 699 dev_info(icd->parent, "%s (queued)\n", __func__);
2066930d
BS		 700 break;
701 case VIDEOBUF_PREPARED:
7dfff953 702 dev_info(icd->parent, "%s (prepared)\n", __func__);
2066930d
BS		 703 break;
704 default:
7dfff953 705 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
2066930d
BS		 706 vb->state);
707 break;
708 }
709#endif
710
711 /*
712 * Terminate only queued but inactive buffers. Active buffers are
713 * released when they become inactive after videobuf_waiton().
714 *
7c6b7319
BS		 715 * FIXME: implement forced termination of active buffers for mx27 and
716 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
717 * state. This requires a specific handling for each of the these DMA
718 * types.
2066930d
BS		 719 */
720 spin_lock_irqsave(&pcdev->lock, flags);
721 if (vb->state == VIDEOBUF_QUEUED) {
722 list_del(&vb->queue);
723 vb->state = VIDEOBUF_ERROR;
7c6b7319
BS		 724 } else if (cpu_is_mx25() && vb->state == VIDEOBUF_ACTIVE) {
725 if (pcdev->fb1_active == buf) {
726 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
727 writel(0, pcdev->base_csi + CSIDMASA_FB1);
728 pcdev->fb1_active = NULL;
729 } else if (pcdev->fb2_active == buf) {
730 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
731 writel(0, pcdev->base_csi + CSIDMASA_FB2);
732 pcdev->fb2_active = NULL;
733 }
734 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
735 vb->state = VIDEOBUF_ERROR;
2066930d
BS		 736 }
737 spin_unlock_irqrestore(&pcdev->lock, flags);
738
739 free_buffer(vq, buf);
740}
741
742static struct videobuf_queue_ops mx2_videobuf_ops = {
743 .buf_setup = mx2_videobuf_setup,
744 .buf_prepare = mx2_videobuf_prepare,
745 .buf_queue = mx2_videobuf_queue,
746 .buf_release = mx2_videobuf_release,
747};
748
749static void mx2_camera_init_videobuf(struct videobuf_queue *q,
750 struct soc_camera_device *icd)
751{
7dfff953 752 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 753 struct mx2_camera_dev *pcdev = ici->priv;
754
755 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
756 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
b6a633c1
GL		 757 V4L2_FIELD_NONE, sizeof(struct mx2_buffer),
758 icd, &icd->video_lock);
2066930d
BS		 759}
760
db592a24
GL		 761#define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
762 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
763 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
764 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
765 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
766 V4L2_MBUS_PCLK_SAMPLE_RISING | \
767 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
768 V4L2_MBUS_DATA_ACTIVE_HIGH | \
769 V4L2_MBUS_DATA_ACTIVE_LOW)
2066930d
BS		 770
771static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
772{
773 u32 cntl;
774 int count = 0;
775
776 cntl = readl(pcdev->base_emma + PRP_CNTL);
777 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
778 while (count++ < 100) {
779 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
780 return 0;
781 barrier();
782 udelay(1);
783 }
784
785 return -ETIMEDOUT;
786}
787
788static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
789 int bytesperline)
790{
791 struct soc_camera_host *ici =
7dfff953 792 to_soc_camera_host(icd->parent);
2066930d 793 struct mx2_camera_dev *pcdev = ici->priv;
f410991d
JM		 794 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
795 u32 imgsize = pcdev->icd->user_height * pcdev->icd->user_width;
796
797 if (prp->cfg.channel == 1) {
798 writel(pcdev->discard_buffer_dma,
799 pcdev->base_emma + PRP_DEST_RGB1_PTR);
800 writel(pcdev->discard_buffer_dma,
801 pcdev->base_emma + PRP_DEST_RGB2_PTR);
802
803 writel(PRP_CNTL_CH1EN |
804 PRP_CNTL_CSIEN |
805 prp->cfg.in_fmt |
806 prp->cfg.out_fmt |
807 PRP_CNTL_CH1_LEN |
808 PRP_CNTL_CH1BYP |
809 PRP_CNTL_CH1_TSKIP(0) |
810 PRP_CNTL_IN_TSKIP(0),
811 pcdev->base_emma + PRP_CNTL);
812
813 writel((icd->user_width << 16) | icd->user_height,
814 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
815 writel((icd->user_width << 16) | icd->user_height,
816 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
817 writel(bytesperline,
818 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
819 writel(prp->cfg.src_pixel,
820 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
821 writel(prp->cfg.ch1_pixel,
822 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
823 } else { /* channel 2 */
824 writel(pcdev->discard_buffer_dma,
825 pcdev->base_emma + PRP_DEST_Y_PTR);
826 writel(pcdev->discard_buffer_dma,
827 pcdev->base_emma + PRP_SOURCE_Y_PTR);
828
829 if (prp->cfg.out_fmt == PRP_CNTL_CH2_OUT_YUV420) {
830 writel(pcdev->discard_buffer_dma + imgsize,
831 pcdev->base_emma + PRP_DEST_CB_PTR);
832 writel(pcdev->discard_buffer_dma + ((5 * imgsize) / 4),
833 pcdev->base_emma + PRP_DEST_CR_PTR);
834 writel(pcdev->discard_buffer_dma + imgsize,
835 pcdev->base_emma + PRP_SOURCE_CB_PTR);
836 writel(pcdev->discard_buffer_dma + ((5 * imgsize) / 4),
837 pcdev->base_emma + PRP_SOURCE_CR_PTR);
838 }
2066930d 839
f410991d 840 writel(PRP_CNTL_CH2EN |
2066930d 841 PRP_CNTL_CSIEN |
f410991d
JM		 842 prp->cfg.in_fmt |
843 prp->cfg.out_fmt |
844 PRP_CNTL_CH2_LEN |
845 PRP_CNTL_CH2_TSKIP(0) |
2066930d
BS		 846 PRP_CNTL_IN_TSKIP(0),
847 pcdev->base_emma + PRP_CNTL);
848
f410991d 849 writel((icd->user_width << 16) | icd->user_height,
2066930d 850 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
f410991d
JM		 851
852 writel((icd->user_width << 16) | icd->user_height,
853 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
854
855 writel(prp->cfg.src_pixel,
2066930d 856 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
f410991d
JM		 857
858 }
2066930d
BS		 859
860 /* Enable interrupts */
f410991d 861 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
2066930d
BS		 862}
863
8843d119 864static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
2066930d 865{
db592a24
GL		 866 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
867 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d 868 struct mx2_camera_dev *pcdev = ici->priv;
db592a24
GL		 869 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
870 unsigned long common_flags;
871 int ret;
2066930d
BS		 872 int bytesperline;
873 u32 csicr1 = pcdev->csicr1;
874
db592a24
GL		 875 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
876 if (!ret) {
877 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
878 if (!common_flags) {
879 dev_warn(icd->parent,
880 "Flags incompatible: camera 0x%x, host 0x%x\n",
881 cfg.flags, MX2_BUS_FLAGS);
882 return -EINVAL;
883 }
884 } else if (ret != -ENOIOCTLCMD) {
885 return ret;
886 } else {
887 common_flags = MX2_BUS_FLAGS;
888 }
2066930d 889
db592a24
GL		 890 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
891 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
2066930d 892 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
db592a24 893 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
2066930d 894 else
db592a24 895 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
2066930d
BS		 896 }
897
db592a24
GL		 898 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
899 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
2066930d 900 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
db592a24 901 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
2066930d 902 else
db592a24 903 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
2066930d
BS		 904 }
905
db592a24
GL		 906 cfg.flags = common_flags;
907 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
908 if (ret < 0 && ret != -ENOIOCTLCMD) {
909 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
910 common_flags, ret);
2066930d 911 return ret;
db592a24 912 }
2066930d 913
db592a24 914 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
d86097e1 915 csicr1 |= CSICR1_REDGE;
db592a24 916 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2066930d 917 csicr1 |= CSICR1_SOF_POL;
db592a24 918 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2066930d
BS		 919 csicr1 |= CSICR1_HSYNC_POL;
920 if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
921 csicr1 |= CSICR1_SWAP16_EN;
922 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
923 csicr1 |= CSICR1_EXT_VSYNC;
924 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
925 csicr1 |= CSICR1_CCIR_EN;
926 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
927 csicr1 |= CSICR1_CCIR_MODE;
928 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
929 csicr1 |= CSICR1_GCLK_MODE;
930 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
931 csicr1 |= CSICR1_INV_DATA;
932 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
933 csicr1 |= CSICR1_PACK_DIR;
934
935 pcdev->csicr1 = csicr1;
936
937 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
938 icd->current_fmt->host_fmt);
939 if (bytesperline < 0)
940 return bytesperline;
941
942 if (mx27_camera_emma(pcdev)) {
943 ret = mx27_camera_emma_prp_reset(pcdev);
944 if (ret)
945 return ret;
946
947 if (pcdev->discard_buffer)
948 dma_free_coherent(ici->v4l2_dev.dev,
949 pcdev->discard_size, pcdev->discard_buffer,
950 pcdev->discard_buffer_dma);
951
952 /*
953 * I didn't manage to properly enable/disable the prp
954 * on a per frame basis during running transfers,
955 * thus we allocate a buffer here and use it to
956 * discard frames when no buffer is available.
957 * Feel free to work on this ;)
958 */
959 pcdev->discard_size = icd->user_height * bytesperline;
960 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
961 pcdev->discard_size, &pcdev->discard_buffer_dma,
962 GFP_KERNEL);
963 if (!pcdev->discard_buffer)
964 return -ENOMEM;
965
966 mx27_camera_emma_buf_init(icd, bytesperline);
967 } else if (cpu_is_mx25()) {
968 writel((bytesperline * icd->user_height) >> 2,
969 pcdev->base_csi + CSIRXCNT);
970 writel((bytesperline << 16) | icd->user_height,
971 pcdev->base_csi + CSIIMAG_PARA);
972 }
973
974 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
975
976 return 0;
977}
978
979static int mx2_camera_set_crop(struct soc_camera_device *icd,
980 struct v4l2_crop *a)
981{
982 struct v4l2_rect *rect = &a->c;
983 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
984 struct v4l2_mbus_framefmt mf;
985 int ret;
986
987 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
988 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
989
990 ret = v4l2_subdev_call(sd, video, s_crop, a);
991 if (ret < 0)
992 return ret;
993
994 /* The capture device might have changed its output */
995 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
996 if (ret < 0)
997 return ret;
998
7dfff953 999 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
2066930d
BS		 1000 mf.width, mf.height);
1001
1002 icd->user_width = mf.width;
1003 icd->user_height = mf.height;
1004
1005 return ret;
1006}
1007
f410991d
JM		 1008static int mx2_camera_get_formats(struct soc_camera_device *icd,
1009 unsigned int idx,
1010 struct soc_camera_format_xlate *xlate)
1011{
1012 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1013 const struct soc_mbus_pixelfmt *fmt;
1014 struct device *dev = icd->parent;
1015 enum v4l2_mbus_pixelcode code;
1016 int ret, formats = 0;
1017
1018 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1019 if (ret < 0)
1020 /* no more formats */
1021 return 0;
1022
1023 fmt = soc_mbus_get_fmtdesc(code);
1024 if (!fmt) {
1025 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1026 return 0;
1027 }
1028
1029 if (code == V4L2_MBUS_FMT_YUYV8_2X8) {
1030 formats++;
1031 if (xlate) {
1032 /*
1033 * CH2 can output YUV420 which is a standard format in
1034 * soc_mediabus.c
1035 */
1036 xlate->host_fmt =
1037 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1038 xlate->code = code;
1039 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1040 xlate->host_fmt->name, code);
1041 xlate++;
1042 }
1043 }
1044
1045 /* Generic pass-trough */
1046 formats++;
1047 if (xlate) {
1048 xlate->host_fmt = fmt;
1049 xlate->code = code;
1050 xlate++;
1051 }
1052 return formats;
1053}
1054
2066930d
BS		 1055static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1056 struct v4l2_format *f)
1057{
f410991d
JM		 1058 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1059 struct mx2_camera_dev *pcdev = ici->priv;
2066930d
BS		 1060 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1061 const struct soc_camera_format_xlate *xlate;
1062 struct v4l2_pix_format *pix = &f->fmt.pix;
1063 struct v4l2_mbus_framefmt mf;
1064 int ret;
1065
1066 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1067 if (!xlate) {
7dfff953 1068 dev_warn(icd->parent, "Format %x not found\n",
2066930d
BS		 1069 pix->pixelformat);
1070 return -EINVAL;
1071 }
1072
2066930d
BS		 1073 mf.width = pix->width;
1074 mf.height = pix->height;
1075 mf.field = pix->field;
1076 mf.colorspace = pix->colorspace;
1077 mf.code = xlate->code;
1078
1079 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1080 if (ret < 0 && ret != -ENOIOCTLCMD)
1081 return ret;
1082
1083 if (mf.code != xlate->code)
1084 return -EINVAL;
1085
1086 pix->width = mf.width;
1087 pix->height = mf.height;
1088 pix->field = mf.field;
1089 pix->colorspace = mf.colorspace;
1090 icd->current_fmt = xlate;
1091
f410991d
JM		 1092 if (mx27_camera_emma(pcdev))
1093 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1094 xlate->host_fmt->fourcc);
1095
2066930d
BS		 1096 return 0;
1097}
1098
1099static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1100 struct v4l2_format *f)
1101{
2066930d
BS		 1102 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1103 const struct soc_camera_format_xlate *xlate;
1104 struct v4l2_pix_format *pix = &f->fmt.pix;
1105 struct v4l2_mbus_framefmt mf;
1106 __u32 pixfmt = pix->pixelformat;
1107 unsigned int width_limit;
1108 int ret;
1109
1110 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1111 if (pixfmt && !xlate) {
7dfff953 1112 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
2066930d
BS		 1113 return -EINVAL;
1114 }
1115
1116 /* FIXME: implement MX27 limits */
1117
2066930d
BS		 1118 /* limit to MX25 hardware capabilities */
1119 if (cpu_is_mx25()) {
1120 if (xlate->host_fmt->bits_per_sample <= 8)
1121 width_limit = 0xffff * 4;
1122 else
1123 width_limit = 0xffff * 2;
1124 /* CSIIMAG_PARA limit */
1125 if (pix->width > width_limit)
1126 pix->width = width_limit;
1127 if (pix->height > 0xffff)
1128 pix->height = 0xffff;
1129
1130 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1131 xlate->host_fmt);
1132 if (pix->bytesperline < 0)
1133 return pix->bytesperline;
1134 pix->sizeimage = pix->height * pix->bytesperline;
28281a71
GL		 1135 /* Check against the CSIRXCNT limit */
1136 if (pix->sizeimage > 4 * 0x3ffff) {
1137 /* Adjust geometry, preserve aspect ratio */
1138 unsigned int new_height = int_sqrt(4 * 0x3ffff *
1139 pix->height / pix->bytesperline);
1140 pix->width = new_height * pix->width / pix->height;
1141 pix->height = new_height;
1142 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1143 xlate->host_fmt);
1144 BUG_ON(pix->bytesperline < 0);
2066930d
BS		 1145 }
1146 }
1147
1148 /* limit to sensor capabilities */
1149 mf.width = pix->width;
1150 mf.height = pix->height;
1151 mf.field = pix->field;
1152 mf.colorspace = pix->colorspace;
1153 mf.code = xlate->code;
1154
1155 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1156 if (ret < 0)
1157 return ret;
1158
1159 if (mf.field == V4L2_FIELD_ANY)
1160 mf.field = V4L2_FIELD_NONE;
f410991d
JM		 1161 /*
1162 * Driver supports interlaced images provided they have
1163 * both fields so that they can be processed as if they
1164 * were progressive.
1165 */
1166 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
7dfff953 1167 dev_err(icd->parent, "Field type %d unsupported.\n",
2066930d
BS		 1168 mf.field);
1169 return -EINVAL;
1170 }
1171
1172 pix->width = mf.width;
1173 pix->height = mf.height;
1174 pix->field = mf.field;
1175 pix->colorspace = mf.colorspace;
1176
1177 return 0;
1178}
1179
1180static int mx2_camera_querycap(struct soc_camera_host *ici,
1181 struct v4l2_capability *cap)
1182{
1183 /* cap->name is set by the friendly caller:-> */
1184 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
2066930d
BS		 1185 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1186
1187 return 0;
1188}
1189
6b101926 1190static int mx2_camera_reqbufs(struct soc_camera_device *icd,
2066930d
BS		 1191 struct v4l2_requestbuffers *p)
1192{
1193 int i;
1194
1195 for (i = 0; i < p->count; i++) {
6b101926 1196 struct mx2_buffer *buf = container_of(icd->vb_vidq.bufs[i],
2066930d
BS		 1197 struct mx2_buffer, vb);
1198 INIT_LIST_HEAD(&buf->vb.queue);
1199 }
1200
1201 return 0;
1202}
1203
1204#ifdef CONFIG_MACH_MX27
1205static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
1206{
1207 struct videobuf_buffer *vb;
1208 struct mx2_buffer *buf;
1209 unsigned long flags;
1210 int ret;
1211
1212 spin_lock_irqsave(&pcdev->lock, flags);
1213
1214 if (!pcdev->active) {
1215 dev_err(pcdev->dev, "%s called with no active buffer!\n",
1216 __func__);
1217 goto out;
1218 }
1219
1220 vb = &pcdev->active->vb;
1221 buf = container_of(vb, struct mx2_buffer, vb);
1222 WARN_ON(list_empty(&vb->queue));
1223 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
1224 vb, vb->baddr, vb->bsize);
1225
1226 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
1227 list_del_init(&vb->queue);
1228 vb->state = state;
1229 do_gettimeofday(&vb->ts);
1230 vb->field_count++;
1231
1232 wake_up(&vb->done);
1233
1234 if (list_empty(&pcdev->capture)) {
1235 pcdev->active = NULL;
1236 goto out;
1237 }
1238
1239 pcdev->active = list_entry(pcdev->capture.next,
1240 struct mx2_buffer, vb.queue);
1241
1242 vb = &pcdev->active->vb;
1243 vb->state = VIDEOBUF_ACTIVE;
1244
1245 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
1246 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
1247
1248 if (ret) {
1249 vb->state = VIDEOBUF_ERROR;
1250 pcdev->active = NULL;
1251 wake_up(&vb->done);
1252 }
1253
1254out:
1255 spin_unlock_irqrestore(&pcdev->lock, flags);
1256}
1257
1258static void mx27_camera_dma_err_callback(int channel, void *data, int err)
1259{
1260 struct mx2_camera_dev *pcdev = data;
1261
1262 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
1263}
1264
1265static void mx27_camera_dma_callback(int channel, void *data)
1266{
1267 struct mx2_camera_dev *pcdev = data;
1268
1269 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
1270}
1271
1272#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */
1273
1274static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
1275 struct mx2_camera_dev *pcdev)
1276{
1277 int err;
1278
1279 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
1280 if (pcdev->dma < 0) {
1281 dev_err(&pdev->dev, "%s failed to request DMA channel\n",
1282 __func__);
1283 return pcdev->dma;
1284 }
1285
1286 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
1287 mx27_camera_dma_err_callback, pcdev);
1288 if (err) {
1289 dev_err(&pdev->dev, "%s failed to set DMA callback\n",
1290 __func__);
1291 goto err_out;
1292 }
1293
1294 err = imx_dma_config_channel(pcdev->dma,
1295 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
1296 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
1297 DMA_REQ_CSI_RX, 1);
1298 if (err) {
1299 dev_err(&pdev->dev, "%s failed to config DMA channel\n",
1300 __func__);
1301 goto err_out;
1302 }
1303
1304 imx_dma_config_burstlen(pcdev->dma, 64);
1305
1306 return 0;
1307
1308err_out:
1309 imx_dma_free(pcdev->dma);
1310
1311 return err;
1312}
1313#endif /* CONFIG_MACH_MX27 */
1314
1315static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1316{
6b101926 1317 struct soc_camera_device *icd = file->private_data;
2066930d 1318
6b101926 1319 return videobuf_poll_stream(file, &icd->vb_vidq, pt);
2066930d
BS		 1320}
1321
1322static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1323 .owner = THIS_MODULE,
1324 .add = mx2_camera_add_device,
1325 .remove = mx2_camera_remove_device,
1326 .set_fmt = mx2_camera_set_fmt,
1327 .set_crop = mx2_camera_set_crop,
f410991d 1328 .get_formats = mx2_camera_get_formats,
2066930d
BS		 1329 .try_fmt = mx2_camera_try_fmt,
1330 .init_videobuf = mx2_camera_init_videobuf,
1331 .reqbufs = mx2_camera_reqbufs,
1332 .poll = mx2_camera_poll,
1333 .querycap = mx2_camera_querycap,
1334 .set_bus_param = mx2_camera_set_bus_param,
1335};
1336
1337static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1338 int bufnum, int state)
1339{
f410991d
JM		 1340 u32 imgsize = pcdev->icd->user_height * pcdev->icd->user_width;
1341 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
2066930d
BS		 1342 struct mx2_buffer *buf;
1343 struct videobuf_buffer *vb;
1344 unsigned long phys;
1345
1346 if (!list_empty(&pcdev->active_bufs)) {
1347 buf = list_entry(pcdev->active_bufs.next,
1348 struct mx2_buffer, vb.queue);
1349
1350 BUG_ON(buf->bufnum != bufnum);
1351
1352 vb = &buf->vb;
1353#ifdef DEBUG
1354 phys = videobuf_to_dma_contig(vb);
f410991d
JM		 1355 if (prp->cfg.channel == 1) {
1356 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1357 4 * bufnum) != phys) {
1358 dev_err(pcdev->dev, "%p != %p\n", phys,
1359 readl(pcdev->base_emma +
1360 PRP_DEST_RGB1_PTR +
1361 4 * bufnum));
1362 }
1363 } else {
1364 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1365 0x14 * bufnum) != phys) {
1366 dev_err(pcdev->dev, "%p != %p\n", phys,
1367 readl(pcdev->base_emma +
1368 PRP_DEST_Y_PTR -
1369 0x14 * bufnum));
1370 }
2066930d
BS		 1371 }
1372#endif
1373 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
1374 vb->baddr, vb->bsize);
1375
1376 list_del(&vb->queue);
1377 vb->state = state;
1378 do_gettimeofday(&vb->ts);
ccd1a499
JM		 1379 vb->field_count = pcdev->frame_count * 2;
1380 pcdev->frame_count++;
2066930d
BS		 1381
1382 wake_up(&vb->done);
1383 }
1384
1385 if (list_empty(&pcdev->capture)) {
f410991d
JM		 1386 if (prp->cfg.channel == 1) {
1387 writel(pcdev->discard_buffer_dma, pcdev->base_emma +
1388 PRP_DEST_RGB1_PTR + 4 * bufnum);
1389 } else {
1390 writel(pcdev->discard_buffer_dma, pcdev->base_emma +
1391 PRP_DEST_Y_PTR -
1392 0x14 * bufnum);
1393 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
1394 writel(pcdev->discard_buffer_dma + imgsize,
1395 pcdev->base_emma + PRP_DEST_CB_PTR -
1396 0x14 * bufnum);
1397 writel(pcdev->discard_buffer_dma +
1398 ((5 * imgsize) / 4), pcdev->base_emma +
1399 PRP_DEST_CR_PTR - 0x14 * bufnum);
1400 }
1401 }
2066930d
BS		 1402 return;
1403 }
1404
1405 buf = list_entry(pcdev->capture.next,
1406 struct mx2_buffer, vb.queue);
1407
cd9ebdbc 1408 buf->bufnum = !bufnum;
2066930d
BS		 1409
1410 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1411
1412 vb = &buf->vb;
1413 vb->state = VIDEOBUF_ACTIVE;
1414
1415 phys = videobuf_to_dma_contig(vb);
f410991d
JM		 1416 if (prp->cfg.channel == 1) {
1417 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
1418 } else {
1419 writel(phys, pcdev->base_emma +
1420 PRP_DEST_Y_PTR - 0x14 * bufnum);
1421 if (prp->cfg.out_fmt == PRP_CNTL_CH2_OUT_YUV420) {
1422 writel(phys + imgsize, pcdev->base_emma +
1423 PRP_DEST_CB_PTR - 0x14 * bufnum);
1424 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
1425 PRP_DEST_CR_PTR - 0x14 * bufnum);
1426 }
1427 }
2066930d
BS		 1428}
1429
1430static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1431{
1432 struct mx2_camera_dev *pcdev = data;
1433 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1434 struct mx2_buffer *buf;
1435
1436 if (status & (1 << 7)) { /* overflow */
1437 u32 cntl;
1438 /*
1439 * We only disable channel 1 here since this is the only
1440 * enabled channel
1441 *
1442 * FIXME: the correct DMA overflow handling should be resetting
1443 * the buffer, returning an error frame, and continuing with
1444 * the next one.
1445 */
1446 cntl = readl(pcdev->base_emma + PRP_CNTL);
f410991d
JM		 1447 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1448 pcdev->base_emma + PRP_CNTL);
2066930d
BS		 1449 writel(cntl, pcdev->base_emma + PRP_CNTL);
1450 }
f410991d
JM		 1451 if ((((status & (3 << 5)) == (3 << 5)) ||
1452 ((status & (3 << 3)) == (3 << 3)))
2066930d
BS		 1453 && !list_empty(&pcdev->active_bufs)) {
1454 /*
1455 * Both buffers have triggered, process the one we're expecting
1456 * to first
1457 */
1458 buf = list_entry(pcdev->active_bufs.next,
1459 struct mx2_buffer, vb.queue);
1460 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
1461 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
1462 }
f410991d 1463 if ((status & (1 << 6)) || (status & (1 << 4)))
2066930d 1464 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
f410991d 1465 if ((status & (1 << 5)) || (status & (1 << 3)))
2066930d
BS		 1466 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
1467
1468 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1469
1470 return IRQ_HANDLED;
1471}
1472
1473static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1474{
1475 struct resource *res_emma = pcdev->res_emma;
1476 int err = 0;
1477
1478 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1479 MX2_CAM_DRV_NAME)) {
1480 err = -EBUSY;
1481 goto out;
1482 }
1483
1484 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1485 if (!pcdev->base_emma) {
1486 err = -ENOMEM;
1487 goto exit_release;
1488 }
1489
1490 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1491 MX2_CAM_DRV_NAME, pcdev);
1492 if (err) {
1493 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1494 goto exit_iounmap;
1495 }
1496
1497 pcdev->clk_emma = clk_get(NULL, "emma");
1498 if (IS_ERR(pcdev->clk_emma)) {
1499 err = PTR_ERR(pcdev->clk_emma);
1500 goto exit_free_irq;
1501 }
1502
1503 clk_enable(pcdev->clk_emma);
1504
1505 err = mx27_camera_emma_prp_reset(pcdev);
1506 if (err)
1507 goto exit_clk_emma_put;
1508
1509 return err;
1510
1511exit_clk_emma_put:
1512 clk_disable(pcdev->clk_emma);
1513 clk_put(pcdev->clk_emma);
1514exit_free_irq:
1515 free_irq(pcdev->irq_emma, pcdev);
1516exit_iounmap:
1517 iounmap(pcdev->base_emma);
1518exit_release:
1519 release_mem_region(res_emma->start, resource_size(res_emma));
1520out:
1521 return err;
1522}
1523
1524static int __devinit mx2_camera_probe(struct platform_device *pdev)
1525{
1526 struct mx2_camera_dev *pcdev;
1527 struct resource *res_csi, *res_emma;
1528 void __iomem *base_csi;
1529 int irq_csi, irq_emma;
1530 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
1531 : mx27_camera_irq;
1532 int err = 0;
1533
1534 dev_dbg(&pdev->dev, "initialising\n");
1535
1536 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 irq_csi = platform_get_irq(pdev, 0);
1538 if (res_csi == NULL || irq_csi < 0) {
1539 dev_err(&pdev->dev, "Missing platform resources data\n");
1540 err = -ENODEV;
1541 goto exit;
1542 }
1543
1544 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1545 if (!pcdev) {
1546 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1547 err = -ENOMEM;
1548 goto exit;
1549 }
1550
1551 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1552 if (IS_ERR(pcdev->clk_csi)) {
1553 err = PTR_ERR(pcdev->clk_csi);
1554 goto exit_kfree;
1555 }
1556
1557 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
1558 clk_get_rate(pcdev->clk_csi));
1559
1560 /* Initialize DMA */
1561#ifdef CONFIG_MACH_MX27
1562 if (cpu_is_mx27()) {
1563 err = mx27_camera_dma_init(pdev, pcdev);
1564 if (err)
1565 goto exit_clk_put;
1566 }
1567#endif /* CONFIG_MACH_MX27 */
1568
1569 pcdev->res_csi = res_csi;
1570 pcdev->pdata = pdev->dev.platform_data;
1571 if (pcdev->pdata) {
1572 long rate;
1573
1574 pcdev->platform_flags = pcdev->pdata->flags;
1575
1576 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1577 if (rate <= 0) {
1578 err = -ENODEV;
1579 goto exit_dma_free;
1580 }
1581 err = clk_set_rate(pcdev->clk_csi, rate);
1582 if (err < 0)
1583 goto exit_dma_free;
1584 }
1585
1586 INIT_LIST_HEAD(&pcdev->capture);
1587 INIT_LIST_HEAD(&pcdev->active_bufs);
1588 spin_lock_init(&pcdev->lock);
1589
1590 /*
1591 * Request the regions.
1592 */
1593 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1594 MX2_CAM_DRV_NAME)) {
1595 err = -EBUSY;
1596 goto exit_dma_free;
1597 }
1598
1599 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1600 if (!base_csi) {
1601 err = -ENOMEM;
1602 goto exit_release;
1603 }
1604 pcdev->irq_csi = irq_csi;
1605 pcdev->base_csi = base_csi;
1606 pcdev->base_dma = res_csi->start;
1607 pcdev->dev = &pdev->dev;
1608
1609 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
1610 MX2_CAM_DRV_NAME, pcdev);
1611 if (err) {
1612 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1613 goto exit_iounmap;
1614 }
1615
1616 if (cpu_is_mx27()) {
1617 /* EMMA support */
1618 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1619 irq_emma = platform_get_irq(pdev, 1);
1620
1621 if (res_emma && irq_emma >= 0) {
1622 dev_info(&pdev->dev, "Using EMMA\n");
1623 pcdev->use_emma = 1;
1624 pcdev->res_emma = res_emma;
1625 pcdev->irq_emma = irq_emma;
1626 if (mx27_camera_emma_init(pcdev))
1627 goto exit_free_irq;
1628 }
1629 }
1630
1631 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1632 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1633 pcdev->soc_host.priv = pcdev;
1634 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1635 pcdev->soc_host.nr = pdev->id;
1636 err = soc_camera_host_register(&pcdev->soc_host);
1637 if (err)
1638 goto exit_free_emma;
1639
45f4d4e8
MG		 1640 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1641 clk_get_rate(pcdev->clk_csi));
1642
2066930d
BS		 1643 return 0;
1644
1645exit_free_emma:
1646 if (mx27_camera_emma(pcdev)) {
1647 free_irq(pcdev->irq_emma, pcdev);
1648 clk_disable(pcdev->clk_emma);
1649 clk_put(pcdev->clk_emma);
1650 iounmap(pcdev->base_emma);
1651 release_mem_region(res_emma->start, resource_size(res_emma));
1652 }
1653exit_free_irq:
1654 free_irq(pcdev->irq_csi, pcdev);
1655exit_iounmap:
1656 iounmap(base_csi);
1657exit_release:
1658 release_mem_region(res_csi->start, resource_size(res_csi));
1659exit_dma_free:
1660#ifdef CONFIG_MACH_MX27
1661 if (cpu_is_mx27())
1662 imx_dma_free(pcdev->dma);
1663exit_clk_put:
1664 clk_put(pcdev->clk_csi);
1665#endif /* CONFIG_MACH_MX27 */
1666exit_kfree:
1667 kfree(pcdev);
1668exit:
1669 return err;
1670}
1671
1672static int __devexit mx2_camera_remove(struct platform_device *pdev)
1673{
1674 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1675 struct mx2_camera_dev *pcdev = container_of(soc_host,
1676 struct mx2_camera_dev, soc_host);
1677 struct resource *res;
1678
1679 clk_put(pcdev->clk_csi);
1680#ifdef CONFIG_MACH_MX27
1681 if (cpu_is_mx27())
1682 imx_dma_free(pcdev->dma);
1683#endif /* CONFIG_MACH_MX27 */
1684 free_irq(pcdev->irq_csi, pcdev);
1685 if (mx27_camera_emma(pcdev))
1686 free_irq(pcdev->irq_emma, pcdev);
1687
1688 soc_camera_host_unregister(&pcdev->soc_host);
1689
1690 iounmap(pcdev->base_csi);
1691
1692 if (mx27_camera_emma(pcdev)) {
1693 clk_disable(pcdev->clk_emma);
1694 clk_put(pcdev->clk_emma);
1695 iounmap(pcdev->base_emma);
1696 res = pcdev->res_emma;
1697 release_mem_region(res->start, resource_size(res));
1698 }
1699
1700 res = pcdev->res_csi;
1701 release_mem_region(res->start, resource_size(res));
1702
1703 kfree(pcdev);
1704
1705 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1706
1707 return 0;
1708}
1709
1710static struct platform_driver mx2_camera_driver = {
1711 .driver = {
1712 .name = MX2_CAM_DRV_NAME,
1713 },
1714 .remove = __devexit_p(mx2_camera_remove),
1715};
1716
1717
1718static int __init mx2_camera_init(void)
1719{
1720 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1721}
1722
1723static void __exit mx2_camera_exit(void)
1724{
1725 return platform_driver_unregister(&mx2_camera_driver);
1726}
1727
1728module_init(mx2_camera_init);
1729module_exit(mx2_camera_exit);
1730
1731MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1732MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1733MODULE_LICENSE("GPL");
64dc3c1a 1734MODULE_VERSION(MX2_CAM_VERSION);
Linux kernel - Deliverables
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