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[media] soc-camera: remove redundant parameter from .set_bus_param()
[deliverable/linux.git] / drivers / media / video / mx2_camera.c
CommitLineData
2066930d
BS		 1/*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/slab.h>
18#include <linux/dma-mapping.h>
19#include <linux/errno.h>
20#include <linux/fs.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/mm.h>
24#include <linux/moduleparam.h>
25#include <linux/time.h>
2066930d
BS		 26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/mutex.h>
29#include <linux/clk.h>
30
31#include <media/v4l2-common.h>
32#include <media/v4l2-dev.h>
6b101926 33#include <media/videobuf-core.h>
2066930d
BS		 34#include <media/videobuf-dma-contig.h>
35#include <media/soc_camera.h>
36#include <media/soc_mediabus.h>
37
38#include <linux/videodev2.h>
39
40#include <mach/mx2_cam.h>
41#ifdef CONFIG_MACH_MX27
42#include <mach/dma-mx1-mx2.h>
43#endif
44#include <mach/hardware.h>
45
46#include <asm/dma.h>
47
48#define MX2_CAM_DRV_NAME "mx2-camera"
64dc3c1a 49#define MX2_CAM_VERSION "0.0.6"
2066930d
BS		 50#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51
52/* reset values */
53#define CSICR1_RESET_VAL 0x40000800
54#define CSICR2_RESET_VAL 0x0
55#define CSICR3_RESET_VAL 0x0
56
57/* csi control reg 1 */
58#define CSICR1_SWAP16_EN (1 << 31)
59#define CSICR1_EXT_VSYNC (1 << 30)
60#define CSICR1_EOF_INTEN (1 << 29)
61#define CSICR1_PRP_IF_EN (1 << 28)
62#define CSICR1_CCIR_MODE (1 << 27)
63#define CSICR1_COF_INTEN (1 << 26)
64#define CSICR1_SF_OR_INTEN (1 << 25)
65#define CSICR1_RF_OR_INTEN (1 << 24)
66#define CSICR1_STATFF_LEVEL (3 << 22)
67#define CSICR1_STATFF_INTEN (1 << 21)
68#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
69#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
70#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
71#define CSICR1_RXFF_INTEN (1 << 18)
72#define CSICR1_SOF_POL (1 << 17)
73#define CSICR1_SOF_INTEN (1 << 16)
74#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
75#define CSICR1_HSYNC_POL (1 << 11)
76#define CSICR1_CCIR_EN (1 << 10)
77#define CSICR1_MCLKEN (1 << 9)
78#define CSICR1_FCC (1 << 8)
79#define CSICR1_PACK_DIR (1 << 7)
80#define CSICR1_CLR_STATFIFO (1 << 6)
81#define CSICR1_CLR_RXFIFO (1 << 5)
82#define CSICR1_GCLK_MODE (1 << 4)
83#define CSICR1_INV_DATA (1 << 3)
84#define CSICR1_INV_PCLK (1 << 2)
85#define CSICR1_REDGE (1 << 1)
86
87#define SHIFT_STATFF_LEVEL 22
88#define SHIFT_RXFF_LEVEL 19
89#define SHIFT_MCLKDIV 12
90
91/* control reg 3 */
92#define CSICR3_FRMCNT (0xFFFF << 16)
93#define CSICR3_FRMCNT_RST (1 << 15)
94#define CSICR3_DMA_REFLASH_RFF (1 << 14)
95#define CSICR3_DMA_REFLASH_SFF (1 << 13)
96#define CSICR3_DMA_REQ_EN_RFF (1 << 12)
97#define CSICR3_DMA_REQ_EN_SFF (1 << 11)
98#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
99#define CSICR3_CSI_SUP (1 << 3)
100#define CSICR3_ZERO_PACK_EN (1 << 2)
101#define CSICR3_ECC_INT_EN (1 << 1)
102#define CSICR3_ECC_AUTO_EN (1 << 0)
103
104#define SHIFT_FRMCNT 16
105
106/* csi status reg */
107#define CSISR_SFF_OR_INT (1 << 25)
108#define CSISR_RFF_OR_INT (1 << 24)
109#define CSISR_STATFF_INT (1 << 21)
110#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
111#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
112#define CSISR_RXFF_INT (1 << 18)
113#define CSISR_EOF_INT (1 << 17)
114#define CSISR_SOF_INT (1 << 16)
115#define CSISR_F2_INT (1 << 15)
116#define CSISR_F1_INT (1 << 14)
117#define CSISR_COF_INT (1 << 13)
118#define CSISR_ECC_INT (1 << 1)
119#define CSISR_DRDY (1 << 0)
120
121#define CSICR1 0x00
122#define CSICR2 0x04
123#define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
124#define CSISTATFIFO 0x0c
125#define CSIRFIFO 0x10
126#define CSIRXCNT 0x14
127#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
128#define CSIDMASA_STATFIFO 0x20
129#define CSIDMATA_STATFIFO 0x24
130#define CSIDMASA_FB1 0x28
131#define CSIDMASA_FB2 0x2c
132#define CSIFBUF_PARA 0x30
133#define CSIIMAG_PARA 0x34
134
135/* EMMA PrP */
136#define PRP_CNTL 0x00
137#define PRP_INTR_CNTL 0x04
138#define PRP_INTRSTATUS 0x08
139#define PRP_SOURCE_Y_PTR 0x0c
140#define PRP_SOURCE_CB_PTR 0x10
141#define PRP_SOURCE_CR_PTR 0x14
142#define PRP_DEST_RGB1_PTR 0x18
143#define PRP_DEST_RGB2_PTR 0x1c
144#define PRP_DEST_Y_PTR 0x20
145#define PRP_DEST_CB_PTR 0x24
146#define PRP_DEST_CR_PTR 0x28
147#define PRP_SRC_FRAME_SIZE 0x2c
148#define PRP_DEST_CH1_LINE_STRIDE 0x30
149#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
150#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
151#define PRP_CH1_OUT_IMAGE_SIZE 0x3c
152#define PRP_CH2_OUT_IMAGE_SIZE 0x40
153#define PRP_SRC_LINE_STRIDE 0x44
154#define PRP_CSC_COEF_012 0x48
155#define PRP_CSC_COEF_345 0x4c
156#define PRP_CSC_COEF_678 0x50
157#define PRP_CH1_RZ_HORI_COEF1 0x54
158#define PRP_CH1_RZ_HORI_COEF2 0x58
159#define PRP_CH1_RZ_HORI_VALID 0x5c
160#define PRP_CH1_RZ_VERT_COEF1 0x60
161#define PRP_CH1_RZ_VERT_COEF2 0x64
162#define PRP_CH1_RZ_VERT_VALID 0x68
163#define PRP_CH2_RZ_HORI_COEF1 0x6c
164#define PRP_CH2_RZ_HORI_COEF2 0x70
165#define PRP_CH2_RZ_HORI_VALID 0x74
166#define PRP_CH2_RZ_VERT_COEF1 0x78
167#define PRP_CH2_RZ_VERT_COEF2 0x7c
168#define PRP_CH2_RZ_VERT_VALID 0x80
169
170#define PRP_CNTL_CH1EN (1 << 0)
171#define PRP_CNTL_CH2EN (1 << 1)
172#define PRP_CNTL_CSIEN (1 << 2)
173#define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
174#define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
175#define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
176#define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
177#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
178#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
179#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
180#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
181#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
182#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
183#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
184#define PRP_CNTL_CH1_LEN (1 << 9)
185#define PRP_CNTL_CH2_LEN (1 << 10)
186#define PRP_CNTL_SKIP_FRAME (1 << 11)
187#define PRP_CNTL_SWRST (1 << 12)
188#define PRP_CNTL_CLKEN (1 << 13)
189#define PRP_CNTL_WEN (1 << 14)
190#define PRP_CNTL_CH1BYP (1 << 15)
191#define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
192#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
193#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
194#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
195#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
196#define PRP_CNTL_CH2B1EN (1 << 29)
197#define PRP_CNTL_CH2B2EN (1 << 30)
198#define PRP_CNTL_CH2FEN (1 << 31)
199
200/* IRQ Enable and status register */
201#define PRP_INTR_RDERR (1 << 0)
202#define PRP_INTR_CH1WERR (1 << 1)
203#define PRP_INTR_CH2WERR (1 << 2)
204#define PRP_INTR_CH1FC (1 << 3)
205#define PRP_INTR_CH2FC (1 << 5)
206#define PRP_INTR_LBOVF (1 << 7)
207#define PRP_INTR_CH2OVF (1 << 8)
208
209#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma)
210
211#define MAX_VIDEO_MEM 16
212
213struct mx2_camera_dev {
214 struct device *dev;
215 struct soc_camera_host soc_host;
216 struct soc_camera_device *icd;
217 struct clk *clk_csi, *clk_emma;
218
219 unsigned int irq_csi, irq_emma;
220 void __iomem *base_csi, *base_emma;
221 unsigned long base_dma;
222
223 struct mx2_camera_platform_data *pdata;
224 struct resource *res_csi, *res_emma;
225 unsigned long platform_flags;
226
227 struct list_head capture;
228 struct list_head active_bufs;
229
230 spinlock_t lock;
231
232 int dma;
233 struct mx2_buffer *active;
234 struct mx2_buffer *fb1_active;
235 struct mx2_buffer *fb2_active;
236
237 int use_emma;
238
239 u32 csicr1;
240
79d3c2c2 241 void *discard_buffer;
2066930d
BS		 242 dma_addr_t discard_buffer_dma;
243 size_t discard_size;
244};
245
246/* buffer for one video frame */
247struct mx2_buffer {
248 /* common v4l buffer stuff -- must be first */
249 struct videobuf_buffer vb;
250
251 enum v4l2_mbus_pixelcode code;
252
253 int bufnum;
254};
255
256static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
257{
258 unsigned long flags;
259
260 clk_disable(pcdev->clk_csi);
261 writel(0, pcdev->base_csi + CSICR1);
262 if (mx27_camera_emma(pcdev)) {
263 writel(0, pcdev->base_emma + PRP_CNTL);
264 } else if (cpu_is_mx25()) {
265 spin_lock_irqsave(&pcdev->lock, flags);
266 pcdev->fb1_active = NULL;
267 pcdev->fb2_active = NULL;
268 writel(0, pcdev->base_csi + CSIDMASA_FB1);
269 writel(0, pcdev->base_csi + CSIDMASA_FB2);
270 spin_unlock_irqrestore(&pcdev->lock, flags);
271 }
272}
273
274/*
275 * The following two functions absolutely depend on the fact, that
276 * there can be only one camera on mx2 camera sensor interface
277 */
278static int mx2_camera_add_device(struct soc_camera_device *icd)
279{
7dfff953 280 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 281 struct mx2_camera_dev *pcdev = ici->priv;
282 int ret;
283 u32 csicr1;
284
285 if (pcdev->icd)
286 return -EBUSY;
287
288 ret = clk_enable(pcdev->clk_csi);
289 if (ret < 0)
290 return ret;
291
292 csicr1 = CSICR1_MCLKEN;
293
294 if (mx27_camera_emma(pcdev)) {
295 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
296 CSICR1_RXFF_LEVEL(0);
297 } else if (cpu_is_mx27())
298 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
299
300 pcdev->csicr1 = csicr1;
301 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
302
303 pcdev->icd = icd;
304
7dfff953 305 dev_info(icd->parent, "Camera driver attached to camera %d\n",
2066930d
BS		 306 icd->devnum);
307
308 return 0;
309}
310
311static void mx2_camera_remove_device(struct soc_camera_device *icd)
312{
7dfff953 313 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 314 struct mx2_camera_dev *pcdev = ici->priv;
315
316 BUG_ON(icd != pcdev->icd);
317
7dfff953 318 dev_info(icd->parent, "Camera driver detached from camera %d\n",
2066930d
BS		 319 icd->devnum);
320
321 mx2_camera_deactivate(pcdev);
322
323 if (pcdev->discard_buffer) {
324 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
325 pcdev->discard_buffer,
326 pcdev->discard_buffer_dma);
327 pcdev->discard_buffer = NULL;
328 }
329
330 pcdev->icd = NULL;
331}
332
333#ifdef CONFIG_MACH_MX27
334static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
335{
336 u32 tmp;
337
338 imx_dma_enable(pcdev->dma);
339
340 tmp = readl(pcdev->base_csi + CSICR1);
341 tmp |= CSICR1_RF_OR_INTEN;
342 writel(tmp, pcdev->base_csi + CSICR1);
343}
344
345static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
346{
347 struct mx2_camera_dev *pcdev = data;
348 u32 status = readl(pcdev->base_csi + CSISR);
349
350 if (status & CSISR_SOF_INT && pcdev->active) {
351 u32 tmp;
352
353 tmp = readl(pcdev->base_csi + CSICR1);
354 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
355 mx27_camera_dma_enable(pcdev);
356 }
357
358 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
359
360 return IRQ_HANDLED;
361}
362#else
363static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
364{
365 return IRQ_NONE;
366}
367#endif /* CONFIG_MACH_MX27 */
368
369static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
370 int state)
371{
372 struct videobuf_buffer *vb;
373 struct mx2_buffer *buf;
374 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
375 &pcdev->fb2_active;
376 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
377 unsigned long flags;
378
379 spin_lock_irqsave(&pcdev->lock, flags);
380
5384a12b
BS		 381 if (*fb_active == NULL)
382 goto out;
383
2066930d
BS		 384 vb = &(*fb_active)->vb;
385 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
386 vb, vb->baddr, vb->bsize);
387
388 vb->state = state;
389 do_gettimeofday(&vb->ts);
390 vb->field_count++;
391
392 wake_up(&vb->done);
393
394 if (list_empty(&pcdev->capture)) {
395 buf = NULL;
396 writel(0, pcdev->base_csi + fb_reg);
397 } else {
398 buf = list_entry(pcdev->capture.next, struct mx2_buffer,
399 vb.queue);
400 vb = &buf->vb;
401 list_del(&vb->queue);
402 vb->state = VIDEOBUF_ACTIVE;
403 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
404 }
405
406 *fb_active = buf;
407
5384a12b 408out:
2066930d
BS		 409 spin_unlock_irqrestore(&pcdev->lock, flags);
410}
411
412static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
413{
414 struct mx2_camera_dev *pcdev = data;
415 u32 status = readl(pcdev->base_csi + CSISR);
416
417 if (status & CSISR_DMA_TSF_FB1_INT)
418 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
419 else if (status & CSISR_DMA_TSF_FB2_INT)
420 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
421
422 /* FIXME: handle CSISR_RFF_OR_INT */
423
424 writel(status, pcdev->base_csi + CSISR);
425
426 return IRQ_HANDLED;
427}
428
429/*
430 * Videobuf operations
431 */
432static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
433 unsigned int *size)
434{
435 struct soc_camera_device *icd = vq->priv_data;
436 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
437 icd->current_fmt->host_fmt);
438
7dfff953 439 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size);
2066930d
BS		 440
441 if (bytes_per_line < 0)
442 return bytes_per_line;
443
444 *size = bytes_per_line * icd->user_height;
445
446 if (0 == *count)
447 *count = 32;
448 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
449 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
450
451 return 0;
452}
453
454static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
455{
456 struct soc_camera_device *icd = vq->priv_data;
457 struct videobuf_buffer *vb = &buf->vb;
458
7dfff953 459 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 460 vb, vb->baddr, vb->bsize);
461
462 /*
463 * This waits until this buffer is out of danger, i.e., until it is no
88bfd0bd 464 * longer in state VIDEOBUF_QUEUED or VIDEOBUF_ACTIVE
2066930d 465 */
0e0809a5 466 videobuf_waiton(vq, vb, 0, 0);
2066930d
BS		 467
468 videobuf_dma_contig_free(vq, vb);
7dfff953 469 dev_dbg(icd->parent, "%s freed\n", __func__);
2066930d
BS		 470
471 vb->state = VIDEOBUF_NEEDS_INIT;
472}
473
474static int mx2_videobuf_prepare(struct videobuf_queue *vq,
475 struct videobuf_buffer *vb, enum v4l2_field field)
476{
477 struct soc_camera_device *icd = vq->priv_data;
478 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
479 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
480 icd->current_fmt->host_fmt);
481 int ret = 0;
482
7dfff953 483 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 484 vb, vb->baddr, vb->bsize);
485
486 if (bytes_per_line < 0)
487 return bytes_per_line;
488
489#ifdef DEBUG
490 /*
491 * This can be useful if you want to see if we actually fill
492 * the buffer with something
493 */
494 memset((void *)vb->baddr, 0xaa, vb->bsize);
495#endif
496
497 if (buf->code != icd->current_fmt->code ||
498 vb->width != icd->user_width ||
499 vb->height != icd->user_height ||
500 vb->field != field) {
501 buf->code = icd->current_fmt->code;
502 vb->width = icd->user_width;
503 vb->height = icd->user_height;
504 vb->field = field;
505 vb->state = VIDEOBUF_NEEDS_INIT;
506 }
507
508 vb->size = bytes_per_line * vb->height;
509 if (vb->baddr && vb->bsize < vb->size) {
510 ret = -EINVAL;
511 goto out;
512 }
513
514 if (vb->state == VIDEOBUF_NEEDS_INIT) {
515 ret = videobuf_iolock(vq, vb, NULL);
516 if (ret)
517 goto fail;
518
519 vb->state = VIDEOBUF_PREPARED;
520 }
521
522 return 0;
523
524fail:
525 free_buffer(vq, buf);
526out:
527 return ret;
528}
529
530static void mx2_videobuf_queue(struct videobuf_queue *vq,
531 struct videobuf_buffer *vb)
532{
533 struct soc_camera_device *icd = vq->priv_data;
534 struct soc_camera_host *ici =
7dfff953 535 to_soc_camera_host(icd->parent);
2066930d
BS		 536 struct mx2_camera_dev *pcdev = ici->priv;
537 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
538 unsigned long flags;
539
7dfff953 540 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 541 vb, vb->baddr, vb->bsize);
542
543 spin_lock_irqsave(&pcdev->lock, flags);
544
545 vb->state = VIDEOBUF_QUEUED;
546 list_add_tail(&vb->queue, &pcdev->capture);
547
548 if (mx27_camera_emma(pcdev)) {
549 goto out;
550#ifdef CONFIG_MACH_MX27
551 } else if (cpu_is_mx27()) {
552 int ret;
553
554 if (pcdev->active == NULL) {
555 ret = imx_dma_setup_single(pcdev->dma,
556 videobuf_to_dma_contig(vb), vb->size,
557 (u32)pcdev->base_dma + 0x10,
558 DMA_MODE_READ);
559 if (ret) {
560 vb->state = VIDEOBUF_ERROR;
561 wake_up(&vb->done);
562 goto out;
563 }
564
565 vb->state = VIDEOBUF_ACTIVE;
566 pcdev->active = buf;
567 }
568#endif
569 } else { /* cpu_is_mx25() */
570 u32 csicr3, dma_inten = 0;
571
572 if (pcdev->fb1_active == NULL) {
573 writel(videobuf_to_dma_contig(vb),
574 pcdev->base_csi + CSIDMASA_FB1);
575 pcdev->fb1_active = buf;
576 dma_inten = CSICR1_FB1_DMA_INTEN;
577 } else if (pcdev->fb2_active == NULL) {
578 writel(videobuf_to_dma_contig(vb),
579 pcdev->base_csi + CSIDMASA_FB2);
580 pcdev->fb2_active = buf;
581 dma_inten = CSICR1_FB2_DMA_INTEN;
582 }
583
584 if (dma_inten) {
585 list_del(&vb->queue);
586 vb->state = VIDEOBUF_ACTIVE;
587
588 csicr3 = readl(pcdev->base_csi + CSICR3);
589
590 /* Reflash DMA */
591 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
592 pcdev->base_csi + CSICR3);
593
594 /* clear & enable interrupts */
595 writel(dma_inten, pcdev->base_csi + CSISR);
596 pcdev->csicr1 |= dma_inten;
597 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
598
599 /* enable DMA */
600 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
601 writel(csicr3, pcdev->base_csi + CSICR3);
602 }
603 }
604
605out:
606 spin_unlock_irqrestore(&pcdev->lock, flags);
607}
608
609static void mx2_videobuf_release(struct videobuf_queue *vq,
610 struct videobuf_buffer *vb)
611{
612 struct soc_camera_device *icd = vq->priv_data;
7dfff953 613 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 614 struct mx2_camera_dev *pcdev = ici->priv;
615 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
616 unsigned long flags;
617
618#ifdef DEBUG
7dfff953 619 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
2066930d
BS		 620 vb, vb->baddr, vb->bsize);
621
622 switch (vb->state) {
623 case VIDEOBUF_ACTIVE:
7dfff953 624 dev_info(icd->parent, "%s (active)\n", __func__);
2066930d
BS		 625 break;
626 case VIDEOBUF_QUEUED:
7dfff953 627 dev_info(icd->parent, "%s (queued)\n", __func__);
2066930d
BS		 628 break;
629 case VIDEOBUF_PREPARED:
7dfff953 630 dev_info(icd->parent, "%s (prepared)\n", __func__);
2066930d
BS		 631 break;
632 default:
7dfff953 633 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
2066930d
BS		 634 vb->state);
635 break;
636 }
637#endif
638
639 /*
640 * Terminate only queued but inactive buffers. Active buffers are
641 * released when they become inactive after videobuf_waiton().
642 *
7c6b7319
BS		 643 * FIXME: implement forced termination of active buffers for mx27 and
644 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
645 * state. This requires a specific handling for each of the these DMA
646 * types.
2066930d
BS		 647 */
648 spin_lock_irqsave(&pcdev->lock, flags);
649 if (vb->state == VIDEOBUF_QUEUED) {
650 list_del(&vb->queue);
651 vb->state = VIDEOBUF_ERROR;
7c6b7319
BS		 652 } else if (cpu_is_mx25() && vb->state == VIDEOBUF_ACTIVE) {
653 if (pcdev->fb1_active == buf) {
654 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
655 writel(0, pcdev->base_csi + CSIDMASA_FB1);
656 pcdev->fb1_active = NULL;
657 } else if (pcdev->fb2_active == buf) {
658 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
659 writel(0, pcdev->base_csi + CSIDMASA_FB2);
660 pcdev->fb2_active = NULL;
661 }
662 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
663 vb->state = VIDEOBUF_ERROR;
2066930d
BS		 664 }
665 spin_unlock_irqrestore(&pcdev->lock, flags);
666
667 free_buffer(vq, buf);
668}
669
670static struct videobuf_queue_ops mx2_videobuf_ops = {
671 .buf_setup = mx2_videobuf_setup,
672 .buf_prepare = mx2_videobuf_prepare,
673 .buf_queue = mx2_videobuf_queue,
674 .buf_release = mx2_videobuf_release,
675};
676
677static void mx2_camera_init_videobuf(struct videobuf_queue *q,
678 struct soc_camera_device *icd)
679{
7dfff953 680 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d
BS		 681 struct mx2_camera_dev *pcdev = ici->priv;
682
683 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
684 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
b6a633c1
GL		 685 V4L2_FIELD_NONE, sizeof(struct mx2_buffer),
686 icd, &icd->video_lock);
2066930d
BS		 687}
688
db592a24
GL		 689#define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
690 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
691 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
692 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
693 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
694 V4L2_MBUS_PCLK_SAMPLE_RISING | \
695 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
696 V4L2_MBUS_DATA_ACTIVE_HIGH | \
697 V4L2_MBUS_DATA_ACTIVE_LOW)
2066930d
BS		 698
699static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
700{
701 u32 cntl;
702 int count = 0;
703
704 cntl = readl(pcdev->base_emma + PRP_CNTL);
705 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
706 while (count++ < 100) {
707 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
708 return 0;
709 barrier();
710 udelay(1);
711 }
712
713 return -ETIMEDOUT;
714}
715
716static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
717 int bytesperline)
718{
719 struct soc_camera_host *ici =
7dfff953 720 to_soc_camera_host(icd->parent);
2066930d
BS		 721 struct mx2_camera_dev *pcdev = ici->priv;
722
723 writel(pcdev->discard_buffer_dma,
724 pcdev->base_emma + PRP_DEST_RGB1_PTR);
725 writel(pcdev->discard_buffer_dma,
726 pcdev->base_emma + PRP_DEST_RGB2_PTR);
727
728 /*
729 * We only use the EMMA engine to get rid of the broken
730 * DMA Engine. No color space consversion at the moment.
7c3a2066
MG		 731 * We set the incomming and outgoing pixelformat to an
732 * 16 Bit wide format and adjust the bytesperline
733 * accordingly. With this configuration the inputdata
734 * will not be changed by the emma and could be any type
735 * of 16 Bit Pixelformat.
2066930d
BS		 736 */
737 writel(PRP_CNTL_CH1EN |
738 PRP_CNTL_CSIEN |
739 PRP_CNTL_DATA_IN_RGB16 |
740 PRP_CNTL_CH1_OUT_RGB16 |
741 PRP_CNTL_CH1_LEN |
742 PRP_CNTL_CH1BYP |
743 PRP_CNTL_CH1_TSKIP(0) |
744 PRP_CNTL_IN_TSKIP(0),
745 pcdev->base_emma + PRP_CNTL);
746
747 writel(((bytesperline >> 1) << 16) | icd->user_height,
748 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
749 writel(((bytesperline >> 1) << 16) | icd->user_height,
750 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
751 writel(bytesperline,
752 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
753 writel(0x2ca00565, /* RGB565 */
754 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
755 writel(0x2ca00565, /* RGB565 */
756 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
757
758 /* Enable interrupts */
759 writel(PRP_INTR_RDERR |
760 PRP_INTR_CH1WERR |
761 PRP_INTR_CH2WERR |
762 PRP_INTR_CH1FC |
763 PRP_INTR_CH2FC |
764 PRP_INTR_LBOVF |
765 PRP_INTR_CH2OVF,
766 pcdev->base_emma + PRP_INTR_CNTL);
767}
768
8843d119 769static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
2066930d 770{
db592a24
GL		 771 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
772 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
2066930d 773 struct mx2_camera_dev *pcdev = ici->priv;
db592a24
GL		 774 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
775 unsigned long common_flags;
776 int ret;
2066930d
BS		 777 int bytesperline;
778 u32 csicr1 = pcdev->csicr1;
779
db592a24
GL		 780 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
781 if (!ret) {
782 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
783 if (!common_flags) {
784 dev_warn(icd->parent,
785 "Flags incompatible: camera 0x%x, host 0x%x\n",
786 cfg.flags, MX2_BUS_FLAGS);
787 return -EINVAL;
788 }
789 } else if (ret != -ENOIOCTLCMD) {
790 return ret;
791 } else {
792 common_flags = MX2_BUS_FLAGS;
793 }
2066930d 794
db592a24
GL		 795 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
796 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
2066930d 797 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
db592a24 798 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
2066930d 799 else
db592a24 800 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
2066930d
BS		 801 }
802
db592a24
GL		 803 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
804 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
2066930d 805 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
db592a24 806 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
2066930d 807 else
db592a24 808 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
2066930d
BS		 809 }
810
db592a24
GL		 811 cfg.flags = common_flags;
812 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
813 if (ret < 0 && ret != -ENOIOCTLCMD) {
814 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
815 common_flags, ret);
2066930d 816 return ret;
db592a24 817 }
2066930d 818
db592a24 819 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
d86097e1 820 csicr1 |= CSICR1_REDGE;
db592a24 821 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2066930d 822 csicr1 |= CSICR1_SOF_POL;
db592a24 823 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2066930d
BS		 824 csicr1 |= CSICR1_HSYNC_POL;
825 if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
826 csicr1 |= CSICR1_SWAP16_EN;
827 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
828 csicr1 |= CSICR1_EXT_VSYNC;
829 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
830 csicr1 |= CSICR1_CCIR_EN;
831 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
832 csicr1 |= CSICR1_CCIR_MODE;
833 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
834 csicr1 |= CSICR1_GCLK_MODE;
835 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
836 csicr1 |= CSICR1_INV_DATA;
837 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
838 csicr1 |= CSICR1_PACK_DIR;
839
840 pcdev->csicr1 = csicr1;
841
842 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
843 icd->current_fmt->host_fmt);
844 if (bytesperline < 0)
845 return bytesperline;
846
847 if (mx27_camera_emma(pcdev)) {
848 ret = mx27_camera_emma_prp_reset(pcdev);
849 if (ret)
850 return ret;
851
852 if (pcdev->discard_buffer)
853 dma_free_coherent(ici->v4l2_dev.dev,
854 pcdev->discard_size, pcdev->discard_buffer,
855 pcdev->discard_buffer_dma);
856
857 /*
858 * I didn't manage to properly enable/disable the prp
859 * on a per frame basis during running transfers,
860 * thus we allocate a buffer here and use it to
861 * discard frames when no buffer is available.
862 * Feel free to work on this ;)
863 */
864 pcdev->discard_size = icd->user_height * bytesperline;
865 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
866 pcdev->discard_size, &pcdev->discard_buffer_dma,
867 GFP_KERNEL);
868 if (!pcdev->discard_buffer)
869 return -ENOMEM;
870
871 mx27_camera_emma_buf_init(icd, bytesperline);
872 } else if (cpu_is_mx25()) {
873 writel((bytesperline * icd->user_height) >> 2,
874 pcdev->base_csi + CSIRXCNT);
875 writel((bytesperline << 16) | icd->user_height,
876 pcdev->base_csi + CSIIMAG_PARA);
877 }
878
879 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
880
881 return 0;
882}
883
884static int mx2_camera_set_crop(struct soc_camera_device *icd,
885 struct v4l2_crop *a)
886{
887 struct v4l2_rect *rect = &a->c;
888 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
889 struct v4l2_mbus_framefmt mf;
890 int ret;
891
892 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
893 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
894
895 ret = v4l2_subdev_call(sd, video, s_crop, a);
896 if (ret < 0)
897 return ret;
898
899 /* The capture device might have changed its output */
900 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
901 if (ret < 0)
902 return ret;
903
7dfff953 904 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
2066930d
BS		 905 mf.width, mf.height);
906
907 icd->user_width = mf.width;
908 icd->user_height = mf.height;
909
910 return ret;
911}
912
913static int mx2_camera_set_fmt(struct soc_camera_device *icd,
914 struct v4l2_format *f)
915{
2066930d
BS		 916 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
917 const struct soc_camera_format_xlate *xlate;
918 struct v4l2_pix_format *pix = &f->fmt.pix;
919 struct v4l2_mbus_framefmt mf;
920 int ret;
921
922 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
923 if (!xlate) {
7dfff953 924 dev_warn(icd->parent, "Format %x not found\n",
2066930d
BS		 925 pix->pixelformat);
926 return -EINVAL;
927 }
928
2066930d
BS		 929 mf.width = pix->width;
930 mf.height = pix->height;
931 mf.field = pix->field;
932 mf.colorspace = pix->colorspace;
933 mf.code = xlate->code;
934
935 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
936 if (ret < 0 && ret != -ENOIOCTLCMD)
937 return ret;
938
939 if (mf.code != xlate->code)
940 return -EINVAL;
941
942 pix->width = mf.width;
943 pix->height = mf.height;
944 pix->field = mf.field;
945 pix->colorspace = mf.colorspace;
946 icd->current_fmt = xlate;
947
948 return 0;
949}
950
951static int mx2_camera_try_fmt(struct soc_camera_device *icd,
952 struct v4l2_format *f)
953{
2066930d
BS		 954 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
955 const struct soc_camera_format_xlate *xlate;
956 struct v4l2_pix_format *pix = &f->fmt.pix;
957 struct v4l2_mbus_framefmt mf;
958 __u32 pixfmt = pix->pixelformat;
959 unsigned int width_limit;
960 int ret;
961
962 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
963 if (pixfmt && !xlate) {
7dfff953 964 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
2066930d
BS		 965 return -EINVAL;
966 }
967
968 /* FIXME: implement MX27 limits */
969
2066930d
BS		 970 /* limit to MX25 hardware capabilities */
971 if (cpu_is_mx25()) {
972 if (xlate->host_fmt->bits_per_sample <= 8)
973 width_limit = 0xffff * 4;
974 else
975 width_limit = 0xffff * 2;
976 /* CSIIMAG_PARA limit */
977 if (pix->width > width_limit)
978 pix->width = width_limit;
979 if (pix->height > 0xffff)
980 pix->height = 0xffff;
981
982 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
983 xlate->host_fmt);
984 if (pix->bytesperline < 0)
985 return pix->bytesperline;
986 pix->sizeimage = pix->height * pix->bytesperline;
28281a71
GL		 987 /* Check against the CSIRXCNT limit */
988 if (pix->sizeimage > 4 * 0x3ffff) {
989 /* Adjust geometry, preserve aspect ratio */
990 unsigned int new_height = int_sqrt(4 * 0x3ffff *
991 pix->height / pix->bytesperline);
992 pix->width = new_height * pix->width / pix->height;
993 pix->height = new_height;
994 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
995 xlate->host_fmt);
996 BUG_ON(pix->bytesperline < 0);
2066930d
BS		 997 }
998 }
999
1000 /* limit to sensor capabilities */
1001 mf.width = pix->width;
1002 mf.height = pix->height;
1003 mf.field = pix->field;
1004 mf.colorspace = pix->colorspace;
1005 mf.code = xlate->code;
1006
1007 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1008 if (ret < 0)
1009 return ret;
1010
1011 if (mf.field == V4L2_FIELD_ANY)
1012 mf.field = V4L2_FIELD_NONE;
1013 if (mf.field != V4L2_FIELD_NONE) {
7dfff953 1014 dev_err(icd->parent, "Field type %d unsupported.\n",
2066930d
BS		 1015 mf.field);
1016 return -EINVAL;
1017 }
1018
1019 pix->width = mf.width;
1020 pix->height = mf.height;
1021 pix->field = mf.field;
1022 pix->colorspace = mf.colorspace;
1023
1024 return 0;
1025}
1026
1027static int mx2_camera_querycap(struct soc_camera_host *ici,
1028 struct v4l2_capability *cap)
1029{
1030 /* cap->name is set by the friendly caller:-> */
1031 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
2066930d
BS		 1032 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1033
1034 return 0;
1035}
1036
6b101926 1037static int mx2_camera_reqbufs(struct soc_camera_device *icd,
2066930d
BS		 1038 struct v4l2_requestbuffers *p)
1039{
1040 int i;
1041
1042 for (i = 0; i < p->count; i++) {
6b101926 1043 struct mx2_buffer *buf = container_of(icd->vb_vidq.bufs[i],
2066930d
BS		 1044 struct mx2_buffer, vb);
1045 INIT_LIST_HEAD(&buf->vb.queue);
1046 }
1047
1048 return 0;
1049}
1050
1051#ifdef CONFIG_MACH_MX27
1052static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
1053{
1054 struct videobuf_buffer *vb;
1055 struct mx2_buffer *buf;
1056 unsigned long flags;
1057 int ret;
1058
1059 spin_lock_irqsave(&pcdev->lock, flags);
1060
1061 if (!pcdev->active) {
1062 dev_err(pcdev->dev, "%s called with no active buffer!\n",
1063 __func__);
1064 goto out;
1065 }
1066
1067 vb = &pcdev->active->vb;
1068 buf = container_of(vb, struct mx2_buffer, vb);
1069 WARN_ON(list_empty(&vb->queue));
1070 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
1071 vb, vb->baddr, vb->bsize);
1072
1073 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
1074 list_del_init(&vb->queue);
1075 vb->state = state;
1076 do_gettimeofday(&vb->ts);
1077 vb->field_count++;
1078
1079 wake_up(&vb->done);
1080
1081 if (list_empty(&pcdev->capture)) {
1082 pcdev->active = NULL;
1083 goto out;
1084 }
1085
1086 pcdev->active = list_entry(pcdev->capture.next,
1087 struct mx2_buffer, vb.queue);
1088
1089 vb = &pcdev->active->vb;
1090 vb->state = VIDEOBUF_ACTIVE;
1091
1092 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
1093 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
1094
1095 if (ret) {
1096 vb->state = VIDEOBUF_ERROR;
1097 pcdev->active = NULL;
1098 wake_up(&vb->done);
1099 }
1100
1101out:
1102 spin_unlock_irqrestore(&pcdev->lock, flags);
1103}
1104
1105static void mx27_camera_dma_err_callback(int channel, void *data, int err)
1106{
1107 struct mx2_camera_dev *pcdev = data;
1108
1109 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
1110}
1111
1112static void mx27_camera_dma_callback(int channel, void *data)
1113{
1114 struct mx2_camera_dev *pcdev = data;
1115
1116 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
1117}
1118
1119#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */
1120
1121static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
1122 struct mx2_camera_dev *pcdev)
1123{
1124 int err;
1125
1126 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
1127 if (pcdev->dma < 0) {
1128 dev_err(&pdev->dev, "%s failed to request DMA channel\n",
1129 __func__);
1130 return pcdev->dma;
1131 }
1132
1133 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
1134 mx27_camera_dma_err_callback, pcdev);
1135 if (err) {
1136 dev_err(&pdev->dev, "%s failed to set DMA callback\n",
1137 __func__);
1138 goto err_out;
1139 }
1140
1141 err = imx_dma_config_channel(pcdev->dma,
1142 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
1143 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
1144 DMA_REQ_CSI_RX, 1);
1145 if (err) {
1146 dev_err(&pdev->dev, "%s failed to config DMA channel\n",
1147 __func__);
1148 goto err_out;
1149 }
1150
1151 imx_dma_config_burstlen(pcdev->dma, 64);
1152
1153 return 0;
1154
1155err_out:
1156 imx_dma_free(pcdev->dma);
1157
1158 return err;
1159}
1160#endif /* CONFIG_MACH_MX27 */
1161
1162static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1163{
6b101926 1164 struct soc_camera_device *icd = file->private_data;
2066930d 1165
6b101926 1166 return videobuf_poll_stream(file, &icd->vb_vidq, pt);
2066930d
BS		 1167}
1168
1169static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1170 .owner = THIS_MODULE,
1171 .add = mx2_camera_add_device,
1172 .remove = mx2_camera_remove_device,
1173 .set_fmt = mx2_camera_set_fmt,
1174 .set_crop = mx2_camera_set_crop,
1175 .try_fmt = mx2_camera_try_fmt,
1176 .init_videobuf = mx2_camera_init_videobuf,
1177 .reqbufs = mx2_camera_reqbufs,
1178 .poll = mx2_camera_poll,
1179 .querycap = mx2_camera_querycap,
1180 .set_bus_param = mx2_camera_set_bus_param,
1181};
1182
1183static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1184 int bufnum, int state)
1185{
1186 struct mx2_buffer *buf;
1187 struct videobuf_buffer *vb;
1188 unsigned long phys;
1189
1190 if (!list_empty(&pcdev->active_bufs)) {
1191 buf = list_entry(pcdev->active_bufs.next,
1192 struct mx2_buffer, vb.queue);
1193
1194 BUG_ON(buf->bufnum != bufnum);
1195
1196 vb = &buf->vb;
1197#ifdef DEBUG
1198 phys = videobuf_to_dma_contig(vb);
1199 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum)
1200 != phys) {
1201 dev_err(pcdev->dev, "%p != %p\n", phys,
1202 readl(pcdev->base_emma +
1203 PRP_DEST_RGB1_PTR +
1204 4 * bufnum));
1205 }
1206#endif
1207 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
1208 vb->baddr, vb->bsize);
1209
1210 list_del(&vb->queue);
1211 vb->state = state;
1212 do_gettimeofday(&vb->ts);
1213 vb->field_count++;
1214
1215 wake_up(&vb->done);
1216 }
1217
1218 if (list_empty(&pcdev->capture)) {
1219 writel(pcdev->discard_buffer_dma, pcdev->base_emma +
1220 PRP_DEST_RGB1_PTR + 4 * bufnum);
1221 return;
1222 }
1223
1224 buf = list_entry(pcdev->capture.next,
1225 struct mx2_buffer, vb.queue);
1226
cd9ebdbc 1227 buf->bufnum = !bufnum;
2066930d
BS		 1228
1229 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1230
1231 vb = &buf->vb;
1232 vb->state = VIDEOBUF_ACTIVE;
1233
1234 phys = videobuf_to_dma_contig(vb);
1235 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
1236}
1237
1238static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1239{
1240 struct mx2_camera_dev *pcdev = data;
1241 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1242 struct mx2_buffer *buf;
1243
1244 if (status & (1 << 7)) { /* overflow */
1245 u32 cntl;
1246 /*
1247 * We only disable channel 1 here since this is the only
1248 * enabled channel
1249 *
1250 * FIXME: the correct DMA overflow handling should be resetting
1251 * the buffer, returning an error frame, and continuing with
1252 * the next one.
1253 */
1254 cntl = readl(pcdev->base_emma + PRP_CNTL);
1255 writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL);
1256 writel(cntl, pcdev->base_emma + PRP_CNTL);
1257 }
1258 if ((status & (3 << 5)) == (3 << 5)
1259 && !list_empty(&pcdev->active_bufs)) {
1260 /*
1261 * Both buffers have triggered, process the one we're expecting
1262 * to first
1263 */
1264 buf = list_entry(pcdev->active_bufs.next,
1265 struct mx2_buffer, vb.queue);
1266 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
1267 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
1268 }
1269 if (status & (1 << 6))
1270 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
1271 if (status & (1 << 5))
1272 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
1273
1274 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1275
1276 return IRQ_HANDLED;
1277}
1278
1279static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1280{
1281 struct resource *res_emma = pcdev->res_emma;
1282 int err = 0;
1283
1284 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1285 MX2_CAM_DRV_NAME)) {
1286 err = -EBUSY;
1287 goto out;
1288 }
1289
1290 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1291 if (!pcdev->base_emma) {
1292 err = -ENOMEM;
1293 goto exit_release;
1294 }
1295
1296 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1297 MX2_CAM_DRV_NAME, pcdev);
1298 if (err) {
1299 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1300 goto exit_iounmap;
1301 }
1302
1303 pcdev->clk_emma = clk_get(NULL, "emma");
1304 if (IS_ERR(pcdev->clk_emma)) {
1305 err = PTR_ERR(pcdev->clk_emma);
1306 goto exit_free_irq;
1307 }
1308
1309 clk_enable(pcdev->clk_emma);
1310
1311 err = mx27_camera_emma_prp_reset(pcdev);
1312 if (err)
1313 goto exit_clk_emma_put;
1314
1315 return err;
1316
1317exit_clk_emma_put:
1318 clk_disable(pcdev->clk_emma);
1319 clk_put(pcdev->clk_emma);
1320exit_free_irq:
1321 free_irq(pcdev->irq_emma, pcdev);
1322exit_iounmap:
1323 iounmap(pcdev->base_emma);
1324exit_release:
1325 release_mem_region(res_emma->start, resource_size(res_emma));
1326out:
1327 return err;
1328}
1329
1330static int __devinit mx2_camera_probe(struct platform_device *pdev)
1331{
1332 struct mx2_camera_dev *pcdev;
1333 struct resource *res_csi, *res_emma;
1334 void __iomem *base_csi;
1335 int irq_csi, irq_emma;
1336 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
1337 : mx27_camera_irq;
1338 int err = 0;
1339
1340 dev_dbg(&pdev->dev, "initialising\n");
1341
1342 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1343 irq_csi = platform_get_irq(pdev, 0);
1344 if (res_csi == NULL || irq_csi < 0) {
1345 dev_err(&pdev->dev, "Missing platform resources data\n");
1346 err = -ENODEV;
1347 goto exit;
1348 }
1349
1350 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1351 if (!pcdev) {
1352 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1353 err = -ENOMEM;
1354 goto exit;
1355 }
1356
1357 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1358 if (IS_ERR(pcdev->clk_csi)) {
1359 err = PTR_ERR(pcdev->clk_csi);
1360 goto exit_kfree;
1361 }
1362
1363 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
1364 clk_get_rate(pcdev->clk_csi));
1365
1366 /* Initialize DMA */
1367#ifdef CONFIG_MACH_MX27
1368 if (cpu_is_mx27()) {
1369 err = mx27_camera_dma_init(pdev, pcdev);
1370 if (err)
1371 goto exit_clk_put;
1372 }
1373#endif /* CONFIG_MACH_MX27 */
1374
1375 pcdev->res_csi = res_csi;
1376 pcdev->pdata = pdev->dev.platform_data;
1377 if (pcdev->pdata) {
1378 long rate;
1379
1380 pcdev->platform_flags = pcdev->pdata->flags;
1381
1382 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1383 if (rate <= 0) {
1384 err = -ENODEV;
1385 goto exit_dma_free;
1386 }
1387 err = clk_set_rate(pcdev->clk_csi, rate);
1388 if (err < 0)
1389 goto exit_dma_free;
1390 }
1391
1392 INIT_LIST_HEAD(&pcdev->capture);
1393 INIT_LIST_HEAD(&pcdev->active_bufs);
1394 spin_lock_init(&pcdev->lock);
1395
1396 /*
1397 * Request the regions.
1398 */
1399 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1400 MX2_CAM_DRV_NAME)) {
1401 err = -EBUSY;
1402 goto exit_dma_free;
1403 }
1404
1405 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1406 if (!base_csi) {
1407 err = -ENOMEM;
1408 goto exit_release;
1409 }
1410 pcdev->irq_csi = irq_csi;
1411 pcdev->base_csi = base_csi;
1412 pcdev->base_dma = res_csi->start;
1413 pcdev->dev = &pdev->dev;
1414
1415 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
1416 MX2_CAM_DRV_NAME, pcdev);
1417 if (err) {
1418 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1419 goto exit_iounmap;
1420 }
1421
1422 if (cpu_is_mx27()) {
1423 /* EMMA support */
1424 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1425 irq_emma = platform_get_irq(pdev, 1);
1426
1427 if (res_emma && irq_emma >= 0) {
1428 dev_info(&pdev->dev, "Using EMMA\n");
1429 pcdev->use_emma = 1;
1430 pcdev->res_emma = res_emma;
1431 pcdev->irq_emma = irq_emma;
1432 if (mx27_camera_emma_init(pcdev))
1433 goto exit_free_irq;
1434 }
1435 }
1436
1437 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1438 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1439 pcdev->soc_host.priv = pcdev;
1440 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1441 pcdev->soc_host.nr = pdev->id;
1442 err = soc_camera_host_register(&pcdev->soc_host);
1443 if (err)
1444 goto exit_free_emma;
1445
45f4d4e8
MG		 1446 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1447 clk_get_rate(pcdev->clk_csi));
1448
2066930d
BS		 1449 return 0;
1450
1451exit_free_emma:
1452 if (mx27_camera_emma(pcdev)) {
1453 free_irq(pcdev->irq_emma, pcdev);
1454 clk_disable(pcdev->clk_emma);
1455 clk_put(pcdev->clk_emma);
1456 iounmap(pcdev->base_emma);
1457 release_mem_region(res_emma->start, resource_size(res_emma));
1458 }
1459exit_free_irq:
1460 free_irq(pcdev->irq_csi, pcdev);
1461exit_iounmap:
1462 iounmap(base_csi);
1463exit_release:
1464 release_mem_region(res_csi->start, resource_size(res_csi));
1465exit_dma_free:
1466#ifdef CONFIG_MACH_MX27
1467 if (cpu_is_mx27())
1468 imx_dma_free(pcdev->dma);
1469exit_clk_put:
1470 clk_put(pcdev->clk_csi);
1471#endif /* CONFIG_MACH_MX27 */
1472exit_kfree:
1473 kfree(pcdev);
1474exit:
1475 return err;
1476}
1477
1478static int __devexit mx2_camera_remove(struct platform_device *pdev)
1479{
1480 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1481 struct mx2_camera_dev *pcdev = container_of(soc_host,
1482 struct mx2_camera_dev, soc_host);
1483 struct resource *res;
1484
1485 clk_put(pcdev->clk_csi);
1486#ifdef CONFIG_MACH_MX27
1487 if (cpu_is_mx27())
1488 imx_dma_free(pcdev->dma);
1489#endif /* CONFIG_MACH_MX27 */
1490 free_irq(pcdev->irq_csi, pcdev);
1491 if (mx27_camera_emma(pcdev))
1492 free_irq(pcdev->irq_emma, pcdev);
1493
1494 soc_camera_host_unregister(&pcdev->soc_host);
1495
1496 iounmap(pcdev->base_csi);
1497
1498 if (mx27_camera_emma(pcdev)) {
1499 clk_disable(pcdev->clk_emma);
1500 clk_put(pcdev->clk_emma);
1501 iounmap(pcdev->base_emma);
1502 res = pcdev->res_emma;
1503 release_mem_region(res->start, resource_size(res));
1504 }
1505
1506 res = pcdev->res_csi;
1507 release_mem_region(res->start, resource_size(res));
1508
1509 kfree(pcdev);
1510
1511 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1512
1513 return 0;
1514}
1515
1516static struct platform_driver mx2_camera_driver = {
1517 .driver = {
1518 .name = MX2_CAM_DRV_NAME,
1519 },
1520 .remove = __devexit_p(mx2_camera_remove),
1521};
1522
1523
1524static int __init mx2_camera_init(void)
1525{
1526 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1527}
1528
1529static void __exit mx2_camera_exit(void)
1530{
1531 return platform_driver_unregister(&mx2_camera_driver);
1532}
1533
1534module_init(mx2_camera_init);
1535module_exit(mx2_camera_exit);
1536
1537MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1538MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1539MODULE_LICENSE("GPL");
64dc3c1a 1540MODULE_VERSION(MX2_CAM_VERSION);
Linux kernel - Deliverables
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