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[media] v4l: soc-camera: switch to .unlocked_ioctl
[deliverable/linux.git] / drivers / media / video / mx3_camera.c
CommitLineData
4f67130a
GL		 1/*
2 * V4L2 Driver for i.MX3x camera host
3 *
4 * Copyright (C) 2008
5 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/version.h>
15#include <linux/videodev2.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
f39c1ab3 20#include <linux/sched.h>
4f67130a
GL		 21
22#include <media/v4l2-common.h>
23#include <media/v4l2-dev.h>
24#include <media/videobuf-dma-contig.h>
25#include <media/soc_camera.h>
760697be 26#include <media/soc_mediabus.h>
4f67130a
GL		 27
28#include <mach/ipu.h>
29#include <mach/mx3_camera.h>
a8de6635 30#include <mach/dma.h>
4f67130a
GL		 31
32#define MX3_CAM_DRV_NAME "mx3-camera"
33
34/* CMOS Sensor Interface Registers */
35#define CSI_REG_START 0x60
36
37#define CSI_SENS_CONF (0x60 - CSI_REG_START)
38#define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
39#define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
40#define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
41#define CSI_TST_CTRL (0x70 - CSI_REG_START)
42#define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
43#define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
44#define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
45#define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
46#define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
47
48#define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
49#define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
50#define CSI_SENS_CONF_DATA_POL_SHIFT 2
51#define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
52#define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
53#define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
54#define CSI_SENS_CONF_DATA_FMT_SHIFT 8
55#define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
56#define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
57#define CSI_SENS_CONF_DIVRATIO_SHIFT 16
58
59#define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
60#define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
61#define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
62
63#define MAX_VIDEO_MEM 16
64
65struct mx3_camera_buffer {
66 /* common v4l buffer stuff -- must be first */
67 struct videobuf_buffer vb;
760697be 68 enum v4l2_mbus_pixelcode code;
4f67130a
GL		 69
70 /* One descriptot per scatterlist (per frame) */
71 struct dma_async_tx_descriptor *txd;
72
73 /* We have to "build" a scatterlist ourselves - one element per frame */
74 struct scatterlist sg;
75};
76
77/**
78 * struct mx3_camera_dev - i.MX3x camera (CSI) object
79 * @dev: camera device, to which the coherent buffer is attached
80 * @icd: currently attached camera sensor
81 * @clk: pointer to clock
82 * @base: remapped register base address
83 * @pdata: platform data
84 * @platform_flags: platform flags
85 * @mclk: master clock frequency in Hz
86 * @capture: list of capture videobuffers
87 * @lock: protects video buffer lists
88 * @active: active video buffer
89 * @idmac_channel: array of pointers to IPU DMAC DMA channels
90 * @soc_host: embedded soc_host object
91 */
92struct mx3_camera_dev {
4f67130a
GL		 93 /*
94 * i.MX3x is only supposed to handle one camera on its Camera Sensor
95 * Interface. If anyone ever builds hardware to enable more than one
96 * camera _simultaneously_, they will have to modify this driver too
97 */
98 struct soc_camera_device *icd;
99 struct clk *clk;
100
101 void __iomem *base;
102
103 struct mx3_camera_pdata *pdata;
104
105 unsigned long platform_flags;
106 unsigned long mclk;
107
108 struct list_head capture;
109 spinlock_t lock; /* Protects video buffer lists */
110 struct mx3_camera_buffer *active;
111
112 /* IDMAC / dmaengine interface */
113 struct idmac_channel *idmac_channel[1]; /* We need one channel */
114
115 struct soc_camera_host soc_host;
116};
117
118struct dma_chan_request {
119 struct mx3_camera_dev *mx3_cam;
120 enum ipu_channel id;
121};
122
4f67130a
GL		 123static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg)
124{
125 return __raw_readl(mx3->base + reg);
126}
127
128static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg)
129{
130 __raw_writel(value, mx3->base + reg);
131}
132
133/* Called from the IPU IDMAC ISR */
134static void mx3_cam_dma_done(void *arg)
135{
136 struct idmac_tx_desc *desc = to_tx_desc(arg);
137 struct dma_chan *chan = desc->txd.chan;
138 struct idmac_channel *ichannel = to_idmac_chan(chan);
139 struct mx3_camera_dev *mx3_cam = ichannel->client;
140 struct videobuf_buffer *vb;
141
142 dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
143 desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0);
144
145 spin_lock(&mx3_cam->lock);
146 if (mx3_cam->active) {
147 vb = &mx3_cam->active->vb;
148
149 list_del_init(&vb->queue);
150 vb->state = VIDEOBUF_DONE;
151 do_gettimeofday(&vb->ts);
152 vb->field_count++;
153 wake_up(&vb->done);
154 }
155
156 if (list_empty(&mx3_cam->capture)) {
157 mx3_cam->active = NULL;
158 spin_unlock(&mx3_cam->lock);
159
160 /*
161 * stop capture - without further buffers IPU_CHA_BUF0_RDY will
162 * not get updated
163 */
164 return;
165 }
166
167 mx3_cam->active = list_entry(mx3_cam->capture.next,
168 struct mx3_camera_buffer, vb.queue);
169 mx3_cam->active->vb.state = VIDEOBUF_ACTIVE;
170 spin_unlock(&mx3_cam->lock);
171}
172
173static void free_buffer(struct videobuf_queue *vq, struct mx3_camera_buffer *buf)
174{
175 struct soc_camera_device *icd = vq->priv_data;
176 struct videobuf_buffer *vb = &buf->vb;
177 struct dma_async_tx_descriptor *txd = buf->txd;
178 struct idmac_channel *ichan;
179
180 BUG_ON(in_interrupt());
181
0166b743 182 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
4f67130a
GL		 183 vb, vb->baddr, vb->bsize);
184
185 /*
186 * This waits until this buffer is out of danger, i.e., until it is no
187 * longer in STATE_QUEUED or STATE_ACTIVE
188 */
0e0809a5 189 videobuf_waiton(vq, vb, 0, 0);
4f67130a
GL		 190 if (txd) {
191 ichan = to_idmac_chan(txd->chan);
192 async_tx_ack(txd);
193 }
194 videobuf_dma_contig_free(vq, vb);
195 buf->txd = NULL;
196
197 vb->state = VIDEOBUF_NEEDS_INIT;
198}
199
200/*
201 * Videobuf operations
202 */
203
204/*
205 * Calculate the __buffer__ (not data) size and number of buffers.
206 * Called with .vb_lock held
207 */
208static int mx3_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
209 unsigned int *size)
210{
211 struct soc_camera_device *icd = vq->priv_data;
212 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
213 struct mx3_camera_dev *mx3_cam = ici->priv;
760697be
GL		 214 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
215 icd->current_fmt->host_fmt);
216
217 if (bytes_per_line < 0)
218 return bytes_per_line;
4f67130a
GL		 219
220 if (!mx3_cam->idmac_channel[0])
221 return -EINVAL;
222
760697be 223 *size = bytes_per_line * icd->user_height;
4f67130a
GL		 224
225 if (!*count)
226 *count = 32;
227
228 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
229 *count = MAX_VIDEO_MEM * 1024 * 1024 / *size;
230
231 return 0;
232}
233
234/* Called with .vb_lock held */
235static int mx3_videobuf_prepare(struct videobuf_queue *vq,
236 struct videobuf_buffer *vb, enum v4l2_field field)
237{
238 struct soc_camera_device *icd = vq->priv_data;
239 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
240 struct mx3_camera_dev *mx3_cam = ici->priv;
241 struct mx3_camera_buffer *buf =
242 container_of(vb, struct mx3_camera_buffer, vb);
760697be 243 size_t new_size;
4f67130a 244 int ret;
760697be
GL		 245 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
246 icd->current_fmt->host_fmt);
247
248 if (bytes_per_line < 0)
249 return bytes_per_line;
250
251 new_size = bytes_per_line * icd->user_height;
4f67130a
GL		 252
253 /*
254 * I think, in buf_prepare you only have to protect global data,
255 * the actual buffer is yours
256 */
257
760697be 258 if (buf->code != icd->current_fmt->code ||
6a6c8786
GL		 259 vb->width != icd->user_width ||
260 vb->height != icd->user_height ||
4f67130a 261 vb->field != field) {
760697be 262 buf->code = icd->current_fmt->code;
6a6c8786
GL		 263 vb->width = icd->user_width;
264 vb->height = icd->user_height;
4f67130a
GL		 265 vb->field = field;
266 if (vb->state != VIDEOBUF_NEEDS_INIT)
267 free_buffer(vq, buf);
268 }
269
270 if (vb->baddr && vb->bsize < new_size) {
271 /* User provided buffer, but it is too small */
272 ret = -ENOMEM;
273 goto out;
274 }
275
276 if (vb->state == VIDEOBUF_NEEDS_INIT) {
277 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
278 struct scatterlist *sg = &buf->sg;
279
280 /*
281 * The total size of video-buffers that will be allocated / mapped.
282 * *size that we calculated in videobuf_setup gets assigned to
283 * vb->bsize, and now we use the same calculation to get vb->size.
284 */
285 vb->size = new_size;
286
287 /* This actually (allocates and) maps buffers */
288 ret = videobuf_iolock(vq, vb, NULL);
289 if (ret)
290 goto fail;
291
292 /*
293 * We will have to configure the IDMAC channel. It has two slots
294 * for DMA buffers, we shall enter the first two buffers there,
295 * and then submit new buffers in DMA-ready interrupts
296 */
297 sg_init_table(sg, 1);
298 sg_dma_address(sg) = videobuf_to_dma_contig(vb);
299 sg_dma_len(sg) = vb->size;
300
301 buf->txd = ichan->dma_chan.device->device_prep_slave_sg(
302 &ichan->dma_chan, sg, 1, DMA_FROM_DEVICE,
303 DMA_PREP_INTERRUPT);
304 if (!buf->txd) {
305 ret = -EIO;
306 goto fail;
307 }
308
309 buf->txd->callback_param = buf->txd;
310 buf->txd->callback = mx3_cam_dma_done;
311
312 vb->state = VIDEOBUF_PREPARED;
313 }
314
315 return 0;
316
317fail:
318 free_buffer(vq, buf);
319out:
320 return ret;
321}
322
323static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc)
324{
325 /* Add more formats as need arises and test possibilities appear... */
326 switch (fourcc) {
327 case V4L2_PIX_FMT_RGB565:
328 return IPU_PIX_FMT_RGB565;
329 case V4L2_PIX_FMT_RGB24:
330 return IPU_PIX_FMT_RGB24;
331 case V4L2_PIX_FMT_RGB332:
332 return IPU_PIX_FMT_RGB332;
333 case V4L2_PIX_FMT_YUV422P:
334 return IPU_PIX_FMT_YVU422P;
335 default:
336 return IPU_PIX_FMT_GENERIC;
337 }
338}
339
2dd54a54
GL		 340/*
341 * Called with .vb_lock mutex held and
342 * under spinlock_irqsave(&mx3_cam->lock, ...)
343 */
4f67130a
GL		 344static void mx3_videobuf_queue(struct videobuf_queue *vq,
345 struct videobuf_buffer *vb)
346{
347 struct soc_camera_device *icd = vq->priv_data;
348 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
349 struct mx3_camera_dev *mx3_cam = ici->priv;
350 struct mx3_camera_buffer *buf =
351 container_of(vb, struct mx3_camera_buffer, vb);
352 struct dma_async_tx_descriptor *txd = buf->txd;
353 struct idmac_channel *ichan = to_idmac_chan(txd->chan);
354 struct idmac_video_param *video = &ichan->params.video;
4f67130a 355 dma_cookie_t cookie;
760697be 356 u32 fourcc = icd->current_fmt->host_fmt->fourcc;
2dd54a54
GL		 357
358 BUG_ON(!irqs_disabled());
4f67130a
GL		 359
360 /* This is the configuration of one sg-element */
760697be 361 video->out_pixel_fmt = fourcc_to_ipu_pix(fourcc);
6a6c8786
GL		 362 video->out_width = icd->user_width;
363 video->out_height = icd->user_height;
364 video->out_stride = icd->user_width;
4f67130a
GL		 365
366#ifdef DEBUG
367 /* helps to see what DMA actually has written */
368 memset((void *)vb->baddr, 0xaa, vb->bsize);
369#endif
370
4f67130a
GL		 371 list_add_tail(&vb->queue, &mx3_cam->capture);
372
373 if (!mx3_cam->active) {
374 mx3_cam->active = buf;
375 vb->state = VIDEOBUF_ACTIVE;
376 } else {
377 vb->state = VIDEOBUF_QUEUED;
378 }
379
2dd54a54 380 spin_unlock_irq(&mx3_cam->lock);
4f67130a
GL		 381
382 cookie = txd->tx_submit(txd);
0166b743
GL		 383 dev_dbg(icd->dev.parent, "Submitted cookie %d DMA 0x%08x\n",
384 cookie, sg_dma_address(&buf->sg));
2dd54a54
GL		 385
386 spin_lock_irq(&mx3_cam->lock);
387
4f67130a
GL		 388 if (cookie >= 0)
389 return;
390
391 /* Submit error */
392 vb->state = VIDEOBUF_PREPARED;
393
4f67130a
GL		 394 list_del_init(&vb->queue);
395
396 if (mx3_cam->active == buf)
397 mx3_cam->active = NULL;
4f67130a
GL		 398}
399
400/* Called with .vb_lock held */
401static void mx3_videobuf_release(struct videobuf_queue *vq,
402 struct videobuf_buffer *vb)
403{
404 struct soc_camera_device *icd = vq->priv_data;
405 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
406 struct mx3_camera_dev *mx3_cam = ici->priv;
407 struct mx3_camera_buffer *buf =
408 container_of(vb, struct mx3_camera_buffer, vb);
409 unsigned long flags;
410
0166b743
GL		 411 dev_dbg(icd->dev.parent,
412 "Release%s DMA 0x%08x (state %d), queue %sempty\n",
4f67130a 413 mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg),
0166b743 414 vb->state, list_empty(&vb->queue) ? "" : "not ");
4f67130a
GL		 415 spin_lock_irqsave(&mx3_cam->lock, flags);
416 if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) &&
417 !list_empty(&vb->queue)) {
418 vb->state = VIDEOBUF_ERROR;
419
420 list_del_init(&vb->queue);
421 if (mx3_cam->active == buf)
422 mx3_cam->active = NULL;
423 }
424 spin_unlock_irqrestore(&mx3_cam->lock, flags);
425 free_buffer(vq, buf);
426}
427
428static struct videobuf_queue_ops mx3_videobuf_ops = {
429 .buf_setup = mx3_videobuf_setup,
430 .buf_prepare = mx3_videobuf_prepare,
431 .buf_queue = mx3_videobuf_queue,
432 .buf_release = mx3_videobuf_release,
433};
434
435static void mx3_camera_init_videobuf(struct videobuf_queue *q,
436 struct soc_camera_device *icd)
437{
438 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
439 struct mx3_camera_dev *mx3_cam = ici->priv;
440
979ea1dd 441 videobuf_queue_dma_contig_init(q, &mx3_videobuf_ops, icd->dev.parent,
4f67130a
GL		 442 &mx3_cam->lock,
443 V4L2_BUF_TYPE_VIDEO_CAPTURE,
444 V4L2_FIELD_NONE,
e3cfd447 445 sizeof(struct mx3_camera_buffer), icd,
b6a633c1 446 &icd->video_lock);
4f67130a
GL		 447}
448
449/* First part of ipu_csi_init_interface() */
450static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam,
451 struct soc_camera_device *icd)
452{
453 u32 conf;
454 long rate;
455
456 /* Set default size: ipu_csi_set_window_size() */
457 csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE);
458 /* ...and position to 0:0: ipu_csi_set_window_pos() */
459 conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
460 csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL);
461
462 /* We use only gated clock synchronisation mode so far */
463 conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT;
464
465 /* Set generic data, platform-biggest bus-width */
466 conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
467
468 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
469 conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
470 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
471 conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
472 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
473 conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
474 else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
475 conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
476
477 if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC)
478 conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
479 if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC)
480 conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT;
481 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
482 conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
483 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
484 conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
485 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
486 conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
487 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
488 conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
489
490 /* ipu_csi_init_interface() */
491 csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
492
493 clk_enable(mx3_cam->clk);
494 rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
0166b743 495 dev_dbg(icd->dev.parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
4f67130a
GL		 496 if (rate)
497 clk_set_rate(mx3_cam->clk, rate);
498}
499
500/* Called with .video_lock held */
501static int mx3_camera_add_device(struct soc_camera_device *icd)
502{
503 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
504 struct mx3_camera_dev *mx3_cam = ici->priv;
4f67130a 505
979ea1dd
GL		 506 if (mx3_cam->icd)
507 return -EBUSY;
4f67130a
GL		 508
509 mx3_camera_activate(mx3_cam, icd);
4f67130a
GL		 510
511 mx3_cam->icd = icd;
512
0166b743 513 dev_info(icd->dev.parent, "MX3 Camera driver attached to camera %d\n",
40e2e092
GL		 514 icd->devnum);
515
516 return 0;
4f67130a
GL		 517}
518
519/* Called with .video_lock held */
520static void mx3_camera_remove_device(struct soc_camera_device *icd)
521{
522 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
523 struct mx3_camera_dev *mx3_cam = ici->priv;
524 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
525
526 BUG_ON(icd != mx3_cam->icd);
527
528 if (*ichan) {
529 dma_release_channel(&(*ichan)->dma_chan);
530 *ichan = NULL;
531 }
532
4f67130a
GL		 533 clk_disable(mx3_cam->clk);
534
535 mx3_cam->icd = NULL;
536
0166b743 537 dev_info(icd->dev.parent, "MX3 Camera driver detached from camera %d\n",
4f67130a
GL		 538 icd->devnum);
539}
540
541static bool channel_change_requested(struct soc_camera_device *icd,
09e231b3 542 struct v4l2_rect *rect)
4f67130a
GL		 543{
544 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
545 struct mx3_camera_dev *mx3_cam = ici->priv;
546 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
547
09e231b3 548 /* Do buffers have to be re-allocated or channel re-configured? */
a0705b07 549 return ichan && rect->width * rect->height >
6a6c8786 550 icd->user_width * icd->user_height;
4f67130a
GL		 551}
552
553static int test_platform_param(struct mx3_camera_dev *mx3_cam,
554 unsigned char buswidth, unsigned long *flags)
555{
556 /*
557 * Platform specified synchronization and pixel clock polarities are
558 * only a recommendation and are only used during probing. MX3x
559 * camera interface only works in master mode, i.e., uses HSYNC and
560 * VSYNC signals from the sensor
561 */
562 *flags = SOCAM_MASTER |
563 SOCAM_HSYNC_ACTIVE_HIGH |
564 SOCAM_HSYNC_ACTIVE_LOW |
565 SOCAM_VSYNC_ACTIVE_HIGH |
566 SOCAM_VSYNC_ACTIVE_LOW |
567 SOCAM_PCLK_SAMPLE_RISING |
568 SOCAM_PCLK_SAMPLE_FALLING |
569 SOCAM_DATA_ACTIVE_HIGH |
570 SOCAM_DATA_ACTIVE_LOW;
571
5d28d525
GL		 572 /*
573 * If requested data width is supported by the platform, use it or any
574 * possible lower value - i.MX31 is smart enough to schift bits
575 */
760697be
GL		 576 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
577 *flags |= SOCAM_DATAWIDTH_15 | SOCAM_DATAWIDTH_10 |
578 SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4;
579 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
580 *flags |= SOCAM_DATAWIDTH_10 | SOCAM_DATAWIDTH_8 |
581 SOCAM_DATAWIDTH_4;
582 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
583 *flags |= SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4;
584 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)
585 *flags |= SOCAM_DATAWIDTH_4;
586
4f67130a
GL		 587 switch (buswidth) {
588 case 15:
760697be 589 if (!(*flags & SOCAM_DATAWIDTH_15))
4f67130a 590 return -EINVAL;
4f67130a
GL		 591 break;
592 case 10:
760697be 593 if (!(*flags & SOCAM_DATAWIDTH_10))
4f67130a 594 return -EINVAL;
4f67130a
GL		 595 break;
596 case 8:
760697be 597 if (!(*flags & SOCAM_DATAWIDTH_8))
4f67130a 598 return -EINVAL;
4f67130a
GL		 599 break;
600 case 4:
760697be 601 if (!(*flags & SOCAM_DATAWIDTH_4))
4f67130a 602 return -EINVAL;
4f67130a
GL		 603 break;
604 default:
6a6c8786
GL		 605 dev_warn(mx3_cam->soc_host.v4l2_dev.dev,
606 "Unsupported bus width %d\n", buswidth);
4f67130a
GL		 607 return -EINVAL;
608 }
609
610 return 0;
611}
612
613static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
614 const unsigned int depth)
615{
616 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
617 struct mx3_camera_dev *mx3_cam = ici->priv;
618 unsigned long bus_flags, camera_flags;
619 int ret = test_platform_param(mx3_cam, depth, &bus_flags);
620
6a6c8786 621 dev_dbg(icd->dev.parent, "request bus width %d bit: %d\n", depth, ret);
4f67130a
GL		 622
623 if (ret < 0)
624 return ret;
625
626 camera_flags = icd->ops->query_bus_param(icd);
627
628 ret = soc_camera_bus_param_compatible(camera_flags, bus_flags);
629 if (ret < 0)
0166b743
GL		 630 dev_warn(icd->dev.parent,
631 "Flags incompatible: camera %lx, host %lx\n",
4f67130a
GL		 632 camera_flags, bus_flags);
633
634 return ret;
635}
636
637static bool chan_filter(struct dma_chan *chan, void *arg)
638{
639 struct dma_chan_request *rq = arg;
640 struct mx3_camera_pdata *pdata;
641
a8de6635
SH		 642 if (!imx_dma_is_ipu(chan))
643 return false;
644
4f67130a
GL		 645 if (!rq)
646 return false;
647
979ea1dd 648 pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data;
4f67130a
GL		 649
650 return rq->id == chan->chan_id &&
651 pdata->dma_dev == chan->device->dev;
652}
653
760697be 654static const struct soc_mbus_pixelfmt mx3_camera_formats[] = {
4f67130a 655 {
760697be
GL		 656 .fourcc = V4L2_PIX_FMT_SBGGR8,
657 .name = "Bayer BGGR (sRGB) 8 bit",
658 .bits_per_sample = 8,
659 .packing = SOC_MBUS_PACKING_NONE,
660 .order = SOC_MBUS_ORDER_LE,
4f67130a 661 }, {
760697be
GL		 662 .fourcc = V4L2_PIX_FMT_GREY,
663 .name = "Monochrome 8 bit",
664 .bits_per_sample = 8,
665 .packing = SOC_MBUS_PACKING_NONE,
666 .order = SOC_MBUS_ORDER_LE,
4f67130a
GL		 667 },
668};
669
760697be
GL		 670/* This will be corrected as we get more formats */
671static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
4f67130a 672{
760697be
GL		 673 return fmt->packing == SOC_MBUS_PACKING_NONE ||
674 (fmt->bits_per_sample == 8 &&
675 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
676 (fmt->bits_per_sample > 8 &&
677 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
4f67130a
GL		 678}
679
3805f201 680static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
4f67130a
GL		 681 struct soc_camera_format_xlate *xlate)
682{
760697be
GL		 683 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
684 struct device *dev = icd->dev.parent;
685 int formats = 0, ret;
686 enum v4l2_mbus_pixelcode code;
687 const struct soc_mbus_pixelfmt *fmt;
4f67130a 688
760697be
GL		 689 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
690 if (ret < 0)
691 /* No more formats */
692 return 0;
4f67130a 693
760697be
GL		 694 fmt = soc_mbus_get_fmtdesc(code);
695 if (!fmt) {
696 dev_err(icd->dev.parent,
3805f201 697 "Invalid format code #%u: %d\n", idx, code);
4f67130a 698 return 0;
760697be 699 }
4f67130a 700
760697be
GL		 701 /* This also checks support for the requested bits-per-sample */
702 ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample);
4f67130a
GL		 703 if (ret < 0)
704 return 0;
705
760697be
GL		 706 switch (code) {
707 case V4L2_MBUS_FMT_SBGGR10_1X10:
4f67130a
GL		 708 formats++;
709 if (xlate) {
760697be
GL		 710 xlate->host_fmt = &mx3_camera_formats[0];
711 xlate->code = code;
4f67130a 712 xlate++;
760697be
GL		 713 dev_dbg(dev, "Providing format %s using code %d\n",
714 mx3_camera_formats[0].name, code);
4f67130a 715 }
760697be
GL		 716 break;
717 case V4L2_MBUS_FMT_Y10_1X10:
4f67130a
GL		 718 formats++;
719 if (xlate) {
760697be
GL		 720 xlate->host_fmt = &mx3_camera_formats[1];
721 xlate->code = code;
4f67130a 722 xlate++;
760697be
GL		 723 dev_dbg(dev, "Providing format %s using code %d\n",
724 mx3_camera_formats[1].name, code);
4f67130a 725 }
760697be 726 break;
4f67130a 727 default:
760697be
GL		 728 if (!mx3_camera_packing_supported(fmt))
729 return 0;
730 }
731
732 /* Generic pass-through */
733 formats++;
734 if (xlate) {
735 xlate->host_fmt = fmt;
736 xlate->code = code;
737 xlate++;
738 dev_dbg(dev, "Providing format %x in pass-through mode\n",
739 xlate->host_fmt->fourcc);
4f67130a
GL		 740 }
741
742 return formats;
743}
744
09e231b3 745static void configure_geometry(struct mx3_camera_dev *mx3_cam,
6a6c8786 746 unsigned int width, unsigned int height)
4f67130a 747{
4f67130a 748 u32 ctrl, width_field, height_field;
4f67130a
GL		 749
750 /* Setup frame size - this cannot be changed on-the-fly... */
6a6c8786
GL		 751 width_field = width - 1;
752 height_field = height - 1;
4f67130a
GL		 753 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE);
754
755 csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1);
756 csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2);
757
758 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE);
759
760 /* ...and position */
761 ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
762 /* Sensor does the cropping */
763 csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL);
09e231b3
GL		 764}
765
766static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam)
767{
768 dma_cap_mask_t mask;
769 struct dma_chan *chan;
770 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
771 /* We have to use IDMAC_IC_7 for Bayer / generic data */
772 struct dma_chan_request rq = {.mx3_cam = mx3_cam,
773 .id = IDMAC_IC_7};
774
775 if (*ichan) {
776 struct videobuf_buffer *vb, *_vb;
777 dma_release_channel(&(*ichan)->dma_chan);
778 *ichan = NULL;
779 mx3_cam->active = NULL;
780 list_for_each_entry_safe(vb, _vb, &mx3_cam->capture, queue) {
781 list_del_init(&vb->queue);
782 vb->state = VIDEOBUF_ERROR;
783 wake_up(&vb->done);
784 }
785 }
786
787 dma_cap_zero(mask);
788 dma_cap_set(DMA_SLAVE, mask);
789 dma_cap_set(DMA_PRIVATE, mask);
790 chan = dma_request_channel(mask, chan_filter, &rq);
791 if (!chan)
792 return -EBUSY;
793
794 *ichan = to_idmac_chan(chan);
795 (*ichan)->client = mx3_cam;
796
797 return 0;
798}
799
6a6c8786
GL		 800/*
801 * FIXME: learn to use stride != width, then we can keep stride properly aligned
802 * and support arbitrary (even) widths.
803 */
e26b3144 804static inline void stride_align(__u32 *width)
6a6c8786
GL		 805{
806 if (((*width + 7) & ~7) < 4096)
807 *width = (*width + 7) & ~7;
808 else
809 *width = *width & ~7;
810}
811
812/*
813 * As long as we don't implement host-side cropping and scaling, we can use
814 * default g_crop and cropcap from soc_camera.c
815 */
09e231b3 816static int mx3_camera_set_crop(struct soc_camera_device *icd,
08590b96 817 struct v4l2_crop *a)
09e231b3 818{
08590b96 819 struct v4l2_rect *rect = &a->c;
09e231b3
GL		 820 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
821 struct mx3_camera_dev *mx3_cam = ici->priv;
c9c1f1c0 822 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
760697be 823 struct v4l2_mbus_framefmt mf;
6a6c8786 824 int ret;
09e231b3 825
6a6c8786
GL		 826 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
827 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
828
829 ret = v4l2_subdev_call(sd, video, s_crop, a);
830 if (ret < 0)
831 return ret;
832
833 /* The capture device might have changed its output */
760697be 834 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
6a6c8786
GL		 835 if (ret < 0)
836 return ret;
837
760697be 838 if (mf.width & 7) {
6a6c8786 839 /* Ouch! We can only handle 8-byte aligned width... */
760697be
GL		 840 stride_align(&mf.width);
841 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
09e231b3
GL		 842 if (ret < 0)
843 return ret;
844 }
845
760697be 846 if (mf.width != icd->user_width || mf.height != icd->user_height) {
6a6c8786
GL		 847 /*
848 * We now know pixel formats and can decide upon DMA-channel(s)
849 * So far only direct camera-to-memory is supported
850 */
851 if (channel_change_requested(icd, rect)) {
e26b3144 852 ret = acquire_dma_channel(mx3_cam);
6a6c8786
GL		 853 if (ret < 0)
854 return ret;
855 }
09e231b3 856
760697be 857 configure_geometry(mx3_cam, mf.width, mf.height);
6a6c8786
GL		 858 }
859
860 dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
760697be 861 mf.width, mf.height);
6a6c8786 862
760697be
GL		 863 icd->user_width = mf.width;
864 icd->user_height = mf.height;
6a6c8786
GL		 865
866 return ret;
09e231b3
GL		 867}
868
869static int mx3_camera_set_fmt(struct soc_camera_device *icd,
870 struct v4l2_format *f)
871{
872 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
873 struct mx3_camera_dev *mx3_cam = ici->priv;
c9c1f1c0 874 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
09e231b3
GL		 875 const struct soc_camera_format_xlate *xlate;
876 struct v4l2_pix_format *pix = &f->fmt.pix;
760697be 877 struct v4l2_mbus_framefmt mf;
09e231b3
GL		 878 int ret;
879
880 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
881 if (!xlate) {
0166b743
GL		 882 dev_warn(icd->dev.parent, "Format %x not found\n",
883 pix->pixelformat);
09e231b3
GL		 884 return -EINVAL;
885 }
886
6a6c8786
GL		 887 stride_align(&pix->width);
888 dev_dbg(icd->dev.parent, "Set format %dx%d\n", pix->width, pix->height);
889
09e231b3
GL		 890 ret = acquire_dma_channel(mx3_cam);
891 if (ret < 0)
892 return ret;
893
894 /*
895 * Might have to perform a complete interface initialisation like in
896 * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
897 * mxc_v4l2_s_fmt()
898 */
899
6a6c8786 900 configure_geometry(mx3_cam, pix->width, pix->height);
4f67130a 901
760697be
GL		 902 mf.width = pix->width;
903 mf.height = pix->height;
904 mf.field = pix->field;
905 mf.colorspace = pix->colorspace;
906 mf.code = xlate->code;
907
908 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
909 if (ret < 0)
910 return ret;
911
912 if (mf.code != xlate->code)
913 return -EINVAL;
914
915 pix->width = mf.width;
916 pix->height = mf.height;
917 pix->field = mf.field;
918 pix->colorspace = mf.colorspace;
919 icd->current_fmt = xlate;
4f67130a 920
6a6c8786
GL		 921 dev_dbg(icd->dev.parent, "Sensor set %dx%d\n", pix->width, pix->height);
922
4f67130a
GL		 923 return ret;
924}
925
926static int mx3_camera_try_fmt(struct soc_camera_device *icd,
927 struct v4l2_format *f)
928{
c9c1f1c0 929 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
4f67130a
GL		 930 const struct soc_camera_format_xlate *xlate;
931 struct v4l2_pix_format *pix = &f->fmt.pix;
760697be 932 struct v4l2_mbus_framefmt mf;
4f67130a 933 __u32 pixfmt = pix->pixelformat;
4f67130a
GL		 934 int ret;
935
936 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
937 if (pixfmt && !xlate) {
979ea1dd 938 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
4f67130a
GL		 939 return -EINVAL;
940 }
941
942 /* limit to MX3 hardware capabilities */
943 if (pix->height > 4096)
944 pix->height = 4096;
945 if (pix->width > 4096)
946 pix->width = 4096;
947
760697be
GL		 948 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
949 xlate->host_fmt);
950 if (pix->bytesperline < 0)
951 return pix->bytesperline;
4f67130a
GL		 952 pix->sizeimage = pix->height * pix->bytesperline;
953
4f67130a 954 /* limit to sensor capabilities */
760697be
GL		 955 mf.width = pix->width;
956 mf.height = pix->height;
957 mf.field = pix->field;
958 mf.colorspace = pix->colorspace;
959 mf.code = xlate->code;
4f67130a 960
760697be
GL		 961 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
962 if (ret < 0)
963 return ret;
4f67130a 964
760697be
GL		 965 pix->width = mf.width;
966 pix->height = mf.height;
967 pix->colorspace = mf.colorspace;
968
969 switch (mf.field) {
970 case V4L2_FIELD_ANY:
4f67130a 971 pix->field = V4L2_FIELD_NONE;
760697be
GL		 972 break;
973 case V4L2_FIELD_NONE:
974 break;
975 default:
976 dev_err(icd->dev.parent, "Field type %d unsupported.\n",
977 mf.field);
978 ret = -EINVAL;
4f67130a
GL		 979 }
980
981 return ret;
982}
983
57bee29d 984static int mx3_camera_reqbufs(struct soc_camera_device *icd,
4f67130a
GL		 985 struct v4l2_requestbuffers *p)
986{
987 return 0;
988}
989
990static unsigned int mx3_camera_poll(struct file *file, poll_table *pt)
991{
57bee29d 992 struct soc_camera_device *icd = file->private_data;
4f67130a 993
57bee29d 994 return videobuf_poll_stream(file, &icd->vb_vidq, pt);
4f67130a
GL		 995}
996
997static int mx3_camera_querycap(struct soc_camera_host *ici,
998 struct v4l2_capability *cap)
999{
1000 /* cap->name is set by the firendly caller:-> */
1001 strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card));
1002 cap->version = KERNEL_VERSION(0, 2, 2);
1003 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1004
1005 return 0;
1006}
1007
1008static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1009{
1010 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1011 struct mx3_camera_dev *mx3_cam = ici->priv;
1012 unsigned long bus_flags, camera_flags, common_flags;
1013 u32 dw, sens_conf;
760697be
GL		 1014 const struct soc_mbus_pixelfmt *fmt;
1015 int buswidth;
1016 int ret;
4f67130a 1017 const struct soc_camera_format_xlate *xlate;
0166b743 1018 struct device *dev = icd->dev.parent;
4f67130a 1019
760697be
GL		 1020 fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
1021 if (!fmt)
1022 return -EINVAL;
1023
1024 buswidth = fmt->bits_per_sample;
1025 ret = test_platform_param(mx3_cam, buswidth, &bus_flags);
1026
4f67130a
GL		 1027 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1028 if (!xlate) {
0166b743 1029 dev_warn(dev, "Format %x not found\n", pixfmt);
4f67130a
GL		 1030 return -EINVAL;
1031 }
1032
760697be 1033 dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret);
4f67130a
GL		 1034
1035 if (ret < 0)
1036 return ret;
1037
1038 camera_flags = icd->ops->query_bus_param(icd);
1039
1040 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
0166b743 1041 dev_dbg(dev, "Flags cam: 0x%lx host: 0x%lx common: 0x%lx\n",
40e2e092 1042 camera_flags, bus_flags, common_flags);
4f67130a 1043 if (!common_flags) {
0166b743 1044 dev_dbg(dev, "no common flags");
4f67130a
GL		 1045 return -EINVAL;
1046 }
1047
1048 /* Make choices, based on platform preferences */
1049 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1050 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1051 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
1052 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1053 else
1054 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1055 }
1056
1057 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1058 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1059 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
1060 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1061 else
1062 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1063 }
1064
1065 if ((common_flags & SOCAM_DATA_ACTIVE_HIGH) &&
1066 (common_flags & SOCAM_DATA_ACTIVE_LOW)) {
1067 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
1068 common_flags &= ~SOCAM_DATA_ACTIVE_HIGH;
1069 else
1070 common_flags &= ~SOCAM_DATA_ACTIVE_LOW;
1071 }
1072
1073 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1074 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1075 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
1076 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1077 else
1078 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1079 }
1080
5d28d525
GL		 1081 /*
1082 * Make the camera work in widest common mode, we'll take care of
1083 * the rest
1084 */
4f67130a
GL		 1085 if (common_flags & SOCAM_DATAWIDTH_15)
1086 common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
1087 SOCAM_DATAWIDTH_15;
1088 else if (common_flags & SOCAM_DATAWIDTH_10)
1089 common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
1090 SOCAM_DATAWIDTH_10;
1091 else if (common_flags & SOCAM_DATAWIDTH_8)
1092 common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
1093 SOCAM_DATAWIDTH_8;
1094 else
1095 common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
1096 SOCAM_DATAWIDTH_4;
1097
1098 ret = icd->ops->set_bus_param(icd, common_flags);
40e2e092 1099 if (ret < 0) {
0166b743 1100 dev_dbg(dev, "camera set_bus_param(%lx) returned %d\n",
40e2e092 1101 common_flags, ret);
4f67130a 1102 return ret;
40e2e092 1103 }
4f67130a
GL		 1104
1105 /*
1106 * So far only gated clock mode is supported. Add a line
1107 * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
1108 * below and select the required mode when supporting other
1109 * synchronisation protocols.
1110 */
1111 sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) &
1112 ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) |
1113 (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) |
1114 (1 << CSI_SENS_CONF_DATA_POL_SHIFT) |
1115 (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) |
1116 (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) |
1117 (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT));
1118
1119 /* TODO: Support RGB and YUV formats */
1120
1121 /* This has been set in mx3_camera_activate(), but we clear it above */
1122 sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
1123
1124 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1125 sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
1126 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1127 sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
1128 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1129 sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
1130 if (common_flags & SOCAM_DATA_ACTIVE_LOW)
1131 sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
1132
1133 /* Just do what we're asked to do */
760697be 1134 switch (xlate->host_fmt->bits_per_sample) {
4f67130a
GL		 1135 case 4:
1136 dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1137 break;
1138 case 8:
1139 dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1140 break;
1141 case 10:
1142 dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1143 break;
1144 default:
1145 /*
1146 * Actually it can only be 15 now, default is just to silence
1147 * compiler warnings
1148 */
1149 case 15:
1150 dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1151 }
1152
1153 csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
1154
0166b743 1155 dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw);
4f67130a
GL		 1156
1157 return 0;
1158}
1159
1160static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
1161 .owner = THIS_MODULE,
1162 .add = mx3_camera_add_device,
1163 .remove = mx3_camera_remove_device,
09e231b3 1164 .set_crop = mx3_camera_set_crop,
4f67130a
GL		 1165 .set_fmt = mx3_camera_set_fmt,
1166 .try_fmt = mx3_camera_try_fmt,
1167 .get_formats = mx3_camera_get_formats,
1168 .init_videobuf = mx3_camera_init_videobuf,
1169 .reqbufs = mx3_camera_reqbufs,
1170 .poll = mx3_camera_poll,
1171 .querycap = mx3_camera_querycap,
1172 .set_bus_param = mx3_camera_set_bus_param,
1173};
1174
e36bc31f 1175static int __devinit mx3_camera_probe(struct platform_device *pdev)
4f67130a
GL		 1176{
1177 struct mx3_camera_dev *mx3_cam;
1178 struct resource *res;
1179 void __iomem *base;
1180 int err = 0;
1181 struct soc_camera_host *soc_host;
1182
1183 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184 if (!res) {
1185 err = -ENODEV;
1186 goto egetres;
1187 }
1188
101b25b5 1189 mx3_cam = vzalloc(sizeof(*mx3_cam));
4f67130a
GL		 1190 if (!mx3_cam) {
1191 dev_err(&pdev->dev, "Could not allocate mx3 camera object\n");
1192 err = -ENOMEM;
1193 goto ealloc;
1194 }
4f67130a 1195
b71df97a 1196 mx3_cam->clk = clk_get(&pdev->dev, NULL);
4f67130a
GL		 1197 if (IS_ERR(mx3_cam->clk)) {
1198 err = PTR_ERR(mx3_cam->clk);
1199 goto eclkget;
1200 }
1201
4f67130a
GL		 1202 mx3_cam->pdata = pdev->dev.platform_data;
1203 mx3_cam->platform_flags = mx3_cam->pdata->flags;
1204 if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 |
1205 MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 |
1206 MX3_CAMERA_DATAWIDTH_15))) {
5d28d525
GL		 1207 /*
1208 * Platform hasn't set available data widths. This is bad.
1209 * Warn and use a default.
1210 */
4f67130a
GL		 1211 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1212 "data widths, using default 8 bit\n");
1213 mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8;
1214 }
1215
1216 mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000;
1217 if (!mx3_cam->mclk) {
1218 dev_warn(&pdev->dev,
1219 "mclk_10khz == 0! Please, fix your platform data. "
1220 "Using default 20MHz\n");
1221 mx3_cam->mclk = 20000000;
1222 }
1223
1224 /* list of video-buffers */
1225 INIT_LIST_HEAD(&mx3_cam->capture);
1226 spin_lock_init(&mx3_cam->lock);
1227
40e2e092 1228 base = ioremap(res->start, resource_size(res));
4f67130a 1229 if (!base) {
40e2e092 1230 pr_err("Couldn't map %x@%x\n", resource_size(res), res->start);
4f67130a
GL		 1231 err = -ENOMEM;
1232 goto eioremap;
1233 }
1234
1235 mx3_cam->base = base;
4f67130a
GL		 1236
1237 soc_host = &mx3_cam->soc_host;
1238 soc_host->drv_name = MX3_CAM_DRV_NAME;
1239 soc_host->ops = &mx3_soc_camera_host_ops;
1240 soc_host->priv = mx3_cam;
979ea1dd 1241 soc_host->v4l2_dev.dev = &pdev->dev;
4f67130a 1242 soc_host->nr = pdev->id;
eff505fa 1243
4f67130a
GL		 1244 err = soc_camera_host_register(soc_host);
1245 if (err)
1246 goto ecamhostreg;
1247
1248 /* IDMAC interface */
1249 dmaengine_get();
1250
1251 return 0;
1252
1253ecamhostreg:
1254 iounmap(base);
1255eioremap:
1256 clk_put(mx3_cam->clk);
1257eclkget:
1258 vfree(mx3_cam);
1259ealloc:
1260egetres:
1261 return err;
1262}
1263
1264static int __devexit mx3_camera_remove(struct platform_device *pdev)
1265{
eff505fa
GL		 1266 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1267 struct mx3_camera_dev *mx3_cam = container_of(soc_host,
1268 struct mx3_camera_dev, soc_host);
4f67130a
GL		 1269
1270 clk_put(mx3_cam->clk);
1271
eff505fa 1272 soc_camera_host_unregister(soc_host);
4f67130a
GL		 1273
1274 iounmap(mx3_cam->base);
1275
1276 /*
1277 * The channel has either not been allocated,
1278 * or should have been released
1279 */
1280 if (WARN_ON(mx3_cam->idmac_channel[0]))
1281 dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan);
1282
1283 vfree(mx3_cam);
1284
1285 dmaengine_put();
1286
1287 dev_info(&pdev->dev, "i.MX3x Camera driver unloaded\n");
1288
1289 return 0;
1290}
1291
1292static struct platform_driver mx3_camera_driver = {
1293 .driver = {
1294 .name = MX3_CAM_DRV_NAME,
1295 },
1296 .probe = mx3_camera_probe,
e36bc31f 1297 .remove = __devexit_p(mx3_camera_remove),
4f67130a
GL		 1298};
1299
1300
e36bc31f 1301static int __init mx3_camera_init(void)
4f67130a
GL		 1302{
1303 return platform_driver_register(&mx3_camera_driver);
1304}
1305
1306static void __exit mx3_camera_exit(void)
1307{
1308 platform_driver_unregister(&mx3_camera_driver);
1309}
1310
1311module_init(mx3_camera_init);
1312module_exit(mx3_camera_exit);
1313
1314MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
1315MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1316MODULE_LICENSE("GPL v2");
40e2e092 1317MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME);
Linux kernel - Deliverables
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