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4f67130a GL |
1 | /* |
2 | * V4L2 Driver for i.MX3x camera host | |
3 | * | |
4 | * Copyright (C) 2008 | |
5 | * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/version.h> | |
15 | #include <linux/videodev2.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/vmalloc.h> | |
19 | #include <linux/interrupt.h> | |
20 | ||
21 | #include <media/v4l2-common.h> | |
22 | #include <media/v4l2-dev.h> | |
23 | #include <media/videobuf-dma-contig.h> | |
24 | #include <media/soc_camera.h> | |
25 | ||
26 | #include <mach/ipu.h> | |
27 | #include <mach/mx3_camera.h> | |
28 | ||
29 | #define MX3_CAM_DRV_NAME "mx3-camera" | |
30 | ||
31 | /* CMOS Sensor Interface Registers */ | |
32 | #define CSI_REG_START 0x60 | |
33 | ||
34 | #define CSI_SENS_CONF (0x60 - CSI_REG_START) | |
35 | #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START) | |
36 | #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START) | |
37 | #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START) | |
38 | #define CSI_TST_CTRL (0x70 - CSI_REG_START) | |
39 | #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START) | |
40 | #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START) | |
41 | #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START) | |
42 | #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START) | |
43 | #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START) | |
44 | ||
45 | #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0 | |
46 | #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1 | |
47 | #define CSI_SENS_CONF_DATA_POL_SHIFT 2 | |
48 | #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3 | |
49 | #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4 | |
50 | #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7 | |
51 | #define CSI_SENS_CONF_DATA_FMT_SHIFT 8 | |
52 | #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10 | |
53 | #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15 | |
54 | #define CSI_SENS_CONF_DIVRATIO_SHIFT 16 | |
55 | ||
56 | #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
57 | #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
58 | #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
59 | ||
60 | #define MAX_VIDEO_MEM 16 | |
61 | ||
62 | struct mx3_camera_buffer { | |
63 | /* common v4l buffer stuff -- must be first */ | |
64 | struct videobuf_buffer vb; | |
65 | const struct soc_camera_data_format *fmt; | |
66 | ||
67 | /* One descriptot per scatterlist (per frame) */ | |
68 | struct dma_async_tx_descriptor *txd; | |
69 | ||
70 | /* We have to "build" a scatterlist ourselves - one element per frame */ | |
71 | struct scatterlist sg; | |
72 | }; | |
73 | ||
74 | /** | |
75 | * struct mx3_camera_dev - i.MX3x camera (CSI) object | |
76 | * @dev: camera device, to which the coherent buffer is attached | |
77 | * @icd: currently attached camera sensor | |
78 | * @clk: pointer to clock | |
79 | * @base: remapped register base address | |
80 | * @pdata: platform data | |
81 | * @platform_flags: platform flags | |
82 | * @mclk: master clock frequency in Hz | |
83 | * @capture: list of capture videobuffers | |
84 | * @lock: protects video buffer lists | |
85 | * @active: active video buffer | |
86 | * @idmac_channel: array of pointers to IPU DMAC DMA channels | |
87 | * @soc_host: embedded soc_host object | |
88 | */ | |
89 | struct mx3_camera_dev { | |
4f67130a GL |
90 | /* |
91 | * i.MX3x is only supposed to handle one camera on its Camera Sensor | |
92 | * Interface. If anyone ever builds hardware to enable more than one | |
93 | * camera _simultaneously_, they will have to modify this driver too | |
94 | */ | |
95 | struct soc_camera_device *icd; | |
96 | struct clk *clk; | |
97 | ||
98 | void __iomem *base; | |
99 | ||
100 | struct mx3_camera_pdata *pdata; | |
101 | ||
102 | unsigned long platform_flags; | |
103 | unsigned long mclk; | |
104 | ||
105 | struct list_head capture; | |
106 | spinlock_t lock; /* Protects video buffer lists */ | |
107 | struct mx3_camera_buffer *active; | |
108 | ||
109 | /* IDMAC / dmaengine interface */ | |
110 | struct idmac_channel *idmac_channel[1]; /* We need one channel */ | |
111 | ||
112 | struct soc_camera_host soc_host; | |
113 | }; | |
114 | ||
115 | struct dma_chan_request { | |
116 | struct mx3_camera_dev *mx3_cam; | |
117 | enum ipu_channel id; | |
118 | }; | |
119 | ||
120 | static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt); | |
121 | ||
122 | static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg) | |
123 | { | |
124 | return __raw_readl(mx3->base + reg); | |
125 | } | |
126 | ||
127 | static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg) | |
128 | { | |
129 | __raw_writel(value, mx3->base + reg); | |
130 | } | |
131 | ||
132 | /* Called from the IPU IDMAC ISR */ | |
133 | static void mx3_cam_dma_done(void *arg) | |
134 | { | |
135 | struct idmac_tx_desc *desc = to_tx_desc(arg); | |
136 | struct dma_chan *chan = desc->txd.chan; | |
137 | struct idmac_channel *ichannel = to_idmac_chan(chan); | |
138 | struct mx3_camera_dev *mx3_cam = ichannel->client; | |
139 | struct videobuf_buffer *vb; | |
140 | ||
141 | dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n", | |
142 | desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0); | |
143 | ||
144 | spin_lock(&mx3_cam->lock); | |
145 | if (mx3_cam->active) { | |
146 | vb = &mx3_cam->active->vb; | |
147 | ||
148 | list_del_init(&vb->queue); | |
149 | vb->state = VIDEOBUF_DONE; | |
150 | do_gettimeofday(&vb->ts); | |
151 | vb->field_count++; | |
152 | wake_up(&vb->done); | |
153 | } | |
154 | ||
155 | if (list_empty(&mx3_cam->capture)) { | |
156 | mx3_cam->active = NULL; | |
157 | spin_unlock(&mx3_cam->lock); | |
158 | ||
159 | /* | |
160 | * stop capture - without further buffers IPU_CHA_BUF0_RDY will | |
161 | * not get updated | |
162 | */ | |
163 | return; | |
164 | } | |
165 | ||
166 | mx3_cam->active = list_entry(mx3_cam->capture.next, | |
167 | struct mx3_camera_buffer, vb.queue); | |
168 | mx3_cam->active->vb.state = VIDEOBUF_ACTIVE; | |
169 | spin_unlock(&mx3_cam->lock); | |
170 | } | |
171 | ||
172 | static void free_buffer(struct videobuf_queue *vq, struct mx3_camera_buffer *buf) | |
173 | { | |
174 | struct soc_camera_device *icd = vq->priv_data; | |
175 | struct videobuf_buffer *vb = &buf->vb; | |
176 | struct dma_async_tx_descriptor *txd = buf->txd; | |
177 | struct idmac_channel *ichan; | |
178 | ||
179 | BUG_ON(in_interrupt()); | |
180 | ||
181 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, | |
182 | vb, vb->baddr, vb->bsize); | |
183 | ||
184 | /* | |
185 | * This waits until this buffer is out of danger, i.e., until it is no | |
186 | * longer in STATE_QUEUED or STATE_ACTIVE | |
187 | */ | |
188 | videobuf_waiton(vb, 0, 0); | |
189 | if (txd) { | |
190 | ichan = to_idmac_chan(txd->chan); | |
191 | async_tx_ack(txd); | |
192 | } | |
193 | videobuf_dma_contig_free(vq, vb); | |
194 | buf->txd = NULL; | |
195 | ||
196 | vb->state = VIDEOBUF_NEEDS_INIT; | |
197 | } | |
198 | ||
199 | /* | |
200 | * Videobuf operations | |
201 | */ | |
202 | ||
203 | /* | |
204 | * Calculate the __buffer__ (not data) size and number of buffers. | |
205 | * Called with .vb_lock held | |
206 | */ | |
207 | static int mx3_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, | |
208 | unsigned int *size) | |
209 | { | |
210 | struct soc_camera_device *icd = vq->priv_data; | |
211 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
212 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
213 | /* | |
214 | * bits-per-pixel (depth) as specified in camera's pixel format does | |
215 | * not necessarily match what the camera interface writes to RAM, but | |
216 | * it should be good enough for now. | |
217 | */ | |
218 | unsigned int bpp = DIV_ROUND_UP(icd->current_fmt->depth, 8); | |
219 | ||
220 | if (!mx3_cam->idmac_channel[0]) | |
221 | return -EINVAL; | |
222 | ||
223 | *size = icd->width * icd->height * bpp; | |
224 | ||
225 | if (!*count) | |
226 | *count = 32; | |
227 | ||
228 | if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) | |
229 | *count = MAX_VIDEO_MEM * 1024 * 1024 / *size; | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | /* Called with .vb_lock held */ | |
235 | static int mx3_videobuf_prepare(struct videobuf_queue *vq, | |
236 | struct videobuf_buffer *vb, enum v4l2_field field) | |
237 | { | |
238 | struct soc_camera_device *icd = vq->priv_data; | |
239 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
240 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
241 | struct mx3_camera_buffer *buf = | |
242 | container_of(vb, struct mx3_camera_buffer, vb); | |
243 | /* current_fmt _must_ always be set */ | |
244 | size_t new_size = icd->width * icd->height * | |
245 | ((icd->current_fmt->depth + 7) >> 3); | |
246 | int ret; | |
247 | ||
248 | /* | |
249 | * I think, in buf_prepare you only have to protect global data, | |
250 | * the actual buffer is yours | |
251 | */ | |
252 | ||
253 | if (buf->fmt != icd->current_fmt || | |
254 | vb->width != icd->width || | |
255 | vb->height != icd->height || | |
256 | vb->field != field) { | |
257 | buf->fmt = icd->current_fmt; | |
258 | vb->width = icd->width; | |
259 | vb->height = icd->height; | |
260 | vb->field = field; | |
261 | if (vb->state != VIDEOBUF_NEEDS_INIT) | |
262 | free_buffer(vq, buf); | |
263 | } | |
264 | ||
265 | if (vb->baddr && vb->bsize < new_size) { | |
266 | /* User provided buffer, but it is too small */ | |
267 | ret = -ENOMEM; | |
268 | goto out; | |
269 | } | |
270 | ||
271 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
272 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
273 | struct scatterlist *sg = &buf->sg; | |
274 | ||
275 | /* | |
276 | * The total size of video-buffers that will be allocated / mapped. | |
277 | * *size that we calculated in videobuf_setup gets assigned to | |
278 | * vb->bsize, and now we use the same calculation to get vb->size. | |
279 | */ | |
280 | vb->size = new_size; | |
281 | ||
282 | /* This actually (allocates and) maps buffers */ | |
283 | ret = videobuf_iolock(vq, vb, NULL); | |
284 | if (ret) | |
285 | goto fail; | |
286 | ||
287 | /* | |
288 | * We will have to configure the IDMAC channel. It has two slots | |
289 | * for DMA buffers, we shall enter the first two buffers there, | |
290 | * and then submit new buffers in DMA-ready interrupts | |
291 | */ | |
292 | sg_init_table(sg, 1); | |
293 | sg_dma_address(sg) = videobuf_to_dma_contig(vb); | |
294 | sg_dma_len(sg) = vb->size; | |
295 | ||
296 | buf->txd = ichan->dma_chan.device->device_prep_slave_sg( | |
297 | &ichan->dma_chan, sg, 1, DMA_FROM_DEVICE, | |
298 | DMA_PREP_INTERRUPT); | |
299 | if (!buf->txd) { | |
300 | ret = -EIO; | |
301 | goto fail; | |
302 | } | |
303 | ||
304 | buf->txd->callback_param = buf->txd; | |
305 | buf->txd->callback = mx3_cam_dma_done; | |
306 | ||
307 | vb->state = VIDEOBUF_PREPARED; | |
308 | } | |
309 | ||
310 | return 0; | |
311 | ||
312 | fail: | |
313 | free_buffer(vq, buf); | |
314 | out: | |
315 | return ret; | |
316 | } | |
317 | ||
318 | static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc) | |
319 | { | |
320 | /* Add more formats as need arises and test possibilities appear... */ | |
321 | switch (fourcc) { | |
322 | case V4L2_PIX_FMT_RGB565: | |
323 | return IPU_PIX_FMT_RGB565; | |
324 | case V4L2_PIX_FMT_RGB24: | |
325 | return IPU_PIX_FMT_RGB24; | |
326 | case V4L2_PIX_FMT_RGB332: | |
327 | return IPU_PIX_FMT_RGB332; | |
328 | case V4L2_PIX_FMT_YUV422P: | |
329 | return IPU_PIX_FMT_YVU422P; | |
330 | default: | |
331 | return IPU_PIX_FMT_GENERIC; | |
332 | } | |
333 | } | |
334 | ||
2dd54a54 GL |
335 | /* |
336 | * Called with .vb_lock mutex held and | |
337 | * under spinlock_irqsave(&mx3_cam->lock, ...) | |
338 | */ | |
4f67130a GL |
339 | static void mx3_videobuf_queue(struct videobuf_queue *vq, |
340 | struct videobuf_buffer *vb) | |
341 | { | |
342 | struct soc_camera_device *icd = vq->priv_data; | |
343 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
344 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
345 | struct mx3_camera_buffer *buf = | |
346 | container_of(vb, struct mx3_camera_buffer, vb); | |
347 | struct dma_async_tx_descriptor *txd = buf->txd; | |
348 | struct idmac_channel *ichan = to_idmac_chan(txd->chan); | |
349 | struct idmac_video_param *video = &ichan->params.video; | |
350 | const struct soc_camera_data_format *data_fmt = icd->current_fmt; | |
351 | dma_cookie_t cookie; | |
2dd54a54 GL |
352 | |
353 | BUG_ON(!irqs_disabled()); | |
4f67130a GL |
354 | |
355 | /* This is the configuration of one sg-element */ | |
356 | video->out_pixel_fmt = fourcc_to_ipu_pix(data_fmt->fourcc); | |
357 | video->out_width = icd->width; | |
358 | video->out_height = icd->height; | |
359 | video->out_stride = icd->width; | |
360 | ||
361 | #ifdef DEBUG | |
362 | /* helps to see what DMA actually has written */ | |
363 | memset((void *)vb->baddr, 0xaa, vb->bsize); | |
364 | #endif | |
365 | ||
4f67130a GL |
366 | list_add_tail(&vb->queue, &mx3_cam->capture); |
367 | ||
368 | if (!mx3_cam->active) { | |
369 | mx3_cam->active = buf; | |
370 | vb->state = VIDEOBUF_ACTIVE; | |
371 | } else { | |
372 | vb->state = VIDEOBUF_QUEUED; | |
373 | } | |
374 | ||
2dd54a54 | 375 | spin_unlock_irq(&mx3_cam->lock); |
4f67130a GL |
376 | |
377 | cookie = txd->tx_submit(txd); | |
378 | dev_dbg(&icd->dev, "Submitted cookie %d DMA 0x%08x\n", cookie, sg_dma_address(&buf->sg)); | |
2dd54a54 GL |
379 | |
380 | spin_lock_irq(&mx3_cam->lock); | |
381 | ||
4f67130a GL |
382 | if (cookie >= 0) |
383 | return; | |
384 | ||
385 | /* Submit error */ | |
386 | vb->state = VIDEOBUF_PREPARED; | |
387 | ||
4f67130a GL |
388 | list_del_init(&vb->queue); |
389 | ||
390 | if (mx3_cam->active == buf) | |
391 | mx3_cam->active = NULL; | |
4f67130a GL |
392 | } |
393 | ||
394 | /* Called with .vb_lock held */ | |
395 | static void mx3_videobuf_release(struct videobuf_queue *vq, | |
396 | struct videobuf_buffer *vb) | |
397 | { | |
398 | struct soc_camera_device *icd = vq->priv_data; | |
399 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
400 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
401 | struct mx3_camera_buffer *buf = | |
402 | container_of(vb, struct mx3_camera_buffer, vb); | |
403 | unsigned long flags; | |
404 | ||
405 | dev_dbg(&icd->dev, "Release%s DMA 0x%08x (state %d), queue %sempty\n", | |
406 | mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg), | |
407 | vb->state, list_empty(&vb->queue) ? "" : "not "); | |
408 | spin_lock_irqsave(&mx3_cam->lock, flags); | |
409 | if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) && | |
410 | !list_empty(&vb->queue)) { | |
411 | vb->state = VIDEOBUF_ERROR; | |
412 | ||
413 | list_del_init(&vb->queue); | |
414 | if (mx3_cam->active == buf) | |
415 | mx3_cam->active = NULL; | |
416 | } | |
417 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
418 | free_buffer(vq, buf); | |
419 | } | |
420 | ||
421 | static struct videobuf_queue_ops mx3_videobuf_ops = { | |
422 | .buf_setup = mx3_videobuf_setup, | |
423 | .buf_prepare = mx3_videobuf_prepare, | |
424 | .buf_queue = mx3_videobuf_queue, | |
425 | .buf_release = mx3_videobuf_release, | |
426 | }; | |
427 | ||
428 | static void mx3_camera_init_videobuf(struct videobuf_queue *q, | |
429 | struct soc_camera_device *icd) | |
430 | { | |
431 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
432 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
433 | ||
eff505fa | 434 | videobuf_queue_dma_contig_init(q, &mx3_videobuf_ops, ici->dev, |
4f67130a GL |
435 | &mx3_cam->lock, |
436 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
437 | V4L2_FIELD_NONE, | |
438 | sizeof(struct mx3_camera_buffer), icd); | |
439 | } | |
440 | ||
441 | /* First part of ipu_csi_init_interface() */ | |
442 | static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam, | |
443 | struct soc_camera_device *icd) | |
444 | { | |
445 | u32 conf; | |
446 | long rate; | |
447 | ||
448 | /* Set default size: ipu_csi_set_window_size() */ | |
449 | csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE); | |
450 | /* ...and position to 0:0: ipu_csi_set_window_pos() */ | |
451 | conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
452 | csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL); | |
453 | ||
454 | /* We use only gated clock synchronisation mode so far */ | |
455 | conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT; | |
456 | ||
457 | /* Set generic data, platform-biggest bus-width */ | |
458 | conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
459 | ||
460 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
461 | conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
462 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
463 | conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
464 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
465 | conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
466 | else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/ | |
467 | conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
468 | ||
469 | if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC) | |
470 | conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT; | |
471 | if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC) | |
472 | conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT; | |
473 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) | |
474 | conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; | |
475 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) | |
476 | conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; | |
477 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) | |
478 | conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; | |
479 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) | |
480 | conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; | |
481 | ||
482 | /* ipu_csi_init_interface() */ | |
483 | csi_reg_write(mx3_cam, conf, CSI_SENS_CONF); | |
484 | ||
485 | clk_enable(mx3_cam->clk); | |
486 | rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk); | |
487 | dev_dbg(&icd->dev, "Set SENS_CONF to %x, rate %ld\n", conf, rate); | |
488 | if (rate) | |
489 | clk_set_rate(mx3_cam->clk, rate); | |
490 | } | |
491 | ||
492 | /* Called with .video_lock held */ | |
493 | static int mx3_camera_add_device(struct soc_camera_device *icd) | |
494 | { | |
495 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
496 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
497 | int ret; | |
498 | ||
499 | if (mx3_cam->icd) { | |
500 | ret = -EBUSY; | |
501 | goto ebusy; | |
502 | } | |
503 | ||
504 | mx3_camera_activate(mx3_cam, icd); | |
505 | ret = icd->ops->init(icd); | |
506 | if (ret < 0) { | |
507 | clk_disable(mx3_cam->clk); | |
508 | goto einit; | |
509 | } | |
510 | ||
511 | mx3_cam->icd = icd; | |
512 | ||
513 | einit: | |
514 | ebusy: | |
515 | if (!ret) | |
516 | dev_info(&icd->dev, "MX3 Camera driver attached to camera %d\n", | |
517 | icd->devnum); | |
518 | ||
519 | return ret; | |
520 | } | |
521 | ||
522 | /* Called with .video_lock held */ | |
523 | static void mx3_camera_remove_device(struct soc_camera_device *icd) | |
524 | { | |
525 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
526 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
527 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
528 | ||
529 | BUG_ON(icd != mx3_cam->icd); | |
530 | ||
531 | if (*ichan) { | |
532 | dma_release_channel(&(*ichan)->dma_chan); | |
533 | *ichan = NULL; | |
534 | } | |
535 | ||
536 | icd->ops->release(icd); | |
537 | ||
538 | clk_disable(mx3_cam->clk); | |
539 | ||
540 | mx3_cam->icd = NULL; | |
541 | ||
542 | dev_info(&icd->dev, "MX3 Camera driver detached from camera %d\n", | |
543 | icd->devnum); | |
544 | } | |
545 | ||
546 | static bool channel_change_requested(struct soc_camera_device *icd, | |
09e231b3 | 547 | struct v4l2_rect *rect) |
4f67130a GL |
548 | { |
549 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
550 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
551 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
552 | ||
09e231b3 GL |
553 | /* Do buffers have to be re-allocated or channel re-configured? */ |
554 | return ichan && rect->width * rect->height > icd->width * icd->height; | |
4f67130a GL |
555 | } |
556 | ||
557 | static int test_platform_param(struct mx3_camera_dev *mx3_cam, | |
558 | unsigned char buswidth, unsigned long *flags) | |
559 | { | |
560 | /* | |
561 | * Platform specified synchronization and pixel clock polarities are | |
562 | * only a recommendation and are only used during probing. MX3x | |
563 | * camera interface only works in master mode, i.e., uses HSYNC and | |
564 | * VSYNC signals from the sensor | |
565 | */ | |
566 | *flags = SOCAM_MASTER | | |
567 | SOCAM_HSYNC_ACTIVE_HIGH | | |
568 | SOCAM_HSYNC_ACTIVE_LOW | | |
569 | SOCAM_VSYNC_ACTIVE_HIGH | | |
570 | SOCAM_VSYNC_ACTIVE_LOW | | |
571 | SOCAM_PCLK_SAMPLE_RISING | | |
572 | SOCAM_PCLK_SAMPLE_FALLING | | |
573 | SOCAM_DATA_ACTIVE_HIGH | | |
574 | SOCAM_DATA_ACTIVE_LOW; | |
575 | ||
576 | /* If requested data width is supported by the platform, use it or any | |
577 | * possible lower value - i.MX31 is smart enough to schift bits */ | |
578 | switch (buswidth) { | |
579 | case 15: | |
580 | if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)) | |
581 | return -EINVAL; | |
582 | *flags |= SOCAM_DATAWIDTH_15 | SOCAM_DATAWIDTH_10 | | |
583 | SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4; | |
584 | break; | |
585 | case 10: | |
586 | if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)) | |
587 | return -EINVAL; | |
588 | *flags |= SOCAM_DATAWIDTH_10 | SOCAM_DATAWIDTH_8 | | |
589 | SOCAM_DATAWIDTH_4; | |
590 | break; | |
591 | case 8: | |
592 | if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)) | |
593 | return -EINVAL; | |
594 | *flags |= SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4; | |
595 | break; | |
596 | case 4: | |
597 | if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)) | |
598 | return -EINVAL; | |
599 | *flags |= SOCAM_DATAWIDTH_4; | |
600 | break; | |
601 | default: | |
eff505fa GL |
602 | dev_info(mx3_cam->soc_host.dev, "Unsupported bus width %d\n", |
603 | buswidth); | |
4f67130a GL |
604 | return -EINVAL; |
605 | } | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static int mx3_camera_try_bus_param(struct soc_camera_device *icd, | |
611 | const unsigned int depth) | |
612 | { | |
613 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
614 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
615 | unsigned long bus_flags, camera_flags; | |
616 | int ret = test_platform_param(mx3_cam, depth, &bus_flags); | |
617 | ||
eff505fa | 618 | dev_dbg(ici->dev, "requested bus width %d bit: %d\n", depth, ret); |
4f67130a GL |
619 | |
620 | if (ret < 0) | |
621 | return ret; | |
622 | ||
623 | camera_flags = icd->ops->query_bus_param(icd); | |
624 | ||
625 | ret = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
626 | if (ret < 0) | |
627 | dev_warn(&icd->dev, "Flags incompatible: camera %lx, host %lx\n", | |
628 | camera_flags, bus_flags); | |
629 | ||
630 | return ret; | |
631 | } | |
632 | ||
633 | static bool chan_filter(struct dma_chan *chan, void *arg) | |
634 | { | |
635 | struct dma_chan_request *rq = arg; | |
636 | struct mx3_camera_pdata *pdata; | |
637 | ||
638 | if (!rq) | |
639 | return false; | |
640 | ||
eff505fa | 641 | pdata = rq->mx3_cam->soc_host.dev->platform_data; |
4f67130a GL |
642 | |
643 | return rq->id == chan->chan_id && | |
644 | pdata->dma_dev == chan->device->dev; | |
645 | } | |
646 | ||
647 | static const struct soc_camera_data_format mx3_camera_formats[] = { | |
648 | { | |
649 | .name = "Bayer (sRGB) 8 bit", | |
650 | .depth = 8, | |
651 | .fourcc = V4L2_PIX_FMT_SBGGR8, | |
652 | .colorspace = V4L2_COLORSPACE_SRGB, | |
653 | }, { | |
654 | .name = "Monochrome 8 bit", | |
655 | .depth = 8, | |
656 | .fourcc = V4L2_PIX_FMT_GREY, | |
657 | .colorspace = V4L2_COLORSPACE_JPEG, | |
658 | }, | |
659 | }; | |
660 | ||
661 | static bool buswidth_supported(struct soc_camera_host *ici, int depth) | |
662 | { | |
663 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
664 | ||
665 | switch (depth) { | |
666 | case 4: | |
667 | return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4); | |
668 | case 8: | |
669 | return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8); | |
670 | case 10: | |
671 | return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10); | |
672 | case 15: | |
673 | return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15); | |
674 | } | |
675 | return false; | |
676 | } | |
677 | ||
678 | static int mx3_camera_get_formats(struct soc_camera_device *icd, int idx, | |
679 | struct soc_camera_format_xlate *xlate) | |
680 | { | |
681 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
682 | int formats = 0, buswidth, ret; | |
683 | ||
684 | buswidth = icd->formats[idx].depth; | |
685 | ||
686 | if (!buswidth_supported(ici, buswidth)) | |
687 | return 0; | |
688 | ||
689 | ret = mx3_camera_try_bus_param(icd, buswidth); | |
690 | if (ret < 0) | |
691 | return 0; | |
692 | ||
693 | switch (icd->formats[idx].fourcc) { | |
694 | case V4L2_PIX_FMT_SGRBG10: | |
695 | formats++; | |
696 | if (xlate) { | |
697 | xlate->host_fmt = &mx3_camera_formats[0]; | |
698 | xlate->cam_fmt = icd->formats + idx; | |
699 | xlate->buswidth = buswidth; | |
700 | xlate++; | |
eff505fa | 701 | dev_dbg(ici->dev, "Providing format %s using %s\n", |
4f67130a GL |
702 | mx3_camera_formats[0].name, |
703 | icd->formats[idx].name); | |
704 | } | |
705 | goto passthrough; | |
706 | case V4L2_PIX_FMT_Y16: | |
707 | formats++; | |
708 | if (xlate) { | |
709 | xlate->host_fmt = &mx3_camera_formats[1]; | |
710 | xlate->cam_fmt = icd->formats + idx; | |
711 | xlate->buswidth = buswidth; | |
712 | xlate++; | |
eff505fa | 713 | dev_dbg(ici->dev, "Providing format %s using %s\n", |
4f67130a GL |
714 | mx3_camera_formats[0].name, |
715 | icd->formats[idx].name); | |
716 | } | |
717 | default: | |
718 | passthrough: | |
719 | /* Generic pass-through */ | |
720 | formats++; | |
721 | if (xlate) { | |
722 | xlate->host_fmt = icd->formats + idx; | |
723 | xlate->cam_fmt = icd->formats + idx; | |
724 | xlate->buswidth = buswidth; | |
725 | xlate++; | |
eff505fa | 726 | dev_dbg(ici->dev, |
4f67130a GL |
727 | "Providing format %s in pass-through mode\n", |
728 | icd->formats[idx].name); | |
729 | } | |
730 | } | |
731 | ||
732 | return formats; | |
733 | } | |
734 | ||
09e231b3 GL |
735 | static void configure_geometry(struct mx3_camera_dev *mx3_cam, |
736 | struct v4l2_rect *rect) | |
4f67130a | 737 | { |
4f67130a | 738 | u32 ctrl, width_field, height_field; |
4f67130a GL |
739 | |
740 | /* Setup frame size - this cannot be changed on-the-fly... */ | |
741 | width_field = rect->width - 1; | |
742 | height_field = rect->height - 1; | |
743 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE); | |
744 | ||
745 | csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1); | |
746 | csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2); | |
747 | ||
748 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE); | |
749 | ||
750 | /* ...and position */ | |
751 | ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
752 | /* Sensor does the cropping */ | |
753 | csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL); | |
754 | ||
755 | /* | |
756 | * No need to free resources here if we fail, we'll see if we need to | |
757 | * do this next time we are called | |
758 | */ | |
09e231b3 GL |
759 | } |
760 | ||
761 | static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam) | |
762 | { | |
763 | dma_cap_mask_t mask; | |
764 | struct dma_chan *chan; | |
765 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
766 | /* We have to use IDMAC_IC_7 for Bayer / generic data */ | |
767 | struct dma_chan_request rq = {.mx3_cam = mx3_cam, | |
768 | .id = IDMAC_IC_7}; | |
769 | ||
770 | if (*ichan) { | |
771 | struct videobuf_buffer *vb, *_vb; | |
772 | dma_release_channel(&(*ichan)->dma_chan); | |
773 | *ichan = NULL; | |
774 | mx3_cam->active = NULL; | |
775 | list_for_each_entry_safe(vb, _vb, &mx3_cam->capture, queue) { | |
776 | list_del_init(&vb->queue); | |
777 | vb->state = VIDEOBUF_ERROR; | |
778 | wake_up(&vb->done); | |
779 | } | |
780 | } | |
781 | ||
782 | dma_cap_zero(mask); | |
783 | dma_cap_set(DMA_SLAVE, mask); | |
784 | dma_cap_set(DMA_PRIVATE, mask); | |
785 | chan = dma_request_channel(mask, chan_filter, &rq); | |
786 | if (!chan) | |
787 | return -EBUSY; | |
788 | ||
789 | *ichan = to_idmac_chan(chan); | |
790 | (*ichan)->client = mx3_cam; | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static int mx3_camera_set_crop(struct soc_camera_device *icd, | |
796 | struct v4l2_rect *rect) | |
797 | { | |
798 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
799 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
800 | ||
801 | /* | |
802 | * We now know pixel formats and can decide upon DMA-channel(s) | |
803 | * So far only direct camera-to-memory is supported | |
804 | */ | |
805 | if (channel_change_requested(icd, rect)) { | |
806 | int ret = acquire_dma_channel(mx3_cam); | |
807 | if (ret < 0) | |
808 | return ret; | |
809 | } | |
810 | ||
811 | configure_geometry(mx3_cam, rect); | |
812 | ||
813 | return icd->ops->set_crop(icd, rect); | |
814 | } | |
815 | ||
816 | static int mx3_camera_set_fmt(struct soc_camera_device *icd, | |
817 | struct v4l2_format *f) | |
818 | { | |
819 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
820 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
821 | const struct soc_camera_format_xlate *xlate; | |
822 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
823 | struct v4l2_rect rect = { | |
824 | .left = icd->x_current, | |
825 | .top = icd->y_current, | |
826 | .width = pix->width, | |
827 | .height = pix->height, | |
828 | }; | |
829 | int ret; | |
830 | ||
831 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); | |
832 | if (!xlate) { | |
eff505fa | 833 | dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat); |
09e231b3 GL |
834 | return -EINVAL; |
835 | } | |
836 | ||
837 | ret = acquire_dma_channel(mx3_cam); | |
838 | if (ret < 0) | |
839 | return ret; | |
840 | ||
841 | /* | |
842 | * Might have to perform a complete interface initialisation like in | |
843 | * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider | |
844 | * mxc_v4l2_s_fmt() | |
845 | */ | |
846 | ||
847 | configure_geometry(mx3_cam, &rect); | |
4f67130a | 848 | |
09e231b3 GL |
849 | ret = icd->ops->set_fmt(icd, f); |
850 | if (!ret) { | |
4f67130a GL |
851 | icd->buswidth = xlate->buswidth; |
852 | icd->current_fmt = xlate->host_fmt; | |
853 | } | |
854 | ||
855 | return ret; | |
856 | } | |
857 | ||
858 | static int mx3_camera_try_fmt(struct soc_camera_device *icd, | |
859 | struct v4l2_format *f) | |
860 | { | |
861 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
862 | const struct soc_camera_format_xlate *xlate; | |
863 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
864 | __u32 pixfmt = pix->pixelformat; | |
865 | enum v4l2_field field; | |
866 | int ret; | |
867 | ||
868 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | |
869 | if (pixfmt && !xlate) { | |
eff505fa | 870 | dev_warn(ici->dev, "Format %x not found\n", pixfmt); |
4f67130a GL |
871 | return -EINVAL; |
872 | } | |
873 | ||
874 | /* limit to MX3 hardware capabilities */ | |
875 | if (pix->height > 4096) | |
876 | pix->height = 4096; | |
877 | if (pix->width > 4096) | |
878 | pix->width = 4096; | |
879 | ||
880 | pix->bytesperline = pix->width * | |
881 | DIV_ROUND_UP(xlate->host_fmt->depth, 8); | |
882 | pix->sizeimage = pix->height * pix->bytesperline; | |
883 | ||
884 | /* camera has to see its format, but the user the original one */ | |
885 | pix->pixelformat = xlate->cam_fmt->fourcc; | |
886 | /* limit to sensor capabilities */ | |
887 | ret = icd->ops->try_fmt(icd, f); | |
888 | pix->pixelformat = xlate->host_fmt->fourcc; | |
889 | ||
890 | field = pix->field; | |
891 | ||
892 | if (field == V4L2_FIELD_ANY) { | |
893 | pix->field = V4L2_FIELD_NONE; | |
894 | } else if (field != V4L2_FIELD_NONE) { | |
895 | dev_err(&icd->dev, "Field type %d unsupported.\n", field); | |
896 | return -EINVAL; | |
897 | } | |
898 | ||
899 | return ret; | |
900 | } | |
901 | ||
902 | static int mx3_camera_reqbufs(struct soc_camera_file *icf, | |
903 | struct v4l2_requestbuffers *p) | |
904 | { | |
905 | return 0; | |
906 | } | |
907 | ||
908 | static unsigned int mx3_camera_poll(struct file *file, poll_table *pt) | |
909 | { | |
910 | struct soc_camera_file *icf = file->private_data; | |
911 | ||
912 | return videobuf_poll_stream(file, &icf->vb_vidq, pt); | |
913 | } | |
914 | ||
915 | static int mx3_camera_querycap(struct soc_camera_host *ici, | |
916 | struct v4l2_capability *cap) | |
917 | { | |
918 | /* cap->name is set by the firendly caller:-> */ | |
919 | strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card)); | |
920 | cap->version = KERNEL_VERSION(0, 2, 2); | |
921 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
927 | { | |
928 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
929 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
930 | unsigned long bus_flags, camera_flags, common_flags; | |
931 | u32 dw, sens_conf; | |
932 | int ret = test_platform_param(mx3_cam, icd->buswidth, &bus_flags); | |
933 | const struct soc_camera_format_xlate *xlate; | |
934 | ||
935 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | |
936 | if (!xlate) { | |
eff505fa | 937 | dev_warn(ici->dev, "Format %x not found\n", pixfmt); |
4f67130a GL |
938 | return -EINVAL; |
939 | } | |
940 | ||
eff505fa | 941 | dev_dbg(ici->dev, "requested bus width %d bit: %d\n", |
4f67130a GL |
942 | icd->buswidth, ret); |
943 | ||
944 | if (ret < 0) | |
945 | return ret; | |
946 | ||
947 | camera_flags = icd->ops->query_bus_param(icd); | |
948 | ||
949 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
950 | if (!common_flags) { | |
eff505fa | 951 | dev_dbg(ici->dev, "no common flags: camera %lx, host %lx\n", |
4f67130a GL |
952 | camera_flags, bus_flags); |
953 | return -EINVAL; | |
954 | } | |
955 | ||
956 | /* Make choices, based on platform preferences */ | |
957 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
958 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
959 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) | |
960 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
961 | else | |
962 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
963 | } | |
964 | ||
965 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
966 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
967 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) | |
968 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
969 | else | |
970 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
971 | } | |
972 | ||
973 | if ((common_flags & SOCAM_DATA_ACTIVE_HIGH) && | |
974 | (common_flags & SOCAM_DATA_ACTIVE_LOW)) { | |
975 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) | |
976 | common_flags &= ~SOCAM_DATA_ACTIVE_HIGH; | |
977 | else | |
978 | common_flags &= ~SOCAM_DATA_ACTIVE_LOW; | |
979 | } | |
980 | ||
981 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
982 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
983 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) | |
984 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
985 | else | |
986 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
987 | } | |
988 | ||
989 | /* Make the camera work in widest common mode, we'll take care of | |
990 | * the rest */ | |
991 | if (common_flags & SOCAM_DATAWIDTH_15) | |
992 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
993 | SOCAM_DATAWIDTH_15; | |
994 | else if (common_flags & SOCAM_DATAWIDTH_10) | |
995 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
996 | SOCAM_DATAWIDTH_10; | |
997 | else if (common_flags & SOCAM_DATAWIDTH_8) | |
998 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
999 | SOCAM_DATAWIDTH_8; | |
1000 | else | |
1001 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
1002 | SOCAM_DATAWIDTH_4; | |
1003 | ||
1004 | ret = icd->ops->set_bus_param(icd, common_flags); | |
1005 | if (ret < 0) | |
1006 | return ret; | |
1007 | ||
1008 | /* | |
1009 | * So far only gated clock mode is supported. Add a line | |
1010 | * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) | | |
1011 | * below and select the required mode when supporting other | |
1012 | * synchronisation protocols. | |
1013 | */ | |
1014 | sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) & | |
1015 | ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) | | |
1016 | (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) | | |
1017 | (1 << CSI_SENS_CONF_DATA_POL_SHIFT) | | |
1018 | (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) | | |
1019 | (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) | | |
1020 | (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT)); | |
1021 | ||
1022 | /* TODO: Support RGB and YUV formats */ | |
1023 | ||
1024 | /* This has been set in mx3_camera_activate(), but we clear it above */ | |
1025 | sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
1026 | ||
1027 | if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) | |
1028 | sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; | |
1029 | if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) | |
1030 | sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; | |
1031 | if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) | |
1032 | sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; | |
1033 | if (common_flags & SOCAM_DATA_ACTIVE_LOW) | |
1034 | sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; | |
1035 | ||
1036 | /* Just do what we're asked to do */ | |
1037 | switch (xlate->host_fmt->depth) { | |
1038 | case 4: | |
1039 | dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1040 | break; | |
1041 | case 8: | |
1042 | dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1043 | break; | |
1044 | case 10: | |
1045 | dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1046 | break; | |
1047 | default: | |
1048 | /* | |
1049 | * Actually it can only be 15 now, default is just to silence | |
1050 | * compiler warnings | |
1051 | */ | |
1052 | case 15: | |
1053 | dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1054 | } | |
1055 | ||
1056 | csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF); | |
1057 | ||
eff505fa | 1058 | dev_dbg(ici->dev, "Set SENS_CONF to %x\n", sens_conf | dw); |
4f67130a GL |
1059 | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | static struct soc_camera_host_ops mx3_soc_camera_host_ops = { | |
1064 | .owner = THIS_MODULE, | |
1065 | .add = mx3_camera_add_device, | |
1066 | .remove = mx3_camera_remove_device, | |
09e231b3 | 1067 | .set_crop = mx3_camera_set_crop, |
4f67130a GL |
1068 | .set_fmt = mx3_camera_set_fmt, |
1069 | .try_fmt = mx3_camera_try_fmt, | |
1070 | .get_formats = mx3_camera_get_formats, | |
1071 | .init_videobuf = mx3_camera_init_videobuf, | |
1072 | .reqbufs = mx3_camera_reqbufs, | |
1073 | .poll = mx3_camera_poll, | |
1074 | .querycap = mx3_camera_querycap, | |
1075 | .set_bus_param = mx3_camera_set_bus_param, | |
1076 | }; | |
1077 | ||
e36bc31f | 1078 | static int __devinit mx3_camera_probe(struct platform_device *pdev) |
4f67130a GL |
1079 | { |
1080 | struct mx3_camera_dev *mx3_cam; | |
1081 | struct resource *res; | |
1082 | void __iomem *base; | |
1083 | int err = 0; | |
1084 | struct soc_camera_host *soc_host; | |
1085 | ||
1086 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1087 | if (!res) { | |
1088 | err = -ENODEV; | |
1089 | goto egetres; | |
1090 | } | |
1091 | ||
1092 | mx3_cam = vmalloc(sizeof(*mx3_cam)); | |
1093 | if (!mx3_cam) { | |
1094 | dev_err(&pdev->dev, "Could not allocate mx3 camera object\n"); | |
1095 | err = -ENOMEM; | |
1096 | goto ealloc; | |
1097 | } | |
1098 | memset(mx3_cam, 0, sizeof(*mx3_cam)); | |
1099 | ||
b71df97a | 1100 | mx3_cam->clk = clk_get(&pdev->dev, NULL); |
4f67130a GL |
1101 | if (IS_ERR(mx3_cam->clk)) { |
1102 | err = PTR_ERR(mx3_cam->clk); | |
1103 | goto eclkget; | |
1104 | } | |
1105 | ||
4f67130a GL |
1106 | mx3_cam->pdata = pdev->dev.platform_data; |
1107 | mx3_cam->platform_flags = mx3_cam->pdata->flags; | |
1108 | if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 | | |
1109 | MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 | | |
1110 | MX3_CAMERA_DATAWIDTH_15))) { | |
1111 | /* Platform hasn't set available data widths. This is bad. | |
1112 | * Warn and use a default. */ | |
1113 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " | |
1114 | "data widths, using default 8 bit\n"); | |
1115 | mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8; | |
1116 | } | |
1117 | ||
1118 | mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000; | |
1119 | if (!mx3_cam->mclk) { | |
1120 | dev_warn(&pdev->dev, | |
1121 | "mclk_10khz == 0! Please, fix your platform data. " | |
1122 | "Using default 20MHz\n"); | |
1123 | mx3_cam->mclk = 20000000; | |
1124 | } | |
1125 | ||
1126 | /* list of video-buffers */ | |
1127 | INIT_LIST_HEAD(&mx3_cam->capture); | |
1128 | spin_lock_init(&mx3_cam->lock); | |
1129 | ||
1130 | base = ioremap(res->start, res->end - res->start + 1); | |
1131 | if (!base) { | |
1132 | err = -ENOMEM; | |
1133 | goto eioremap; | |
1134 | } | |
1135 | ||
1136 | mx3_cam->base = base; | |
4f67130a GL |
1137 | |
1138 | soc_host = &mx3_cam->soc_host; | |
1139 | soc_host->drv_name = MX3_CAM_DRV_NAME; | |
1140 | soc_host->ops = &mx3_soc_camera_host_ops; | |
1141 | soc_host->priv = mx3_cam; | |
eff505fa | 1142 | soc_host->dev = &pdev->dev; |
4f67130a | 1143 | soc_host->nr = pdev->id; |
eff505fa | 1144 | |
4f67130a GL |
1145 | err = soc_camera_host_register(soc_host); |
1146 | if (err) | |
1147 | goto ecamhostreg; | |
1148 | ||
1149 | /* IDMAC interface */ | |
1150 | dmaengine_get(); | |
1151 | ||
1152 | return 0; | |
1153 | ||
1154 | ecamhostreg: | |
1155 | iounmap(base); | |
1156 | eioremap: | |
1157 | clk_put(mx3_cam->clk); | |
1158 | eclkget: | |
1159 | vfree(mx3_cam); | |
1160 | ealloc: | |
1161 | egetres: | |
1162 | return err; | |
1163 | } | |
1164 | ||
1165 | static int __devexit mx3_camera_remove(struct platform_device *pdev) | |
1166 | { | |
eff505fa GL |
1167 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1168 | struct mx3_camera_dev *mx3_cam = container_of(soc_host, | |
1169 | struct mx3_camera_dev, soc_host); | |
4f67130a GL |
1170 | |
1171 | clk_put(mx3_cam->clk); | |
1172 | ||
eff505fa | 1173 | soc_camera_host_unregister(soc_host); |
4f67130a GL |
1174 | |
1175 | iounmap(mx3_cam->base); | |
1176 | ||
1177 | /* | |
1178 | * The channel has either not been allocated, | |
1179 | * or should have been released | |
1180 | */ | |
1181 | if (WARN_ON(mx3_cam->idmac_channel[0])) | |
1182 | dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan); | |
1183 | ||
1184 | vfree(mx3_cam); | |
1185 | ||
1186 | dmaengine_put(); | |
1187 | ||
1188 | dev_info(&pdev->dev, "i.MX3x Camera driver unloaded\n"); | |
1189 | ||
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | static struct platform_driver mx3_camera_driver = { | |
1194 | .driver = { | |
1195 | .name = MX3_CAM_DRV_NAME, | |
1196 | }, | |
1197 | .probe = mx3_camera_probe, | |
e36bc31f | 1198 | .remove = __devexit_p(mx3_camera_remove), |
4f67130a GL |
1199 | }; |
1200 | ||
1201 | ||
e36bc31f | 1202 | static int __init mx3_camera_init(void) |
4f67130a GL |
1203 | { |
1204 | return platform_driver_register(&mx3_camera_driver); | |
1205 | } | |
1206 | ||
1207 | static void __exit mx3_camera_exit(void) | |
1208 | { | |
1209 | platform_driver_unregister(&mx3_camera_driver); | |
1210 | } | |
1211 | ||
1212 | module_init(mx3_camera_init); | |
1213 | module_exit(mx3_camera_exit); | |
1214 | ||
1215 | MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver"); | |
1216 | MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>"); | |
1217 | MODULE_LICENSE("GPL v2"); |