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448de7e7 SA |
1 | /* |
2 | * isp.h | |
3 | * | |
4 | * TI OMAP3 ISP - Core | |
5 | * | |
6 | * Copyright (C) 2009-2010 Nokia Corporation | |
7 | * Copyright (C) 2009 Texas Instruments, Inc. | |
8 | * | |
9 | * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
10 | * Sakari Ailus <sakari.ailus@iki.fi> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
24 | * 02110-1301 USA | |
25 | */ | |
26 | ||
27 | #ifndef OMAP3_ISP_CORE_H | |
28 | #define OMAP3_ISP_CORE_H | |
29 | ||
30 | #include <media/v4l2-device.h> | |
31 | #include <linux/device.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/wait.h> | |
f626b52d | 35 | #include <linux/iommu.h> |
448de7e7 SA |
36 | #include <plat/iommu.h> |
37 | #include <plat/iovmm.h> | |
38 | ||
39 | #include "ispstat.h" | |
40 | #include "ispccdc.h" | |
41 | #include "ispreg.h" | |
42 | #include "ispresizer.h" | |
43 | #include "isppreview.h" | |
44 | #include "ispcsiphy.h" | |
45 | #include "ispcsi2.h" | |
46 | #include "ispccp2.h" | |
47 | ||
48 | #define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8) | |
49 | ||
50 | #define ISP_TOK_TERM 0xFFFFFFFF /* | |
51 | * terminating token for ISP | |
52 | * modules reg list | |
53 | */ | |
54 | #define to_isp_device(ptr_module) \ | |
55 | container_of(ptr_module, struct isp_device, isp_##ptr_module) | |
56 | #define to_device(ptr_module) \ | |
57 | (to_isp_device(ptr_module)->dev) | |
58 | ||
59 | enum isp_mem_resources { | |
60 | OMAP3_ISP_IOMEM_MAIN, | |
61 | OMAP3_ISP_IOMEM_CCP2, | |
62 | OMAP3_ISP_IOMEM_CCDC, | |
63 | OMAP3_ISP_IOMEM_HIST, | |
64 | OMAP3_ISP_IOMEM_H3A, | |
65 | OMAP3_ISP_IOMEM_PREV, | |
66 | OMAP3_ISP_IOMEM_RESZ, | |
67 | OMAP3_ISP_IOMEM_SBL, | |
68 | OMAP3_ISP_IOMEM_CSI2A_REGS1, | |
69 | OMAP3_ISP_IOMEM_CSIPHY2, | |
70 | OMAP3_ISP_IOMEM_CSI2A_REGS2, | |
71 | OMAP3_ISP_IOMEM_CSI2C_REGS1, | |
72 | OMAP3_ISP_IOMEM_CSIPHY1, | |
73 | OMAP3_ISP_IOMEM_CSI2C_REGS2, | |
74 | OMAP3_ISP_IOMEM_LAST | |
75 | }; | |
76 | ||
77 | enum isp_sbl_resource { | |
78 | OMAP3_ISP_SBL_CSI1_READ = 0x1, | |
79 | OMAP3_ISP_SBL_CSI1_WRITE = 0x2, | |
80 | OMAP3_ISP_SBL_CSI2A_WRITE = 0x4, | |
81 | OMAP3_ISP_SBL_CSI2C_WRITE = 0x8, | |
82 | OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10, | |
83 | OMAP3_ISP_SBL_CCDC_WRITE = 0x20, | |
84 | OMAP3_ISP_SBL_PREVIEW_READ = 0x40, | |
85 | OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80, | |
86 | OMAP3_ISP_SBL_RESIZER_READ = 0x100, | |
87 | OMAP3_ISP_SBL_RESIZER_WRITE = 0x200, | |
88 | }; | |
89 | ||
90 | enum isp_subclk_resource { | |
91 | OMAP3_ISP_SUBCLK_CCDC = (1 << 0), | |
92 | OMAP3_ISP_SUBCLK_H3A = (1 << 1), | |
93 | OMAP3_ISP_SUBCLK_HIST = (1 << 2), | |
94 | OMAP3_ISP_SUBCLK_PREVIEW = (1 << 3), | |
95 | OMAP3_ISP_SUBCLK_RESIZER = (1 << 4), | |
96 | }; | |
97 | ||
98 | enum isp_interface_type { | |
99 | ISP_INTERFACE_PARALLEL, | |
100 | ISP_INTERFACE_CSI2A_PHY2, | |
101 | ISP_INTERFACE_CCP2B_PHY1, | |
102 | ISP_INTERFACE_CCP2B_PHY2, | |
103 | ISP_INTERFACE_CSI2C_PHY1, | |
104 | }; | |
105 | ||
106 | /* ISP: OMAP 34xx ES 1.0 */ | |
107 | #define ISP_REVISION_1_0 0x10 | |
108 | /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */ | |
109 | #define ISP_REVISION_2_0 0x20 | |
110 | /* ISP2P: OMAP 36xx */ | |
111 | #define ISP_REVISION_15_0 0xF0 | |
112 | ||
113 | /* | |
114 | * struct isp_res_mapping - Map ISP io resources to ISP revision. | |
115 | * @isp_rev: ISP_REVISION_x_x | |
116 | * @map: bitmap for enum isp_mem_resources | |
117 | */ | |
118 | struct isp_res_mapping { | |
119 | u32 isp_rev; | |
120 | u32 map; | |
121 | }; | |
122 | ||
123 | /* | |
124 | * struct isp_reg - Structure for ISP register values. | |
125 | * @reg: 32-bit Register address. | |
126 | * @val: 32-bit Register value. | |
127 | */ | |
128 | struct isp_reg { | |
129 | enum isp_mem_resources mmio_range; | |
130 | u32 reg; | |
131 | u32 val; | |
132 | }; | |
133 | ||
134 | /** | |
135 | * struct isp_parallel_platform_data - Parallel interface platform data | |
448de7e7 SA |
136 | * @data_lane_shift: Data lane shifter |
137 | * 0 - CAMEXT[13:0] -> CAM[13:0] | |
138 | * 1 - CAMEXT[13:2] -> CAM[11:0] | |
139 | * 2 - CAMEXT[13:4] -> CAM[9:0] | |
140 | * 3 - CAMEXT[13:6] -> CAM[7:0] | |
141 | * @clk_pol: Pixel clock polarity | |
142 | * 0 - Non Inverted, 1 - Inverted | |
1752cd5d LP |
143 | * @hs_pol: Horizontal synchronization polarity |
144 | * 0 - Active high, 1 - Active low | |
145 | * @vs_pol: Vertical synchronization polarity | |
146 | * 0 - Active high, 1 - Active low | |
448de7e7 SA |
147 | * @bridge: CCDC Bridge input control |
148 | * ISPCTRL_PAR_BRIDGE_DISABLE - Disable | |
149 | * ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian | |
150 | * ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian | |
151 | */ | |
152 | struct isp_parallel_platform_data { | |
448de7e7 SA |
153 | unsigned int data_lane_shift:2; |
154 | unsigned int clk_pol:1; | |
1752cd5d LP |
155 | unsigned int hs_pol:1; |
156 | unsigned int vs_pol:1; | |
448de7e7 SA |
157 | unsigned int bridge:4; |
158 | }; | |
159 | ||
160 | /** | |
161 | * struct isp_ccp2_platform_data - CCP2 interface platform data | |
162 | * @strobe_clk_pol: Strobe/clock polarity | |
163 | * 0 - Non Inverted, 1 - Inverted | |
164 | * @crc: Enable the cyclic redundancy check | |
165 | * @ccp2_mode: Enable CCP2 compatibility mode | |
166 | * 0 - MIPI-CSI1 mode, 1 - CCP2 mode | |
167 | * @phy_layer: Physical layer selection | |
168 | * ISPCCP2_CTRL_PHY_SEL_CLOCK - Data/clock physical layer | |
169 | * ISPCCP2_CTRL_PHY_SEL_STROBE - Data/strobe physical layer | |
170 | * @vpclk_div: Video port output clock control | |
171 | */ | |
172 | struct isp_ccp2_platform_data { | |
173 | unsigned int strobe_clk_pol:1; | |
174 | unsigned int crc:1; | |
175 | unsigned int ccp2_mode:1; | |
176 | unsigned int phy_layer:1; | |
177 | unsigned int vpclk_div:2; | |
178 | }; | |
179 | ||
180 | /** | |
181 | * struct isp_csi2_platform_data - CSI2 interface platform data | |
182 | * @crc: Enable the cyclic redundancy check | |
183 | * @vpclk_div: Video port output clock control | |
184 | */ | |
185 | struct isp_csi2_platform_data { | |
186 | unsigned crc:1; | |
187 | unsigned vpclk_div:2; | |
188 | }; | |
189 | ||
190 | struct isp_subdev_i2c_board_info { | |
191 | struct i2c_board_info *board_info; | |
192 | int i2c_adapter_id; | |
193 | }; | |
194 | ||
195 | struct isp_v4l2_subdevs_group { | |
196 | struct isp_subdev_i2c_board_info *subdevs; | |
197 | enum isp_interface_type interface; | |
198 | union { | |
199 | struct isp_parallel_platform_data parallel; | |
200 | struct isp_ccp2_platform_data ccp2; | |
201 | struct isp_csi2_platform_data csi2; | |
202 | } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */ | |
203 | }; | |
204 | ||
205 | struct isp_platform_data { | |
206 | struct isp_v4l2_subdevs_group *subdevs; | |
4b0ec19e | 207 | void (*set_constraints)(struct isp_device *isp, bool enable); |
448de7e7 SA |
208 | }; |
209 | ||
210 | struct isp_platform_callback { | |
211 | u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel); | |
212 | int (*csiphy_config)(struct isp_csiphy *phy, | |
213 | struct isp_csiphy_dphy_cfg *dphy, | |
214 | struct isp_csiphy_lanes_cfg *lanes); | |
215 | void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk); | |
216 | }; | |
217 | ||
218 | /* | |
219 | * struct isp_device - ISP device structure. | |
220 | * @dev: Device pointer specific to the OMAP3 ISP. | |
221 | * @revision: Stores current ISP module revision. | |
222 | * @irq_num: Currently used IRQ number. | |
223 | * @mmio_base: Array with kernel base addresses for ioremapped ISP register | |
224 | * regions. | |
225 | * @mmio_base_phys: Array with physical L4 bus addresses for ISP register | |
226 | * regions. | |
227 | * @mmio_size: Array with ISP register regions size in bytes. | |
228 | * @raw_dmamask: Raw DMA mask | |
229 | * @stat_lock: Spinlock for handling statistics | |
230 | * @isp_mutex: Mutex for serializing requests to ISP. | |
231 | * @has_context: Context has been saved at least once and can be restored. | |
232 | * @ref_count: Reference count for handling multiple ISP requests. | |
233 | * @cam_ick: Pointer to camera interface clock structure. | |
234 | * @cam_mclk: Pointer to camera functional clock structure. | |
235 | * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure. | |
236 | * @csi2_fck: Pointer to camera CSI2 complexIO clock structure. | |
237 | * @l3_ick: Pointer to OMAP3 L3 bus interface clock. | |
238 | * @irq: Currently attached ISP ISR callbacks information structure. | |
239 | * @isp_af: Pointer to current settings for ISP AutoFocus SCM. | |
240 | * @isp_hist: Pointer to current settings for ISP Histogram SCM. | |
241 | * @isp_h3a: Pointer to current settings for ISP Auto Exposure and | |
242 | * White Balance SCM. | |
243 | * @isp_res: Pointer to current settings for ISP Resizer. | |
244 | * @isp_prev: Pointer to current settings for ISP Preview. | |
245 | * @isp_ccdc: Pointer to current settings for ISP CCDC. | |
246 | * @iommu: Pointer to requested IOMMU instance for ISP. | |
247 | * @platform_cb: ISP driver callback function pointers for platform code | |
248 | * | |
249 | * This structure is used to store the OMAP ISP Information. | |
250 | */ | |
251 | struct isp_device { | |
252 | struct v4l2_device v4l2_dev; | |
253 | struct media_device media_dev; | |
254 | struct device *dev; | |
255 | u32 revision; | |
256 | ||
257 | /* platform HW resources */ | |
258 | struct isp_platform_data *pdata; | |
259 | unsigned int irq_num; | |
260 | ||
261 | void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST]; | |
262 | unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST]; | |
263 | resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST]; | |
264 | ||
265 | u64 raw_dmamask; | |
266 | ||
267 | /* ISP Obj */ | |
268 | spinlock_t stat_lock; /* common lock for statistic drivers */ | |
269 | struct mutex isp_mutex; /* For handling ref_count field */ | |
994d5375 | 270 | bool needs_reset; |
448de7e7 SA |
271 | int has_context; |
272 | int ref_count; | |
273 | unsigned int autoidle; | |
274 | u32 xclk_divisor[2]; /* Two clocks, a and b. */ | |
275 | #define ISP_CLK_CAM_ICK 0 | |
276 | #define ISP_CLK_CAM_MCLK 1 | |
277 | #define ISP_CLK_DPLL4_M5_CK 2 | |
278 | #define ISP_CLK_CSI2_FCK 3 | |
279 | #define ISP_CLK_L3_ICK 4 | |
280 | struct clk *clock[5]; | |
281 | ||
282 | /* ISP modules */ | |
283 | struct ispstat isp_af; | |
284 | struct ispstat isp_aewb; | |
285 | struct ispstat isp_hist; | |
286 | struct isp_res_device isp_res; | |
287 | struct isp_prev_device isp_prev; | |
288 | struct isp_ccdc_device isp_ccdc; | |
289 | struct isp_csi2_device isp_csi2a; | |
290 | struct isp_csi2_device isp_csi2c; | |
291 | struct isp_ccp2_device isp_ccp2; | |
292 | struct isp_csiphy isp_csiphy1; | |
293 | struct isp_csiphy isp_csiphy2; | |
294 | ||
295 | unsigned int sbl_resources; | |
296 | unsigned int subclk_resources; | |
297 | ||
6c32df43 | 298 | struct omap_iommu *iommu; |
f626b52d OBC |
299 | struct iommu_domain *domain; |
300 | struct device *iommu_dev; | |
448de7e7 SA |
301 | |
302 | struct isp_platform_callback platform_cb; | |
303 | }; | |
304 | ||
305 | #define v4l2_dev_to_isp_device(dev) \ | |
306 | container_of(dev, struct isp_device, v4l2_dev) | |
307 | ||
308 | void omap3isp_hist_dma_done(struct isp_device *isp); | |
309 | ||
310 | void omap3isp_flush(struct isp_device *isp); | |
311 | ||
312 | int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, | |
313 | atomic_t *stopping); | |
314 | ||
315 | int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait, | |
316 | atomic_t *stopping); | |
317 | ||
318 | int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe, | |
319 | enum isp_pipeline_stream_state state); | |
320 | void omap3isp_configure_bridge(struct isp_device *isp, | |
321 | enum ccdc_input_entity input, | |
c09af044 MJ |
322 | const struct isp_parallel_platform_data *pdata, |
323 | unsigned int shift); | |
448de7e7 | 324 | |
7c2c8f42 SV |
325 | #define ISP_XCLK_NONE 0 |
326 | #define ISP_XCLK_A 1 | |
327 | #define ISP_XCLK_B 2 | |
448de7e7 SA |
328 | |
329 | struct isp_device *omap3isp_get(struct isp_device *isp); | |
330 | void omap3isp_put(struct isp_device *isp); | |
331 | ||
332 | void omap3isp_print_status(struct isp_device *isp); | |
333 | ||
334 | void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res); | |
335 | void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res); | |
336 | ||
337 | void omap3isp_subclk_enable(struct isp_device *isp, | |
338 | enum isp_subclk_resource res); | |
339 | void omap3isp_subclk_disable(struct isp_device *isp, | |
340 | enum isp_subclk_resource res); | |
341 | ||
342 | int omap3isp_pipeline_pm_use(struct media_entity *entity, int use); | |
343 | ||
344 | int omap3isp_register_entities(struct platform_device *pdev, | |
345 | struct v4l2_device *v4l2_dev); | |
346 | void omap3isp_unregister_entities(struct platform_device *pdev); | |
347 | ||
348 | /* | |
349 | * isp_reg_readl - Read value of an OMAP3 ISP register | |
350 | * @dev: Device pointer specific to the OMAP3 ISP. | |
351 | * @isp_mmio_range: Range to which the register offset refers to. | |
352 | * @reg_offset: Register offset to read from. | |
353 | * | |
354 | * Returns an unsigned 32 bit value with the required register contents. | |
355 | */ | |
356 | static inline | |
357 | u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, | |
358 | u32 reg_offset) | |
359 | { | |
360 | return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); | |
361 | } | |
362 | ||
363 | /* | |
364 | * isp_reg_writel - Write value to an OMAP3 ISP register | |
365 | * @dev: Device pointer specific to the OMAP3 ISP. | |
366 | * @reg_value: 32 bit value to write to the register. | |
367 | * @isp_mmio_range: Range to which the register offset refers to. | |
368 | * @reg_offset: Register offset to write into. | |
369 | */ | |
370 | static inline | |
371 | void isp_reg_writel(struct isp_device *isp, u32 reg_value, | |
372 | enum isp_mem_resources isp_mmio_range, u32 reg_offset) | |
373 | { | |
374 | __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset); | |
375 | } | |
376 | ||
377 | /* | |
378 | * isp_reg_and - Clear individual bits in an OMAP3 ISP register | |
379 | * @dev: Device pointer specific to the OMAP3 ISP. | |
380 | * @mmio_range: Range to which the register offset refers to. | |
381 | * @reg: Register offset to work on. | |
382 | * @clr_bits: 32 bit value which would be cleared in the register. | |
383 | */ | |
384 | static inline | |
385 | void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range, | |
386 | u32 reg, u32 clr_bits) | |
387 | { | |
388 | u32 v = isp_reg_readl(isp, mmio_range, reg); | |
389 | ||
390 | isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg); | |
391 | } | |
392 | ||
393 | /* | |
394 | * isp_reg_set - Set individual bits in an OMAP3 ISP register | |
395 | * @dev: Device pointer specific to the OMAP3 ISP. | |
396 | * @mmio_range: Range to which the register offset refers to. | |
397 | * @reg: Register offset to work on. | |
398 | * @set_bits: 32 bit value which would be set in the register. | |
399 | */ | |
400 | static inline | |
401 | void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, | |
402 | u32 reg, u32 set_bits) | |
403 | { | |
404 | u32 v = isp_reg_readl(isp, mmio_range, reg); | |
405 | ||
406 | isp_reg_writel(isp, v | set_bits, mmio_range, reg); | |
407 | } | |
408 | ||
409 | /* | |
410 | * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register | |
411 | * @dev: Device pointer specific to the OMAP3 ISP. | |
412 | * @mmio_range: Range to which the register offset refers to. | |
413 | * @reg: Register offset to work on. | |
414 | * @clr_bits: 32 bit value which would be cleared in the register. | |
415 | * @set_bits: 32 bit value which would be set in the register. | |
416 | * | |
417 | * The clear operation is done first, and then the set operation. | |
418 | */ | |
419 | static inline | |
420 | void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range, | |
421 | u32 reg, u32 clr_bits, u32 set_bits) | |
422 | { | |
423 | u32 v = isp_reg_readl(isp, mmio_range, reg); | |
424 | ||
425 | isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); | |
426 | } | |
427 | ||
428 | static inline enum v4l2_buf_type | |
429 | isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad) | |
430 | { | |
431 | if (pad >= subdev->entity.num_pads) | |
432 | return 0; | |
433 | ||
434 | if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK) | |
435 | return V4L2_BUF_TYPE_VIDEO_OUTPUT; | |
436 | else | |
437 | return V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
438 | } | |
439 | ||
440 | #endif /* OMAP3_ISP_CORE_H */ |