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de1135d4 LP |
1 | /* |
2 | * isppreview.c | |
3 | * | |
4 | * TI OMAP3 ISP driver - Preview module | |
5 | * | |
6 | * Copyright (C) 2010 Nokia Corporation | |
7 | * Copyright (C) 2009 Texas Instruments, Inc. | |
8 | * | |
9 | * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
10 | * Sakari Ailus <sakari.ailus@iki.fi> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
24 | * 02110-1301 USA | |
25 | */ | |
26 | ||
27 | #include <linux/device.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/mutex.h> | |
31 | #include <linux/uaccess.h> | |
32 | ||
33 | #include "isp.h" | |
34 | #include "ispreg.h" | |
35 | #include "isppreview.h" | |
36 | ||
25985edc | 37 | /* Default values in Office Fluorescent Light for RGBtoRGB Blending */ |
de1135d4 LP |
38 | static struct omap3isp_prev_rgbtorgb flr_rgb2rgb = { |
39 | { /* RGB-RGB Matrix */ | |
40 | {0x01E2, 0x0F30, 0x0FEE}, | |
41 | {0x0F9B, 0x01AC, 0x0FB9}, | |
42 | {0x0FE0, 0x0EC0, 0x0260} | |
43 | }, /* RGB Offset */ | |
44 | {0x0000, 0x0000, 0x0000} | |
45 | }; | |
46 | ||
25985edc | 47 | /* Default values in Office Fluorescent Light for RGB to YUV Conversion*/ |
de1135d4 LP |
48 | static struct omap3isp_prev_csc flr_prev_csc = { |
49 | { /* CSC Coef Matrix */ | |
50 | {66, 129, 25}, | |
51 | {-38, -75, 112}, | |
52 | {112, -94 , -18} | |
53 | }, /* CSC Offset */ | |
54 | {0x0, 0x0, 0x0} | |
55 | }; | |
56 | ||
25985edc | 57 | /* Default values in Office Fluorescent Light for CFA Gradient*/ |
de1135d4 LP |
58 | #define FLR_CFA_GRADTHRS_HORZ 0x28 |
59 | #define FLR_CFA_GRADTHRS_VERT 0x28 | |
60 | ||
25985edc | 61 | /* Default values in Office Fluorescent Light for Chroma Suppression*/ |
de1135d4 LP |
62 | #define FLR_CSUP_GAIN 0x0D |
63 | #define FLR_CSUP_THRES 0xEB | |
64 | ||
25985edc | 65 | /* Default values in Office Fluorescent Light for Noise Filter*/ |
de1135d4 LP |
66 | #define FLR_NF_STRGTH 0x03 |
67 | ||
68 | /* Default values for White Balance */ | |
69 | #define FLR_WBAL_DGAIN 0x100 | |
70 | #define FLR_WBAL_COEF 0x20 | |
71 | ||
25985edc | 72 | /* Default values in Office Fluorescent Light for Black Adjustment*/ |
de1135d4 LP |
73 | #define FLR_BLKADJ_BLUE 0x0 |
74 | #define FLR_BLKADJ_GREEN 0x0 | |
75 | #define FLR_BLKADJ_RED 0x0 | |
76 | ||
77 | #define DEF_DETECT_CORRECT_VAL 0xe | |
78 | ||
1f69fd97 LP |
79 | /* |
80 | * Margins and image size limits. | |
81 | * | |
82 | * The preview engine crops several rows and columns internally depending on | |
83 | * which filters are enabled. To avoid format changes when the filters are | |
84 | * enabled or disabled (which would prevent them from being turned on or off | |
85 | * during streaming), the driver assumes all the filters are enabled when | |
86 | * computing sink crop and source format limits. | |
87 | * | |
88 | * If a filter is disabled, additional cropping is automatically added at the | |
89 | * preview engine input by the driver to avoid overflow at line and frame end. | |
90 | * This is completely transparent for applications. | |
91 | * | |
92 | * Median filter 4 pixels | |
93 | * Noise filter, | |
94 | * Faulty pixels correction 4 pixels, 4 lines | |
95 | * CFA filter 4 pixels, 4 lines in Bayer mode | |
96 | * 2 lines in other modes | |
97 | * Color suppression 2 pixels | |
98 | * or luma enhancement | |
99 | * ------------------------------------------------------------- | |
100 | * Maximum total 14 pixels, 8 lines | |
101 | * | |
102 | * The color suppression and luma enhancement filters are applied after bayer to | |
103 | * YUV conversion. They thus can crop one pixel on the left and one pixel on the | |
104 | * right side of the image without changing the color pattern. When both those | |
105 | * filters are disabled, the driver must crop the two pixels on the same side of | |
106 | * the image to avoid changing the bayer pattern. The left margin is thus set to | |
107 | * 8 pixels and the right margin to 6 pixels. | |
108 | */ | |
109 | ||
110 | #define PREV_MARGIN_LEFT 8 | |
111 | #define PREV_MARGIN_RIGHT 6 | |
112 | #define PREV_MARGIN_TOP 4 | |
113 | #define PREV_MARGIN_BOTTOM 4 | |
114 | ||
059dc1d9 LP |
115 | #define PREV_MIN_IN_WIDTH 64 |
116 | #define PREV_MIN_IN_HEIGHT 8 | |
117 | #define PREV_MAX_IN_HEIGHT 16384 | |
118 | ||
ec0cae7a LP |
119 | #define PREV_MIN_OUT_WIDTH 0 |
120 | #define PREV_MIN_OUT_HEIGHT 0 | |
121 | #define PREV_MAX_OUT_WIDTH_REV_1 1280 | |
122 | #define PREV_MAX_OUT_WIDTH_REV_2 3300 | |
123 | #define PREV_MAX_OUT_WIDTH_REV_15 4096 | |
de1135d4 LP |
124 | |
125 | /* | |
126 | * Coeficient Tables for the submodules in Preview. | |
127 | * Array is initialised with the values from.the tables text file. | |
128 | */ | |
129 | ||
130 | /* | |
131 | * CFA Filter Coefficient Table | |
132 | * | |
133 | */ | |
134 | static u32 cfa_coef_table[] = { | |
135 | #include "cfa_coef_table.h" | |
136 | }; | |
137 | ||
138 | /* | |
139 | * Default Gamma Correction Table - All components | |
140 | */ | |
141 | static u32 gamma_table[] = { | |
142 | #include "gamma_table.h" | |
143 | }; | |
144 | ||
145 | /* | |
146 | * Noise Filter Threshold table | |
147 | */ | |
148 | static u32 noise_filter_table[] = { | |
149 | #include "noise_filter_table.h" | |
150 | }; | |
151 | ||
152 | /* | |
153 | * Luminance Enhancement Table | |
154 | */ | |
155 | static u32 luma_enhance_table[] = { | |
156 | #include "luma_enhance_table.h" | |
157 | }; | |
158 | ||
159 | /* | |
160 | * preview_enable_invalaw - Enable/Disable Inverse A-Law module in Preview. | |
161 | * @enable: 1 - Reverse the A-Law done in CCDC. | |
162 | */ | |
163 | static void | |
164 | preview_enable_invalaw(struct isp_prev_device *prev, u8 enable) | |
165 | { | |
166 | struct isp_device *isp = to_isp_device(prev); | |
167 | ||
168 | if (enable) | |
169 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
170 | ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW); | |
171 | else | |
172 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
173 | ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW); | |
174 | } | |
175 | ||
176 | /* | |
177 | * preview_enable_drkframe_capture - Enable/Disable of the darkframe capture. | |
178 | * @prev - | |
179 | * @enable: 1 - Enable, 0 - Disable | |
180 | * | |
181 | * NOTE: PRV_WSDR_ADDR and PRV_WADD_OFFSET must be set also | |
25985edc | 182 | * The process is applied for each captured frame. |
de1135d4 LP |
183 | */ |
184 | static void | |
185 | preview_enable_drkframe_capture(struct isp_prev_device *prev, u8 enable) | |
186 | { | |
187 | struct isp_device *isp = to_isp_device(prev); | |
188 | ||
189 | if (enable) | |
190 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
191 | ISPPRV_PCR_DRKFCAP); | |
192 | else | |
193 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
194 | ISPPRV_PCR_DRKFCAP); | |
195 | } | |
196 | ||
197 | /* | |
198 | * preview_enable_drkframe - Enable/Disable of the darkframe subtract. | |
199 | * @enable: 1 - Acquires memory bandwidth since the pixels in each frame is | |
200 | * subtracted with the pixels in the current frame. | |
201 | * | |
25985edc | 202 | * The process is applied for each captured frame. |
de1135d4 LP |
203 | */ |
204 | static void | |
205 | preview_enable_drkframe(struct isp_prev_device *prev, u8 enable) | |
206 | { | |
207 | struct isp_device *isp = to_isp_device(prev); | |
208 | ||
209 | if (enable) | |
210 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
211 | ISPPRV_PCR_DRKFEN); | |
212 | else | |
213 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
214 | ISPPRV_PCR_DRKFEN); | |
215 | } | |
216 | ||
217 | /* | |
218 | * preview_config_drkf_shadcomp - Configures shift value in shading comp. | |
219 | * @scomp_shtval: 3bit value of shift used in shading compensation. | |
220 | */ | |
221 | static void | |
222 | preview_config_drkf_shadcomp(struct isp_prev_device *prev, | |
223 | const void *scomp_shtval) | |
224 | { | |
225 | struct isp_device *isp = to_isp_device(prev); | |
226 | const u32 *shtval = scomp_shtval; | |
227 | ||
228 | isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
229 | ISPPRV_PCR_SCOMP_SFT_MASK, | |
230 | *shtval << ISPPRV_PCR_SCOMP_SFT_SHIFT); | |
231 | } | |
232 | ||
233 | /* | |
234 | * preview_enable_hmed - Enables/Disables of the Horizontal Median Filter. | |
235 | * @enable: 1 - Enables Horizontal Median Filter. | |
236 | */ | |
237 | static void | |
238 | preview_enable_hmed(struct isp_prev_device *prev, u8 enable) | |
239 | { | |
240 | struct isp_device *isp = to_isp_device(prev); | |
241 | ||
242 | if (enable) | |
243 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
244 | ISPPRV_PCR_HMEDEN); | |
245 | else | |
246 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
247 | ISPPRV_PCR_HMEDEN); | |
248 | } | |
249 | ||
250 | /* | |
251 | * preview_config_hmed - Configures the Horizontal Median Filter. | |
252 | * @prev_hmed: Structure containing the odd and even distance between the | |
253 | * pixels in the image along with the filter threshold. | |
254 | */ | |
255 | static void | |
256 | preview_config_hmed(struct isp_prev_device *prev, const void *prev_hmed) | |
257 | { | |
258 | struct isp_device *isp = to_isp_device(prev); | |
259 | const struct omap3isp_prev_hmed *hmed = prev_hmed; | |
260 | ||
261 | isp_reg_writel(isp, (hmed->odddist == 1 ? 0 : ISPPRV_HMED_ODDDIST) | | |
262 | (hmed->evendist == 1 ? 0 : ISPPRV_HMED_EVENDIST) | | |
263 | (hmed->thres << ISPPRV_HMED_THRESHOLD_SHIFT), | |
264 | OMAP3_ISP_IOMEM_PREV, ISPPRV_HMED); | |
265 | } | |
266 | ||
267 | /* | |
268 | * preview_config_noisefilter - Configures the Noise Filter. | |
269 | * @prev_nf: Structure containing the noisefilter table, strength to be used | |
270 | * for the noise filter and the defect correction enable flag. | |
271 | */ | |
272 | static void | |
273 | preview_config_noisefilter(struct isp_prev_device *prev, const void *prev_nf) | |
274 | { | |
275 | struct isp_device *isp = to_isp_device(prev); | |
276 | const struct omap3isp_prev_nf *nf = prev_nf; | |
277 | unsigned int i; | |
278 | ||
279 | isp_reg_writel(isp, nf->spread, OMAP3_ISP_IOMEM_PREV, ISPPRV_NF); | |
280 | isp_reg_writel(isp, ISPPRV_NF_TABLE_ADDR, | |
281 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR); | |
282 | for (i = 0; i < OMAP3ISP_PREV_NF_TBL_SIZE; i++) { | |
283 | isp_reg_writel(isp, nf->table[i], | |
284 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA); | |
285 | } | |
286 | } | |
287 | ||
288 | /* | |
289 | * preview_config_dcor - Configures the defect correction | |
290 | * @prev_dcor: Structure containing the defect correct thresholds | |
291 | */ | |
292 | static void | |
293 | preview_config_dcor(struct isp_prev_device *prev, const void *prev_dcor) | |
294 | { | |
295 | struct isp_device *isp = to_isp_device(prev); | |
296 | const struct omap3isp_prev_dcor *dcor = prev_dcor; | |
297 | ||
298 | isp_reg_writel(isp, dcor->detect_correct[0], | |
299 | OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR0); | |
300 | isp_reg_writel(isp, dcor->detect_correct[1], | |
301 | OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR1); | |
302 | isp_reg_writel(isp, dcor->detect_correct[2], | |
303 | OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR2); | |
304 | isp_reg_writel(isp, dcor->detect_correct[3], | |
305 | OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR3); | |
306 | isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
307 | ISPPRV_PCR_DCCOUP, | |
308 | dcor->couplet_mode_en ? ISPPRV_PCR_DCCOUP : 0); | |
309 | } | |
310 | ||
311 | /* | |
312 | * preview_config_cfa - Configures the CFA Interpolation parameters. | |
313 | * @prev_cfa: Structure containing the CFA interpolation table, CFA format | |
314 | * in the image, vertical and horizontal gradient threshold. | |
315 | */ | |
316 | static void | |
317 | preview_config_cfa(struct isp_prev_device *prev, const void *prev_cfa) | |
318 | { | |
319 | struct isp_device *isp = to_isp_device(prev); | |
320 | const struct omap3isp_prev_cfa *cfa = prev_cfa; | |
321 | unsigned int i; | |
322 | ||
323 | isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
324 | ISPPRV_PCR_CFAFMT_MASK, | |
325 | cfa->format << ISPPRV_PCR_CFAFMT_SHIFT); | |
326 | ||
327 | isp_reg_writel(isp, | |
328 | (cfa->gradthrs_vert << ISPPRV_CFA_GRADTH_VER_SHIFT) | | |
329 | (cfa->gradthrs_horz << ISPPRV_CFA_GRADTH_HOR_SHIFT), | |
330 | OMAP3_ISP_IOMEM_PREV, ISPPRV_CFA); | |
331 | ||
332 | isp_reg_writel(isp, ISPPRV_CFA_TABLE_ADDR, | |
333 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR); | |
334 | ||
335 | for (i = 0; i < OMAP3ISP_PREV_CFA_TBL_SIZE; i++) { | |
336 | isp_reg_writel(isp, cfa->table[i], | |
337 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA); | |
338 | } | |
339 | } | |
340 | ||
341 | /* | |
342 | * preview_config_gammacorrn - Configures the Gamma Correction table values | |
343 | * @gtable: Structure containing the table for red, blue, green gamma table. | |
344 | */ | |
345 | static void | |
346 | preview_config_gammacorrn(struct isp_prev_device *prev, const void *gtable) | |
347 | { | |
348 | struct isp_device *isp = to_isp_device(prev); | |
349 | const struct omap3isp_prev_gtables *gt = gtable; | |
350 | unsigned int i; | |
351 | ||
352 | isp_reg_writel(isp, ISPPRV_REDGAMMA_TABLE_ADDR, | |
353 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR); | |
354 | for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++) | |
355 | isp_reg_writel(isp, gt->red[i], OMAP3_ISP_IOMEM_PREV, | |
356 | ISPPRV_SET_TBL_DATA); | |
357 | ||
358 | isp_reg_writel(isp, ISPPRV_GREENGAMMA_TABLE_ADDR, | |
359 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR); | |
360 | for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++) | |
361 | isp_reg_writel(isp, gt->green[i], OMAP3_ISP_IOMEM_PREV, | |
362 | ISPPRV_SET_TBL_DATA); | |
363 | ||
364 | isp_reg_writel(isp, ISPPRV_BLUEGAMMA_TABLE_ADDR, | |
365 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR); | |
366 | for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++) | |
367 | isp_reg_writel(isp, gt->blue[i], OMAP3_ISP_IOMEM_PREV, | |
368 | ISPPRV_SET_TBL_DATA); | |
369 | } | |
370 | ||
371 | /* | |
372 | * preview_config_luma_enhancement - Sets the Luminance Enhancement table. | |
373 | * @ytable: Structure containing the table for Luminance Enhancement table. | |
374 | */ | |
375 | static void | |
376 | preview_config_luma_enhancement(struct isp_prev_device *prev, | |
377 | const void *ytable) | |
378 | { | |
379 | struct isp_device *isp = to_isp_device(prev); | |
380 | const struct omap3isp_prev_luma *yt = ytable; | |
381 | unsigned int i; | |
382 | ||
383 | isp_reg_writel(isp, ISPPRV_YENH_TABLE_ADDR, | |
384 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR); | |
385 | for (i = 0; i < OMAP3ISP_PREV_YENH_TBL_SIZE; i++) { | |
386 | isp_reg_writel(isp, yt->table[i], | |
387 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA); | |
388 | } | |
389 | } | |
390 | ||
391 | /* | |
392 | * preview_config_chroma_suppression - Configures the Chroma Suppression. | |
393 | * @csup: Structure containing the threshold value for suppression | |
394 | * and the hypass filter enable flag. | |
395 | */ | |
396 | static void | |
397 | preview_config_chroma_suppression(struct isp_prev_device *prev, | |
398 | const void *csup) | |
399 | { | |
400 | struct isp_device *isp = to_isp_device(prev); | |
401 | const struct omap3isp_prev_csup *cs = csup; | |
402 | ||
403 | isp_reg_writel(isp, | |
404 | cs->gain | (cs->thres << ISPPRV_CSUP_THRES_SHIFT) | | |
405 | (cs->hypf_en << ISPPRV_CSUP_HPYF_SHIFT), | |
406 | OMAP3_ISP_IOMEM_PREV, ISPPRV_CSUP); | |
407 | } | |
408 | ||
409 | /* | |
410 | * preview_enable_noisefilter - Enables/Disables the Noise Filter. | |
411 | * @enable: 1 - Enables the Noise Filter. | |
412 | */ | |
413 | static void | |
414 | preview_enable_noisefilter(struct isp_prev_device *prev, u8 enable) | |
415 | { | |
416 | struct isp_device *isp = to_isp_device(prev); | |
417 | ||
418 | if (enable) | |
419 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
420 | ISPPRV_PCR_NFEN); | |
421 | else | |
422 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
423 | ISPPRV_PCR_NFEN); | |
424 | } | |
425 | ||
426 | /* | |
427 | * preview_enable_dcor - Enables/Disables the defect correction. | |
428 | * @enable: 1 - Enables the defect correction. | |
429 | */ | |
430 | static void | |
431 | preview_enable_dcor(struct isp_prev_device *prev, u8 enable) | |
432 | { | |
433 | struct isp_device *isp = to_isp_device(prev); | |
434 | ||
435 | if (enable) | |
436 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
437 | ISPPRV_PCR_DCOREN); | |
438 | else | |
439 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
440 | ISPPRV_PCR_DCOREN); | |
441 | } | |
442 | ||
de1135d4 LP |
443 | /* |
444 | * preview_enable_gammabypass - Enables/Disables the GammaByPass | |
445 | * @enable: 1 - Bypasses Gamma - 10bit input is cropped to 8MSB. | |
446 | * 0 - Goes through Gamma Correction. input and output is 10bit. | |
447 | */ | |
448 | static void | |
449 | preview_enable_gammabypass(struct isp_prev_device *prev, u8 enable) | |
450 | { | |
451 | struct isp_device *isp = to_isp_device(prev); | |
452 | ||
453 | if (enable) | |
454 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
455 | ISPPRV_PCR_GAMMA_BYPASS); | |
456 | else | |
457 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
458 | ISPPRV_PCR_GAMMA_BYPASS); | |
459 | } | |
460 | ||
461 | /* | |
462 | * preview_enable_luma_enhancement - Enables/Disables Luminance Enhancement | |
463 | * @enable: 1 - Enable the Luminance Enhancement. | |
464 | */ | |
465 | static void | |
466 | preview_enable_luma_enhancement(struct isp_prev_device *prev, u8 enable) | |
467 | { | |
468 | struct isp_device *isp = to_isp_device(prev); | |
469 | ||
470 | if (enable) | |
471 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
472 | ISPPRV_PCR_YNENHEN); | |
473 | else | |
474 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
475 | ISPPRV_PCR_YNENHEN); | |
476 | } | |
477 | ||
478 | /* | |
479 | * preview_enable_chroma_suppression - Enables/Disables Chrominance Suppr. | |
480 | * @enable: 1 - Enable the Chrominance Suppression. | |
481 | */ | |
482 | static void | |
483 | preview_enable_chroma_suppression(struct isp_prev_device *prev, u8 enable) | |
484 | { | |
485 | struct isp_device *isp = to_isp_device(prev); | |
486 | ||
487 | if (enable) | |
488 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
489 | ISPPRV_PCR_SUPEN); | |
490 | else | |
491 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
492 | ISPPRV_PCR_SUPEN); | |
493 | } | |
494 | ||
495 | /* | |
496 | * preview_config_whitebalance - Configures the White Balance parameters. | |
497 | * @prev_wbal: Structure containing the digital gain and white balance | |
498 | * coefficient. | |
499 | * | |
500 | * Coefficient matrix always with default values. | |
501 | */ | |
502 | static void | |
503 | preview_config_whitebalance(struct isp_prev_device *prev, const void *prev_wbal) | |
504 | { | |
505 | struct isp_device *isp = to_isp_device(prev); | |
506 | const struct omap3isp_prev_wbal *wbal = prev_wbal; | |
507 | u32 val; | |
508 | ||
509 | isp_reg_writel(isp, wbal->dgain, OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN); | |
510 | ||
511 | val = wbal->coef0 << ISPPRV_WBGAIN_COEF0_SHIFT; | |
512 | val |= wbal->coef1 << ISPPRV_WBGAIN_COEF1_SHIFT; | |
513 | val |= wbal->coef2 << ISPPRV_WBGAIN_COEF2_SHIFT; | |
514 | val |= wbal->coef3 << ISPPRV_WBGAIN_COEF3_SHIFT; | |
515 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN); | |
516 | ||
517 | isp_reg_writel(isp, | |
518 | ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_0_SHIFT | | |
519 | ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_1_SHIFT | | |
520 | ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_2_SHIFT | | |
521 | ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_3_SHIFT | | |
522 | ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_0_SHIFT | | |
523 | ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_1_SHIFT | | |
524 | ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_2_SHIFT | | |
525 | ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_3_SHIFT | | |
526 | ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_0_SHIFT | | |
527 | ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_1_SHIFT | | |
528 | ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_2_SHIFT | | |
529 | ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_3_SHIFT | | |
530 | ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_0_SHIFT | | |
531 | ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_1_SHIFT | | |
532 | ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_2_SHIFT | | |
533 | ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_3_SHIFT, | |
534 | OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL); | |
535 | } | |
536 | ||
537 | /* | |
538 | * preview_config_blkadj - Configures the Black Adjustment parameters. | |
539 | * @prev_blkadj: Structure containing the black adjustment towards red, green, | |
540 | * blue. | |
541 | */ | |
542 | static void | |
543 | preview_config_blkadj(struct isp_prev_device *prev, const void *prev_blkadj) | |
544 | { | |
545 | struct isp_device *isp = to_isp_device(prev); | |
546 | const struct omap3isp_prev_blkadj *blkadj = prev_blkadj; | |
547 | ||
548 | isp_reg_writel(isp, (blkadj->blue << ISPPRV_BLKADJOFF_B_SHIFT) | | |
549 | (blkadj->green << ISPPRV_BLKADJOFF_G_SHIFT) | | |
550 | (blkadj->red << ISPPRV_BLKADJOFF_R_SHIFT), | |
551 | OMAP3_ISP_IOMEM_PREV, ISPPRV_BLKADJOFF); | |
552 | } | |
553 | ||
554 | /* | |
555 | * preview_config_rgb_blending - Configures the RGB-RGB Blending matrix. | |
556 | * @rgb2rgb: Structure containing the rgb to rgb blending matrix and the rgb | |
557 | * offset. | |
558 | */ | |
559 | static void | |
560 | preview_config_rgb_blending(struct isp_prev_device *prev, const void *rgb2rgb) | |
561 | { | |
562 | struct isp_device *isp = to_isp_device(prev); | |
563 | const struct omap3isp_prev_rgbtorgb *rgbrgb = rgb2rgb; | |
564 | u32 val; | |
565 | ||
566 | val = (rgbrgb->matrix[0][0] & 0xfff) << ISPPRV_RGB_MAT1_MTX_RR_SHIFT; | |
567 | val |= (rgbrgb->matrix[0][1] & 0xfff) << ISPPRV_RGB_MAT1_MTX_GR_SHIFT; | |
568 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1); | |
569 | ||
570 | val = (rgbrgb->matrix[0][2] & 0xfff) << ISPPRV_RGB_MAT2_MTX_BR_SHIFT; | |
571 | val |= (rgbrgb->matrix[1][0] & 0xfff) << ISPPRV_RGB_MAT2_MTX_RG_SHIFT; | |
572 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2); | |
573 | ||
574 | val = (rgbrgb->matrix[1][1] & 0xfff) << ISPPRV_RGB_MAT3_MTX_GG_SHIFT; | |
575 | val |= (rgbrgb->matrix[1][2] & 0xfff) << ISPPRV_RGB_MAT3_MTX_BG_SHIFT; | |
576 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3); | |
577 | ||
578 | val = (rgbrgb->matrix[2][0] & 0xfff) << ISPPRV_RGB_MAT4_MTX_RB_SHIFT; | |
579 | val |= (rgbrgb->matrix[2][1] & 0xfff) << ISPPRV_RGB_MAT4_MTX_GB_SHIFT; | |
580 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4); | |
581 | ||
582 | val = (rgbrgb->matrix[2][2] & 0xfff) << ISPPRV_RGB_MAT5_MTX_BB_SHIFT; | |
583 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5); | |
584 | ||
585 | val = (rgbrgb->offset[0] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT; | |
586 | val |= (rgbrgb->offset[1] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT; | |
587 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1); | |
588 | ||
589 | val = (rgbrgb->offset[2] & 0x3ff) << ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT; | |
590 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2); | |
591 | } | |
592 | ||
593 | /* | |
6173850c | 594 | * Configures the color space conversion (RGB toYCbYCr) matrix |
de1135d4 LP |
595 | * @prev_csc: Structure containing the RGB to YCbYCr matrix and the |
596 | * YCbCr offset. | |
597 | */ | |
598 | static void | |
6173850c | 599 | preview_config_csc(struct isp_prev_device *prev, const void *prev_csc) |
de1135d4 LP |
600 | { |
601 | struct isp_device *isp = to_isp_device(prev); | |
602 | const struct omap3isp_prev_csc *csc = prev_csc; | |
603 | u32 val; | |
604 | ||
605 | val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT; | |
606 | val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT; | |
607 | val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT; | |
608 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0); | |
609 | ||
610 | val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT; | |
611 | val |= (csc->matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT; | |
612 | val |= (csc->matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT; | |
613 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1); | |
614 | ||
615 | val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT; | |
616 | val |= (csc->matrix[2][1] & 0x3ff) << ISPPRV_CSC2_GCR_SHIFT; | |
617 | val |= (csc->matrix[2][2] & 0x3ff) << ISPPRV_CSC2_BCR_SHIFT; | |
618 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2); | |
619 | ||
620 | val = (csc->offset[0] & 0xff) << ISPPRV_CSC_OFFSET_Y_SHIFT; | |
621 | val |= (csc->offset[1] & 0xff) << ISPPRV_CSC_OFFSET_CB_SHIFT; | |
622 | val |= (csc->offset[2] & 0xff) << ISPPRV_CSC_OFFSET_CR_SHIFT; | |
623 | isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET); | |
624 | } | |
625 | ||
626 | /* | |
627 | * preview_update_contrast - Updates the contrast. | |
628 | * @contrast: Pointer to hold the current programmed contrast value. | |
629 | * | |
630 | * Value should be programmed before enabling the module. | |
631 | */ | |
632 | static void | |
633 | preview_update_contrast(struct isp_prev_device *prev, u8 contrast) | |
634 | { | |
b0b29e1e LP |
635 | struct prev_params *params; |
636 | unsigned long flags; | |
637 | ||
638 | spin_lock_irqsave(&prev->params.lock, flags); | |
639 | params = (prev->params.active & OMAP3ISP_PREV_CONTRAST) | |
640 | ? &prev->params.params[0] : &prev->params.params[1]; | |
de1135d4 LP |
641 | |
642 | if (params->contrast != (contrast * ISPPRV_CONTRAST_UNITS)) { | |
643 | params->contrast = contrast * ISPPRV_CONTRAST_UNITS; | |
b0b29e1e | 644 | params->update |= OMAP3ISP_PREV_CONTRAST; |
de1135d4 | 645 | } |
b0b29e1e | 646 | spin_unlock_irqrestore(&prev->params.lock, flags); |
de1135d4 LP |
647 | } |
648 | ||
649 | /* | |
650 | * preview_config_contrast - Configures the Contrast. | |
651 | * @params: Contrast value (u8 pointer, U8Q0 format). | |
652 | * | |
653 | * Value should be programmed before enabling the module. | |
654 | */ | |
655 | static void | |
656 | preview_config_contrast(struct isp_prev_device *prev, const void *params) | |
657 | { | |
658 | struct isp_device *isp = to_isp_device(prev); | |
659 | ||
660 | isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT, | |
661 | 0xff << ISPPRV_CNT_BRT_CNT_SHIFT, | |
662 | *(u8 *)params << ISPPRV_CNT_BRT_CNT_SHIFT); | |
663 | } | |
664 | ||
665 | /* | |
666 | * preview_update_brightness - Updates the brightness in preview module. | |
667 | * @brightness: Pointer to hold the current programmed brightness value. | |
668 | * | |
669 | */ | |
670 | static void | |
671 | preview_update_brightness(struct isp_prev_device *prev, u8 brightness) | |
672 | { | |
b0b29e1e LP |
673 | struct prev_params *params; |
674 | unsigned long flags; | |
675 | ||
676 | spin_lock_irqsave(&prev->params.lock, flags); | |
677 | params = (prev->params.active & OMAP3ISP_PREV_BRIGHTNESS) | |
678 | ? &prev->params.params[0] : &prev->params.params[1]; | |
de1135d4 LP |
679 | |
680 | if (params->brightness != (brightness * ISPPRV_BRIGHT_UNITS)) { | |
681 | params->brightness = brightness * ISPPRV_BRIGHT_UNITS; | |
b0b29e1e | 682 | params->update |= OMAP3ISP_PREV_BRIGHTNESS; |
de1135d4 | 683 | } |
b0b29e1e | 684 | spin_unlock_irqrestore(&prev->params.lock, flags); |
de1135d4 LP |
685 | } |
686 | ||
687 | /* | |
688 | * preview_config_brightness - Configures the brightness. | |
689 | * @params: Brightness value (u8 pointer, U8Q0 format). | |
690 | */ | |
691 | static void | |
692 | preview_config_brightness(struct isp_prev_device *prev, const void *params) | |
693 | { | |
694 | struct isp_device *isp = to_isp_device(prev); | |
695 | ||
696 | isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT, | |
697 | 0xff << ISPPRV_CNT_BRT_BRT_SHIFT, | |
698 | *(u8 *)params << ISPPRV_CNT_BRT_BRT_SHIFT); | |
699 | } | |
700 | ||
701 | /* | |
702 | * preview_config_yc_range - Configures the max and min Y and C values. | |
703 | * @yclimit: Structure containing the range of Y and C values. | |
704 | */ | |
705 | static void | |
706 | preview_config_yc_range(struct isp_prev_device *prev, const void *yclimit) | |
707 | { | |
708 | struct isp_device *isp = to_isp_device(prev); | |
709 | const struct omap3isp_prev_yclimit *yc = yclimit; | |
710 | ||
711 | isp_reg_writel(isp, | |
712 | yc->maxC << ISPPRV_SETUP_YC_MAXC_SHIFT | | |
713 | yc->maxY << ISPPRV_SETUP_YC_MAXY_SHIFT | | |
714 | yc->minC << ISPPRV_SETUP_YC_MINC_SHIFT | | |
715 | yc->minY << ISPPRV_SETUP_YC_MINY_SHIFT, | |
716 | OMAP3_ISP_IOMEM_PREV, ISPPRV_SETUP_YC); | |
717 | } | |
718 | ||
b0b29e1e LP |
719 | static u32 |
720 | preview_params_lock(struct isp_prev_device *prev, u32 update, bool shadow) | |
721 | { | |
722 | u32 active = prev->params.active; | |
723 | ||
724 | if (shadow) { | |
725 | /* Mark all shadow parameters we are going to touch as busy. */ | |
726 | prev->params.params[0].busy |= ~active & update; | |
727 | prev->params.params[1].busy |= active & update; | |
728 | } else { | |
729 | /* Mark all active parameters we are going to touch as busy. */ | |
730 | update = (prev->params.params[0].update & active) | |
731 | | (prev->params.params[1].update & ~active); | |
732 | ||
733 | prev->params.params[0].busy |= active & update; | |
734 | prev->params.params[1].busy |= ~active & update; | |
735 | } | |
736 | ||
737 | return update; | |
738 | } | |
739 | ||
740 | static void | |
741 | preview_params_unlock(struct isp_prev_device *prev, u32 update, bool shadow) | |
742 | { | |
743 | u32 active = prev->params.active; | |
744 | ||
745 | if (shadow) { | |
746 | /* Set the update flag for shadow parameters that have been | |
747 | * updated and clear the busy flag for all shadow parameters. | |
748 | */ | |
749 | prev->params.params[0].update |= (~active & update); | |
750 | prev->params.params[1].update |= (active & update); | |
751 | prev->params.params[0].busy &= active; | |
752 | prev->params.params[1].busy &= ~active; | |
753 | } else { | |
754 | /* Clear the update flag for active parameters that have been | |
755 | * applied and the busy flag for all active parameters. | |
756 | */ | |
757 | prev->params.params[0].update &= ~(active & update); | |
758 | prev->params.params[1].update &= ~(~active & update); | |
759 | prev->params.params[0].busy &= ~active; | |
760 | prev->params.params[1].busy &= active; | |
761 | } | |
762 | } | |
763 | ||
764 | static void preview_params_switch(struct isp_prev_device *prev) | |
765 | { | |
766 | u32 to_switch; | |
767 | ||
768 | /* Switch active parameters with updated shadow parameters when the | |
769 | * shadow parameter has been updated and neither the active not the | |
770 | * shadow parameter is busy. | |
771 | */ | |
772 | to_switch = (prev->params.params[0].update & ~prev->params.active) | |
773 | | (prev->params.params[1].update & prev->params.active); | |
774 | to_switch &= ~(prev->params.params[0].busy | | |
775 | prev->params.params[1].busy); | |
776 | if (to_switch == 0) | |
777 | return; | |
778 | ||
779 | prev->params.active ^= to_switch; | |
780 | ||
781 | /* Remove the update flag for the shadow copy of parameters we have | |
782 | * switched. | |
783 | */ | |
784 | prev->params.params[0].update &= ~(~prev->params.active & to_switch); | |
785 | prev->params.params[1].update &= ~(prev->params.active & to_switch); | |
786 | } | |
787 | ||
de1135d4 LP |
788 | /* preview parameters update structure */ |
789 | struct preview_update { | |
de1135d4 LP |
790 | void (*config)(struct isp_prev_device *, const void *); |
791 | void (*enable)(struct isp_prev_device *, u8); | |
bac387ef LP |
792 | unsigned int param_offset; |
793 | unsigned int param_size; | |
794 | unsigned int config_offset; | |
3108e026 | 795 | bool skip; |
de1135d4 LP |
796 | }; |
797 | ||
7ed5de97 | 798 | /* Keep the array indexed by the OMAP3ISP_PREV_* bit number. */ |
bac387ef | 799 | static const struct preview_update update_attrs[] = { |
7ed5de97 | 800 | /* OMAP3ISP_PREV_LUMAENH */ { |
de1135d4 | 801 | preview_config_luma_enhancement, |
7ed5de97 | 802 | preview_enable_luma_enhancement, |
bac387ef LP |
803 | offsetof(struct prev_params, luma), |
804 | FIELD_SIZEOF(struct prev_params, luma), | |
805 | offsetof(struct omap3isp_prev_update_config, luma), | |
7ed5de97 | 806 | }, /* OMAP3ISP_PREV_INVALAW */ { |
de1135d4 | 807 | NULL, |
7ed5de97 LP |
808 | preview_enable_invalaw, |
809 | }, /* OMAP3ISP_PREV_HRZ_MED */ { | |
de1135d4 | 810 | preview_config_hmed, |
7ed5de97 | 811 | preview_enable_hmed, |
bac387ef LP |
812 | offsetof(struct prev_params, hmed), |
813 | FIELD_SIZEOF(struct prev_params, hmed), | |
814 | offsetof(struct omap3isp_prev_update_config, hmed), | |
7ed5de97 | 815 | }, /* OMAP3ISP_PREV_CFA */ { |
de1135d4 | 816 | preview_config_cfa, |
b2da46e5 | 817 | NULL, |
bac387ef LP |
818 | offsetof(struct prev_params, cfa), |
819 | FIELD_SIZEOF(struct prev_params, cfa), | |
820 | offsetof(struct omap3isp_prev_update_config, cfa), | |
7ed5de97 | 821 | }, /* OMAP3ISP_PREV_CHROMA_SUPP */ { |
de1135d4 | 822 | preview_config_chroma_suppression, |
7ed5de97 | 823 | preview_enable_chroma_suppression, |
bac387ef LP |
824 | offsetof(struct prev_params, csup), |
825 | FIELD_SIZEOF(struct prev_params, csup), | |
826 | offsetof(struct omap3isp_prev_update_config, csup), | |
7ed5de97 | 827 | }, /* OMAP3ISP_PREV_WB */ { |
de1135d4 | 828 | preview_config_whitebalance, |
7ed5de97 | 829 | NULL, |
bac387ef LP |
830 | offsetof(struct prev_params, wbal), |
831 | FIELD_SIZEOF(struct prev_params, wbal), | |
832 | offsetof(struct omap3isp_prev_update_config, wbal), | |
7ed5de97 | 833 | }, /* OMAP3ISP_PREV_BLKADJ */ { |
de1135d4 | 834 | preview_config_blkadj, |
7ed5de97 | 835 | NULL, |
bac387ef LP |
836 | offsetof(struct prev_params, blkadj), |
837 | FIELD_SIZEOF(struct prev_params, blkadj), | |
838 | offsetof(struct omap3isp_prev_update_config, blkadj), | |
7ed5de97 | 839 | }, /* OMAP3ISP_PREV_RGB2RGB */ { |
de1135d4 | 840 | preview_config_rgb_blending, |
7ed5de97 | 841 | NULL, |
bac387ef LP |
842 | offsetof(struct prev_params, rgb2rgb), |
843 | FIELD_SIZEOF(struct prev_params, rgb2rgb), | |
844 | offsetof(struct omap3isp_prev_update_config, rgb2rgb), | |
7ed5de97 | 845 | }, /* OMAP3ISP_PREV_COLOR_CONV */ { |
6173850c | 846 | preview_config_csc, |
7ed5de97 | 847 | NULL, |
bac387ef LP |
848 | offsetof(struct prev_params, csc), |
849 | FIELD_SIZEOF(struct prev_params, csc), | |
850 | offsetof(struct omap3isp_prev_update_config, csc), | |
7ed5de97 | 851 | }, /* OMAP3ISP_PREV_YC_LIMIT */ { |
de1135d4 | 852 | preview_config_yc_range, |
7ed5de97 | 853 | NULL, |
bac387ef LP |
854 | offsetof(struct prev_params, yclimit), |
855 | FIELD_SIZEOF(struct prev_params, yclimit), | |
856 | offsetof(struct omap3isp_prev_update_config, yclimit), | |
7ed5de97 | 857 | }, /* OMAP3ISP_PREV_DEFECT_COR */ { |
de1135d4 | 858 | preview_config_dcor, |
7ed5de97 | 859 | preview_enable_dcor, |
bac387ef LP |
860 | offsetof(struct prev_params, dcor), |
861 | FIELD_SIZEOF(struct prev_params, dcor), | |
862 | offsetof(struct omap3isp_prev_update_config, dcor), | |
7ed5de97 | 863 | }, /* OMAP3ISP_PREV_GAMMABYPASS */ { |
de1135d4 | 864 | NULL, |
7ed5de97 LP |
865 | preview_enable_gammabypass, |
866 | }, /* OMAP3ISP_PREV_DRK_FRM_CAPTURE */ { | |
de1135d4 | 867 | NULL, |
7ed5de97 LP |
868 | preview_enable_drkframe_capture, |
869 | }, /* OMAP3ISP_PREV_DRK_FRM_SUBTRACT */ { | |
de1135d4 | 870 | NULL, |
7ed5de97 LP |
871 | preview_enable_drkframe, |
872 | }, /* OMAP3ISP_PREV_LENS_SHADING */ { | |
de1135d4 | 873 | preview_config_drkf_shadcomp, |
7ed5de97 LP |
874 | preview_enable_drkframe, |
875 | }, /* OMAP3ISP_PREV_NF */ { | |
de1135d4 | 876 | preview_config_noisefilter, |
7ed5de97 | 877 | preview_enable_noisefilter, |
bac387ef LP |
878 | offsetof(struct prev_params, nf), |
879 | FIELD_SIZEOF(struct prev_params, nf), | |
880 | offsetof(struct omap3isp_prev_update_config, nf), | |
7ed5de97 | 881 | }, /* OMAP3ISP_PREV_GAMMA */ { |
de1135d4 | 882 | preview_config_gammacorrn, |
7ed5de97 | 883 | NULL, |
bac387ef LP |
884 | offsetof(struct prev_params, gamma), |
885 | FIELD_SIZEOF(struct prev_params, gamma), | |
886 | offsetof(struct omap3isp_prev_update_config, gamma), | |
7ed5de97 | 887 | }, /* OMAP3ISP_PREV_CONTRAST */ { |
de1135d4 | 888 | preview_config_contrast, |
bac387ef LP |
889 | NULL, |
890 | offsetof(struct prev_params, contrast), | |
5aedc109 | 891 | 0, 0, true, |
7ed5de97 | 892 | }, /* OMAP3ISP_PREV_BRIGHTNESS */ { |
de1135d4 | 893 | preview_config_brightness, |
bac387ef LP |
894 | NULL, |
895 | offsetof(struct prev_params, brightness), | |
5aedc109 | 896 | 0, 0, true, |
7ed5de97 | 897 | }, |
de1135d4 LP |
898 | }; |
899 | ||
de1135d4 LP |
900 | /* |
901 | * preview_config - Copy and update local structure with userspace preview | |
902 | * configuration. | |
903 | * @prev: ISP preview engine | |
904 | * @cfg: Configuration | |
905 | * | |
906 | * Return zero if success or -EFAULT if the configuration can't be copied from | |
907 | * userspace. | |
908 | */ | |
909 | static int preview_config(struct isp_prev_device *prev, | |
910 | struct omap3isp_prev_update_config *cfg) | |
911 | { | |
b0b29e1e LP |
912 | unsigned long flags; |
913 | unsigned int i; | |
914 | int rval = 0; | |
915 | u32 update; | |
916 | u32 active; | |
de1135d4 | 917 | |
f22926e0 LP |
918 | if (cfg->update == 0) |
919 | return 0; | |
920 | ||
b0b29e1e LP |
921 | /* Mark the shadow parameters we're going to update as busy. */ |
922 | spin_lock_irqsave(&prev->params.lock, flags); | |
923 | preview_params_lock(prev, cfg->update, true); | |
924 | active = prev->params.active; | |
925 | spin_unlock_irqrestore(&prev->params.lock, flags); | |
de1135d4 | 926 | |
b0b29e1e | 927 | update = 0; |
de1135d4 LP |
928 | |
929 | for (i = 0; i < ARRAY_SIZE(update_attrs); i++) { | |
b0b29e1e LP |
930 | const struct preview_update *attr = &update_attrs[i]; |
931 | struct prev_params *params; | |
932 | unsigned int bit = 1 << i; | |
de1135d4 | 933 | |
7ed5de97 | 934 | if (attr->skip || !(cfg->update & bit)) |
de1135d4 LP |
935 | continue; |
936 | ||
b0b29e1e LP |
937 | params = &prev->params.params[!!(active & bit)]; |
938 | ||
7ed5de97 | 939 | if (cfg->flag & bit) { |
b0b29e1e LP |
940 | void __user *from = *(void * __user *) |
941 | ((void *)cfg + attr->config_offset); | |
942 | void *to = (void *)params + attr->param_offset; | |
943 | size_t size = attr->param_size; | |
de1135d4 | 944 | |
b0b29e1e LP |
945 | if (to && from && size) { |
946 | if (copy_from_user(to, from, size)) { | |
de1135d4 LP |
947 | rval = -EFAULT; |
948 | break; | |
949 | } | |
950 | } | |
7ed5de97 | 951 | params->features |= bit; |
de1135d4 | 952 | } else { |
7ed5de97 | 953 | params->features &= ~bit; |
de1135d4 LP |
954 | } |
955 | ||
b0b29e1e | 956 | update |= bit; |
de1135d4 LP |
957 | } |
958 | ||
b0b29e1e LP |
959 | spin_lock_irqsave(&prev->params.lock, flags); |
960 | preview_params_unlock(prev, update, true); | |
961 | preview_params_switch(prev); | |
962 | spin_unlock_irqrestore(&prev->params.lock, flags); | |
963 | ||
de1135d4 LP |
964 | return rval; |
965 | } | |
966 | ||
967 | /* | |
968 | * preview_setup_hw - Setup preview registers and/or internal memory | |
969 | * @prev: pointer to preview private structure | |
b0b29e1e LP |
970 | * @update: Bitmask of parameters to setup |
971 | * @active: Bitmask of parameters active in set 0 | |
de1135d4 LP |
972 | * Note: can be called from interrupt context |
973 | * Return none | |
974 | */ | |
b0b29e1e LP |
975 | static void preview_setup_hw(struct isp_prev_device *prev, u32 update, |
976 | u32 active) | |
de1135d4 | 977 | { |
7ed5de97 | 978 | unsigned int i; |
b0b29e1e | 979 | u32 features; |
de1135d4 | 980 | |
b0b29e1e | 981 | if (update == 0) |
f22926e0 LP |
982 | return; |
983 | ||
b0b29e1e LP |
984 | features = (prev->params.params[0].features & active) |
985 | | (prev->params.params[1].features & ~active); | |
986 | ||
de1135d4 | 987 | for (i = 0; i < ARRAY_SIZE(update_attrs); i++) { |
b0b29e1e LP |
988 | const struct preview_update *attr = &update_attrs[i]; |
989 | struct prev_params *params; | |
990 | unsigned int bit = 1 << i; | |
991 | void *param_ptr; | |
de1135d4 | 992 | |
b0b29e1e | 993 | if (!(update & bit)) |
de1135d4 | 994 | continue; |
7ed5de97 | 995 | |
b0b29e1e LP |
996 | params = &prev->params.params[!(active & bit)]; |
997 | ||
7ed5de97 | 998 | if (params->features & bit) { |
de1135d4 | 999 | if (attr->config) { |
b0b29e1e | 1000 | param_ptr = (void *)params + attr->param_offset; |
de1135d4 LP |
1001 | attr->config(prev, param_ptr); |
1002 | } | |
1003 | if (attr->enable) | |
1004 | attr->enable(prev, 1); | |
b0b29e1e | 1005 | } else { |
de1135d4 LP |
1006 | if (attr->enable) |
1007 | attr->enable(prev, 0); | |
b0b29e1e | 1008 | } |
de1135d4 LP |
1009 | } |
1010 | } | |
1011 | ||
1012 | /* | |
1013 | * preview_config_ycpos - Configure byte layout of YUV image. | |
1014 | * @mode: Indicates the required byte layout. | |
1015 | */ | |
1016 | static void | |
1017 | preview_config_ycpos(struct isp_prev_device *prev, | |
1018 | enum v4l2_mbus_pixelcode pixelcode) | |
1019 | { | |
1020 | struct isp_device *isp = to_isp_device(prev); | |
1021 | enum preview_ycpos_mode mode; | |
1022 | ||
1023 | switch (pixelcode) { | |
1024 | case V4L2_MBUS_FMT_YUYV8_1X16: | |
1025 | mode = YCPOS_CrYCbY; | |
1026 | break; | |
1027 | case V4L2_MBUS_FMT_UYVY8_1X16: | |
1028 | mode = YCPOS_YCrYCb; | |
1029 | break; | |
1030 | default: | |
1031 | return; | |
1032 | } | |
1033 | ||
1034 | isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1035 | ISPPRV_PCR_YCPOS_CrYCbY, | |
1036 | mode << ISPPRV_PCR_YCPOS_SHIFT); | |
1037 | } | |
1038 | ||
1039 | /* | |
1040 | * preview_config_averager - Enable / disable / configure averager | |
1041 | * @average: Average value to be configured. | |
1042 | */ | |
1043 | static void preview_config_averager(struct isp_prev_device *prev, u8 average) | |
1044 | { | |
1045 | struct isp_device *isp = to_isp_device(prev); | |
b0b29e1e | 1046 | struct prev_params *params; |
de1135d4 LP |
1047 | int reg = 0; |
1048 | ||
b0b29e1e LP |
1049 | params = (prev->params.active & OMAP3ISP_PREV_CFA) |
1050 | ? &prev->params.params[0] : &prev->params.params[1]; | |
1051 | ||
1052 | if (params->cfa.format == OMAP3ISP_CFAFMT_BAYER) | |
de1135d4 LP |
1053 | reg = ISPPRV_AVE_EVENDIST_2 << ISPPRV_AVE_EVENDIST_SHIFT | |
1054 | ISPPRV_AVE_ODDDIST_2 << ISPPRV_AVE_ODDDIST_SHIFT | | |
1055 | average; | |
b0b29e1e | 1056 | else if (params->cfa.format == OMAP3ISP_CFAFMT_RGBFOVEON) |
de1135d4 LP |
1057 | reg = ISPPRV_AVE_EVENDIST_3 << ISPPRV_AVE_EVENDIST_SHIFT | |
1058 | ISPPRV_AVE_ODDDIST_3 << ISPPRV_AVE_ODDDIST_SHIFT | | |
1059 | average; | |
1060 | isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE); | |
1061 | } | |
1062 | ||
b2da46e5 LP |
1063 | /* |
1064 | * preview_config_input_format - Configure the input format | |
1065 | * @prev: The preview engine | |
1066 | * @format: Format on the preview engine sink pad | |
1067 | * | |
1068 | * Enable CFA interpolation for Bayer formats and disable it for greyscale | |
1069 | * formats. | |
1070 | */ | |
1071 | static void preview_config_input_format(struct isp_prev_device *prev, | |
1072 | const struct v4l2_mbus_framefmt *format) | |
1073 | { | |
1074 | struct isp_device *isp = to_isp_device(prev); | |
1075 | ||
1076 | if (format->code != V4L2_MBUS_FMT_Y10_1X10) | |
1077 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1078 | ISPPRV_PCR_CFAEN); | |
1079 | else | |
1080 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1081 | ISPPRV_PCR_CFAEN); | |
1082 | } | |
1083 | ||
de1135d4 LP |
1084 | /* |
1085 | * preview_config_input_size - Configure the input frame size | |
1086 | * | |
1087 | * The preview engine crops several rows and columns internally depending on | |
1088 | * which processing blocks are enabled. The driver assumes all those blocks are | |
1089 | * enabled when reporting source pad formats to userspace. If this assumption is | |
1090 | * not true, rows and columns must be manually cropped at the preview engine | |
1091 | * input to avoid overflows at the end of lines and frames. | |
1f69fd97 LP |
1092 | * |
1093 | * See the explanation at the PREV_MARGIN_* definitions for more details. | |
de1135d4 | 1094 | */ |
b0b29e1e | 1095 | static void preview_config_input_size(struct isp_prev_device *prev, u32 active) |
de1135d4 | 1096 | { |
b2da46e5 | 1097 | const struct v4l2_mbus_framefmt *format = &prev->formats[PREV_PAD_SINK]; |
de1135d4 | 1098 | struct isp_device *isp = to_isp_device(prev); |
1f69fd97 LP |
1099 | unsigned int sph = prev->crop.left; |
1100 | unsigned int eph = prev->crop.left + prev->crop.width - 1; | |
1101 | unsigned int slv = prev->crop.top; | |
1102 | unsigned int elv = prev->crop.top + prev->crop.height - 1; | |
b0b29e1e | 1103 | u32 features; |
1f69fd97 | 1104 | |
7103180b | 1105 | if (format->code != V4L2_MBUS_FMT_Y10_1X10) { |
1f69fd97 LP |
1106 | sph -= 2; |
1107 | eph += 2; | |
1108 | slv -= 2; | |
1109 | elv += 2; | |
de1135d4 | 1110 | } |
b2da46e5 LP |
1111 | |
1112 | features = (prev->params.params[0].features & active) | |
1113 | | (prev->params.params[1].features & ~active); | |
1114 | ||
b0b29e1e | 1115 | if (features & (OMAP3ISP_PREV_DEFECT_COR | OMAP3ISP_PREV_NF)) { |
1f69fd97 LP |
1116 | sph -= 2; |
1117 | eph += 2; | |
1118 | slv -= 2; | |
1119 | elv += 2; | |
de1135d4 | 1120 | } |
b0b29e1e | 1121 | if (features & OMAP3ISP_PREV_HRZ_MED) { |
1f69fd97 LP |
1122 | sph -= 2; |
1123 | eph += 2; | |
de1135d4 | 1124 | } |
b0b29e1e | 1125 | if (features & (OMAP3ISP_PREV_CHROMA_SUPP | OMAP3ISP_PREV_LUMAENH)) |
1f69fd97 | 1126 | sph -= 2; |
de1135d4 LP |
1127 | |
1128 | isp_reg_writel(isp, (sph << ISPPRV_HORZ_INFO_SPH_SHIFT) | eph, | |
1129 | OMAP3_ISP_IOMEM_PREV, ISPPRV_HORZ_INFO); | |
1130 | isp_reg_writel(isp, (slv << ISPPRV_VERT_INFO_SLV_SHIFT) | elv, | |
1131 | OMAP3_ISP_IOMEM_PREV, ISPPRV_VERT_INFO); | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * preview_config_inlineoffset - Configures the Read address line offset. | |
1136 | * @prev: Preview module | |
1137 | * @offset: Line offset | |
1138 | * | |
1139 | * According to the TRM, the line offset must be aligned on a 32 bytes boundary. | |
1140 | * However, a hardware bug requires the memory start address to be aligned on a | |
1141 | * 64 bytes boundary, so the offset probably should be aligned on 64 bytes as | |
1142 | * well. | |
1143 | */ | |
1144 | static void | |
1145 | preview_config_inlineoffset(struct isp_prev_device *prev, u32 offset) | |
1146 | { | |
1147 | struct isp_device *isp = to_isp_device(prev); | |
1148 | ||
1149 | isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV, | |
1150 | ISPPRV_RADR_OFFSET); | |
1151 | } | |
1152 | ||
1153 | /* | |
1154 | * preview_set_inaddr - Sets memory address of input frame. | |
1155 | * @addr: 32bit memory address aligned on 32byte boundary. | |
1156 | * | |
1157 | * Configures the memory address from which the input frame is to be read. | |
1158 | */ | |
1159 | static void preview_set_inaddr(struct isp_prev_device *prev, u32 addr) | |
1160 | { | |
1161 | struct isp_device *isp = to_isp_device(prev); | |
1162 | ||
1163 | isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_RSDR_ADDR); | |
1164 | } | |
1165 | ||
1166 | /* | |
1167 | * preview_config_outlineoffset - Configures the Write address line offset. | |
1168 | * @offset: Line Offset for the preview output. | |
1169 | * | |
1170 | * The offset must be a multiple of 32 bytes. | |
1171 | */ | |
1172 | static void preview_config_outlineoffset(struct isp_prev_device *prev, | |
1173 | u32 offset) | |
1174 | { | |
1175 | struct isp_device *isp = to_isp_device(prev); | |
1176 | ||
1177 | isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV, | |
1178 | ISPPRV_WADD_OFFSET); | |
1179 | } | |
1180 | ||
1181 | /* | |
1182 | * preview_set_outaddr - Sets the memory address to store output frame | |
1183 | * @addr: 32bit memory address aligned on 32byte boundary. | |
1184 | * | |
1185 | * Configures the memory address to which the output frame is written. | |
1186 | */ | |
1187 | static void preview_set_outaddr(struct isp_prev_device *prev, u32 addr) | |
1188 | { | |
1189 | struct isp_device *isp = to_isp_device(prev); | |
1190 | ||
1191 | isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_WSDR_ADDR); | |
1192 | } | |
1193 | ||
1194 | static void preview_adjust_bandwidth(struct isp_prev_device *prev) | |
1195 | { | |
1196 | struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity); | |
1197 | struct isp_device *isp = to_isp_device(prev); | |
1198 | const struct v4l2_mbus_framefmt *ifmt = &prev->formats[PREV_PAD_SINK]; | |
1199 | unsigned long l3_ick = pipe->l3_ick; | |
1200 | struct v4l2_fract *timeperframe; | |
1201 | unsigned int cycles_per_frame; | |
1202 | unsigned int requests_per_frame; | |
1203 | unsigned int cycles_per_request; | |
1204 | unsigned int minimum; | |
1205 | unsigned int maximum; | |
1206 | unsigned int value; | |
1207 | ||
1208 | if (prev->input != PREVIEW_INPUT_MEMORY) { | |
1209 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP, | |
1210 | ISPSBL_SDR_REQ_PRV_EXP_MASK); | |
1211 | return; | |
1212 | } | |
1213 | ||
1214 | /* Compute the minimum number of cycles per request, based on the | |
1215 | * pipeline maximum data rate. This is an absolute lower bound if we | |
1216 | * don't want SBL overflows, so round the value up. | |
1217 | */ | |
1218 | cycles_per_request = div_u64((u64)l3_ick / 2 * 256 + pipe->max_rate - 1, | |
1219 | pipe->max_rate); | |
1220 | minimum = DIV_ROUND_UP(cycles_per_request, 32); | |
1221 | ||
1222 | /* Compute the maximum number of cycles per request, based on the | |
1223 | * requested frame rate. This is a soft upper bound to achieve a frame | |
1224 | * rate equal or higher than the requested value, so round the value | |
1225 | * down. | |
1226 | */ | |
1227 | timeperframe = &pipe->max_timeperframe; | |
1228 | ||
1229 | requests_per_frame = DIV_ROUND_UP(ifmt->width * 2, 256) * ifmt->height; | |
1230 | cycles_per_frame = div_u64((u64)l3_ick * timeperframe->numerator, | |
1231 | timeperframe->denominator); | |
1232 | cycles_per_request = cycles_per_frame / requests_per_frame; | |
1233 | ||
1234 | maximum = cycles_per_request / 32; | |
1235 | ||
1236 | value = max(minimum, maximum); | |
1237 | ||
1238 | dev_dbg(isp->dev, "%s: cycles per request = %u\n", __func__, value); | |
1239 | isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP, | |
1240 | ISPSBL_SDR_REQ_PRV_EXP_MASK, | |
1241 | value << ISPSBL_SDR_REQ_PRV_EXP_SHIFT); | |
1242 | } | |
1243 | ||
1244 | /* | |
1245 | * omap3isp_preview_busy - Gets busy state of preview module. | |
1246 | */ | |
1247 | int omap3isp_preview_busy(struct isp_prev_device *prev) | |
1248 | { | |
1249 | struct isp_device *isp = to_isp_device(prev); | |
1250 | ||
1251 | return isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR) | |
1252 | & ISPPRV_PCR_BUSY; | |
1253 | } | |
1254 | ||
1255 | /* | |
1256 | * omap3isp_preview_restore_context - Restores the values of preview registers | |
1257 | */ | |
1258 | void omap3isp_preview_restore_context(struct isp_device *isp) | |
1259 | { | |
b0b29e1e LP |
1260 | struct isp_prev_device *prev = &isp->isp_prev; |
1261 | const u32 update = OMAP3ISP_PREV_FEATURES_END - 1; | |
1262 | ||
1263 | prev->params.params[0].update = prev->params.active & update; | |
1264 | prev->params.params[1].update = ~prev->params.active & update; | |
1265 | ||
1266 | preview_setup_hw(prev, update, prev->params.active); | |
1267 | ||
1268 | prev->params.params[0].update = 0; | |
1269 | prev->params.params[1].update = 0; | |
de1135d4 LP |
1270 | } |
1271 | ||
1272 | /* | |
1273 | * preview_print_status - Dump preview module registers to the kernel log | |
1274 | */ | |
1275 | #define PREV_PRINT_REGISTER(isp, name)\ | |
1276 | dev_dbg(isp->dev, "###PRV " #name "=0x%08x\n", \ | |
1277 | isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_##name)) | |
1278 | ||
1279 | static void preview_print_status(struct isp_prev_device *prev) | |
1280 | { | |
1281 | struct isp_device *isp = to_isp_device(prev); | |
1282 | ||
1283 | dev_dbg(isp->dev, "-------------Preview Register dump----------\n"); | |
1284 | ||
1285 | PREV_PRINT_REGISTER(isp, PCR); | |
1286 | PREV_PRINT_REGISTER(isp, HORZ_INFO); | |
1287 | PREV_PRINT_REGISTER(isp, VERT_INFO); | |
1288 | PREV_PRINT_REGISTER(isp, RSDR_ADDR); | |
1289 | PREV_PRINT_REGISTER(isp, RADR_OFFSET); | |
1290 | PREV_PRINT_REGISTER(isp, DSDR_ADDR); | |
1291 | PREV_PRINT_REGISTER(isp, DRKF_OFFSET); | |
1292 | PREV_PRINT_REGISTER(isp, WSDR_ADDR); | |
1293 | PREV_PRINT_REGISTER(isp, WADD_OFFSET); | |
1294 | PREV_PRINT_REGISTER(isp, AVE); | |
1295 | PREV_PRINT_REGISTER(isp, HMED); | |
1296 | PREV_PRINT_REGISTER(isp, NF); | |
1297 | PREV_PRINT_REGISTER(isp, WB_DGAIN); | |
1298 | PREV_PRINT_REGISTER(isp, WBGAIN); | |
1299 | PREV_PRINT_REGISTER(isp, WBSEL); | |
1300 | PREV_PRINT_REGISTER(isp, CFA); | |
1301 | PREV_PRINT_REGISTER(isp, BLKADJOFF); | |
1302 | PREV_PRINT_REGISTER(isp, RGB_MAT1); | |
1303 | PREV_PRINT_REGISTER(isp, RGB_MAT2); | |
1304 | PREV_PRINT_REGISTER(isp, RGB_MAT3); | |
1305 | PREV_PRINT_REGISTER(isp, RGB_MAT4); | |
1306 | PREV_PRINT_REGISTER(isp, RGB_MAT5); | |
1307 | PREV_PRINT_REGISTER(isp, RGB_OFF1); | |
1308 | PREV_PRINT_REGISTER(isp, RGB_OFF2); | |
1309 | PREV_PRINT_REGISTER(isp, CSC0); | |
1310 | PREV_PRINT_REGISTER(isp, CSC1); | |
1311 | PREV_PRINT_REGISTER(isp, CSC2); | |
1312 | PREV_PRINT_REGISTER(isp, CSC_OFFSET); | |
1313 | PREV_PRINT_REGISTER(isp, CNT_BRT); | |
1314 | PREV_PRINT_REGISTER(isp, CSUP); | |
1315 | PREV_PRINT_REGISTER(isp, SETUP_YC); | |
1316 | PREV_PRINT_REGISTER(isp, SET_TBL_ADDR); | |
1317 | PREV_PRINT_REGISTER(isp, CDC_THR0); | |
1318 | PREV_PRINT_REGISTER(isp, CDC_THR1); | |
1319 | PREV_PRINT_REGISTER(isp, CDC_THR2); | |
1320 | PREV_PRINT_REGISTER(isp, CDC_THR3); | |
1321 | ||
1322 | dev_dbg(isp->dev, "--------------------------------------------\n"); | |
1323 | } | |
1324 | ||
1325 | /* | |
1326 | * preview_init_params - init image processing parameters. | |
1327 | * @prev: pointer to previewer private structure | |
de1135d4 LP |
1328 | */ |
1329 | static void preview_init_params(struct isp_prev_device *prev) | |
1330 | { | |
b0b29e1e LP |
1331 | struct prev_params *params; |
1332 | unsigned int i; | |
1333 | ||
1334 | spin_lock_init(&prev->params.lock); | |
1335 | ||
1336 | prev->params.active = ~0; | |
1337 | prev->params.params[0].busy = 0; | |
1338 | prev->params.params[0].update = OMAP3ISP_PREV_FEATURES_END - 1; | |
1339 | prev->params.params[1].busy = 0; | |
1340 | prev->params.params[1].update = 0; | |
1341 | ||
1342 | params = &prev->params.params[0]; | |
de1135d4 LP |
1343 | |
1344 | /* Init values */ | |
1345 | params->contrast = ISPPRV_CONTRAST_DEF * ISPPRV_CONTRAST_UNITS; | |
1346 | params->brightness = ISPPRV_BRIGHT_DEF * ISPPRV_BRIGHT_UNITS; | |
de1135d4 LP |
1347 | params->cfa.format = OMAP3ISP_CFAFMT_BAYER; |
1348 | memcpy(params->cfa.table, cfa_coef_table, | |
1349 | sizeof(params->cfa.table)); | |
1350 | params->cfa.gradthrs_horz = FLR_CFA_GRADTHRS_HORZ; | |
1351 | params->cfa.gradthrs_vert = FLR_CFA_GRADTHRS_VERT; | |
1352 | params->csup.gain = FLR_CSUP_GAIN; | |
1353 | params->csup.thres = FLR_CSUP_THRES; | |
1354 | params->csup.hypf_en = 0; | |
1355 | memcpy(params->luma.table, luma_enhance_table, | |
1356 | sizeof(params->luma.table)); | |
1357 | params->nf.spread = FLR_NF_STRGTH; | |
1358 | memcpy(params->nf.table, noise_filter_table, sizeof(params->nf.table)); | |
1359 | params->dcor.couplet_mode_en = 1; | |
1360 | for (i = 0; i < OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS; i++) | |
1361 | params->dcor.detect_correct[i] = DEF_DETECT_CORRECT_VAL; | |
1362 | memcpy(params->gamma.blue, gamma_table, sizeof(params->gamma.blue)); | |
1363 | memcpy(params->gamma.green, gamma_table, sizeof(params->gamma.green)); | |
1364 | memcpy(params->gamma.red, gamma_table, sizeof(params->gamma.red)); | |
1365 | params->wbal.dgain = FLR_WBAL_DGAIN; | |
1366 | params->wbal.coef0 = FLR_WBAL_COEF; | |
1367 | params->wbal.coef1 = FLR_WBAL_COEF; | |
1368 | params->wbal.coef2 = FLR_WBAL_COEF; | |
1369 | params->wbal.coef3 = FLR_WBAL_COEF; | |
9b00184d LP |
1370 | params->blkadj.red = FLR_BLKADJ_RED; |
1371 | params->blkadj.green = FLR_BLKADJ_GREEN; | |
1372 | params->blkadj.blue = FLR_BLKADJ_BLUE; | |
de1135d4 | 1373 | params->rgb2rgb = flr_rgb2rgb; |
9b00184d | 1374 | params->csc = flr_prev_csc; |
de1135d4 LP |
1375 | params->yclimit.minC = ISPPRV_YC_MIN; |
1376 | params->yclimit.maxC = ISPPRV_YC_MAX; | |
1377 | params->yclimit.minY = ISPPRV_YC_MIN; | |
1378 | params->yclimit.maxY = ISPPRV_YC_MAX; | |
1379 | ||
3108e026 LP |
1380 | params->features = OMAP3ISP_PREV_CFA | OMAP3ISP_PREV_DEFECT_COR |
1381 | | OMAP3ISP_PREV_NF | OMAP3ISP_PREV_GAMMA | |
1382 | | OMAP3ISP_PREV_BLKADJ | OMAP3ISP_PREV_YC_LIMIT | |
1383 | | OMAP3ISP_PREV_RGB2RGB | OMAP3ISP_PREV_COLOR_CONV | |
1384 | | OMAP3ISP_PREV_WB | OMAP3ISP_PREV_BRIGHTNESS | |
1385 | | OMAP3ISP_PREV_CONTRAST; | |
de1135d4 LP |
1386 | } |
1387 | ||
1388 | /* | |
1389 | * preview_max_out_width - Handle previewer hardware ouput limitations | |
1390 | * @isp_revision : ISP revision | |
1391 | * returns maximum width output for current isp revision | |
1392 | */ | |
1393 | static unsigned int preview_max_out_width(struct isp_prev_device *prev) | |
1394 | { | |
1395 | struct isp_device *isp = to_isp_device(prev); | |
1396 | ||
1397 | switch (isp->revision) { | |
1398 | case ISP_REVISION_1_0: | |
ec0cae7a | 1399 | return PREV_MAX_OUT_WIDTH_REV_1; |
de1135d4 LP |
1400 | |
1401 | case ISP_REVISION_2_0: | |
1402 | default: | |
ec0cae7a | 1403 | return PREV_MAX_OUT_WIDTH_REV_2; |
de1135d4 LP |
1404 | |
1405 | case ISP_REVISION_15_0: | |
ec0cae7a | 1406 | return PREV_MAX_OUT_WIDTH_REV_15; |
de1135d4 LP |
1407 | } |
1408 | } | |
1409 | ||
1410 | static void preview_configure(struct isp_prev_device *prev) | |
1411 | { | |
1412 | struct isp_device *isp = to_isp_device(prev); | |
1413 | struct v4l2_mbus_framefmt *format; | |
b0b29e1e LP |
1414 | unsigned long flags; |
1415 | u32 update; | |
1416 | u32 active; | |
de1135d4 | 1417 | |
b0b29e1e LP |
1418 | spin_lock_irqsave(&prev->params.lock, flags); |
1419 | /* Mark all active parameters we are going to touch as busy. */ | |
1420 | update = preview_params_lock(prev, 0, false); | |
1421 | active = prev->params.active; | |
1422 | spin_unlock_irqrestore(&prev->params.lock, flags); | |
1423 | ||
1424 | preview_setup_hw(prev, update, active); | |
de1135d4 LP |
1425 | |
1426 | if (prev->output & PREVIEW_OUTPUT_MEMORY) | |
1427 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1428 | ISPPRV_PCR_SDRPORT); | |
1429 | else | |
1430 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1431 | ISPPRV_PCR_SDRPORT); | |
1432 | ||
1433 | if (prev->output & PREVIEW_OUTPUT_RESIZER) | |
1434 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1435 | ISPPRV_PCR_RSZPORT); | |
1436 | else | |
1437 | isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1438 | ISPPRV_PCR_RSZPORT); | |
1439 | ||
1440 | /* PREV_PAD_SINK */ | |
1441 | format = &prev->formats[PREV_PAD_SINK]; | |
1442 | ||
1443 | preview_adjust_bandwidth(prev); | |
1444 | ||
b2da46e5 | 1445 | preview_config_input_format(prev, format); |
b0b29e1e | 1446 | preview_config_input_size(prev, active); |
de1135d4 LP |
1447 | |
1448 | if (prev->input == PREVIEW_INPUT_CCDC) | |
1449 | preview_config_inlineoffset(prev, 0); | |
1450 | else | |
1451 | preview_config_inlineoffset(prev, | |
1452 | ALIGN(format->width, 0x20) * 2); | |
1453 | ||
1454 | /* PREV_PAD_SOURCE */ | |
1455 | format = &prev->formats[PREV_PAD_SOURCE]; | |
1456 | ||
1457 | if (prev->output & PREVIEW_OUTPUT_MEMORY) | |
1458 | preview_config_outlineoffset(prev, | |
1459 | ALIGN(format->width, 0x10) * 2); | |
1460 | ||
e4bc6272 | 1461 | preview_config_averager(prev, 0); |
de1135d4 | 1462 | preview_config_ycpos(prev, format->code); |
b0b29e1e LP |
1463 | |
1464 | spin_lock_irqsave(&prev->params.lock, flags); | |
1465 | preview_params_unlock(prev, update, false); | |
1466 | spin_unlock_irqrestore(&prev->params.lock, flags); | |
de1135d4 LP |
1467 | } |
1468 | ||
1469 | /* ----------------------------------------------------------------------------- | |
1470 | * Interrupt handling | |
1471 | */ | |
1472 | ||
1473 | static void preview_enable_oneshot(struct isp_prev_device *prev) | |
1474 | { | |
1475 | struct isp_device *isp = to_isp_device(prev); | |
1476 | ||
1477 | /* The PCR.SOURCE bit is automatically reset to 0 when the PCR.ENABLE | |
1478 | * bit is set. As the preview engine is used in single-shot mode, we | |
1479 | * need to set PCR.SOURCE before enabling the preview engine. | |
1480 | */ | |
1481 | if (prev->input == PREVIEW_INPUT_MEMORY) | |
1482 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1483 | ISPPRV_PCR_SOURCE); | |
1484 | ||
1485 | isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, | |
1486 | ISPPRV_PCR_EN | ISPPRV_PCR_ONESHOT); | |
1487 | } | |
1488 | ||
1489 | void omap3isp_preview_isr_frame_sync(struct isp_prev_device *prev) | |
1490 | { | |
1491 | /* | |
1492 | * If ISP_VIDEO_DMAQUEUE_QUEUED is set, DMA queue had an underrun | |
1493 | * condition, the module was paused and now we have a buffer queued | |
1494 | * on the output again. Restart the pipeline if running in continuous | |
1495 | * mode. | |
1496 | */ | |
1497 | if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS && | |
1498 | prev->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED) { | |
1499 | preview_enable_oneshot(prev); | |
1500 | isp_video_dmaqueue_flags_clr(&prev->video_out); | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | static void preview_isr_buffer(struct isp_prev_device *prev) | |
1505 | { | |
1506 | struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity); | |
1507 | struct isp_buffer *buffer; | |
1508 | int restart = 0; | |
1509 | ||
1510 | if (prev->input == PREVIEW_INPUT_MEMORY) { | |
875e2e3e | 1511 | buffer = omap3isp_video_buffer_next(&prev->video_in); |
de1135d4 LP |
1512 | if (buffer != NULL) |
1513 | preview_set_inaddr(prev, buffer->isp_addr); | |
1514 | pipe->state |= ISP_PIPELINE_IDLE_INPUT; | |
1515 | } | |
1516 | ||
1517 | if (prev->output & PREVIEW_OUTPUT_MEMORY) { | |
875e2e3e | 1518 | buffer = omap3isp_video_buffer_next(&prev->video_out); |
de1135d4 LP |
1519 | if (buffer != NULL) { |
1520 | preview_set_outaddr(prev, buffer->isp_addr); | |
1521 | restart = 1; | |
1522 | } | |
1523 | pipe->state |= ISP_PIPELINE_IDLE_OUTPUT; | |
1524 | } | |
1525 | ||
1526 | switch (prev->state) { | |
1527 | case ISP_PIPELINE_STREAM_SINGLESHOT: | |
1528 | if (isp_pipeline_ready(pipe)) | |
1529 | omap3isp_pipeline_set_stream(pipe, | |
1530 | ISP_PIPELINE_STREAM_SINGLESHOT); | |
1531 | break; | |
1532 | ||
1533 | case ISP_PIPELINE_STREAM_CONTINUOUS: | |
1534 | /* If an underrun occurs, the video queue operation handler will | |
1535 | * restart the preview engine. Otherwise restart it immediately. | |
1536 | */ | |
1537 | if (restart) | |
1538 | preview_enable_oneshot(prev); | |
1539 | break; | |
1540 | ||
1541 | case ISP_PIPELINE_STREAM_STOPPED: | |
1542 | default: | |
1543 | return; | |
1544 | } | |
de1135d4 LP |
1545 | } |
1546 | ||
1547 | /* | |
1548 | * omap3isp_preview_isr - ISP preview engine interrupt handler | |
1549 | * | |
1550 | * Manage the preview engine video buffers and configure shadowed registers. | |
1551 | */ | |
1552 | void omap3isp_preview_isr(struct isp_prev_device *prev) | |
1553 | { | |
1554 | unsigned long flags; | |
b0b29e1e LP |
1555 | u32 update; |
1556 | u32 active; | |
de1135d4 LP |
1557 | |
1558 | if (omap3isp_module_sync_is_stopping(&prev->wait, &prev->stopping)) | |
1559 | return; | |
1560 | ||
b0b29e1e LP |
1561 | spin_lock_irqsave(&prev->params.lock, flags); |
1562 | preview_params_switch(prev); | |
1563 | update = preview_params_lock(prev, 0, false); | |
1564 | active = prev->params.active; | |
1565 | spin_unlock_irqrestore(&prev->params.lock, flags); | |
de1135d4 | 1566 | |
b0b29e1e LP |
1567 | preview_setup_hw(prev, update, active); |
1568 | preview_config_input_size(prev, active); | |
de1135d4 LP |
1569 | |
1570 | if (prev->input == PREVIEW_INPUT_MEMORY || | |
1571 | prev->output & PREVIEW_OUTPUT_MEMORY) | |
1572 | preview_isr_buffer(prev); | |
1573 | else if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS) | |
1574 | preview_enable_oneshot(prev); | |
b0b29e1e LP |
1575 | |
1576 | spin_lock_irqsave(&prev->params.lock, flags); | |
1577 | preview_params_unlock(prev, update, false); | |
1578 | spin_unlock_irqrestore(&prev->params.lock, flags); | |
de1135d4 LP |
1579 | } |
1580 | ||
1581 | /* ----------------------------------------------------------------------------- | |
1582 | * ISP video operations | |
1583 | */ | |
1584 | ||
1585 | static int preview_video_queue(struct isp_video *video, | |
1586 | struct isp_buffer *buffer) | |
1587 | { | |
1588 | struct isp_prev_device *prev = &video->isp->isp_prev; | |
1589 | ||
1590 | if (video->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) | |
1591 | preview_set_inaddr(prev, buffer->isp_addr); | |
1592 | ||
1593 | if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1594 | preview_set_outaddr(prev, buffer->isp_addr); | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | static const struct isp_video_operations preview_video_ops = { | |
1600 | .queue = preview_video_queue, | |
1601 | }; | |
1602 | ||
1603 | /* ----------------------------------------------------------------------------- | |
1604 | * V4L2 subdev operations | |
1605 | */ | |
1606 | ||
1607 | /* | |
1608 | * preview_s_ctrl - Handle set control subdev method | |
1609 | * @ctrl: pointer to v4l2 control structure | |
1610 | */ | |
1611 | static int preview_s_ctrl(struct v4l2_ctrl *ctrl) | |
1612 | { | |
1613 | struct isp_prev_device *prev = | |
1614 | container_of(ctrl->handler, struct isp_prev_device, ctrls); | |
1615 | ||
1616 | switch (ctrl->id) { | |
1617 | case V4L2_CID_BRIGHTNESS: | |
1618 | preview_update_brightness(prev, ctrl->val); | |
1619 | break; | |
1620 | case V4L2_CID_CONTRAST: | |
1621 | preview_update_contrast(prev, ctrl->val); | |
1622 | break; | |
1623 | } | |
1624 | ||
1625 | return 0; | |
1626 | } | |
1627 | ||
1628 | static const struct v4l2_ctrl_ops preview_ctrl_ops = { | |
1629 | .s_ctrl = preview_s_ctrl, | |
1630 | }; | |
1631 | ||
1632 | /* | |
1633 | * preview_ioctl - Handle preview module private ioctl's | |
1634 | * @prev: pointer to preview context structure | |
1635 | * @cmd: configuration command | |
1636 | * @arg: configuration argument | |
1637 | * return -EINVAL or zero on success | |
1638 | */ | |
1639 | static long preview_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) | |
1640 | { | |
1641 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
1642 | ||
1643 | switch (cmd) { | |
1644 | case VIDIOC_OMAP3ISP_PRV_CFG: | |
1645 | return preview_config(prev, arg); | |
1646 | ||
1647 | default: | |
1648 | return -ENOIOCTLCMD; | |
1649 | } | |
1650 | } | |
1651 | ||
1652 | /* | |
1653 | * preview_set_stream - Enable/Disable streaming on preview subdev | |
1654 | * @sd : pointer to v4l2 subdev structure | |
1655 | * @enable: 1 == Enable, 0 == Disable | |
25985edc | 1656 | * return -EINVAL or zero on success |
de1135d4 LP |
1657 | */ |
1658 | static int preview_set_stream(struct v4l2_subdev *sd, int enable) | |
1659 | { | |
1660 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
1661 | struct isp_video *video_out = &prev->video_out; | |
1662 | struct isp_device *isp = to_isp_device(prev); | |
1663 | struct device *dev = to_device(prev); | |
de1135d4 LP |
1664 | |
1665 | if (prev->state == ISP_PIPELINE_STREAM_STOPPED) { | |
1666 | if (enable == ISP_PIPELINE_STREAM_STOPPED) | |
1667 | return 0; | |
1668 | ||
1669 | omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_PREVIEW); | |
1670 | preview_configure(prev); | |
1671 | atomic_set(&prev->stopping, 0); | |
de1135d4 LP |
1672 | preview_print_status(prev); |
1673 | } | |
1674 | ||
1675 | switch (enable) { | |
1676 | case ISP_PIPELINE_STREAM_CONTINUOUS: | |
1677 | if (prev->output & PREVIEW_OUTPUT_MEMORY) | |
1678 | omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE); | |
1679 | ||
1680 | if (video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED || | |
1681 | !(prev->output & PREVIEW_OUTPUT_MEMORY)) | |
1682 | preview_enable_oneshot(prev); | |
1683 | ||
1684 | isp_video_dmaqueue_flags_clr(video_out); | |
1685 | break; | |
1686 | ||
1687 | case ISP_PIPELINE_STREAM_SINGLESHOT: | |
1688 | if (prev->input == PREVIEW_INPUT_MEMORY) | |
1689 | omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_READ); | |
1690 | if (prev->output & PREVIEW_OUTPUT_MEMORY) | |
1691 | omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE); | |
1692 | ||
1693 | preview_enable_oneshot(prev); | |
1694 | break; | |
1695 | ||
1696 | case ISP_PIPELINE_STREAM_STOPPED: | |
1697 | if (omap3isp_module_sync_idle(&sd->entity, &prev->wait, | |
1698 | &prev->stopping)) | |
1699 | dev_dbg(dev, "%s: stop timeout.\n", sd->name); | |
de1135d4 LP |
1700 | omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_READ); |
1701 | omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE); | |
1702 | omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_PREVIEW); | |
de1135d4 LP |
1703 | isp_video_dmaqueue_flags_clr(video_out); |
1704 | break; | |
1705 | } | |
1706 | ||
1707 | prev->state = enable; | |
1708 | return 0; | |
1709 | } | |
1710 | ||
1711 | static struct v4l2_mbus_framefmt * | |
1712 | __preview_get_format(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh, | |
1713 | unsigned int pad, enum v4l2_subdev_format_whence which) | |
1714 | { | |
1715 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
1716 | return v4l2_subdev_get_try_format(fh, pad); | |
1717 | else | |
1718 | return &prev->formats[pad]; | |
1719 | } | |
1720 | ||
1f69fd97 LP |
1721 | static struct v4l2_rect * |
1722 | __preview_get_crop(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh, | |
1723 | enum v4l2_subdev_format_whence which) | |
1724 | { | |
1725 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
1726 | return v4l2_subdev_get_try_crop(fh, PREV_PAD_SINK); | |
1727 | else | |
1728 | return &prev->crop; | |
1729 | } | |
1730 | ||
de1135d4 LP |
1731 | /* previewer format descriptions */ |
1732 | static const unsigned int preview_input_fmts[] = { | |
b2da46e5 | 1733 | V4L2_MBUS_FMT_Y10_1X10, |
de1135d4 LP |
1734 | V4L2_MBUS_FMT_SGRBG10_1X10, |
1735 | V4L2_MBUS_FMT_SRGGB10_1X10, | |
1736 | V4L2_MBUS_FMT_SBGGR10_1X10, | |
1737 | V4L2_MBUS_FMT_SGBRG10_1X10, | |
1738 | }; | |
1739 | ||
1740 | static const unsigned int preview_output_fmts[] = { | |
1741 | V4L2_MBUS_FMT_UYVY8_1X16, | |
1742 | V4L2_MBUS_FMT_YUYV8_1X16, | |
1743 | }; | |
1744 | ||
1745 | /* | |
1f69fd97 LP |
1746 | * preview_try_format - Validate a format |
1747 | * @prev: ISP preview engine | |
1748 | * @fh: V4L2 subdev file handle | |
1749 | * @pad: pad number | |
1750 | * @fmt: format to be validated | |
1751 | * @which: try/active format selector | |
1752 | * | |
1753 | * Validate and adjust the given format for the given pad based on the preview | |
1754 | * engine limits and the format and crop rectangles on other pads. | |
de1135d4 LP |
1755 | */ |
1756 | static void preview_try_format(struct isp_prev_device *prev, | |
1757 | struct v4l2_subdev_fh *fh, unsigned int pad, | |
1758 | struct v4l2_mbus_framefmt *fmt, | |
1759 | enum v4l2_subdev_format_whence which) | |
1760 | { | |
de1135d4 | 1761 | enum v4l2_mbus_pixelcode pixelcode; |
1f69fd97 | 1762 | struct v4l2_rect *crop; |
de1135d4 LP |
1763 | unsigned int i; |
1764 | ||
de1135d4 LP |
1765 | switch (pad) { |
1766 | case PREV_PAD_SINK: | |
1767 | /* When reading data from the CCDC, the input size has already | |
1768 | * been mangled by the CCDC output pad so it can be accepted | |
1769 | * as-is. | |
1770 | * | |
1771 | * When reading data from memory, clamp the requested width and | |
1772 | * height. The TRM doesn't specify a minimum input height, make | |
1773 | * sure we got enough lines to enable the noise filter and color | |
1774 | * filter array interpolation. | |
1775 | */ | |
1776 | if (prev->input == PREVIEW_INPUT_MEMORY) { | |
059dc1d9 LP |
1777 | fmt->width = clamp_t(u32, fmt->width, PREV_MIN_IN_WIDTH, |
1778 | preview_max_out_width(prev)); | |
1779 | fmt->height = clamp_t(u32, fmt->height, | |
1780 | PREV_MIN_IN_HEIGHT, | |
1781 | PREV_MAX_IN_HEIGHT); | |
de1135d4 LP |
1782 | } |
1783 | ||
1784 | fmt->colorspace = V4L2_COLORSPACE_SRGB; | |
1785 | ||
1786 | for (i = 0; i < ARRAY_SIZE(preview_input_fmts); i++) { | |
1787 | if (fmt->code == preview_input_fmts[i]) | |
1788 | break; | |
1789 | } | |
1790 | ||
1791 | /* If not found, use SGRBG10 as default */ | |
1792 | if (i >= ARRAY_SIZE(preview_input_fmts)) | |
1793 | fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
1794 | break; | |
1795 | ||
1796 | case PREV_PAD_SOURCE: | |
1797 | pixelcode = fmt->code; | |
1f69fd97 | 1798 | *fmt = *__preview_get_format(prev, fh, PREV_PAD_SINK, which); |
de1135d4 | 1799 | |
de1135d4 LP |
1800 | switch (pixelcode) { |
1801 | case V4L2_MBUS_FMT_YUYV8_1X16: | |
1802 | case V4L2_MBUS_FMT_UYVY8_1X16: | |
1803 | fmt->code = pixelcode; | |
1804 | break; | |
1805 | ||
1806 | default: | |
1807 | fmt->code = V4L2_MBUS_FMT_YUYV8_1X16; | |
1808 | break; | |
1809 | } | |
1810 | ||
1f69fd97 LP |
1811 | /* The preview module output size is configurable through the |
1812 | * averager (horizontal scaling by 1/1, 1/2, 1/4 or 1/8). This | |
1813 | * is not supported yet, hardcode the output size to the crop | |
1814 | * rectangle size. | |
de1135d4 | 1815 | */ |
1f69fd97 LP |
1816 | crop = __preview_get_crop(prev, fh, which); |
1817 | fmt->width = crop->width; | |
1818 | fmt->height = crop->height; | |
de1135d4 LP |
1819 | |
1820 | fmt->colorspace = V4L2_COLORSPACE_JPEG; | |
1821 | break; | |
1822 | } | |
1823 | ||
1824 | fmt->field = V4L2_FIELD_NONE; | |
1825 | } | |
1826 | ||
1f69fd97 LP |
1827 | /* |
1828 | * preview_try_crop - Validate a crop rectangle | |
1829 | * @prev: ISP preview engine | |
1830 | * @sink: format on the sink pad | |
1831 | * @crop: crop rectangle to be validated | |
1832 | * | |
1833 | * The preview engine crops lines and columns for its internal operation, | |
1834 | * depending on which filters are enabled. Enforce minimum crop margins to | |
1835 | * handle that transparently for userspace. | |
1836 | * | |
1837 | * See the explanation at the PREV_MARGIN_* definitions for more details. | |
1838 | */ | |
1839 | static void preview_try_crop(struct isp_prev_device *prev, | |
1840 | const struct v4l2_mbus_framefmt *sink, | |
1841 | struct v4l2_rect *crop) | |
1842 | { | |
1843 | unsigned int left = PREV_MARGIN_LEFT; | |
1844 | unsigned int right = sink->width - PREV_MARGIN_RIGHT; | |
1845 | unsigned int top = PREV_MARGIN_TOP; | |
1846 | unsigned int bottom = sink->height - PREV_MARGIN_BOTTOM; | |
1847 | ||
1848 | /* When processing data on-the-fly from the CCDC, at least 2 pixels must | |
1849 | * be cropped from the left and right sides of the image. As we don't | |
1850 | * know which filters will be enabled, increase the left and right | |
1851 | * margins by two. | |
1852 | */ | |
1853 | if (prev->input == PREVIEW_INPUT_CCDC) { | |
1854 | left += 2; | |
1855 | right -= 2; | |
1856 | } | |
1857 | ||
1858 | /* Restrict left/top to even values to keep the Bayer pattern. */ | |
1859 | crop->left &= ~1; | |
1860 | crop->top &= ~1; | |
1861 | ||
1862 | crop->left = clamp_t(u32, crop->left, left, right - PREV_MIN_OUT_WIDTH); | |
1863 | crop->top = clamp_t(u32, crop->top, top, bottom - PREV_MIN_OUT_HEIGHT); | |
1864 | crop->width = clamp_t(u32, crop->width, PREV_MIN_OUT_WIDTH, | |
1865 | right - crop->left); | |
1866 | crop->height = clamp_t(u32, crop->height, PREV_MIN_OUT_HEIGHT, | |
1867 | bottom - crop->top); | |
1868 | } | |
1869 | ||
de1135d4 LP |
1870 | /* |
1871 | * preview_enum_mbus_code - Handle pixel format enumeration | |
1872 | * @sd : pointer to v4l2 subdev structure | |
1873 | * @fh : V4L2 subdev file handle | |
1874 | * @code : pointer to v4l2_subdev_mbus_code_enum structure | |
1875 | * return -EINVAL or zero on success | |
1876 | */ | |
1877 | static int preview_enum_mbus_code(struct v4l2_subdev *sd, | |
1878 | struct v4l2_subdev_fh *fh, | |
1879 | struct v4l2_subdev_mbus_code_enum *code) | |
1880 | { | |
1881 | switch (code->pad) { | |
1882 | case PREV_PAD_SINK: | |
1883 | if (code->index >= ARRAY_SIZE(preview_input_fmts)) | |
1884 | return -EINVAL; | |
1885 | ||
1886 | code->code = preview_input_fmts[code->index]; | |
1887 | break; | |
1888 | case PREV_PAD_SOURCE: | |
1889 | if (code->index >= ARRAY_SIZE(preview_output_fmts)) | |
1890 | return -EINVAL; | |
1891 | ||
1892 | code->code = preview_output_fmts[code->index]; | |
1893 | break; | |
1894 | default: | |
1895 | return -EINVAL; | |
1896 | } | |
1897 | ||
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | static int preview_enum_frame_size(struct v4l2_subdev *sd, | |
1902 | struct v4l2_subdev_fh *fh, | |
1903 | struct v4l2_subdev_frame_size_enum *fse) | |
1904 | { | |
1905 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
1906 | struct v4l2_mbus_framefmt format; | |
1907 | ||
1908 | if (fse->index != 0) | |
1909 | return -EINVAL; | |
1910 | ||
1911 | format.code = fse->code; | |
1912 | format.width = 1; | |
1913 | format.height = 1; | |
1914 | preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY); | |
1915 | fse->min_width = format.width; | |
1916 | fse->min_height = format.height; | |
1917 | ||
1918 | if (format.code != fse->code) | |
1919 | return -EINVAL; | |
1920 | ||
1921 | format.code = fse->code; | |
1922 | format.width = -1; | |
1923 | format.height = -1; | |
1924 | preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY); | |
1925 | fse->max_width = format.width; | |
1926 | fse->max_height = format.height; | |
1927 | ||
1928 | return 0; | |
1929 | } | |
1930 | ||
1f69fd97 | 1931 | /* |
684c8e26 | 1932 | * preview_get_selection - Retrieve a selection rectangle on a pad |
1f69fd97 LP |
1933 | * @sd: ISP preview V4L2 subdevice |
1934 | * @fh: V4L2 subdev file handle | |
684c8e26 LP |
1935 | * @sel: Selection rectangle |
1936 | * | |
1937 | * The only supported rectangles are the crop rectangles on the sink pad. | |
1f69fd97 LP |
1938 | * |
1939 | * Return 0 on success or a negative error code otherwise. | |
1940 | */ | |
684c8e26 LP |
1941 | static int preview_get_selection(struct v4l2_subdev *sd, |
1942 | struct v4l2_subdev_fh *fh, | |
1943 | struct v4l2_subdev_selection *sel) | |
1f69fd97 LP |
1944 | { |
1945 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
684c8e26 LP |
1946 | struct v4l2_mbus_framefmt *format; |
1947 | ||
1948 | if (sel->pad != PREV_PAD_SINK) | |
1949 | return -EINVAL; | |
1950 | ||
1951 | switch (sel->target) { | |
1952 | case V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS: | |
1953 | sel->r.left = 0; | |
1954 | sel->r.top = 0; | |
1955 | sel->r.width = INT_MAX; | |
1956 | sel->r.height = INT_MAX; | |
1957 | ||
1958 | format = __preview_get_format(prev, fh, PREV_PAD_SINK, | |
1959 | sel->which); | |
1960 | preview_try_crop(prev, format, &sel->r); | |
1961 | break; | |
1962 | ||
1963 | case V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL: | |
1964 | sel->r = *__preview_get_crop(prev, fh, sel->which); | |
1965 | break; | |
1f69fd97 | 1966 | |
684c8e26 | 1967 | default: |
1f69fd97 | 1968 | return -EINVAL; |
684c8e26 | 1969 | } |
1f69fd97 | 1970 | |
1f69fd97 LP |
1971 | return 0; |
1972 | } | |
1973 | ||
1974 | /* | |
684c8e26 | 1975 | * preview_set_selection - Set a selection rectangle on a pad |
1f69fd97 LP |
1976 | * @sd: ISP preview V4L2 subdevice |
1977 | * @fh: V4L2 subdev file handle | |
684c8e26 LP |
1978 | * @sel: Selection rectangle |
1979 | * | |
1980 | * The only supported rectangle is the actual crop rectangle on the sink pad. | |
1f69fd97 LP |
1981 | * |
1982 | * Return 0 on success or a negative error code otherwise. | |
1983 | */ | |
684c8e26 LP |
1984 | static int preview_set_selection(struct v4l2_subdev *sd, |
1985 | struct v4l2_subdev_fh *fh, | |
1986 | struct v4l2_subdev_selection *sel) | |
1f69fd97 LP |
1987 | { |
1988 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
1989 | struct v4l2_mbus_framefmt *format; | |
1990 | ||
684c8e26 LP |
1991 | if (sel->target != V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL || |
1992 | sel->pad != PREV_PAD_SINK) | |
1f69fd97 LP |
1993 | return -EINVAL; |
1994 | ||
1995 | /* The crop rectangle can't be changed while streaming. */ | |
1996 | if (prev->state != ISP_PIPELINE_STREAM_STOPPED) | |
1997 | return -EBUSY; | |
1998 | ||
684c8e26 LP |
1999 | /* Modifying the crop rectangle always changes the format on the source |
2000 | * pad. If the KEEP_CONFIG flag is set, just return the current crop | |
2001 | * rectangle. | |
2002 | */ | |
2003 | if (sel->flags & V4L2_SUBDEV_SEL_FLAG_KEEP_CONFIG) { | |
2004 | sel->r = *__preview_get_crop(prev, fh, sel->which); | |
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | format = __preview_get_format(prev, fh, PREV_PAD_SINK, sel->which); | |
2009 | preview_try_crop(prev, format, &sel->r); | |
2010 | *__preview_get_crop(prev, fh, sel->which) = sel->r; | |
1f69fd97 LP |
2011 | |
2012 | /* Update the source format. */ | |
684c8e26 LP |
2013 | format = __preview_get_format(prev, fh, PREV_PAD_SOURCE, sel->which); |
2014 | preview_try_format(prev, fh, PREV_PAD_SOURCE, format, sel->which); | |
1f69fd97 LP |
2015 | |
2016 | return 0; | |
2017 | } | |
2018 | ||
de1135d4 LP |
2019 | /* |
2020 | * preview_get_format - Handle get format by pads subdev method | |
2021 | * @sd : pointer to v4l2 subdev structure | |
2022 | * @fh : V4L2 subdev file handle | |
2023 | * @fmt: pointer to v4l2 subdev format structure | |
25985edc | 2024 | * return -EINVAL or zero on success |
de1135d4 LP |
2025 | */ |
2026 | static int preview_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
2027 | struct v4l2_subdev_format *fmt) | |
2028 | { | |
2029 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
2030 | struct v4l2_mbus_framefmt *format; | |
2031 | ||
2032 | format = __preview_get_format(prev, fh, fmt->pad, fmt->which); | |
2033 | if (format == NULL) | |
2034 | return -EINVAL; | |
2035 | ||
2036 | fmt->format = *format; | |
2037 | return 0; | |
2038 | } | |
2039 | ||
2040 | /* | |
2041 | * preview_set_format - Handle set format by pads subdev method | |
2042 | * @sd : pointer to v4l2 subdev structure | |
2043 | * @fh : V4L2 subdev file handle | |
2044 | * @fmt: pointer to v4l2 subdev format structure | |
2045 | * return -EINVAL or zero on success | |
2046 | */ | |
2047 | static int preview_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
2048 | struct v4l2_subdev_format *fmt) | |
2049 | { | |
2050 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
2051 | struct v4l2_mbus_framefmt *format; | |
1f69fd97 | 2052 | struct v4l2_rect *crop; |
de1135d4 LP |
2053 | |
2054 | format = __preview_get_format(prev, fh, fmt->pad, fmt->which); | |
2055 | if (format == NULL) | |
2056 | return -EINVAL; | |
2057 | ||
2058 | preview_try_format(prev, fh, fmt->pad, &fmt->format, fmt->which); | |
2059 | *format = fmt->format; | |
2060 | ||
2061 | /* Propagate the format from sink to source */ | |
2062 | if (fmt->pad == PREV_PAD_SINK) { | |
1f69fd97 LP |
2063 | /* Reset the crop rectangle. */ |
2064 | crop = __preview_get_crop(prev, fh, fmt->which); | |
2065 | crop->left = 0; | |
2066 | crop->top = 0; | |
2067 | crop->width = fmt->format.width; | |
2068 | crop->height = fmt->format.height; | |
2069 | ||
2070 | preview_try_crop(prev, &fmt->format, crop); | |
2071 | ||
2072 | /* Update the source format. */ | |
de1135d4 LP |
2073 | format = __preview_get_format(prev, fh, PREV_PAD_SOURCE, |
2074 | fmt->which); | |
de1135d4 LP |
2075 | preview_try_format(prev, fh, PREV_PAD_SOURCE, format, |
2076 | fmt->which); | |
2077 | } | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
2082 | /* | |
2083 | * preview_init_formats - Initialize formats on all pads | |
2084 | * @sd: ISP preview V4L2 subdevice | |
2085 | * @fh: V4L2 subdev file handle | |
2086 | * | |
2087 | * Initialize all pad formats with default values. If fh is not NULL, try | |
2088 | * formats are initialized on the file handle. Otherwise active formats are | |
2089 | * initialized on the device. | |
2090 | */ | |
2091 | static int preview_init_formats(struct v4l2_subdev *sd, | |
2092 | struct v4l2_subdev_fh *fh) | |
2093 | { | |
2094 | struct v4l2_subdev_format format; | |
2095 | ||
2096 | memset(&format, 0, sizeof(format)); | |
2097 | format.pad = PREV_PAD_SINK; | |
2098 | format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; | |
2099 | format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
2100 | format.format.width = 4096; | |
2101 | format.format.height = 4096; | |
2102 | preview_set_format(sd, fh, &format); | |
2103 | ||
2104 | return 0; | |
2105 | } | |
2106 | ||
2107 | /* subdev core operations */ | |
2108 | static const struct v4l2_subdev_core_ops preview_v4l2_core_ops = { | |
2109 | .ioctl = preview_ioctl, | |
2110 | }; | |
2111 | ||
2112 | /* subdev video operations */ | |
2113 | static const struct v4l2_subdev_video_ops preview_v4l2_video_ops = { | |
2114 | .s_stream = preview_set_stream, | |
2115 | }; | |
2116 | ||
2117 | /* subdev pad operations */ | |
2118 | static const struct v4l2_subdev_pad_ops preview_v4l2_pad_ops = { | |
2119 | .enum_mbus_code = preview_enum_mbus_code, | |
2120 | .enum_frame_size = preview_enum_frame_size, | |
2121 | .get_fmt = preview_get_format, | |
2122 | .set_fmt = preview_set_format, | |
684c8e26 LP |
2123 | .get_selection = preview_get_selection, |
2124 | .set_selection = preview_set_selection, | |
de1135d4 LP |
2125 | }; |
2126 | ||
2127 | /* subdev operations */ | |
2128 | static const struct v4l2_subdev_ops preview_v4l2_ops = { | |
2129 | .core = &preview_v4l2_core_ops, | |
2130 | .video = &preview_v4l2_video_ops, | |
2131 | .pad = &preview_v4l2_pad_ops, | |
2132 | }; | |
2133 | ||
2134 | /* subdev internal operations */ | |
2135 | static const struct v4l2_subdev_internal_ops preview_v4l2_internal_ops = { | |
2136 | .open = preview_init_formats, | |
2137 | }; | |
2138 | ||
2139 | /* ----------------------------------------------------------------------------- | |
2140 | * Media entity operations | |
2141 | */ | |
2142 | ||
2143 | /* | |
2144 | * preview_link_setup - Setup previewer connections. | |
2145 | * @entity : Pointer to media entity structure | |
2146 | * @local : Pointer to local pad array | |
2147 | * @remote : Pointer to remote pad array | |
2148 | * @flags : Link flags | |
2149 | * return -EINVAL or zero on success | |
2150 | */ | |
2151 | static int preview_link_setup(struct media_entity *entity, | |
2152 | const struct media_pad *local, | |
2153 | const struct media_pad *remote, u32 flags) | |
2154 | { | |
2155 | struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); | |
2156 | struct isp_prev_device *prev = v4l2_get_subdevdata(sd); | |
2157 | ||
2158 | switch (local->index | media_entity_type(remote->entity)) { | |
2159 | case PREV_PAD_SINK | MEDIA_ENT_T_DEVNODE: | |
2160 | /* read from memory */ | |
2161 | if (flags & MEDIA_LNK_FL_ENABLED) { | |
2162 | if (prev->input == PREVIEW_INPUT_CCDC) | |
2163 | return -EBUSY; | |
2164 | prev->input = PREVIEW_INPUT_MEMORY; | |
2165 | } else { | |
2166 | if (prev->input == PREVIEW_INPUT_MEMORY) | |
2167 | prev->input = PREVIEW_INPUT_NONE; | |
2168 | } | |
2169 | break; | |
2170 | ||
2171 | case PREV_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV: | |
2172 | /* read from ccdc */ | |
2173 | if (flags & MEDIA_LNK_FL_ENABLED) { | |
2174 | if (prev->input == PREVIEW_INPUT_MEMORY) | |
2175 | return -EBUSY; | |
2176 | prev->input = PREVIEW_INPUT_CCDC; | |
2177 | } else { | |
2178 | if (prev->input == PREVIEW_INPUT_CCDC) | |
2179 | prev->input = PREVIEW_INPUT_NONE; | |
2180 | } | |
2181 | break; | |
2182 | ||
2183 | /* | |
2184 | * The ISP core doesn't support pipelines with multiple video outputs. | |
2185 | * Revisit this when it will be implemented, and return -EBUSY for now. | |
2186 | */ | |
2187 | ||
2188 | case PREV_PAD_SOURCE | MEDIA_ENT_T_DEVNODE: | |
2189 | /* write to memory */ | |
2190 | if (flags & MEDIA_LNK_FL_ENABLED) { | |
2191 | if (prev->output & ~PREVIEW_OUTPUT_MEMORY) | |
2192 | return -EBUSY; | |
2193 | prev->output |= PREVIEW_OUTPUT_MEMORY; | |
2194 | } else { | |
2195 | prev->output &= ~PREVIEW_OUTPUT_MEMORY; | |
2196 | } | |
2197 | break; | |
2198 | ||
2199 | case PREV_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV: | |
2200 | /* write to resizer */ | |
2201 | if (flags & MEDIA_LNK_FL_ENABLED) { | |
2202 | if (prev->output & ~PREVIEW_OUTPUT_RESIZER) | |
2203 | return -EBUSY; | |
2204 | prev->output |= PREVIEW_OUTPUT_RESIZER; | |
2205 | } else { | |
2206 | prev->output &= ~PREVIEW_OUTPUT_RESIZER; | |
2207 | } | |
2208 | break; | |
2209 | ||
2210 | default: | |
2211 | return -EINVAL; | |
2212 | } | |
2213 | ||
2214 | return 0; | |
2215 | } | |
2216 | ||
2217 | /* media operations */ | |
2218 | static const struct media_entity_operations preview_media_ops = { | |
2219 | .link_setup = preview_link_setup, | |
20d4ab7b | 2220 | .link_validate = v4l2_subdev_link_validate, |
de1135d4 LP |
2221 | }; |
2222 | ||
39099d09 LP |
2223 | void omap3isp_preview_unregister_entities(struct isp_prev_device *prev) |
2224 | { | |
2225 | v4l2_device_unregister_subdev(&prev->subdev); | |
2226 | omap3isp_video_unregister(&prev->video_in); | |
2227 | omap3isp_video_unregister(&prev->video_out); | |
2228 | } | |
2229 | ||
2230 | int omap3isp_preview_register_entities(struct isp_prev_device *prev, | |
2231 | struct v4l2_device *vdev) | |
2232 | { | |
2233 | int ret; | |
2234 | ||
2235 | /* Register the subdev and video nodes. */ | |
2236 | ret = v4l2_device_register_subdev(vdev, &prev->subdev); | |
2237 | if (ret < 0) | |
2238 | goto error; | |
2239 | ||
2240 | ret = omap3isp_video_register(&prev->video_in, vdev); | |
2241 | if (ret < 0) | |
2242 | goto error; | |
2243 | ||
2244 | ret = omap3isp_video_register(&prev->video_out, vdev); | |
2245 | if (ret < 0) | |
2246 | goto error; | |
2247 | ||
2248 | return 0; | |
2249 | ||
2250 | error: | |
2251 | omap3isp_preview_unregister_entities(prev); | |
2252 | return ret; | |
2253 | } | |
2254 | ||
2255 | /* ----------------------------------------------------------------------------- | |
2256 | * ISP previewer initialisation and cleanup | |
2257 | */ | |
2258 | ||
de1135d4 | 2259 | /* |
39099d09 | 2260 | * preview_init_entities - Initialize subdev and media entity. |
de1135d4 LP |
2261 | * @prev : Pointer to preview structure |
2262 | * return -ENOMEM or zero on success | |
2263 | */ | |
2264 | static int preview_init_entities(struct isp_prev_device *prev) | |
2265 | { | |
2266 | struct v4l2_subdev *sd = &prev->subdev; | |
2267 | struct media_pad *pads = prev->pads; | |
2268 | struct media_entity *me = &sd->entity; | |
2269 | int ret; | |
2270 | ||
2271 | prev->input = PREVIEW_INPUT_NONE; | |
2272 | ||
2273 | v4l2_subdev_init(sd, &preview_v4l2_ops); | |
2274 | sd->internal_ops = &preview_v4l2_internal_ops; | |
2275 | strlcpy(sd->name, "OMAP3 ISP preview", sizeof(sd->name)); | |
2276 | sd->grp_id = 1 << 16; /* group ID for isp subdevs */ | |
2277 | v4l2_set_subdevdata(sd, prev); | |
2278 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
2279 | ||
2280 | v4l2_ctrl_handler_init(&prev->ctrls, 2); | |
2281 | v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_BRIGHTNESS, | |
2282 | ISPPRV_BRIGHT_LOW, ISPPRV_BRIGHT_HIGH, | |
2283 | ISPPRV_BRIGHT_STEP, ISPPRV_BRIGHT_DEF); | |
2284 | v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_CONTRAST, | |
2285 | ISPPRV_CONTRAST_LOW, ISPPRV_CONTRAST_HIGH, | |
2286 | ISPPRV_CONTRAST_STEP, ISPPRV_CONTRAST_DEF); | |
2287 | v4l2_ctrl_handler_setup(&prev->ctrls); | |
2288 | sd->ctrl_handler = &prev->ctrls; | |
2289 | ||
2290 | pads[PREV_PAD_SINK].flags = MEDIA_PAD_FL_SINK; | |
2291 | pads[PREV_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; | |
2292 | ||
2293 | me->ops = &preview_media_ops; | |
2294 | ret = media_entity_init(me, PREV_PADS_NUM, pads, 0); | |
2295 | if (ret < 0) | |
2296 | return ret; | |
2297 | ||
2298 | preview_init_formats(sd, NULL); | |
2299 | ||
2300 | /* According to the OMAP34xx TRM, video buffers need to be aligned on a | |
2301 | * 32 bytes boundary. However, an undocumented hardware bug requires a | |
2302 | * 64 bytes boundary at the preview engine input. | |
2303 | */ | |
2304 | prev->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; | |
2305 | prev->video_in.ops = &preview_video_ops; | |
2306 | prev->video_in.isp = to_isp_device(prev); | |
2307 | prev->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3; | |
2308 | prev->video_in.bpl_alignment = 64; | |
2309 | prev->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
2310 | prev->video_out.ops = &preview_video_ops; | |
2311 | prev->video_out.isp = to_isp_device(prev); | |
2312 | prev->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3; | |
2313 | prev->video_out.bpl_alignment = 32; | |
2314 | ||
2315 | ret = omap3isp_video_init(&prev->video_in, "preview"); | |
2316 | if (ret < 0) | |
9b6390bd | 2317 | goto error_video_in; |
de1135d4 LP |
2318 | |
2319 | ret = omap3isp_video_init(&prev->video_out, "preview"); | |
2320 | if (ret < 0) | |
9b6390bd | 2321 | goto error_video_out; |
de1135d4 LP |
2322 | |
2323 | /* Connect the video nodes to the previewer subdev. */ | |
2324 | ret = media_entity_create_link(&prev->video_in.video.entity, 0, | |
2325 | &prev->subdev.entity, PREV_PAD_SINK, 0); | |
2326 | if (ret < 0) | |
9b6390bd | 2327 | goto error_link; |
de1135d4 LP |
2328 | |
2329 | ret = media_entity_create_link(&prev->subdev.entity, PREV_PAD_SOURCE, | |
2330 | &prev->video_out.video.entity, 0, 0); | |
2331 | if (ret < 0) | |
9b6390bd | 2332 | goto error_link; |
de1135d4 LP |
2333 | |
2334 | return 0; | |
9b6390bd LP |
2335 | |
2336 | error_link: | |
2337 | omap3isp_video_cleanup(&prev->video_out); | |
2338 | error_video_out: | |
2339 | omap3isp_video_cleanup(&prev->video_in); | |
2340 | error_video_in: | |
2341 | media_entity_cleanup(&prev->subdev.entity); | |
2342 | return ret; | |
de1135d4 LP |
2343 | } |
2344 | ||
de1135d4 | 2345 | /* |
b0b29e1e | 2346 | * omap3isp_preview_init - Previewer initialization. |
de1135d4 LP |
2347 | * @dev : Pointer to ISP device |
2348 | * return -ENOMEM or zero on success | |
2349 | */ | |
2350 | int omap3isp_preview_init(struct isp_device *isp) | |
2351 | { | |
2352 | struct isp_prev_device *prev = &isp->isp_prev; | |
de1135d4 | 2353 | |
de1135d4 | 2354 | init_waitqueue_head(&prev->wait); |
b0b29e1e | 2355 | |
de1135d4 LP |
2356 | preview_init_params(prev); |
2357 | ||
9b6390bd | 2358 | return preview_init_entities(prev); |
de1135d4 | 2359 | } |
39099d09 LP |
2360 | |
2361 | void omap3isp_preview_cleanup(struct isp_device *isp) | |
2362 | { | |
2363 | struct isp_prev_device *prev = &isp->isp_prev; | |
2364 | ||
2365 | v4l2_ctrl_handler_free(&prev->ctrls); | |
2366 | omap3isp_video_cleanup(&prev->video_in); | |
2367 | omap3isp_video_cleanup(&prev->video_out); | |
2368 | media_entity_cleanup(&prev->subdev.entity); | |
2369 | } |