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08a66aea KM |
1 | /* |
2 | * ov772x Camera Driver | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ov7670 and soc_camera_platform driver, | |
8 | * | |
9 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> | |
10 | * Copyright (C) 2008 Magnus Damm | |
11 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/videodev2.h> | |
24 | #include <media/v4l2-chip-ident.h> | |
25 | #include <media/v4l2-common.h> | |
26 | #include <media/soc_camera.h> | |
27 | #include <media/ov772x.h> | |
28 | ||
29 | /* | |
30 | * register offset | |
31 | */ | |
32 | #define GAIN 0x00 /* AGC - Gain control gain setting */ | |
33 | #define BLUE 0x01 /* AWB - Blue channel gain setting */ | |
34 | #define RED 0x02 /* AWB - Red channel gain setting */ | |
35 | #define GREEN 0x03 /* AWB - Green channel gain setting */ | |
36 | #define COM1 0x04 /* Common control 1 */ | |
37 | #define BAVG 0x05 /* U/B Average Level */ | |
38 | #define GAVG 0x06 /* Y/Gb Average Level */ | |
39 | #define RAVG 0x07 /* V/R Average Level */ | |
40 | #define AECH 0x08 /* Exposure Value - AEC MSBs */ | |
41 | #define COM2 0x09 /* Common control 2 */ | |
42 | #define PID 0x0A /* Product ID Number MSB */ | |
43 | #define VER 0x0B /* Product ID Number LSB */ | |
44 | #define COM3 0x0C /* Common control 3 */ | |
45 | #define COM4 0x0D /* Common control 4 */ | |
46 | #define COM5 0x0E /* Common control 5 */ | |
47 | #define COM6 0x0F /* Common control 6 */ | |
48 | #define AEC 0x10 /* Exposure Value */ | |
49 | #define CLKRC 0x11 /* Internal clock */ | |
50 | #define COM7 0x12 /* Common control 7 */ | |
51 | #define COM8 0x13 /* Common control 8 */ | |
52 | #define COM9 0x14 /* Common control 9 */ | |
53 | #define COM10 0x15 /* Common control 10 */ | |
3cac2cab | 54 | #define REG16 0x16 /* Register 16 */ |
08a66aea KM |
55 | #define HSTART 0x17 /* Horizontal sensor size */ |
56 | #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */ | |
57 | #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */ | |
58 | #define VSIZE 0x1A /* Vertical sensor size */ | |
59 | #define PSHFT 0x1B /* Data format - pixel delay select */ | |
60 | #define MIDH 0x1C /* Manufacturer ID byte - high */ | |
61 | #define MIDL 0x1D /* Manufacturer ID byte - low */ | |
62 | #define LAEC 0x1F /* Fine AEC value */ | |
63 | #define COM11 0x20 /* Common control 11 */ | |
64 | #define BDBASE 0x22 /* Banding filter Minimum AEC value */ | |
65 | #define DBSTEP 0x23 /* Banding filter Maximum Setp */ | |
66 | #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ | |
67 | #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ | |
68 | #define VPT 0x26 /* AGC/AEC Fast mode operating region */ | |
3cac2cab | 69 | #define REG28 0x28 /* Register 28 */ |
08a66aea KM |
70 | #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */ |
71 | #define EXHCH 0x2A /* Dummy pixel insert MSB */ | |
72 | #define EXHCL 0x2B /* Dummy pixel insert LSB */ | |
73 | #define VOUTSIZE 0x2C /* Vertical data output size MSBs */ | |
74 | #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ | |
75 | #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */ | |
76 | #define YAVE 0x2F /* Y/G Channel Average value */ | |
77 | #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */ | |
78 | #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */ | |
79 | #define HREF 0x32 /* Image start and size control */ | |
80 | #define DM_LNL 0x33 /* Dummy line low 8 bits */ | |
81 | #define DM_LNH 0x34 /* Dummy line high 8 bits */ | |
82 | #define ADOFF_B 0x35 /* AD offset compensation value for B channel */ | |
83 | #define ADOFF_R 0x36 /* AD offset compensation value for R channel */ | |
84 | #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */ | |
85 | #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */ | |
86 | #define OFF_B 0x39 /* Analog process B channel offset value */ | |
87 | #define OFF_R 0x3A /* Analog process R channel offset value */ | |
88 | #define OFF_GB 0x3B /* Analog process Gb channel offset value */ | |
89 | #define OFF_GR 0x3C /* Analog process Gr channel offset value */ | |
90 | #define COM12 0x3D /* Common control 12 */ | |
91 | #define COM13 0x3E /* Common control 13 */ | |
92 | #define COM14 0x3F /* Common control 14 */ | |
93 | #define COM15 0x40 /* Common control 15*/ | |
94 | #define COM16 0x41 /* Common control 16 */ | |
95 | #define TGT_B 0x42 /* BLC blue channel target value */ | |
96 | #define TGT_R 0x43 /* BLC red channel target value */ | |
97 | #define TGT_GB 0x44 /* BLC Gb channel target value */ | |
98 | #define TGT_GR 0x45 /* BLC Gr channel target value */ | |
3cac2cab | 99 | /* for ov7720 */ |
08a66aea KM |
100 | #define LCC0 0x46 /* Lens correction control 0 */ |
101 | #define LCC1 0x47 /* Lens correction option 1 - X coordinate */ | |
102 | #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */ | |
103 | #define LCC3 0x49 /* Lens correction option 3 */ | |
104 | #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */ | |
105 | #define LCC5 0x4B /* Lens correction option 5 */ | |
106 | #define LCC6 0x4C /* Lens correction option 6 */ | |
3cac2cab KM |
107 | /* for ov7725 */ |
108 | #define LC_CTR 0x46 /* Lens correction control */ | |
109 | #define LC_XC 0x47 /* X coordinate of lens correction center relative */ | |
110 | #define LC_YC 0x48 /* Y coordinate of lens correction center relative */ | |
111 | #define LC_COEF 0x49 /* Lens correction coefficient */ | |
112 | #define LC_RADI 0x4A /* Lens correction radius */ | |
113 | #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */ | |
114 | #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */ | |
115 | ||
08a66aea KM |
116 | #define FIXGAIN 0x4D /* Analog fix gain amplifer */ |
117 | #define AREF0 0x4E /* Sensor reference control */ | |
118 | #define AREF1 0x4F /* Sensor reference current control */ | |
119 | #define AREF2 0x50 /* Analog reference control */ | |
120 | #define AREF3 0x51 /* ADC reference control */ | |
121 | #define AREF4 0x52 /* ADC reference control */ | |
122 | #define AREF5 0x53 /* ADC reference control */ | |
123 | #define AREF6 0x54 /* Analog reference control */ | |
124 | #define AREF7 0x55 /* Analog reference control */ | |
125 | #define UFIX 0x60 /* U channel fixed value output */ | |
126 | #define VFIX 0x61 /* V channel fixed value output */ | |
b3d7b2ad KM |
127 | #define AWBB_BLK 0x62 /* AWB option for advanced AWB */ |
128 | #define AWB_CTRL0 0x63 /* AWB control byte 0 */ | |
08a66aea KM |
129 | #define DSP_CTRL1 0x64 /* DSP control byte 1 */ |
130 | #define DSP_CTRL2 0x65 /* DSP control byte 2 */ | |
131 | #define DSP_CTRL3 0x66 /* DSP control byte 3 */ | |
132 | #define DSP_CTRL4 0x67 /* DSP control byte 4 */ | |
b3d7b2ad KM |
133 | #define AWB_BIAS 0x68 /* AWB BLC level clip */ |
134 | #define AWB_CTRL1 0x69 /* AWB control 1 */ | |
135 | #define AWB_CTRL2 0x6A /* AWB control 2 */ | |
136 | #define AWB_CTRL3 0x6B /* AWB control 3 */ | |
137 | #define AWB_CTRL4 0x6C /* AWB control 4 */ | |
138 | #define AWB_CTRL5 0x6D /* AWB control 5 */ | |
139 | #define AWB_CTRL6 0x6E /* AWB control 6 */ | |
140 | #define AWB_CTRL7 0x6F /* AWB control 7 */ | |
141 | #define AWB_CTRL8 0x70 /* AWB control 8 */ | |
142 | #define AWB_CTRL9 0x71 /* AWB control 9 */ | |
143 | #define AWB_CTRL10 0x72 /* AWB control 10 */ | |
144 | #define AWB_CTRL11 0x73 /* AWB control 11 */ | |
145 | #define AWB_CTRL12 0x74 /* AWB control 12 */ | |
146 | #define AWB_CTRL13 0x75 /* AWB control 13 */ | |
147 | #define AWB_CTRL14 0x76 /* AWB control 14 */ | |
148 | #define AWB_CTRL15 0x77 /* AWB control 15 */ | |
149 | #define AWB_CTRL16 0x78 /* AWB control 16 */ | |
150 | #define AWB_CTRL17 0x79 /* AWB control 17 */ | |
151 | #define AWB_CTRL18 0x7A /* AWB control 18 */ | |
152 | #define AWB_CTRL19 0x7B /* AWB control 19 */ | |
153 | #define AWB_CTRL20 0x7C /* AWB control 20 */ | |
154 | #define AWB_CTRL21 0x7D /* AWB control 21 */ | |
08a66aea KM |
155 | #define GAM1 0x7E /* Gamma Curve 1st segment input end point */ |
156 | #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */ | |
157 | #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */ | |
158 | #define GAM4 0x81 /* Gamma Curve 4th segment input end point */ | |
159 | #define GAM5 0x82 /* Gamma Curve 5th segment input end point */ | |
160 | #define GAM6 0x83 /* Gamma Curve 6th segment input end point */ | |
161 | #define GAM7 0x84 /* Gamma Curve 7th segment input end point */ | |
162 | #define GAM8 0x85 /* Gamma Curve 8th segment input end point */ | |
163 | #define GAM9 0x86 /* Gamma Curve 9th segment input end point */ | |
164 | #define GAM10 0x87 /* Gamma Curve 10th segment input end point */ | |
165 | #define GAM11 0x88 /* Gamma Curve 11th segment input end point */ | |
166 | #define GAM12 0x89 /* Gamma Curve 12th segment input end point */ | |
167 | #define GAM13 0x8A /* Gamma Curve 13th segment input end point */ | |
168 | #define GAM14 0x8B /* Gamma Curve 14th segment input end point */ | |
169 | #define GAM15 0x8C /* Gamma Curve 15th segment input end point */ | |
170 | #define SLOP 0x8D /* Gamma curve highest segment slope */ | |
171 | #define DNSTH 0x8E /* De-noise threshold */ | |
db6cbc8c KM |
172 | #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */ |
173 | #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */ | |
08a66aea | 174 | #define DNSOFF 0x91 /* Auto De-noise threshold control */ |
db6cbc8c KM |
175 | #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */ |
176 | #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */ | |
08a66aea KM |
177 | #define MTX1 0x94 /* Matrix coefficient 1 */ |
178 | #define MTX2 0x95 /* Matrix coefficient 2 */ | |
179 | #define MTX3 0x96 /* Matrix coefficient 3 */ | |
180 | #define MTX4 0x97 /* Matrix coefficient 4 */ | |
181 | #define MTX5 0x98 /* Matrix coefficient 5 */ | |
182 | #define MTX6 0x99 /* Matrix coefficient 6 */ | |
183 | #define MTX_CTRL 0x9A /* Matrix control */ | |
184 | #define BRIGHT 0x9B /* Brightness control */ | |
185 | #define CNTRST 0x9C /* Contrast contrast */ | |
186 | #define CNTRST_CTRL 0x9D /* Contrast contrast center */ | |
187 | #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */ | |
188 | #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */ | |
189 | #define SCAL0 0xA0 /* Scaling control 0 */ | |
190 | #define SCAL1 0xA1 /* Scaling control 1 */ | |
191 | #define SCAL2 0xA2 /* Scaling control 2 */ | |
192 | #define FIFODLYM 0xA3 /* FIFO manual mode delay control */ | |
193 | #define FIFODLYA 0xA4 /* FIFO auto mode delay control */ | |
194 | #define SDE 0xA6 /* Special digital effect control */ | |
195 | #define USAT 0xA7 /* U component saturation control */ | |
196 | #define VSAT 0xA8 /* V component saturation control */ | |
3cac2cab | 197 | /* for ov7720 */ |
08a66aea KM |
198 | #define HUE0 0xA9 /* Hue control 0 */ |
199 | #define HUE1 0xAA /* Hue control 1 */ | |
3cac2cab KM |
200 | /* for ov7725 */ |
201 | #define HUECOS 0xA9 /* Cosine value */ | |
202 | #define HUESIN 0xAA /* Sine value */ | |
203 | ||
08a66aea KM |
204 | #define SIGN 0xAB /* Sign bit for Hue and contrast */ |
205 | #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */ | |
206 | ||
207 | /* | |
208 | * register detail | |
209 | */ | |
210 | ||
211 | /* COM2 */ | |
212 | #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ | |
213 | /* Output drive capability */ | |
214 | #define OCAP_1x 0x00 /* 1x */ | |
215 | #define OCAP_2x 0x01 /* 2x */ | |
216 | #define OCAP_3x 0x02 /* 3x */ | |
217 | #define OCAP_4x 0x03 /* 4x */ | |
218 | ||
219 | /* COM3 */ | |
05148911 KM |
220 | #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML) |
221 | #define IMG_MASK (VFLIP_IMG | HFLIP_IMG) | |
08a66aea | 222 | |
05148911 KM |
223 | #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */ |
224 | #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */ | |
08a66aea KM |
225 | #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */ |
226 | #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */ | |
227 | #define SWAP_ML 0x08 /* Swap output MSB/LSB */ | |
228 | /* Tri-state option for output clock */ | |
229 | #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */ | |
230 | /* 1: No tri-state at this period */ | |
231 | /* Tri-state option for output data */ | |
232 | #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */ | |
233 | /* 1: No tri-state at this period */ | |
234 | #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */ | |
235 | ||
236 | /* COM4 */ | |
237 | /* PLL frequency control */ | |
238 | #define PLL_BYPASS 0x00 /* 00: Bypass PLL */ | |
239 | #define PLL_4x 0x40 /* 01: PLL 4x */ | |
240 | #define PLL_6x 0x80 /* 10: PLL 6x */ | |
241 | #define PLL_8x 0xc0 /* 11: PLL 8x */ | |
242 | /* AEC evaluate window */ | |
243 | #define AEC_FULL 0x00 /* 00: Full window */ | |
244 | #define AEC_1p2 0x10 /* 01: 1/2 window */ | |
245 | #define AEC_1p4 0x20 /* 10: 1/4 window */ | |
246 | #define AEC_2p3 0x30 /* 11: Low 2/3 window */ | |
247 | ||
248 | /* COM5 */ | |
249 | #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */ | |
250 | #define AFR_SPPED 0x40 /* Auto frame rate control speed slection */ | |
251 | /* Auto frame rate max rate control */ | |
252 | #define AFR_NO_RATE 0x00 /* No reduction of frame rate */ | |
253 | #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */ | |
254 | #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */ | |
255 | #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */ | |
256 | /* Auto frame rate active point control */ | |
257 | #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */ | |
258 | #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */ | |
259 | #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */ | |
260 | #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */ | |
261 | /* AEC max step control */ | |
262 | #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */ | |
263 | /* 1 : No limit to AEC increase step */ | |
264 | ||
265 | /* COM7 */ | |
266 | /* SCCB Register Reset */ | |
267 | #define SCCB_RESET 0x80 /* 0 : No change */ | |
268 | /* 1 : Resets all registers to default */ | |
269 | /* Resolution selection */ | |
270 | #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */ | |
271 | #define SLCT_VGA 0x00 /* 0 : VGA */ | |
272 | #define SLCT_QVGA 0x40 /* 1 : QVGA */ | |
273 | #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */ | |
274 | /* RGB output format control */ | |
cdce7c0b | 275 | #define FMT_MASK 0x0c /* Mask of color format */ |
08a66aea KM |
276 | #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */ |
277 | #define FMT_RGB565 0x04 /* 01 : RGB 565 */ | |
278 | #define FMT_RGB555 0x08 /* 10 : RGB 555 */ | |
279 | #define FMT_RGB444 0x0c /* 11 : RGB 444 */ | |
280 | /* Output format control */ | |
cdce7c0b | 281 | #define OFMT_MASK 0x03 /* Mask of output format */ |
08a66aea KM |
282 | #define OFMT_YUV 0x00 /* 00 : YUV */ |
283 | #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */ | |
284 | #define OFMT_RGB 0x02 /* 10 : RGB */ | |
285 | #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */ | |
286 | ||
287 | /* COM8 */ | |
288 | #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */ | |
289 | /* AEC Setp size limit */ | |
290 | #define UNLMT_STEP 0x40 /* 0 : Step size is limited */ | |
291 | /* 1 : Unlimited step size */ | |
292 | #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */ | |
293 | #define AEC_BND 0x10 /* Enable AEC below banding value */ | |
294 | #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */ | |
295 | #define AGC_ON 0x04 /* AGC Enable */ | |
296 | #define AWB_ON 0x02 /* AWB Enable */ | |
297 | #define AEC_ON 0x01 /* AEC Enable */ | |
298 | ||
299 | /* COM9 */ | |
300 | #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */ | |
301 | /* Automatic gain ceiling - maximum AGC value */ | |
302 | #define GAIN_2x 0x00 /* 000 : 2x */ | |
303 | #define GAIN_4x 0x10 /* 001 : 4x */ | |
304 | #define GAIN_8x 0x20 /* 010 : 8x */ | |
cdce7c0b | 305 | #define GAIN_16x 0x30 /* 011 : 16x */ |
08a66aea KM |
306 | #define GAIN_32x 0x40 /* 100 : 32x */ |
307 | #define GAIN_64x 0x50 /* 101 : 64x */ | |
308 | #define GAIN_128x 0x60 /* 110 : 128x */ | |
309 | #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */ | |
310 | #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */ | |
311 | ||
312 | /* COM11 */ | |
313 | #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */ | |
314 | #define SGLF_TRIG 0x01 /* Single frame transfer trigger */ | |
315 | ||
316 | /* EXHCH */ | |
317 | #define VSIZE_LSB 0x04 /* Vertical data output size LSB */ | |
318 | ||
319 | /* DSP_CTRL1 */ | |
320 | #define FIFO_ON 0x80 /* FIFO enable/disable selection */ | |
321 | #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */ | |
322 | #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */ | |
323 | #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */ | |
324 | #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */ | |
325 | #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */ | |
326 | #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */ | |
327 | #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */ | |
328 | ||
329 | /* DSP_CTRL3 */ | |
330 | #define UV_MASK 0x80 /* UV output sequence option */ | |
331 | #define UV_ON 0x80 /* ON */ | |
332 | #define UV_OFF 0x00 /* OFF */ | |
333 | #define CBAR_MASK 0x20 /* DSP Color bar mask */ | |
334 | #define CBAR_ON 0x20 /* ON */ | |
335 | #define CBAR_OFF 0x00 /* OFF */ | |
336 | ||
337 | /* HSTART */ | |
338 | #define HST_VGA 0x23 | |
339 | #define HST_QVGA 0x3F | |
340 | ||
341 | /* HSIZE */ | |
342 | #define HSZ_VGA 0xA0 | |
343 | #define HSZ_QVGA 0x50 | |
344 | ||
345 | /* VSTART */ | |
346 | #define VST_VGA 0x07 | |
347 | #define VST_QVGA 0x03 | |
348 | ||
349 | /* VSIZE */ | |
350 | #define VSZ_VGA 0xF0 | |
351 | #define VSZ_QVGA 0x78 | |
352 | ||
353 | /* HOUTSIZE */ | |
354 | #define HOSZ_VGA 0xA0 | |
355 | #define HOSZ_QVGA 0x50 | |
356 | ||
357 | /* VOUTSIZE */ | |
358 | #define VOSZ_VGA 0xF0 | |
359 | #define VOSZ_QVGA 0x78 | |
360 | ||
db6cbc8c KM |
361 | /* DSPAUTO (DSP Auto Function ON/OFF Control) */ |
362 | #define AWB_ACTRL 0x80 /* AWB auto threshold control */ | |
363 | #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */ | |
364 | #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */ | |
365 | #define UV_ACTRL 0x10 /* UV adjust auto slope control */ | |
366 | #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */ | |
367 | #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */ | |
368 | ||
aeabc882 KM |
369 | /* |
370 | * ID | |
371 | */ | |
372 | #define OV7720 0x7720 | |
3cac2cab | 373 | #define OV7725 0x7721 |
aeabc882 KM |
374 | #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF)) |
375 | ||
08a66aea KM |
376 | /* |
377 | * struct | |
378 | */ | |
379 | struct regval_list { | |
380 | unsigned char reg_num; | |
381 | unsigned char value; | |
382 | }; | |
383 | ||
384 | struct ov772x_color_format { | |
385 | char *name; | |
386 | __u32 fourcc; | |
cdce7c0b KM |
387 | u8 dsp3; |
388 | u8 com3; | |
389 | u8 com7; | |
08a66aea KM |
390 | }; |
391 | ||
392 | struct ov772x_win_size { | |
393 | char *name; | |
394 | __u32 width; | |
395 | __u32 height; | |
396 | unsigned char com7_bit; | |
397 | const struct regval_list *regs; | |
398 | }; | |
399 | ||
400 | struct ov772x_priv { | |
401 | struct ov772x_camera_info *info; | |
402 | struct i2c_client *client; | |
403 | struct soc_camera_device icd; | |
404 | const struct ov772x_color_format *fmt; | |
405 | const struct ov772x_win_size *win; | |
aeabc882 | 406 | int model; |
05148911 KM |
407 | unsigned int flag_vflip:1; |
408 | unsigned int flag_hflip:1; | |
08a66aea KM |
409 | }; |
410 | ||
411 | #define ENDMARKER { 0xff, 0xff } | |
412 | ||
08a66aea KM |
413 | /* |
414 | * register setting for window size | |
415 | */ | |
416 | static const struct regval_list ov772x_qvga_regs[] = { | |
417 | { HSTART, HST_QVGA }, | |
418 | { HSIZE, HSZ_QVGA }, | |
419 | { VSTART, VST_QVGA }, | |
420 | { VSIZE, VSZ_QVGA }, | |
421 | { HOUTSIZE, HOSZ_QVGA }, | |
422 | { VOUTSIZE, VOSZ_QVGA }, | |
423 | ENDMARKER, | |
424 | }; | |
425 | ||
426 | static const struct regval_list ov772x_vga_regs[] = { | |
427 | { HSTART, HST_VGA }, | |
428 | { HSIZE, HSZ_VGA }, | |
429 | { VSTART, VST_VGA }, | |
430 | { VSIZE, VSZ_VGA }, | |
431 | { HOUTSIZE, HOSZ_VGA }, | |
432 | { VOUTSIZE, VOSZ_VGA }, | |
433 | ENDMARKER, | |
434 | }; | |
435 | ||
436 | /* | |
437 | * supported format list | |
438 | */ | |
439 | ||
440 | #define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type) | |
441 | static const struct soc_camera_data_format ov772x_fmt_lists[] = { | |
442 | { | |
443 | SETFOURCC(YUYV), | |
444 | .depth = 16, | |
445 | .colorspace = V4L2_COLORSPACE_JPEG, | |
446 | }, | |
447 | { | |
448 | SETFOURCC(YVYU), | |
449 | .depth = 16, | |
450 | .colorspace = V4L2_COLORSPACE_JPEG, | |
451 | }, | |
452 | { | |
453 | SETFOURCC(UYVY), | |
454 | .depth = 16, | |
455 | .colorspace = V4L2_COLORSPACE_JPEG, | |
456 | }, | |
457 | { | |
458 | SETFOURCC(RGB555), | |
459 | .depth = 16, | |
460 | .colorspace = V4L2_COLORSPACE_SRGB, | |
461 | }, | |
462 | { | |
463 | SETFOURCC(RGB555X), | |
464 | .depth = 16, | |
465 | .colorspace = V4L2_COLORSPACE_SRGB, | |
466 | }, | |
467 | { | |
468 | SETFOURCC(RGB565), | |
469 | .depth = 16, | |
470 | .colorspace = V4L2_COLORSPACE_SRGB, | |
471 | }, | |
472 | { | |
473 | SETFOURCC(RGB565X), | |
474 | .depth = 16, | |
475 | .colorspace = V4L2_COLORSPACE_SRGB, | |
476 | }, | |
477 | }; | |
478 | ||
479 | /* | |
480 | * color format list | |
481 | */ | |
08a66aea | 482 | static const struct ov772x_color_format ov772x_cfmts[] = { |
2941e81f | 483 | { |
08a66aea | 484 | SETFOURCC(YUYV), |
cdce7c0b KM |
485 | .dsp3 = 0x0, |
486 | .com3 = SWAP_YUV, | |
487 | .com7 = OFMT_YUV, | |
08a66aea KM |
488 | }, |
489 | { | |
490 | SETFOURCC(YVYU), | |
cdce7c0b KM |
491 | .dsp3 = UV_ON, |
492 | .com3 = SWAP_YUV, | |
493 | .com7 = OFMT_YUV, | |
08a66aea KM |
494 | }, |
495 | { | |
496 | SETFOURCC(UYVY), | |
cdce7c0b KM |
497 | .dsp3 = 0x0, |
498 | .com3 = 0x0, | |
499 | .com7 = OFMT_YUV, | |
08a66aea KM |
500 | }, |
501 | { | |
502 | SETFOURCC(RGB555), | |
cdce7c0b KM |
503 | .dsp3 = 0x0, |
504 | .com3 = SWAP_RGB, | |
505 | .com7 = FMT_RGB555 | OFMT_RGB, | |
08a66aea KM |
506 | }, |
507 | { | |
508 | SETFOURCC(RGB555X), | |
cdce7c0b KM |
509 | .dsp3 = 0x0, |
510 | .com3 = 0x0, | |
511 | .com7 = FMT_RGB555 | OFMT_RGB, | |
08a66aea KM |
512 | }, |
513 | { | |
514 | SETFOURCC(RGB565), | |
cdce7c0b KM |
515 | .dsp3 = 0x0, |
516 | .com3 = SWAP_RGB, | |
517 | .com7 = FMT_RGB565 | OFMT_RGB, | |
08a66aea KM |
518 | }, |
519 | { | |
520 | SETFOURCC(RGB565X), | |
cdce7c0b KM |
521 | .dsp3 = 0x0, |
522 | .com3 = 0x0, | |
523 | .com7 = FMT_RGB565 | OFMT_RGB, | |
08a66aea KM |
524 | }, |
525 | }; | |
526 | ||
527 | ||
528 | /* | |
529 | * window size list | |
530 | */ | |
531 | #define VGA_WIDTH 640 | |
532 | #define VGA_HEIGHT 480 | |
533 | #define QVGA_WIDTH 320 | |
534 | #define QVGA_HEIGHT 240 | |
535 | #define MAX_WIDTH VGA_WIDTH | |
536 | #define MAX_HEIGHT VGA_HEIGHT | |
537 | ||
538 | static const struct ov772x_win_size ov772x_win_vga = { | |
539 | .name = "VGA", | |
540 | .width = VGA_WIDTH, | |
541 | .height = VGA_HEIGHT, | |
542 | .com7_bit = SLCT_VGA, | |
543 | .regs = ov772x_vga_regs, | |
544 | }; | |
545 | ||
546 | static const struct ov772x_win_size ov772x_win_qvga = { | |
547 | .name = "QVGA", | |
548 | .width = QVGA_WIDTH, | |
549 | .height = QVGA_HEIGHT, | |
550 | .com7_bit = SLCT_QVGA, | |
551 | .regs = ov772x_qvga_regs, | |
552 | }; | |
553 | ||
05148911 KM |
554 | static const struct v4l2_queryctrl ov772x_controls[] = { |
555 | { | |
556 | .id = V4L2_CID_VFLIP, | |
557 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
558 | .name = "Flip Vertically", | |
559 | .minimum = 0, | |
560 | .maximum = 1, | |
561 | .step = 1, | |
562 | .default_value = 0, | |
563 | }, | |
564 | { | |
565 | .id = V4L2_CID_HFLIP, | |
566 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
567 | .name = "Flip Horizontally", | |
568 | .minimum = 0, | |
569 | .maximum = 1, | |
570 | .step = 1, | |
571 | .default_value = 0, | |
572 | }, | |
573 | }; | |
574 | ||
08a66aea KM |
575 | |
576 | /* | |
577 | * general function | |
578 | */ | |
579 | ||
580 | static int ov772x_write_array(struct i2c_client *client, | |
581 | const struct regval_list *vals) | |
582 | { | |
583 | while (vals->reg_num != 0xff) { | |
584 | int ret = i2c_smbus_write_byte_data(client, | |
585 | vals->reg_num, | |
586 | vals->value); | |
587 | if (ret < 0) | |
588 | return ret; | |
589 | vals++; | |
590 | } | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static int ov772x_mask_set(struct i2c_client *client, | |
595 | u8 command, | |
596 | u8 mask, | |
597 | u8 set) | |
598 | { | |
599 | s32 val = i2c_smbus_read_byte_data(client, command); | |
66b46e68 KM |
600 | if (val < 0) |
601 | return val; | |
602 | ||
08a66aea | 603 | val &= ~mask; |
66b46e68 | 604 | val |= set & mask; |
08a66aea KM |
605 | |
606 | return i2c_smbus_write_byte_data(client, command, val); | |
607 | } | |
608 | ||
609 | static int ov772x_reset(struct i2c_client *client) | |
610 | { | |
611 | int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET); | |
612 | msleep(1); | |
613 | return ret; | |
614 | } | |
615 | ||
616 | /* | |
617 | * soc_camera_ops function | |
618 | */ | |
619 | ||
620 | static int ov772x_init(struct soc_camera_device *icd) | |
621 | { | |
b90c032b KM |
622 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); |
623 | int ret = 0; | |
624 | ||
625 | if (priv->info->link.power) { | |
626 | ret = priv->info->link.power(&priv->client->dev, 1); | |
627 | if (ret < 0) | |
628 | return ret; | |
629 | } | |
630 | ||
631 | if (priv->info->link.reset) | |
632 | ret = priv->info->link.reset(&priv->client->dev); | |
633 | ||
634 | return ret; | |
08a66aea KM |
635 | } |
636 | ||
637 | static int ov772x_release(struct soc_camera_device *icd) | |
638 | { | |
b90c032b KM |
639 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); |
640 | int ret = 0; | |
641 | ||
642 | if (priv->info->link.power) | |
643 | ret = priv->info->link.power(&priv->client->dev, 0); | |
644 | ||
645 | return ret; | |
08a66aea KM |
646 | } |
647 | ||
648 | static int ov772x_start_capture(struct soc_camera_device *icd) | |
649 | { | |
650 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
08a66aea | 651 | |
2941e81f KM |
652 | if (!priv->win || !priv->fmt) { |
653 | dev_err(&icd->dev, "norm or win select error\n"); | |
654 | return -EPERM; | |
08a66aea KM |
655 | } |
656 | ||
f340e3f6 KM |
657 | ov772x_mask_set(priv->client, COM2, SOFT_SLEEP_MODE, 0); |
658 | ||
7dcb212e | 659 | dev_dbg(&icd->dev, |
08a66aea KM |
660 | "format %s, win %s\n", priv->fmt->name, priv->win->name); |
661 | ||
2941e81f | 662 | return 0; |
08a66aea KM |
663 | } |
664 | ||
665 | static int ov772x_stop_capture(struct soc_camera_device *icd) | |
666 | { | |
f340e3f6 KM |
667 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); |
668 | ov772x_mask_set(priv->client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE); | |
08a66aea KM |
669 | return 0; |
670 | } | |
671 | ||
672 | static int ov772x_set_bus_param(struct soc_camera_device *icd, | |
673 | unsigned long flags) | |
674 | { | |
675 | return 0; | |
676 | } | |
677 | ||
678 | static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd) | |
679 | { | |
680 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
6cb2c000 | 681 | struct soc_camera_link *icl = &priv->info->link; |
bd73b36f GL |
682 | unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER | |
683 | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH | | |
2d9329f3 | 684 | SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth; |
bd73b36f GL |
685 | |
686 | return soc_camera_apply_sensor_flags(icl, flags); | |
08a66aea KM |
687 | } |
688 | ||
05148911 KM |
689 | static int ov772x_get_control(struct soc_camera_device *icd, |
690 | struct v4l2_control *ctrl) | |
691 | { | |
692 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
693 | ||
694 | switch (ctrl->id) { | |
695 | case V4L2_CID_VFLIP: | |
696 | ctrl->value = priv->flag_vflip; | |
697 | break; | |
698 | case V4L2_CID_HFLIP: | |
699 | ctrl->value = priv->flag_hflip; | |
700 | break; | |
701 | } | |
702 | return 0; | |
703 | } | |
704 | ||
705 | static int ov772x_set_control(struct soc_camera_device *icd, | |
706 | struct v4l2_control *ctrl) | |
707 | { | |
708 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
709 | int ret = 0; | |
710 | u8 val; | |
711 | ||
712 | switch (ctrl->id) { | |
713 | case V4L2_CID_VFLIP: | |
714 | val = ctrl->value ? VFLIP_IMG : 0x00; | |
715 | priv->flag_vflip = ctrl->value; | |
716 | if (priv->info->flags & OV772X_FLAG_VFLIP) | |
717 | val ^= VFLIP_IMG; | |
718 | ret = ov772x_mask_set(priv->client, COM3, VFLIP_IMG, val); | |
719 | break; | |
720 | case V4L2_CID_HFLIP: | |
721 | val = ctrl->value ? HFLIP_IMG : 0x00; | |
722 | priv->flag_hflip = ctrl->value; | |
723 | if (priv->info->flags & OV772X_FLAG_HFLIP) | |
724 | val ^= HFLIP_IMG; | |
725 | ret = ov772x_mask_set(priv->client, COM3, HFLIP_IMG, val); | |
726 | break; | |
727 | } | |
728 | ||
729 | return ret; | |
730 | } | |
731 | ||
08a66aea | 732 | static int ov772x_get_chip_id(struct soc_camera_device *icd, |
aecde8b5 | 733 | struct v4l2_dbg_chip_ident *id) |
08a66aea | 734 | { |
aeabc882 KM |
735 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); |
736 | ||
737 | id->ident = priv->model; | |
08a66aea KM |
738 | id->revision = 0; |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
743 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
744 | static int ov772x_get_register(struct soc_camera_device *icd, | |
aecde8b5 | 745 | struct v4l2_dbg_register *reg) |
08a66aea KM |
746 | { |
747 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
748 | int ret; | |
749 | ||
aecde8b5 | 750 | reg->size = 1; |
08a66aea KM |
751 | if (reg->reg > 0xff) |
752 | return -EINVAL; | |
753 | ||
754 | ret = i2c_smbus_read_byte_data(priv->client, reg->reg); | |
755 | if (ret < 0) | |
756 | return ret; | |
757 | ||
758 | reg->val = (__u64)ret; | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | static int ov772x_set_register(struct soc_camera_device *icd, | |
aecde8b5 | 764 | struct v4l2_dbg_register *reg) |
08a66aea KM |
765 | { |
766 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
767 | ||
768 | if (reg->reg > 0xff || | |
769 | reg->val > 0xff) | |
770 | return -EINVAL; | |
771 | ||
772 | return i2c_smbus_write_byte_data(priv->client, reg->reg, reg->val); | |
773 | } | |
774 | #endif | |
775 | ||
f82a8569 KM |
776 | static const struct ov772x_win_size* |
777 | ov772x_select_win(u32 width, u32 height) | |
778 | { | |
779 | __u32 diff; | |
780 | const struct ov772x_win_size *win; | |
781 | ||
782 | /* default is QVGA */ | |
783 | diff = abs(width - ov772x_win_qvga.width) + | |
784 | abs(height - ov772x_win_qvga.height); | |
785 | win = &ov772x_win_qvga; | |
786 | ||
787 | /* VGA */ | |
788 | if (diff > | |
789 | abs(width - ov772x_win_vga.width) + | |
790 | abs(height - ov772x_win_vga.height)) | |
791 | win = &ov772x_win_vga; | |
792 | ||
793 | return win; | |
794 | } | |
795 | ||
09e231b3 GL |
796 | static int ov772x_set_params(struct ov772x_priv *priv, u32 width, u32 height, |
797 | u32 pixfmt) | |
08a66aea | 798 | { |
08a66aea | 799 | int ret = -EINVAL; |
cdce7c0b | 800 | u8 val; |
08a66aea KM |
801 | int i; |
802 | ||
803 | /* | |
804 | * select format | |
805 | */ | |
806 | priv->fmt = NULL; | |
807 | for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) { | |
808 | if (pixfmt == ov772x_cfmts[i].fourcc) { | |
809 | priv->fmt = ov772x_cfmts + i; | |
08a66aea KM |
810 | break; |
811 | } | |
812 | } | |
2941e81f KM |
813 | if (!priv->fmt) |
814 | goto ov772x_set_fmt_error; | |
08a66aea | 815 | |
f82a8569 KM |
816 | /* |
817 | * select win | |
818 | */ | |
09e231b3 | 819 | priv->win = ov772x_select_win(width, height); |
f82a8569 | 820 | |
2941e81f KM |
821 | /* |
822 | * reset hardware | |
823 | */ | |
824 | ov772x_reset(priv->client); | |
825 | ||
db6cbc8c KM |
826 | /* |
827 | * Edge Ctrl | |
828 | */ | |
829 | if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) { | |
830 | ||
831 | /* | |
832 | * Manual Edge Control Mode | |
833 | * | |
834 | * Edge auto strength bit is set by default. | |
835 | * Remove it when manual mode. | |
836 | */ | |
837 | ||
838 | ret = ov772x_mask_set(priv->client, DSPAUTO, EDGE_ACTRL, 0x00); | |
839 | if (ret < 0) | |
840 | goto ov772x_set_fmt_error; | |
841 | ||
842 | ret = ov772x_mask_set(priv->client, | |
843 | EDGE_TRSHLD, EDGE_THRESHOLD_MASK, | |
844 | priv->info->edgectrl.threshold); | |
845 | if (ret < 0) | |
846 | goto ov772x_set_fmt_error; | |
847 | ||
848 | ret = ov772x_mask_set(priv->client, | |
849 | EDGE_STRNGT, EDGE_STRENGTH_MASK, | |
850 | priv->info->edgectrl.strength); | |
851 | if (ret < 0) | |
852 | goto ov772x_set_fmt_error; | |
853 | ||
854 | } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) { | |
855 | /* | |
856 | * Auto Edge Control Mode | |
857 | * | |
858 | * set upper and lower limit | |
859 | */ | |
860 | ret = ov772x_mask_set(priv->client, | |
861 | EDGE_UPPER, EDGE_UPPER_MASK, | |
862 | priv->info->edgectrl.upper); | |
863 | if (ret < 0) | |
864 | goto ov772x_set_fmt_error; | |
865 | ||
866 | ret = ov772x_mask_set(priv->client, | |
867 | EDGE_LOWER, EDGE_LOWER_MASK, | |
868 | priv->info->edgectrl.lower); | |
869 | if (ret < 0) | |
870 | goto ov772x_set_fmt_error; | |
871 | } | |
872 | ||
2941e81f KM |
873 | /* |
874 | * set size format | |
875 | */ | |
876 | ret = ov772x_write_array(priv->client, priv->win->regs); | |
877 | if (ret < 0) | |
878 | goto ov772x_set_fmt_error; | |
879 | ||
880 | /* | |
cdce7c0b | 881 | * set DSP_CTRL3 |
2941e81f | 882 | */ |
cdce7c0b KM |
883 | val = priv->fmt->dsp3; |
884 | if (val) { | |
2941e81f | 885 | ret = ov772x_mask_set(priv->client, |
cdce7c0b | 886 | DSP_CTRL3, UV_MASK, val); |
2941e81f KM |
887 | if (ret < 0) |
888 | goto ov772x_set_fmt_error; | |
889 | } | |
890 | ||
891 | /* | |
cdce7c0b | 892 | * set COM3 |
2941e81f | 893 | */ |
cdce7c0b | 894 | val = priv->fmt->com3; |
05148911 KM |
895 | if (priv->info->flags & OV772X_FLAG_VFLIP) |
896 | val |= VFLIP_IMG; | |
897 | if (priv->info->flags & OV772X_FLAG_HFLIP) | |
898 | val |= HFLIP_IMG; | |
899 | if (priv->flag_vflip) | |
900 | val ^= VFLIP_IMG; | |
901 | if (priv->flag_hflip) | |
902 | val ^= HFLIP_IMG; | |
903 | ||
cdce7c0b | 904 | ret = ov772x_mask_set(priv->client, |
05148911 | 905 | COM3, SWAP_MASK | IMG_MASK, val); |
cdce7c0b KM |
906 | if (ret < 0) |
907 | goto ov772x_set_fmt_error; | |
908 | ||
909 | /* | |
910 | * set COM7 | |
911 | */ | |
912 | val = priv->win->com7_bit | priv->fmt->com7; | |
913 | ret = ov772x_mask_set(priv->client, | |
914 | COM7, (SLCT_MASK | FMT_MASK | OFMT_MASK), | |
915 | val); | |
916 | if (ret < 0) | |
917 | goto ov772x_set_fmt_error; | |
2941e81f KM |
918 | |
919 | return ret; | |
920 | ||
921 | ov772x_set_fmt_error: | |
922 | ||
923 | ov772x_reset(priv->client); | |
924 | priv->win = NULL; | |
925 | priv->fmt = NULL; | |
926 | ||
08a66aea KM |
927 | return ret; |
928 | } | |
929 | ||
09e231b3 GL |
930 | static int ov772x_set_crop(struct soc_camera_device *icd, |
931 | struct v4l2_rect *rect) | |
932 | { | |
933 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
934 | ||
935 | if (!priv->fmt) | |
936 | return -EINVAL; | |
937 | ||
938 | return ov772x_set_params(priv, rect->width, rect->height, | |
939 | priv->fmt->fourcc); | |
940 | } | |
941 | ||
942 | static int ov772x_set_fmt(struct soc_camera_device *icd, | |
943 | struct v4l2_format *f) | |
944 | { | |
945 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
946 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
947 | ||
948 | return ov772x_set_params(priv, pix->width, pix->height, | |
949 | pix->pixelformat); | |
950 | } | |
951 | ||
d8fac217 GL |
952 | static int ov772x_try_fmt(struct soc_camera_device *icd, |
953 | struct v4l2_format *f) | |
08a66aea | 954 | { |
f82a8569 KM |
955 | struct v4l2_pix_format *pix = &f->fmt.pix; |
956 | const struct ov772x_win_size *win; | |
08a66aea | 957 | |
f82a8569 KM |
958 | /* |
959 | * select suitable win | |
960 | */ | |
961 | win = ov772x_select_win(pix->width, pix->height); | |
08a66aea | 962 | |
f82a8569 KM |
963 | pix->width = win->width; |
964 | pix->height = win->height; | |
965 | pix->field = V4L2_FIELD_NONE; | |
08a66aea KM |
966 | |
967 | return 0; | |
968 | } | |
969 | ||
970 | static int ov772x_video_probe(struct soc_camera_device *icd) | |
971 | { | |
972 | struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd); | |
973 | u8 pid, ver; | |
aeabc882 | 974 | const char *devname; |
08a66aea KM |
975 | |
976 | /* | |
977 | * We must have a parent by now. And it cannot be a wrong one. | |
978 | * So this entire test is completely redundant. | |
979 | */ | |
980 | if (!icd->dev.parent || | |
981 | to_soc_camera_host(icd->dev.parent)->nr != icd->iface) | |
982 | return -ENODEV; | |
983 | ||
984 | /* | |
985 | * ov772x only use 8 or 10 bit bus width | |
986 | */ | |
987 | if (SOCAM_DATAWIDTH_10 != priv->info->buswidth && | |
988 | SOCAM_DATAWIDTH_8 != priv->info->buswidth) { | |
989 | dev_err(&icd->dev, "bus width error\n"); | |
990 | return -ENODEV; | |
991 | } | |
992 | ||
993 | icd->formats = ov772x_fmt_lists; | |
994 | icd->num_formats = ARRAY_SIZE(ov772x_fmt_lists); | |
995 | ||
08a66aea KM |
996 | /* |
997 | * check and show product ID and manufacturer ID | |
998 | */ | |
999 | pid = i2c_smbus_read_byte_data(priv->client, PID); | |
1000 | ver = i2c_smbus_read_byte_data(priv->client, VER); | |
aeabc882 KM |
1001 | |
1002 | switch (VERSION(pid, ver)) { | |
1003 | case OV7720: | |
1004 | devname = "ov7720"; | |
1005 | priv->model = V4L2_IDENT_OV7720; | |
1006 | break; | |
3cac2cab KM |
1007 | case OV7725: |
1008 | devname = "ov7725"; | |
1009 | priv->model = V4L2_IDENT_OV7725; | |
1010 | break; | |
aeabc882 | 1011 | default: |
b90c032b KM |
1012 | dev_err(&icd->dev, |
1013 | "Product ID error %x:%x\n", pid, ver); | |
08a66aea KM |
1014 | return -ENODEV; |
1015 | } | |
1016 | ||
1017 | dev_info(&icd->dev, | |
aeabc882 KM |
1018 | "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", |
1019 | devname, | |
08a66aea KM |
1020 | pid, |
1021 | ver, | |
1022 | i2c_smbus_read_byte_data(priv->client, MIDH), | |
1023 | i2c_smbus_read_byte_data(priv->client, MIDL)); | |
1024 | ||
08a66aea KM |
1025 | return soc_camera_video_start(icd); |
1026 | } | |
1027 | ||
1028 | static void ov772x_video_remove(struct soc_camera_device *icd) | |
1029 | { | |
08a66aea | 1030 | soc_camera_video_stop(icd); |
08a66aea KM |
1031 | } |
1032 | ||
1033 | static struct soc_camera_ops ov772x_ops = { | |
1034 | .owner = THIS_MODULE, | |
1035 | .probe = ov772x_video_probe, | |
1036 | .remove = ov772x_video_remove, | |
1037 | .init = ov772x_init, | |
1038 | .release = ov772x_release, | |
1039 | .start_capture = ov772x_start_capture, | |
1040 | .stop_capture = ov772x_stop_capture, | |
09e231b3 | 1041 | .set_crop = ov772x_set_crop, |
d8fac217 GL |
1042 | .set_fmt = ov772x_set_fmt, |
1043 | .try_fmt = ov772x_try_fmt, | |
08a66aea KM |
1044 | .set_bus_param = ov772x_set_bus_param, |
1045 | .query_bus_param = ov772x_query_bus_param, | |
05148911 KM |
1046 | .controls = ov772x_controls, |
1047 | .num_controls = ARRAY_SIZE(ov772x_controls), | |
1048 | .get_control = ov772x_get_control, | |
1049 | .set_control = ov772x_set_control, | |
08a66aea KM |
1050 | .get_chip_id = ov772x_get_chip_id, |
1051 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1052 | .get_register = ov772x_get_register, | |
1053 | .set_register = ov772x_set_register, | |
1054 | #endif | |
1055 | }; | |
1056 | ||
1057 | /* | |
1058 | * i2c_driver function | |
1059 | */ | |
1060 | ||
bef216b7 HV |
1061 | static int ov772x_probe(struct i2c_client *client, |
1062 | const struct i2c_device_id *did) | |
08a66aea KM |
1063 | { |
1064 | struct ov772x_priv *priv; | |
1065 | struct ov772x_camera_info *info; | |
1066 | struct soc_camera_device *icd; | |
1067 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); | |
1068 | int ret; | |
1069 | ||
0a861e9e | 1070 | if (!client->dev.platform_data) |
08a66aea KM |
1071 | return -EINVAL; |
1072 | ||
0a861e9e GL |
1073 | info = container_of(client->dev.platform_data, |
1074 | struct ov772x_camera_info, link); | |
1075 | ||
08a66aea KM |
1076 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { |
1077 | dev_err(&adapter->dev, | |
1078 | "I2C-Adapter doesn't support " | |
1079 | "I2C_FUNC_SMBUS_BYTE_DATA\n"); | |
1080 | return -EIO; | |
1081 | } | |
1082 | ||
1083 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1084 | if (!priv) | |
1085 | return -ENOMEM; | |
1086 | ||
1087 | priv->info = info; | |
1088 | priv->client = client; | |
1089 | i2c_set_clientdata(client, priv); | |
1090 | ||
1091 | icd = &priv->icd; | |
1092 | icd->ops = &ov772x_ops; | |
1093 | icd->control = &client->dev; | |
1094 | icd->width_max = MAX_WIDTH; | |
1095 | icd->height_max = MAX_HEIGHT; | |
1096 | icd->iface = priv->info->link.bus_id; | |
1097 | ||
1098 | ret = soc_camera_device_register(icd); | |
1099 | ||
77fe3d4a KM |
1100 | if (ret) { |
1101 | i2c_set_clientdata(client, NULL); | |
08a66aea | 1102 | kfree(priv); |
77fe3d4a | 1103 | } |
08a66aea KM |
1104 | |
1105 | return ret; | |
1106 | } | |
1107 | ||
1108 | static int ov772x_remove(struct i2c_client *client) | |
1109 | { | |
1110 | struct ov772x_priv *priv = i2c_get_clientdata(client); | |
1111 | ||
1112 | soc_camera_device_unregister(&priv->icd); | |
77fe3d4a | 1113 | i2c_set_clientdata(client, NULL); |
08a66aea KM |
1114 | kfree(priv); |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static const struct i2c_device_id ov772x_id[] = { | |
aeabc882 | 1119 | { "ov772x", 0 }, |
08a66aea KM |
1120 | { } |
1121 | }; | |
1122 | MODULE_DEVICE_TABLE(i2c, ov772x_id); | |
1123 | ||
08a66aea KM |
1124 | static struct i2c_driver ov772x_i2c_driver = { |
1125 | .driver = { | |
1126 | .name = "ov772x", | |
1127 | }, | |
1128 | .probe = ov772x_probe, | |
1129 | .remove = ov772x_remove, | |
1130 | .id_table = ov772x_id, | |
1131 | }; | |
1132 | ||
1133 | /* | |
1134 | * module function | |
1135 | */ | |
1136 | ||
1137 | static int __init ov772x_module_init(void) | |
1138 | { | |
08a66aea KM |
1139 | return i2c_add_driver(&ov772x_i2c_driver); |
1140 | } | |
1141 | ||
1142 | static void __exit ov772x_module_exit(void) | |
1143 | { | |
1144 | i2c_del_driver(&ov772x_i2c_driver); | |
1145 | } | |
1146 | ||
1147 | module_init(ov772x_module_init); | |
1148 | module_exit(ov772x_module_exit); | |
1149 | ||
1150 | MODULE_DESCRIPTION("SoC Camera driver for ov772x"); | |
1151 | MODULE_AUTHOR("Kuninori Morimoto"); | |
1152 | MODULE_LICENSE("GPL v2"); |